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Mock Turtle
Commit f5dbdb5e authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: import of squashed updates from legacy wr-node-core repository. 

Import of commit 8266053 from git://ohwr.org/white-rabbit/wr-node-core.git.

This is essentially the wr-node-core repository including all the latest untested features,
including:

  * uRV CPU
  * updated message queues
  * TPU
  * renaming of WRNC to MT
  * ...
parent 04fa428e
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Showing with 10591 additions and 2466 deletions
.gitignore
View file @ f5dbdb5e
......@@ -76,4 +76,8 @@ xst/
*stacktrace*
rtl/*.h
scp.sh
disasm.S
\ No newline at end of file
disasm.S
*.mif
*.asy
*.xco
*.debug
hdl/rtl/Manifest.py
View file @ f5dbdb5e
files = [
"mock_turtle_core.vhd",
"mock_turtle_pkg.vhd",
"mt_wb_remapper.vhd",
]
modules = {
"local" : [ "wrnc" ] }
"local" : [
"cpu",
"mqueue",
"smem",
],
}
hdl/rtl/cpu/Manifest.py 0 → 100644
View file @ f5dbdb5e
files = [
"mt_cpu_cb.vhd",
"mt_cpu_csr_wbgen2_pkg.vhd",
"mt_cpu_csr_wb.vhd",
"mt_cpu_iram.vhd",
"mt_cpu_lr_wbgen2_pkg.vhd",
"mt_cpu_lr_wb.vhd",
"mt_lm32_wrapper.vhd",
"mt_private_pkg.vhd",
"mt_urv_wrapper.vhd",
"mt_trace_profiler.vhd",
"mt_tpu_csr_wb.vhd",
"mt_tpu_csr_wbgen2_pkg.vhd"
];
hdl/rtl/cpu/build_wb.sh 0 → 100755
View file @ f5dbdb5e
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/mt_cpu_csr.html -V mt_cpu_csr_wb.vhd -p mt_cpu_csr_wbgen2_pkg.vhd --cstyle defines -C mt_cpu_csr.h --hstyle record --lang vhdl -K mt_cpu_csr_regs.vh mt_cpu_csr.wb
wbgen2 -D ./doc/mt_cpu_lr.html -V mt_cpu_lr_wb.vhd -p mt_cpu_lr_wbgen2_pkg.vhd --cstyle defines -C mt_cpu_lr.h --hstyle record --lang vhdl mt_cpu_lr.wb
wbgen2 -D ./doc/mt_tpu_csr.html -V mt_tpu_csr_wb.vhd -p mt_tpu_csr_wbgen2_pkg.vhd --cstyle defines -C mt_tpu_csr.h -K mt_tpu_csr.vh --hstyle record --lang vhdl mt_tpu_csr.wb
hdl/rtl/wrnc/cpu/wrn_cpu_cb.vhd → hdl/rtl/cpu/mt_cpu_cb.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Node Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_cpu_cb.vhd
-- File : mt_cpu_cb.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-08-13
-- Last update: 2017-05-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -44,19 +44,21 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.wrn_cpu_csr_wbgen2_pkg.all;
use work.wrn_cpu_lr_wbgen2_pkg.all;
use work.mt_cpu_csr_wbgen2_pkg.all;
use work.mt_cpu_lr_wbgen2_pkg.all;
use work.wr_node_pkg.all;
use work.mock_turtle_pkg.all;
use work.mt_private_pkg.all;
entity wrn_cpu_cb is
entity mt_cpu_cb is
generic (
g_cpu_id : integer;
g_iram_size : integer;
g_system_clock_freq : integer;
g_double_core_clock : boolean;
g_with_white_rabbit : boolean
g_with_white_rabbit : boolean;
g_cpu_arch : string
);
port (
......@@ -69,7 +71,7 @@ entity wrn_cpu_cb is
clk_cpu_i : in std_logic;
tm_i : in t_wrn_timing_if;
tm_i : in t_mt_timing_if;
sh_master_i : in t_wishbone_master_in := cc_dummy_master_in;
sh_master_o : out t_wishbone_master_out;
......@@ -77,8 +79,8 @@ entity wrn_cpu_cb is
dp_master_i : in t_wishbone_master_in := cc_dummy_master_in;
dp_master_o : out t_wishbone_master_out;
cpu_csr_i : in t_wrn_cpu_csr_out_registers;
cpu_csr_o : out t_wrn_cpu_csr_in_registers := c_wrn_cpu_csr_in_registers_init_value;
cpu_csr_i : in t_mt_cpu_csr_out_registers;
cpu_csr_o : out t_mt_cpu_csr_in_registers := c_mt_cpu_csr_in_registers_init_value;
rmq_ready_i : in std_logic_vector(15 downto 0);
hmq_ready_i : in std_logic_vector(15 downto 0);
......@@ -86,6 +88,9 @@ entity wrn_cpu_cb is
gpio_i : in std_logic_vector(31 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
pc_o : out std_logic_vector(c_mt_pc_bits-1 downto 0);
pc_valid_o : out std_logic;
dbg_drdy_o : out std_logic;
dbg_dack_i : in std_logic;
dbg_data_o : out std_logic_vector(7 downto 0)
......@@ -93,11 +98,11 @@ entity wrn_cpu_cb is
);
end wrn_cpu_cb;
end mt_cpu_cb;
architecture rtl of wrn_cpu_cb is
architecture rtl of mt_cpu_cb is
component wrn_cpu_lr_wb_slave
component mt_cpu_lr_wb_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -111,11 +116,29 @@ architecture rtl of wrn_cpu_cb is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
tai_sec_rd_ack_o : out std_logic;
regs_i : in t_wrn_cpu_lr_in_registers;
regs_o : out t_wrn_cpu_lr_out_registers);
regs_i : in t_mt_cpu_lr_in_registers;
regs_o : out t_mt_cpu_lr_out_registers);
end component;
component wrn_lm32_wrapper
component mt_urv_wrapper is
generic (
g_iram_size : integer;
g_cpu_id : integer;
g_double_core_clock : boolean);
port (
clk_cpu_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0) := x"00000000";
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
pc_o : out std_logic_vector(c_mt_pc_bits-1 downto 0);
pc_valid_o : out std_logic;
cpu_csr_i : in t_mt_cpu_csr_out_registers;
cpu_csr_o : out t_mt_cpu_csr_in_registers);
end component mt_urv_wrapper;
component mt_lm32_wrapper
generic (
g_iram_size : integer;
g_cpu_id : integer;
......@@ -127,8 +150,10 @@ architecture rtl of wrn_cpu_cb is
irq_i : in std_logic_vector(31 downto 0) := x"00000000";
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
cpu_csr_i : in t_wrn_cpu_csr_out_registers;
cpu_csr_o : out t_wrn_cpu_csr_in_registers);
pc_o : out std_logic_vector(c_mt_pc_bits-1 downto 0);
pc_valid_o : out std_logic;
cpu_csr_i : in t_mt_cpu_csr_out_registers;
cpu_csr_o : out t_mt_cpu_csr_in_registers);
end component;
constant c_local_wishbone_masters : integer := 3;
......@@ -153,8 +178,8 @@ architecture rtl of wrn_cpu_cb is
);
signal tai_sec_rd_ack : std_logic;
signal local_regs_in : t_wrn_cpu_lr_in_registers;
signal local_regs_out : t_wrn_cpu_lr_out_registers;
signal local_regs_in : t_mt_cpu_lr_in_registers;
signal local_regs_out : t_mt_cpu_lr_out_registers;
signal cpu_dwb_out : t_wishbone_master_out;
signal cpu_dwb_in : t_wishbone_master_in;
......@@ -169,6 +194,7 @@ architecture rtl of wrn_cpu_cb is
signal tm_p_ref, tm_ready_ref, tm_p_sys, tm_p_ref_d0 : std_logic;
signal dbg_fifo_empty, dbg_fifo_full, dbg_fifo_wr : std_logic;
signal dbg_fifo_reset_n : std_logic;
begin -- rtl
......@@ -324,7 +350,12 @@ begin -- rtl
end if;
end process;
U_TheCoreCPU : wrn_lm32_wrapper
gen_check_cpu_arch : if g_cpu_arch /= "LM32" and g_cpu_arch /= "URV" generate
assert false report "Unsupported CPU architecture specified in g_cpu_arch. We currently support LM32 and uRV" severity failure;
end generate gen_check_cpu_arch;
gen_with_lm32 : if g_cpu_arch = "LM32" generate
U_TheCoreCPU : mt_lm32_wrapper
generic map (
g_iram_size => g_iram_size,
g_cpu_id => g_cpu_id,
......@@ -336,11 +367,34 @@ begin -- rtl
irq_i => x"00000000", -- no irqs, we want to be deterministic...
dwb_o => cpu_dwb_out,
dwb_i => cpu_dwb_in,
pc_valid_o => pc_valid_o,
pc_o => pc_o,
cpu_csr_i => cpu_csr_i,
cpu_csr_o => cpu_csr_o);
end generate gen_with_lm32;
gen_with_urv : if g_cpu_arch = "URV" generate
U_TheCoreCPU : mt_urv_wrapper
generic map (
g_iram_size => g_iram_size,
g_cpu_id => g_cpu_id,
g_double_core_clock => g_double_core_clock)
port map (
clk_sys_i => clk_sys_i,
clk_cpu_i => clk_cpu_i,
rst_n_i => rst_n_i,
irq_i => x"00000000", -- no irqs, we want to be deterministic...
dwb_o => cpu_dwb_out,
dwb_i => cpu_dwb_in,
pc_valid_o => pc_valid_o,
pc_o => pc_o,
cpu_csr_i => cpu_csr_i,
cpu_csr_o => cpu_csr_o);
end generate gen_with_urv;
U_Local_Registrers : wrn_cpu_lr_wb_slave
U_Local_Registrers : mt_cpu_lr_wb_slave
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......@@ -390,10 +444,12 @@ begin -- rtl
U_Debug_Message_FIFO : generic_sync_fifo
generic map (
g_data_width => 8,
g_size => c_wrn_debug_message_fifo_size,
g_show_ahead => true)
g_size => c_mt_debug_message_fifo_size,
g_show_ahead => true,
g_with_count => true)
port map (
rst_n_i => rst_n_i,
rst_n_i => dbg_fifo_reset_n,
clk_i => clk_sys_i,
d_i => local_regs_out.dbg_chr_o,
we_i => dbg_fifo_wr,
......@@ -402,7 +458,25 @@ begin -- rtl
empty_o => dbg_fifo_empty,
full_o => dbg_fifo_full);
dbg_drdy_o <= not dbg_fifo_empty;
p_debug_fifo_overflow : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dbg_fifo_reset_n <= '0';
dbg_drdy_o <= '0';
else
if (dbg_fifo_full = '1') then
dbg_fifo_reset_n <= '0';
dbg_drdy_o <= '0';
else
dbg_fifo_reset_n <= '1';
dbg_drdy_o <= not dbg_fifo_empty;
end if;
end if;
end if;
end process;
local_regs_in.stat_core_id_i <= std_logic_vector(to_unsigned(g_cpu_id, 4));
......
hdl/rtl/wrnc/cpu/wrn_cpu_csr.wb → hdl/rtl/cpu/mt_cpu_csr.wb
View file @ f5dbdb5e
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_cpu_csr.wb
-- File : mt_cpu_csr.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
......@@ -36,9 +36,9 @@
-------------------------------------------------------------------------------
peripheral {
name = "WR Node CPU Control/Status registers block";
prefix = "wrn_cpu_csr";
hdl_entity = "wrn_cpu_csr_wb_slave";
name = "Mock Turtle CPU Control/Status registers block";
prefix = "mt_cpu_csr";
hdl_entity = "mt_cpu_csr_wb_slave";
reg {
name = "Application ID Register";
......@@ -267,5 +267,7 @@ access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/rtl/wrnc/cpu/wrn_cpu_csr_wb.vhd → hdl/rtl/cpu/mt_cpu_csr_wb.vhd
View file @ f5dbdb5e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Node CPU Control/Status registers block
-- Title : Wishbone slave core for Mock Turtle CPU Control/Status registers block
---------------------------------------------------------------------------------------
-- File : wrn_cpu_csr_wb.vhd
-- Author : auto-generated by wbgen2 from wrn_cpu_csr.wb
-- Created : Fri Sep 18 15:20:23 2015
-- File : mt_cpu_csr_wb.vhd
-- Author : auto-generated by wbgen2 from mt_cpu_csr.wb
-- Created : Mon Feb 26 11:11:22 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_cpu_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -14,10 +14,10 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wrn_cpu_csr_wbgen2_pkg.all;
use work.mt_cpu_csr_wbgen2_pkg.all;
entity wrn_cpu_csr_wb_slave is
entity mt_cpu_csr_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -31,38 +31,28 @@ entity wrn_cpu_csr_wb_slave is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
dbg_msg_data_rd_ack_o : out std_logic;
regs_i : in t_wrn_cpu_csr_in_registers;
regs_o : out t_wrn_cpu_csr_out_registers
regs_i : in t_mt_cpu_csr_in_registers;
regs_o : out t_mt_cpu_csr_out_registers
);
end wrn_cpu_csr_wb_slave;
end mt_cpu_csr_wb_slave;
architecture syn of wrn_cpu_csr_wb_slave is
architecture syn of mt_cpu_csr_wb_slave is
signal wrn_cpu_csr_reset_int : std_logic_vector(7 downto 0);
signal wrn_cpu_csr_enable_int : std_logic_vector(7 downto 0);
signal wrn_cpu_csr_uaddr_addr_int : std_logic_vector(19 downto 0);
signal wrn_cpu_csr_core_sel_int : std_logic_vector(3 downto 0);
signal wrn_cpu_csr_dbg_imsk_enable_int : std_logic_vector(7 downto 0);
signal wrn_cpu_csr_smem_op_int : std_logic_vector(2 downto 0);
signal mt_cpu_csr_reset_int : std_logic_vector(7 downto 0);
signal mt_cpu_csr_enable_int : std_logic_vector(7 downto 0);
signal mt_cpu_csr_uaddr_addr_int : std_logic_vector(19 downto 0);
signal mt_cpu_csr_core_sel_int : std_logic_vector(3 downto 0);
signal mt_cpu_csr_dbg_imsk_enable_int : std_logic_vector(7 downto 0);
signal mt_cpu_csr_smem_op_int : std_logic_vector(2 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -71,10 +61,10 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
wrn_cpu_csr_reset_int <= "11111111";
wrn_cpu_csr_enable_int <= "00000000";
wrn_cpu_csr_uaddr_addr_int <= "00000000000000000000";
wrn_cpu_csr_core_sel_int <= "0000";
mt_cpu_csr_reset_int <= "11111111";
mt_cpu_csr_enable_int <= "00000000";
mt_cpu_csr_uaddr_addr_int <= "00000000000000000000";
mt_cpu_csr_core_sel_int <= "0000";
regs_o.udata_load_o <= '0';
regs_o.dbg_jtag_jdata_load_o <= '0';
regs_o.dbg_jtag_jaddr_load_o <= '0';
......@@ -82,8 +72,8 @@ begin
regs_o.dbg_jtag_tck_load_o <= '0';
regs_o.dbg_jtag_update_load_o <= '0';
dbg_msg_data_rd_ack_o <= '0';
wrn_cpu_csr_dbg_imsk_enable_int <= "00000000";
wrn_cpu_csr_smem_op_int <= "000";
mt_cpu_csr_dbg_imsk_enable_int <= "00000000";
mt_cpu_csr_smem_op_int <= "000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -117,9 +107,9 @@ begin
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
wrn_cpu_csr_reset_int <= wrdata_reg(7 downto 0);
mt_cpu_csr_reset_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= wrn_cpu_csr_reset_int;
rddata_reg(7 downto 0) <= mt_cpu_csr_reset_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -148,9 +138,9 @@ begin
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
wrn_cpu_csr_enable_int <= wrdata_reg(7 downto 0);
mt_cpu_csr_enable_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= wrn_cpu_csr_enable_int;
rddata_reg(7 downto 0) <= mt_cpu_csr_enable_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -179,9 +169,9 @@ begin
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
wrn_cpu_csr_uaddr_addr_int <= wrdata_reg(19 downto 0);
mt_cpu_csr_uaddr_addr_int <= wrdata_reg(19 downto 0);
end if;
rddata_reg(19 downto 0) <= wrn_cpu_csr_uaddr_addr_int;
rddata_reg(19 downto 0) <= mt_cpu_csr_uaddr_addr_int;
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
......@@ -198,9 +188,9 @@ begin
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
wrn_cpu_csr_core_sel_int <= wrdata_reg(3 downto 0);
mt_cpu_csr_core_sel_int <= wrdata_reg(3 downto 0);
end if;
rddata_reg(3 downto 0) <= wrn_cpu_csr_core_sel_int;
rddata_reg(3 downto 0) <= mt_cpu_csr_core_sel_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -374,9 +364,9 @@ begin
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
wrn_cpu_csr_dbg_imsk_enable_int <= wrdata_reg(7 downto 0);
mt_cpu_csr_dbg_imsk_enable_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= wrn_cpu_csr_dbg_imsk_enable_int;
rddata_reg(7 downto 0) <= mt_cpu_csr_dbg_imsk_enable_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -405,9 +395,9 @@ begin
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
wrn_cpu_csr_smem_op_int <= wrdata_reg(2 downto 0);
mt_cpu_csr_smem_op_int <= wrdata_reg(2 downto 0);
end if;
rddata_reg(2 downto 0) <= wrn_cpu_csr_smem_op_int;
rddata_reg(2 downto 0) <= mt_cpu_csr_smem_op_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -454,13 +444,13 @@ begin
wb_dat_o <= rddata_reg;
-- User application ID
-- CPU reset lines
regs_o.reset_o <= wrn_cpu_csr_reset_int;
regs_o.reset_o <= mt_cpu_csr_reset_int;
-- CPU enable lines
regs_o.enable_o <= wrn_cpu_csr_enable_int;
regs_o.enable_o <= mt_cpu_csr_enable_int;
-- Address
regs_o.uaddr_addr_o <= wrn_cpu_csr_uaddr_addr_int;
regs_o.uaddr_addr_o <= mt_cpu_csr_uaddr_addr_int;
-- CPU core select
regs_o.core_sel_o <= wrn_cpu_csr_core_sel_int;
regs_o.core_sel_o <= mt_cpu_csr_core_sel_int;
-- Number of CPU Cores
-- Memory size for the selected core.
-- CPU IRAM read/write data
......@@ -478,9 +468,9 @@ begin
-- Debug message byte for the selected core
-- Debug Message data available
-- Per-CPU Debug Message Interrupt Enable
regs_o.dbg_imsk_enable_o <= wrn_cpu_csr_dbg_imsk_enable_int;
regs_o.dbg_imsk_enable_o <= mt_cpu_csr_dbg_imsk_enable_int;
-- Operation code
regs_o.smem_op_o <= wrn_cpu_csr_smem_op_int;
regs_o.smem_op_o <= mt_cpu_csr_smem_op_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd → hdl/rtl/cpu/mt_cpu_csr_wbgen2_pkg.vhd
View file @ f5dbdb5e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Node CPU Control/Status registers block
-- Title : Wishbone slave core for Mock Turtle CPU Control/Status registers block
---------------------------------------------------------------------------------------
-- File : wrn_cpu_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrn_cpu_csr.wb
-- Created : Fri Sep 18 15:20:23 2015
-- File : mt_cpu_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mt_cpu_csr.wb
-- Created : Mon Feb 26 11:11:22 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_cpu_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -14,12 +14,12 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wrn_cpu_csr_wbgen2_pkg is
package mt_cpu_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wrn_cpu_csr_in_registers is record
type t_mt_cpu_csr_in_registers is record
app_id_i : std_logic_vector(31 downto 0);
core_count_i : std_logic_vector(3 downto 0);
core_memsize_i : std_logic_vector(31 downto 0);
......@@ -33,7 +33,7 @@ package wrn_cpu_csr_wbgen2_pkg is
dbg_poll_ready_i : std_logic_vector(7 downto 0);
end record;
constant c_wrn_cpu_csr_in_registers_init_value: t_wrn_cpu_csr_in_registers := (
constant c_mt_cpu_csr_in_registers_init_value: t_mt_cpu_csr_in_registers := (
app_id_i => (others => '0'),
core_count_i => (others => '0'),
core_memsize_i => (others => '0'),
......@@ -49,7 +49,7 @@ package wrn_cpu_csr_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_wrn_cpu_csr_out_registers is record
type t_mt_cpu_csr_out_registers is record
reset_o : std_logic_vector(7 downto 0);
enable_o : std_logic_vector(7 downto 0);
uaddr_addr_o : std_logic_vector(19 downto 0);
......@@ -70,7 +70,7 @@ package wrn_cpu_csr_wbgen2_pkg is
smem_op_o : std_logic_vector(2 downto 0);
end record;
constant c_wrn_cpu_csr_out_registers_init_value: t_wrn_cpu_csr_out_registers := (
constant c_mt_cpu_csr_out_registers_init_value: t_mt_cpu_csr_out_registers := (
reset_o => (others => '0'),
enable_o => (others => '0'),
uaddr_addr_o => (others => '0'),
......@@ -90,12 +90,12 @@ package wrn_cpu_csr_wbgen2_pkg is
dbg_imsk_enable_o => (others => '0'),
smem_op_o => (others => '0')
);
function "or" (left, right: t_wrn_cpu_csr_in_registers) return t_wrn_cpu_csr_in_registers;
function "or" (left, right: t_mt_cpu_csr_in_registers) return t_mt_cpu_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body wrn_cpu_csr_wbgen2_pkg is
package body mt_cpu_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
......@@ -116,8 +116,8 @@ end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wrn_cpu_csr_in_registers) return t_wrn_cpu_csr_in_registers is
variable tmp: t_wrn_cpu_csr_in_registers;
function "or" (left, right: t_mt_cpu_csr_in_registers) return t_mt_cpu_csr_in_registers is
variable tmp: t_mt_cpu_csr_in_registers;
begin
tmp.app_id_i := f_x_to_zero(left.app_id_i) or f_x_to_zero(right.app_id_i);
tmp.core_count_i := f_x_to_zero(left.core_count_i) or f_x_to_zero(right.core_count_i);
......
hdl/rtl/wrnc/cpu/wrn_cpu_iram.vhd → hdl/rtl/cpu/mt_cpu_iram.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_cpu_iram.vhd
-- File : mt_cpu_iram.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
......@@ -12,7 +12,7 @@
-------------------------------------------------------------------------------
-- Description:
--
-- WR Node CPU Internal RAM block. To be replaced with direct cache execution.
-- MT CPU Internal RAM block. To be replaced with direct cache execution.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
......@@ -41,7 +41,7 @@ use ieee.NUMERIC_STD.all;
use work.genram_pkg.all;
entity wrn_cpu_iram is
entity mt_cpu_iram is
generic (
g_size : integer);
......@@ -66,9 +66,9 @@ entity wrn_cpu_iram is
web_i : in std_logic
);
end wrn_cpu_iram;
end mt_cpu_iram;
architecture rtl of wrn_cpu_iram is
architecture rtl of mt_cpu_iram is
type t_ram_type is array(0 to g_size - 1) of std_logic_vector(31 downto 0);
......
hdl/rtl/wrnc/cpu/wrn_cpu_lr.wb → hdl/rtl/cpu/mt_cpu_lr.wb
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_cpu_lr.wb
-- File : mt_cpu_lr.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
......@@ -37,8 +37,8 @@
peripheral {
name = "WR Node CPU Local Registers";
prefix = "wrn_cpu_lr";
hdl_entity = "wrn_cpu_lr_wb_slave";
prefix = "mt_cpu_lr";
hdl_entity = "mt_cpu_lr_wb_slave";
reg {
name = "CPU Polling Register";
......
hdl/rtl/wrnc/cpu/wrn_cpu_lr_wb.vhd → hdl/rtl/cpu/mt_cpu_lr_wb.vhd
View file @ f5dbdb5e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Node CPU Local Registers
---------------------------------------------------------------------------------------
-- File : wrn_cpu_lr_wb.vhd
-- Author : auto-generated by wbgen2 from wrn_cpu_lr.wb
-- Created : Thu Aug 13 10:15:46 2015
-- File : mt_cpu_lr_wb.vhd
-- Author : auto-generated by wbgen2 from mt_cpu_lr.wb
-- Created : Mon Feb 26 11:11:22 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_lr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_cpu_lr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -14,10 +14,10 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wrn_cpu_lr_wbgen2_pkg.all;
use work.mt_cpu_lr_wbgen2_pkg.all;
entity wrn_cpu_lr_wb_slave is
entity mt_cpu_lr_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -31,32 +31,22 @@ entity wrn_cpu_lr_wb_slave is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
tai_sec_rd_ack_o : out std_logic;
regs_i : in t_wrn_cpu_lr_in_registers;
regs_o : out t_wrn_cpu_lr_out_registers
regs_i : in t_mt_cpu_lr_in_registers;
regs_o : out t_mt_cpu_lr_out_registers
);
end wrn_cpu_lr_wb_slave;
end mt_cpu_lr_wb_slave;
architecture syn of wrn_cpu_lr_wb_slave is
architecture syn of mt_cpu_lr_wb_slave is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -129,10 +119,10 @@ begin
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= regs_i.tai_cycles_i;
rddata_reg(28) <= '0';
rddata_reg(29) <= '0';
rddata_reg(30) <= '0';
rddata_reg(31) <= '0';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
......
hdl/rtl/wrnc/cpu/wrn_cpu_lr_wbgen2_pkg.vhd → hdl/rtl/cpu/mt_cpu_lr_wbgen2_pkg.vhd
View file @ f5dbdb5e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Node CPU Local Registers
---------------------------------------------------------------------------------------
-- File : wrn_cpu_lr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrn_cpu_lr.wb
-- Created : Thu Aug 13 10:15:46 2015
-- File : mt_cpu_lr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mt_cpu_lr.wb
-- Created : Mon Feb 26 11:11:22 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_lr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_cpu_lr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -14,12 +14,12 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wrn_cpu_lr_wbgen2_pkg is
package mt_cpu_lr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wrn_cpu_lr_in_registers is record
type t_mt_cpu_lr_in_registers is record
poll_hmq_i : std_logic_vector(15 downto 0);
poll_rmq_i : std_logic_vector(15 downto 0);
stat_wr_link_i : std_logic;
......@@ -33,7 +33,7 @@ package wrn_cpu_lr_wbgen2_pkg is
app_id_i : std_logic_vector(31 downto 0);
end record;
constant c_wrn_cpu_lr_in_registers_init_value: t_wrn_cpu_lr_in_registers := (
constant c_mt_cpu_lr_in_registers_init_value: t_mt_cpu_lr_in_registers := (
poll_hmq_i => (others => '0'),
poll_rmq_i => (others => '0'),
stat_wr_link_i => '0',
......@@ -49,7 +49,7 @@ package wrn_cpu_lr_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_wrn_cpu_lr_out_registers is record
type t_mt_cpu_lr_out_registers is record
gpio_set_o : std_logic_vector(31 downto 0);
gpio_set_wr_o : std_logic;
gpio_clear_o : std_logic_vector(31 downto 0);
......@@ -60,7 +60,7 @@ package wrn_cpu_lr_wbgen2_pkg is
delay_cnt_load_o : std_logic;
end record;
constant c_wrn_cpu_lr_out_registers_init_value: t_wrn_cpu_lr_out_registers := (
constant c_mt_cpu_lr_out_registers_init_value: t_mt_cpu_lr_out_registers := (
gpio_set_o => (others => '0'),
gpio_set_wr_o => '0',
gpio_clear_o => (others => '0'),
......@@ -70,12 +70,12 @@ package wrn_cpu_lr_wbgen2_pkg is
delay_cnt_o => (others => '0'),
delay_cnt_load_o => '0'
);
function "or" (left, right: t_wrn_cpu_lr_in_registers) return t_wrn_cpu_lr_in_registers;
function "or" (left, right: t_mt_cpu_lr_in_registers) return t_mt_cpu_lr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body wrn_cpu_lr_wbgen2_pkg is
package body mt_cpu_lr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
......@@ -96,8 +96,8 @@ end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wrn_cpu_lr_in_registers) return t_wrn_cpu_lr_in_registers is
variable tmp: t_wrn_cpu_lr_in_registers;
function "or" (left, right: t_mt_cpu_lr_in_registers) return t_mt_cpu_lr_in_registers is
variable tmp: t_mt_cpu_lr_in_registers;
begin
tmp.poll_hmq_i := f_x_to_zero(left.poll_hmq_i) or f_x_to_zero(right.poll_hmq_i);
tmp.poll_rmq_i := f_x_to_zero(left.poll_rmq_i) or f_x_to_zero(right.poll_rmq_i);
......
hdl/rtl/wrnc/cpu/wrn_lm32_wrapper.vhd → hdl/rtl/cpu/mt_lm32_wrapper.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_lm32_wrapper.vhd
-- File : mt_lm32_wrapper.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2016-09-27
-- Last update: 2016-09-29
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -42,10 +42,10 @@ use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.wrn_cpu_csr_wbgen2_pkg.all;
use work.wrn_private_pkg.all;
use work.mt_cpu_csr_wbgen2_pkg.all;
use work.mt_private_pkg.all;
entity wrn_lm32_wrapper is
entity mt_lm32_wrapper is
generic(
g_iram_size : integer;
g_cpu_id : integer;
......@@ -62,12 +62,15 @@ entity wrn_lm32_wrapper is
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
cpu_csr_i : in t_wrn_cpu_csr_out_registers;
cpu_csr_o : out t_wrn_cpu_csr_in_registers
pc_o: out std_logic_vector(c_mt_pc_bits-1 downto 0);
pc_valid_o : out std_logic;
cpu_csr_i : in t_mt_cpu_csr_out_registers;
cpu_csr_o : out t_mt_cpu_csr_in_registers
);
end wrn_lm32_wrapper;
end mt_lm32_wrapper;
architecture wrapper of wrn_lm32_wrapper is
architecture wrapper of mt_lm32_wrapper is
constant c_iram_addr_width : integer := f_log2_size(g_iram_size)-2;
......@@ -102,7 +105,7 @@ architecture wrapper of wrn_lm32_wrapper is
iram_d_we_o : out std_logic;
iram_d_en_o : out std_logic;
--trace_pc : out std_logic_vector(31 downto 0);
--trace_pc : out std_logic_vector(29 downto 0);
--trace_pc_valid : out std_logic;
--trace_exception : out std_logic;
--trace_eid : out std_logic_vector(2 downto 0);
......@@ -123,7 +126,7 @@ architecture wrapper of wrn_lm32_wrapper is
end component;
component wrn_cpu_iram
component mt_cpu_iram
generic (
g_size : integer);
port (
......@@ -231,8 +234,13 @@ architecture wrapper of wrn_lm32_wrapper is
signal bus_timeout : unsigned(7 downto 0);
signal bus_timeout_hit : std_logic;
signal trace_pc : std_logic_vector(29 downto 0);
signal trace_pc_valid : std_logic;
begin
pc_valid_o <= trace_pc_valid;
pc_o <= trace_pc(c_mt_pc_bits-3 downto 0) & "00";
gen_with_double_core_clock : if g_double_core_clock generate
......@@ -256,6 +264,9 @@ begin
iram_d_we_o => iram_d_wr,
iram_d_en_o => iram_d_en,
--trace_pc => trace_pc,
--trace_pc_valid => trace_pc_valid,
D_DAT_O => cpu_dwb_out.dat,
D_ADR_O => cpu_dwb_out.adr,
D_CYC_O => cpu_dwb_out.cyc,
......@@ -397,6 +408,9 @@ begin
iram_d_we_o => iram_d_wr,
iram_d_en_o => iram_d_en,
--trace_pc => trace_pc,
--trace_pc_valid => trace_pc_valid,
D_DAT_O => cpu_dwb_out.dat,
D_ADR_O => cpu_dwb_out.adr,
D_CYC_O => cpu_dwb_out.cyc,
......@@ -409,35 +423,6 @@ begin
D_RTY_I => cpu_dwb_in.rty);
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_sys_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
trig0(0) <= cpu_reset;
trig0(1) <= iram_i_en_cpu;
trig0(2) <= cpu_dwb_out.cyc;
trig0(3) <= cpu_dwb_out.stb;
trig0(4) <= cpu_dwb_out.we;
trig0(5) <= cpu_dwb_in.ack;
trig0(6) <= cpu_dwb_in.err;
trig0(7) <= cpu_dwb_in.rty;
trig0(8) <= cpu_dwb_in.stall;
trig0(9) <= dwb_i.ack;
trig0(10) <= dwb_i.err;
trig0(11) <= dwb_i.rty;
trig0(12) <= dwb_i.stall;
trig3 <= cpu_dwb_out.adr;
trig1 <= iram_i_adr_cpu;
trig2 <= iram_d_adr;
cpu_dwb_in.dat <= cpu_dwb_in_sys.dat;
......
hdl/rtl/wrnc/cpu/wrn_private_pkg.vhd → hdl/rtl/cpu/mt_private_pkg.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_private_pkg.vhd
-- File : mt_private_pkg.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
......@@ -12,7 +12,7 @@
-------------------------------------------------------------------------------
-- Description:
--
-- Private definitions for the WR node core.
-- Private definitions for the Mock Turtle core.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
......@@ -38,7 +38,13 @@
library ieee;
use ieee.std_logic_1164.all;
package wrn_private_pkg is
package mt_private_pkg is
constant c_mt_pc_bits : integer := 20;
subtype t_pc_counter is std_logic_vector(c_mt_pc_bits-1 downto 0);
type t_pc_array is array(integer range<>) of t_pc_counter;
function f_pick (
cond : boolean;
if_1 : std_logic;
......@@ -65,7 +71,7 @@ package wrn_private_pkg is
end package;
package body wrn_private_pkg is
package body mt_private_pkg is
function f_pick (
cond : boolean;
......
hdl/rtl/cpu/mt_tpu_csr.wb 0 → 100644
View file @ f5dbdb5e
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : Mock Turtle Trace/Profile Unit
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : mt_tpu_csr.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2014-11-26
-------------------------------------------------------------------------------
-- Description:
--
-- CPU Control/Status Registers block layout (wbgen2)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
peripheral {
name = "Mock Turtle Trace/Priofile Unit Control Registers Block";
prefix = "tpu";
hdl_entity = "mt_tpu_csr_wb_slave";
reg {
name = "TPU Control/Status Register";
description = "Controls the Trace/Profile Unit (TPU) if available";
prefix = "CSR";
field {
name = "Present";
prefix = "PRESENT";
description = "1: TPU is present";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Enable";
prefix = "ENABLE";
description = "1: enable TPU";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Force Start";
prefix = "FORCE_START";
description = "write 1: Forces TPU logging start";
type = MONOSTABLE;
};
field {
name = "Ready";
prefix = "READY";
description = "1: indicates the profiling cycle has completed";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Probe Count";
prefix = "PROBE_COUNT";
description = "Number of probes supported by this TPU instance (1-31)";
size = 5;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Probe Select";
prefix = "PROBE_SEL";
description = "Selects the active TPU probe accessed by the PROBE_CSR register (0..PROBE_COUNT-1)";
size = 5;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TPU Probe Control/Status Register";
description = "Configures the selected TPU probe";
prefix = "PROBE_CSR";
field {
name = "Program Counter match value";
description = "If the PC value in the core selected by CORE_ID bits matches the value of this field, the corresponding ACTION is triggered";
prefix = "PC";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Core select for PC match";
description = "Selects the core that the probe applies to";
prefix = "CORE_ID";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Action";
prefix = "ACTION";
description = "Action to take when the PC match occurs:\
0: start recording\
1: stop recording\
2: save timestamp (period start)\
3: save timestamp (period end)";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TPU Sample Buffer Current Sample Count";
prefix = "BUF_COUNT";
description = "Current number of samples in the TPU buffer";
field {
name = "Count";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TPU Sample Buffer Size";
prefix = "BUF_SIZE";
description = "Max samples the TPU buffer can hold";
field {
name = "Size";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TPU Sample Buffer Address";
prefix = "BUF_ADDR";
name = "Address to read from the TPU sample buffer (in 32-bit words)";
field {
name = "Address";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TPU Sample Buffer Data";
prefix = "BUF_DATA";
description = "Data in the TPU sample buffer read from BUF_ADDR (indirect access)";
field {
name = "Probe ID the timestamp corresponds to";
prefix = "ID";
size = 5;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp (in system clock ticks)";
prefix = "TSTAMP";
size = 27;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/rtl/cpu/mt_tpu_csr_wb.vhd 0 → 100644
View file @ f5dbdb5e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Mock Turtle Trace/Priofile Unit Control Registers Block
---------------------------------------------------------------------------------------
-- File : mt_tpu_csr_wb.vhd
-- Author : auto-generated by wbgen2 from mt_tpu_csr.wb
-- Created : Mon Feb 26 11:11:23 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_tpu_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tpu_wbgen2_pkg.all;
entity mt_tpu_csr_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_tpu_in_registers;
regs_o : out t_tpu_out_registers
);
end mt_tpu_csr_wb_slave;
architecture syn of mt_tpu_csr_wb_slave is
signal tpu_csr_enable_int : std_logic ;
signal tpu_csr_force_start_dly0 : std_logic ;
signal tpu_csr_force_start_int : std_logic ;
signal tpu_csr_probe_sel_int : std_logic_vector(4 downto 0);
signal tpu_buf_addr_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tpu_csr_enable_int <= '0';
tpu_csr_force_start_int <= '0';
tpu_csr_probe_sel_int <= "00000";
regs_o.probe_csr_pc_load_o <= '0';
regs_o.probe_csr_core_id_load_o <= '0';
regs_o.probe_csr_action_load_o <= '0';
tpu_buf_addr_int <= "0000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tpu_csr_force_start_int <= '0';
regs_o.probe_csr_pc_load_o <= '0';
regs_o.probe_csr_core_id_load_o <= '0';
regs_o.probe_csr_action_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.probe_csr_pc_load_o <= '0';
regs_o.probe_csr_core_id_load_o <= '0';
regs_o.probe_csr_action_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
tpu_csr_enable_int <= wrdata_reg(1);
tpu_csr_force_start_int <= wrdata_reg(2);
tpu_csr_probe_sel_int <= wrdata_reg(13 downto 9);
end if;
rddata_reg(0) <= regs_i.csr_present_i;
rddata_reg(1) <= tpu_csr_enable_int;
rddata_reg(2) <= '0';
rddata_reg(3) <= regs_i.csr_ready_i;
rddata_reg(8 downto 4) <= regs_i.csr_probe_count_i;
rddata_reg(13 downto 9) <= tpu_csr_probe_sel_int;
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
regs_o.probe_csr_pc_load_o <= '1';
regs_o.probe_csr_core_id_load_o <= '1';
regs_o.probe_csr_action_load_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.probe_csr_pc_i;
rddata_reg(27 downto 24) <= regs_i.probe_csr_core_id_i;
rddata_reg(31 downto 28) <= regs_i.probe_csr_action_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.buf_count_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.buf_size_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
tpu_buf_addr_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= tpu_buf_addr_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= regs_i.buf_data_id_i;
rddata_reg(31 downto 5) <= regs_i.buf_data_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Present
-- Enable
regs_o.csr_enable_o <= tpu_csr_enable_int;
-- Force Start
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tpu_csr_force_start_dly0 <= '0';
regs_o.csr_force_start_o <= '0';
elsif rising_edge(clk_sys_i) then
tpu_csr_force_start_dly0 <= tpu_csr_force_start_int;
regs_o.csr_force_start_o <= tpu_csr_force_start_int and (not tpu_csr_force_start_dly0);
end if;
end process;
-- Ready
-- Probe Count
-- Probe Select
regs_o.csr_probe_sel_o <= tpu_csr_probe_sel_int;
-- Program Counter match value
regs_o.probe_csr_pc_o <= wrdata_reg(23 downto 0);
-- Core select for PC match
regs_o.probe_csr_core_id_o <= wrdata_reg(27 downto 24);
-- Action
regs_o.probe_csr_action_o <= wrdata_reg(31 downto 28);
-- Count
-- Size
-- Address
regs_o.buf_addr_o <= tpu_buf_addr_int;
-- Probe ID the timestamp corresponds to
-- Timestamp (in system clock ticks)
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/cpu/mt_tpu_csr_wbgen2_pkg.vhd 0 → 100644
View file @ f5dbdb5e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Mock Turtle Trace/Priofile Unit Control Registers Block
---------------------------------------------------------------------------------------
-- File : mt_tpu_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mt_tpu_csr.wb
-- Created : Mon Feb 26 11:11:23 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_tpu_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tpu_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_tpu_in_registers is record
csr_present_i : std_logic;
csr_ready_i : std_logic;
csr_probe_count_i : std_logic_vector(4 downto 0);
probe_csr_pc_i : std_logic_vector(23 downto 0);
probe_csr_core_id_i : std_logic_vector(3 downto 0);
probe_csr_action_i : std_logic_vector(3 downto 0);
buf_count_i : std_logic_vector(15 downto 0);
buf_size_i : std_logic_vector(15 downto 0);
buf_data_id_i : std_logic_vector(4 downto 0);
buf_data_tstamp_i : std_logic_vector(26 downto 0);
end record;
constant c_tpu_in_registers_init_value: t_tpu_in_registers := (
csr_present_i => '0',
csr_ready_i => '0',
csr_probe_count_i => (others => '0'),
probe_csr_pc_i => (others => '0'),
probe_csr_core_id_i => (others => '0'),
probe_csr_action_i => (others => '0'),
buf_count_i => (others => '0'),
buf_size_i => (others => '0'),
buf_data_id_i => (others => '0'),
buf_data_tstamp_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_tpu_out_registers is record
csr_enable_o : std_logic;
csr_force_start_o : std_logic;
csr_probe_sel_o : std_logic_vector(4 downto 0);
probe_csr_pc_o : std_logic_vector(23 downto 0);
probe_csr_pc_load_o : std_logic;
probe_csr_core_id_o : std_logic_vector(3 downto 0);
probe_csr_core_id_load_o : std_logic;
probe_csr_action_o : std_logic_vector(3 downto 0);
probe_csr_action_load_o : std_logic;
buf_addr_o : std_logic_vector(15 downto 0);
end record;
constant c_tpu_out_registers_init_value: t_tpu_out_registers := (
csr_enable_o => '0',
csr_force_start_o => '0',
csr_probe_sel_o => (others => '0'),
probe_csr_pc_o => (others => '0'),
probe_csr_pc_load_o => '0',
probe_csr_core_id_o => (others => '0'),
probe_csr_core_id_load_o => '0',
probe_csr_action_o => (others => '0'),
probe_csr_action_load_o => '0',
buf_addr_o => (others => '0')
);
function "or" (left, right: t_tpu_in_registers) return t_tpu_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body tpu_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tpu_in_registers) return t_tpu_in_registers is
variable tmp: t_tpu_in_registers;
begin
tmp.csr_present_i := f_x_to_zero(left.csr_present_i) or f_x_to_zero(right.csr_present_i);
tmp.csr_ready_i := f_x_to_zero(left.csr_ready_i) or f_x_to_zero(right.csr_ready_i);
tmp.csr_probe_count_i := f_x_to_zero(left.csr_probe_count_i) or f_x_to_zero(right.csr_probe_count_i);
tmp.probe_csr_pc_i := f_x_to_zero(left.probe_csr_pc_i) or f_x_to_zero(right.probe_csr_pc_i);
tmp.probe_csr_core_id_i := f_x_to_zero(left.probe_csr_core_id_i) or f_x_to_zero(right.probe_csr_core_id_i);
tmp.probe_csr_action_i := f_x_to_zero(left.probe_csr_action_i) or f_x_to_zero(right.probe_csr_action_i);
tmp.buf_count_i := f_x_to_zero(left.buf_count_i) or f_x_to_zero(right.buf_count_i);
tmp.buf_size_i := f_x_to_zero(left.buf_size_i) or f_x_to_zero(right.buf_size_i);
tmp.buf_data_id_i := f_x_to_zero(left.buf_data_id_i) or f_x_to_zero(right.buf_data_id_i);
tmp.buf_data_tstamp_i := f_x_to_zero(left.buf_data_tstamp_i) or f_x_to_zero(right.buf_data_tstamp_i);
return tmp;
end function;
end package body;
hdl/rtl/cpu/mt_trace_profiler.vhd 0 → 100644
View file @ f5dbdb5e
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.mock_turtle_pkg.all;
use work.mt_private_pkg.all;
use work.tpu_wbgen2_pkg.all;
entity mt_trace_profiler is
generic (
g_config : t_mock_turtle_config);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
cpu_pc_i : in t_pc_array(0 to g_config.cpu_count-1);
cpu_pc_valid_i : in std_logic_vector(g_config.cpu_count-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
);
end mt_trace_profiler;
architecture rtl of mt_trace_profiler is
component mt_tpu_csr_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_tpu_in_registers;
regs_o : out t_tpu_out_registers);
end component mt_tpu_csr_wb_slave;
constant c_ACTION_DISABLED : std_logic_vector(3 downto 0) := x"0";
constant c_ACTION_START_REC : std_logic_vector(3 downto 0) := x"1";
constant c_ACTION_STOP_REC : std_logic_vector(3 downto 0) := x"2";
constant c_ACTION_PROBE_START : std_logic_vector(3 downto 0) := x"3";
constant c_ACTION_PROBE_END : std_logic_vector(3 downto 0) := x"4";
type t_channel is record
core_id : std_logic_vector(2 downto 0);
pc : std_logic_vector(c_mt_pc_bits-1 downto 0);
pc_valid : std_logic;
pc_match : std_logic_vector(c_mt_pc_bits-1 downto 0);
action : std_logic_vector(3 downto 0);
hit : std_logic;
ack : std_logic;
ts : unsigned(26 downto 0);
end record;
type t_channel_array is array(0 to g_config.tpu_channels-1) of t_channel;
type t_state is (ST_IDLE, ST_RECORDING, ST_DONE);
signal ts_counter : unsigned(26 downto 0);
signal ch : t_channel_array;
signal state : t_state;
signal chan_sel : integer range 0 to g_config.tpu_channels-1;
signal start_rec_v, stop_rec_v : std_logic_vector(g_config.tpu_channels-1 downto 0);
signal start_rec, stop_rec : std_logic;
constant c_mem_addr_width : integer := f_log2_size(g_config.tpu_buffer_size);
signal arb_input_data : std_logic_vector(32 * g_config.tpu_channels-1 downto 0);
signal arb_input_req : std_logic_vector(g_config.tpu_channels-1 downto 0);
signal arb_input_valid : std_logic_vector(g_config.tpu_channels-1 downto 0);
signal arb_out_data : std_logic_vector(31 downto 0);
signal arb_out_valid : std_logic;
signal mem_addr : unsigned(c_mem_addr_width - 1 downto 0);
signal mem_rdata : std_logic_vector(31 downto 0);
signal channel_id : integer range 0 to g_config.tpu_channels-1;
signal regs_out : t_tpu_out_registers;
signal regs_in : t_tpu_in_registers;
begin
U_WB_Regs : mt_tpu_csr_wb_slave
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => slave_i.adr(4 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
regs_i => regs_in,
regs_o => regs_out);
p_ts_counter : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ts_counter <= (others => '0');
else
ts_counter <= ts_counter + 1;
end if;
end if;
end process;
gen_channels : for i in 0 to g_config.tpu_channels-1 generate
p_mux_pcs : process(clk_i)
begin
if rising_edge(clk_i) then
ch(i).pc <= cpu_pc_i(to_integer(unsigned(ch(i).core_id)));
ch(i).pc_valid <= cpu_pc_valid_i(to_integer(unsigned(ch(i).core_id)));
end if;
end process;
p_match_logic : process(clk_i)
begin
if rising_edge(clk_i) then
start_rec_v(i) <= '0';
stop_rec_v(i) <= '0';
if rst_n_i = '0' or ch(i).action = c_ACTION_DISABLED or ch(i).ack = '1' then
ch(i).hit <= '0';
elsif (ch(i).pc = ch(i).pc_match and ch(i).pc_valid = '1') then
ch(i).ts <= ts_counter;
if (ch(i).action = c_ACTION_START_REC) then
start_rec_v(i) <= '1';
ch(i).hit <= '1';
elsif (ch(i).action = c_ACTION_STOP_REC) then
stop_rec_v(i) <= '1';
ch(i).hit <= '1';
elsif (state = ST_RECORDING) then
ch(i).hit <= '1';
end if;
end if;
end if;
end process;
p_gen_arb_req_ack : process(state, ch, arb_input_req)
begin
if (ch(i).hit = '1') then
arb_input_valid(i) <= '1';
else
arb_input_valid(i) <= '0';
end if;
arb_input_data(32 * (i+1) -1 downto 32 * i) <= std_logic_vector(to_unsigned(i, 5)) & std_logic_vector(ch(i).ts);
ch(i).ack <= ch(i).hit and arb_input_req(i);
end process;
p_channel_regs_write : process(clk_i)
begin
if rising_edge(clk_i) then
if (regs_out.probe_csr_pc_load_o = '1' and i = channel_id) then
ch(i).pc_match <= regs_out.probe_csr_pc_o(c_mt_pc_bits-1 downto 0);
ch(i).core_id <= regs_out.probe_csr_core_id_o(2 downto 0);
ch(i).action <= regs_out.probe_csr_action_o;
end if;
end if;
end process;
end generate gen_channels;
start_rec <= f_reduce_or (start_rec_v);
stop_rec <= f_reduce_or (stop_rec_v);
U_Arbitrate_Buffer : gc_arbitrated_mux
generic map (
g_num_inputs => g_config.tpu_channels,
g_width => 32)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
d_i => arb_input_data,
d_valid_i => arb_input_valid,
d_req_o => arb_input_req,
q_o => arb_out_data,
q_valid_o => arb_out_valid);
U_Sample_Buffer : generic_dpram
generic map (
g_data_width => 32,
g_size => g_config.tpu_buffer_size,
g_with_byte_enable => false,
g_dual_clock => false)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
wea_i => arb_out_valid,
aa_i => std_logic_vector(mem_addr),
da_i => arb_out_data,
clkb_i => clk_i,
web_i => '0',
ab_i => regs_out.buf_addr_o(c_mem_addr_width-1 downto 0),
qb_o => mem_rdata);
p_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' or regs_out.csr_enable_o = '0' then
state <= ST_IDLE;
mem_addr <= (others => '0');
else
case state is
when ST_IDLE =>
regs_in.csr_ready_i <= '0';
if (start_rec = '1' or regs_out.csr_force_start_o = '1') then
state <= ST_RECORDING;
mem_addr <= (others => '0');
end if;
when ST_RECORDING =>
if (arb_out_valid = '1') then
mem_addr <= mem_addr + 1;
if(mem_addr = g_config.tpu_buffer_size - 1) then
state <= ST_DONE;
end if;
end if;
if (stop_rec = '1') then
state <= ST_DONE;
end if;
when ST_DONE =>
regs_in.csr_ready_i <= '1';
end case;
end if;
end if;
end process;
channel_id <= to_integer(unsigned(regs_out.csr_probe_sel_o));
p_channel_regs_read : process(clk_i)
begin
if rising_edge(clk_i) then
regs_in.probe_csr_pc_i <= std_logic_vector(resize (unsigned(ch(channel_id).pc_match), 24));
regs_in.probe_csr_action_i <= ch(channel_id).action;
regs_in.probe_csr_core_id_i <= '0'&ch(channel_id).core_id;
end if;
end process;
regs_in.buf_count_i <= std_logic_vector (resize(mem_addr + 1, 16));
regs_in.buf_size_i <= std_logic_vector (to_unsigned(g_config.tpu_buffer_size, 16));
regs_in.csr_probe_count_i <= std_logic_vector(to_unsigned (g_config.tpu_channels, 5));
regs_in.buf_data_id_i <= mem_rdata(31 downto 27);
regs_in.buf_data_tstamp_i <= mem_rdata(26 downto 0);
regs_in.csr_present_i <= '1';
end rtl;
hdl/rtl/cpu/mt_urv_wrapper.vhd 0 → 100644
View file @ f5dbdb5e
This diff is collapsed.
hdl/rtl/wrnc/wr_node_pkg.vhd → hdl/rtl/mock_turtle_pkg.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wr_node_pkg.vhd
-- File : mock_turtle_pkg.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-08-13
-- Last update: 2017-05-15
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- White Rabbit Node Core - top level package, with public types, definitions
-- Mock Turtle Core - top level package, with public types, definitions
-- and components.
-------------------------------------------------------------------------------
--
......@@ -42,15 +42,15 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.mt_mqueue_pkg.all;
use work.wr_fabric_pkg.all;
package wr_node_pkg is
package mock_turtle_pkg is
constant c_wrn_debug_message_fifo_size : integer := 512;
constant c_mt_debug_message_fifo_size : integer := 512;
type t_wrn_timing_if is record
type t_mt_timing_if is record
link_up : std_logic;
dac_value : std_logic_vector(23 downto 0);
dac_wr : std_logic;
......@@ -62,25 +62,32 @@ package wr_node_pkg is
type t_int_array is array(integer range<>) of integer;
type t_wr_node_config is record
app_id : std_logic_vector(31 downto 0);
cpu_count : integer;
type t_mock_turtle_config is record
app_id : std_logic_vector(31 downto 0);
cpu_count : integer;
-- CPU memory sizes, in bytes
cpu_memsizes : t_int_array (0 to 7);
hmq_config : t_wrn_mqueue_config;
rmq_config : t_wrn_mqueue_config;
cpu_memsizes : t_int_array (0 to 7);
hmq_config : t_mt_mqueue_config;
rmq_config : t_mt_mqueue_config;
-- shared memory size, in bytes
shared_mem_size : integer range 256 to 65536;
tpu_enable : boolean;
tpu_channels : integer range 1 to 32;
tpu_buffer_size : integer range 256 to 65536;
end record;
constant c_default_node_config : t_wr_node_config :=
constant c_default_mock_turtle_config : t_mock_turtle_config :=
(
app_id => x"115790de",
cpu_count => 2,
cpu_memsizes => (32768, 32768, 0, 0, 0, 0, 0, 0),
hmq_config => c_wrn_default_mqueue_config,
rmq_config => c_wrn_default_mqueue_config,
shared_mem_size => 8192
app_id => x"115790de",
cpu_count => 2,
cpu_memsizes => (32768, 32768, 0, 0, 0, 0, 0, 0),
hmq_config => c_mt_default_mqueue_config,
rmq_config => c_mt_default_mqueue_config,
shared_mem_size => 8192,
tpu_enable => true,
tpu_channels => 8,
tpu_buffer_size => 2048
);
--- Functions
......@@ -89,67 +96,8 @@ package wr_node_pkg is
return t_wishbone_master_in_array;
component wr_node_core is
generic (
g_config : t_wr_node_config;
g_double_core_clock : boolean := false;
g_with_rmq : boolean := true;
g_system_clock_freq : integer := 62500000;
g_with_white_rabbit : boolean := false);
port (
clk_i : in std_logic;
clk_cpu_i : in std_logic := '0';
rst_n_i : in std_logic;
sp_master_o : out t_wishbone_master_out;
sp_master_i : in t_wishbone_master_in := cc_dummy_master_in;
dp_master_o : out t_wishbone_master_out_array(0 to g_config.cpu_count-1);
dp_master_i : in t_wishbone_master_in_array(0 to g_config.cpu_count-1) := f_dummy_master_in_array(g_config.cpu_count);
ebm_master_o : out t_wishbone_master_out;
ebm_master_i : in t_wishbone_master_in := cc_dummy_master_in;
ebs_slave_o : out t_wishbone_slave_out;
ebs_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
host_slave_i : in t_wishbone_slave_in;
host_slave_o : out t_wishbone_slave_out;
clk_ref_i : in std_logic := '0';
tm_i : in t_wrn_timing_if;
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0);
host_irq_o : out std_logic;
debug_msg_irq_o : out std_logic);
end component wr_node_core;
component wr_node_core_with_etherbone is
generic (
g_config : t_wr_node_config;
g_double_core_clock : boolean := false);
port (
clk_i : in std_logic;
clk_cpu_i : in std_logic := '0';
rst_n_i : in std_logic;
rst_net_n_i : in std_logic;
sp_master_o : out t_wishbone_master_out;
sp_master_i : in t_wishbone_master_in := cc_dummy_master_in;
dp_master_o : out t_wishbone_master_out_array(0 to g_config.cpu_count-1);
dp_master_i : in t_wishbone_master_in_array(0 to g_config.cpu_count-1) := f_dummy_master_in_array(g_config.cpu_count);
wr_src_o : out t_wrf_source_out;
wr_src_i : in t_wrf_source_in;
wr_snk_o : out t_wrf_sink_out;
wr_snk_i : in t_wrf_sink_in;
eb_config_i : in t_wishbone_slave_in;
eb_config_o : out t_wishbone_slave_out;
host_slave_i : in t_wishbone_slave_in;
host_slave_o : out t_wishbone_slave_out;
host_irq_o : out std_logic;
clk_ref_i : in std_logic;
tm_i : in t_wrn_timing_if;
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0);
debug_msg_irq_o : out std_logic
);
end component wr_node_core_with_etherbone;
constant c_wr_node_sdb : t_sdb_device := (
constant c_mock_turtle_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
......@@ -163,11 +111,85 @@ package wr_node_pkg is
device_id => x"000090de",
version => x"00000001",
date => x"20141201",
name => "WR-Node-Core ")));
name => "Mock-Turtle-Core ")));
component mock_turtle_core is
generic (
-- Message Queue and CPU configuration
g_config : t_mock_turtle_config := c_default_mock_turtle_config;
-- When true, the CPUs can run with 2x the system clock. User design must
-- supply the clk_cpu_i signal which is in phase with the clk_i signal.
g_double_core_clock : boolean := false;
-- When true, the Remote Message Queue is implemented.
g_with_rmq : boolean := true;
g_use_wr_fabric : boolean := true;
-- Frequency of clk_sys_i, in Hz
g_system_clock_freq : integer := 62500000;
-- Enables/disables WR support
g_with_white_rabbit : boolean := false;
g_cpu_arch : string := "LM32"
);
port (
clk_i : in std_logic;
-- optional, 2x faster CPU core clock
clk_cpu_i : in std_logic := '0';
rst_n_i : in std_logic;
sp_master_o : out t_wishbone_master_out;
sp_master_i : in t_wishbone_master_in := cc_dummy_master_in;
end wr_node_pkg;
dp_master_o : out t_wishbone_master_out_array(0 to g_config.cpu_count-1);
dp_master_i : in t_wishbone_master_in_array(0 to g_config.cpu_count-1) := f_dummy_master_in_array(g_config.cpu_count);
package body wr_node_pkg is
rmq_src_o : out t_mt_stream_source_out;
rmq_src_i : in t_mt_stream_source_in := c_mt_dummy_source_in;
rmq_snk_o : out t_mt_stream_sink_out;
rmq_snk_i : in t_mt_stream_sink_in := c_mt_dummy_sink_in;
wr_src_o : out t_wrf_source_out;
wr_src_i : in t_wrf_source_in := c_dummy_src_in;
wr_snk_o : out t_wrf_sink_out;
wr_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
host_slave_i : in t_wishbone_slave_in;
host_slave_o : out t_wishbone_slave_out;
clk_ref_i : in std_logic := '0';
tm_i : in t_mt_timing_if;
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0) := x"00000000";
rmq_swrst_o : out std_logic;
host_irq_o : out std_logic;
debug_msg_irq_o : out std_logic
);
end component;
function f_reduce_or (x : std_logic_vector) return std_logic;
end mock_turtle_pkg;
package body mock_turtle_pkg is
function f_reduce_or (x : std_logic_vector) return std_logic is
variable rv : std_logic;
begin
rv := '0';
for n in 0 to x'length-1 loop
if(x(n) = '1') then
rv := '1';
end if;
end loop;
return rv;
end f_reduce_or;
function f_dummy_master_in_array(size : integer)
......@@ -184,4 +206,4 @@ package body wr_node_pkg is
end wr_node_pkg;
end mock_turtle_pkg;
hdl/rtl/mqueue/Manifest.py 0 → 100644
View file @ f5dbdb5e
files = [ "mt_mqueue_host.vhd",
"mt_mqueue_remote.vhd",
"mt_rmq_outgoing_slot.vhd",
"mt_rmq_incoming_slot.vhd",
"mt_mqueue_irq_unit.vhd",
"mt_mqueue_pkg.vhd",
"mt_mqueue_slot.vhd",
"mt_mqueue_remote.vhd",
"mt_mqueue_wishbone_slave.vhd",
"mt_ethernet_tx_framer.vhd",
"mt_rmq_rx_deframer.vhd",
"mt_rmq_rx_path.vhd",
"mt_rmq_tx_path.vhd",
"mt_stream_register.vhd",
"mt_udp_tx_framer.vhd",
"mt_rmq_packet_output.vhd",
"mt_wr_sink.vhd",
"mt_wr_source.vhd"];
hdl/rtl/mqueue/mt_ethernet_tx_framer.vhd 0 → 100644
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : Mock Turtle Node Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : mt_mqueue_remote.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2017-05-10
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Remote MQ implementation. Exchanges messages between CPU CBs in remote
-- nodes.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
use work.mt_mqueue_pkg.all;
use work.wr_fabric_pkg.all;
entity mt_ethernet_tx_framer is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_mt_stream_sink_in;
snk_o : out t_mt_stream_sink_out;
src_i : in t_mt_stream_source_in;
src_o : out t_mt_stream_source_out;
p_dst_mac_i : in std_logic_vector(47 downto 0);
p_ethertype_i : in std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of mt_ethernet_tx_framer is
type t_state is (IDLE, DMAC0, DMAC1, SMAC0, SMAC1, SMAC2, ETHERTYPE, PAYLOAD);
signal state : t_state;
signal d_prev : std_logic_vector(15 downto 0);
begin
p_comb : process(state, snk_i, src_i)
begin
if state = PAYLOAD then
snk_o.ready <= src_i.ready;
else
snk_o.ready <= '0';
end if;
end process;
p_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= IDLE;
src_o.valid <= '0';
else
case state is
when IDLE =>
if src_i.ready = '1' then
src_o.valid <= '0';
end if;
if snk_i.valid = '1' then
state <= DMAC0;
src_o.last <= '0';
src_o.data(15 downto 0) <= p_dst_mac_i(47 downto 32);
src_o.valid <= '1';
end if;
when DMAC0 =>
if (src_i.ready = '1') then
src_o.data(15 downto 0) <= p_dst_mac_i(31 downto 16);
src_o.valid <= '1';
state <= DMAC1;
end if;
when DMAC1 =>
if (src_i.ready = '1') then
src_o.data(15 downto 0) <= p_dst_mac_i(15 downto 0);
src_o.valid <= '1';
state <= SMAC0;
end if;
when SMAC0 =>
if (src_i.ready = '1') then
src_o.data(15 downto 0) <= (others => '0');
src_o.valid <= '1';
state <= SMAC1;
end if;
when SMAC1 =>
if (src_i.ready = '1') then
src_o.data(15 downto 0) <= (others => '0');
src_o.valid <= '1';
state <= SMAC2;
end if;
when SMAC2 =>
if (src_i.ready = '1') then
src_o.data(15 downto 0) <= (others => '0');
src_o.valid <= '1';
state <= ETHERTYPE;
end if;
when ETHERTYPE =>
if (src_i.ready = '1') then
src_o.data(15 downto 0) <= p_ethertype_i;
src_o.valid <= '1';
state <= PAYLOAD;
end if;
when PAYLOAD =>
if(src_i.ready = '1') then
src_o.data(15 downto 0) <= snk_i.data(15 downto 0);
src_o.valid <= snk_i.valid;
src_o.last <= snk_i.last;
if(snk_i.last = '1' and snk_i.valid = '1') then
state <= IDLE;
end if;
end if;
end case;
end if;
end if;
end process;
src_o.tag <= "00";
src_o.error <= '0';
end rtl;
hdl/rtl/wrnc/mqueue/wrn_mqueue_host.vhd → hdl/rtl/mqueue/mt_mqueue_host.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Node Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_mqueue_host.vhd
-- File : mt_mqueue_host.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
......@@ -41,11 +41,11 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.mt_mqueue_pkg.all;
entity wrn_mqueue_host is
entity mt_mqueue_host is
generic (
g_config : t_wrn_mqueue_config := c_wrn_default_mqueue_config
g_config : t_mt_mqueue_config := c_mt_default_mqueue_config
);
port (
......@@ -62,9 +62,9 @@ entity wrn_mqueue_host is
hmq_status_o : out std_logic_vector(15 downto 0)
);
end wrn_mqueue_host;
end mt_mqueue_host;
architecture rtl of wrn_mqueue_host is
architecture rtl of mt_mqueue_host is
signal si_incoming_in, host_incoming_in : t_slot_bus_in_array(0 to g_config.in_slot_count-1);
signal si_incoming_out, host_incoming_out : t_slot_bus_out_array(0 to g_config.in_slot_count-1);
......@@ -76,7 +76,7 @@ architecture rtl of wrn_mqueue_host is
signal hmq_status : std_logic_vector(g_config.in_slot_count-1 downto 0);
signal irq_config : t_wrn_irq_config;
signal irq_config : t_mt_irq_config;
signal tmr_div : unsigned(23 downto 0);
signal tmr_tick : std_logic;
......@@ -86,7 +86,7 @@ architecture rtl of wrn_mqueue_host is
begin -- rtl
U_SI_Wishbone_Slave : wrn_mqueue_wishbone_slave
U_SI_Wishbone_Slave : mt_mqueue_wishbone_slave
generic map (
g_with_gcr => true,
g_config => g_config)
......@@ -107,7 +107,7 @@ begin -- rtl
-- CB to Host direction (outgoing slots)
gen_outgoing_slots : for i in 0 to g_config.out_slot_count-1 generate
U_Out_SlotX : wrn_mqueue_slot
U_Out_SlotX : mt_mqueue_slot
generic map (
g_entries => g_config.out_slot_config(i).entries,
g_width => g_config.out_slot_config(i).width)
......@@ -125,7 +125,7 @@ begin -- rtl
-- Host to CB direction (incoming slots)
gen_incoming_slots : for i in 0 to g_config.in_slot_count-1 generate
U_In_SlotX : wrn_mqueue_slot
U_In_SlotX : mt_mqueue_slot
generic map (
g_entries => g_config.in_slot_config(i).entries,
g_width => g_config.in_slot_config(i).width)
......@@ -142,7 +142,7 @@ begin -- rtl
end generate gen_incoming_slots;
U_Host_Wishbone_Slave : wrn_mqueue_wishbone_slave
U_Host_Wishbone_Slave : mt_mqueue_wishbone_slave
generic map (
g_with_gcr => true,
g_config => g_config)
......
hdl/rtl/wrnc/mqueue/wrn_mqueue_irq_unit.vhd → hdl/rtl/mqueue/mt_mqueue_irq_unit.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Node Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_mqueue_irq_unit.vhd
-- File : mt_mqueue_irq_unit.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
......@@ -39,13 +39,13 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wrn_mqueue_pkg.all;
use work.mt_mqueue_pkg.all;
use work.genram_pkg.all;
entity wrn_mqueue_irq_unit is
entity mt_mqueue_irq_unit is
generic (
g_config : t_wrn_mqueue_config);
g_config : t_mt_mqueue_config);
port (
clk_i : in std_logic;
......@@ -54,19 +54,19 @@ entity wrn_mqueue_irq_unit is
incoming_status_i : t_slot_status_out_array(0 to g_config.in_slot_count-1);
outgoing_status_i : t_slot_status_out_array(0 to g_config.out_slot_count-1);
irq_config_i : t_wrn_irq_config;
irq_config_i : t_mt_irq_config;
irq_o : out std_logic
);
end wrn_mqueue_irq_unit;
end mt_mqueue_irq_unit;
architecture rtl of wrn_mqueue_irq_unit is
architecture rtl of mt_mqueue_irq_unit is
constant c_wrn_clk_freq : integer := 62500000;
constant c_mt_clk_freq : integer := 62500000;
signal tmr_div : unsigned(f_log2_size(c_wrn_clk_freq/1000+1)-1 downto 0);
signal tmr_div : unsigned(f_log2_size(c_mt_clk_freq/1000+1)-1 downto 0);
signal tmr_tick : std_logic;
signal tmr_timeout : unsigned(9 downto 0);
......@@ -101,7 +101,7 @@ begin -- rtl
tmr_div <= (others => '0');
tmr_tick <= '0';
else
if(tmr_div /= c_wrn_clk_freq/1000-1) then
if(tmr_div /= c_mt_clk_freq/1000-1) then
tmr_div <= tmr_div + 1;
tmr_tick <= '1';
else
......
hdl/rtl/wrnc/mqueue/wrn_mqueue_pkg.vhd → hdl/rtl/mqueue/mt_mqueue_pkg.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_mqueue_pkg.vhd
-- File : mt_mqueue_pkg.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2016-06-06
-- Last update: 2017-04-26
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Global package for the MQs.
-- Global package for the Message Queues
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
......@@ -38,26 +38,109 @@
library ieee;
use ieee.std_logic_1164.all;
use work.wrn_private_pkg.all;
use work.mt_private_pkg.all;
use work.wishbone_pkg.all;
package wrn_mqueue_pkg is
package mt_mqueue_pkg is
type t_wrn_mqueue_slot_config is record
constant c_rmq_data_start_offset : integer := 32;
constant c_MT_STREAM_TAG_HEADER : std_logic_vector(1 downto 0) := "00";
constant c_MT_STREAM_TAG_PAYLOAD : std_logic_vector(1 downto 0) := "01";
type t_rmq_outgoing_slot_config is record
dst_mac : std_logic_vector(47 downto 0);
src_ip : std_logic_vector(31 downto 0);
dst_ip : std_logic_vector(31 downto 0);
src_port : std_logic_vector(15 downto 0);
dst_port : std_logic_vector(15 downto 0);
ethertype : std_logic_vector(15 downto 0);
is_udp : std_logic;
payload_size : std_logic_vector(15 downto 0);
end record;
type t_rmq_incoming_slot_config is record
dst_mac : std_logic_vector(47 downto 0);
dst_ip : std_logic_vector(31 downto 0);
dst_port : std_logic_vector(15 downto 0);
ethertype : std_logic_vector(15 downto 0);
type0 : std_logic_vector(31 downto 0);
type1 : std_logic_vector(31 downto 0);
type2 : std_logic_vector(31 downto 0);
type3 : std_logic_vector(31 downto 0);
store_header : std_logic;
is_tlv : std_logic;
filter_dst_mac : std_logic;
filter_dst_ip : std_logic;
filter_dst_port : std_logic;
filter_ethertype : std_logic;
filter_udp : std_logic;
filter_type0 : std_logic;
filter_type1 : std_logic;
filter_type2 : std_logic;
filter_type3 : std_logic;
filter_raw : std_logic;
end record;
type t_rmq_rx_header is record
is_udp : std_logic;
is_raw : std_logic;
is_tlv : std_logic;
src_mac : std_logic_vector(47 downto 0);
dst_mac : std_logic_vector(47 downto 0);
ethertype : std_logic_vector(15 downto 0);
src_port : std_logic_vector(15 downto 0);
dst_port : std_logic_vector(15 downto 0);
src_ip : std_logic_vector(31 downto 0);
dst_ip : std_logic_vector(31 downto 0);
udp_length : std_logic_vector(15 downto 0);
tlv_type : std_logic_vector(31 downto 0);
tlv_size : std_logic_vector(15 downto 0);
end record;
type t_mt_stream_sink_in is record
data : std_logic_vector(31 downto 0);
tag : std_logic_vector(1 downto 0);
valid : std_logic;
last : std_logic;
error : std_logic;
end record;
type t_mt_stream_sink_out is record
ready : std_logic;
end record;
subtype t_mt_stream_source_in is t_mt_stream_sink_out;
subtype t_mt_stream_source_out is t_mt_stream_sink_in;
constant c_mt_dummy_source_in : t_mt_stream_sink_out := ( ready => '0' );
constant c_mt_dummy_sink_in : t_mt_stream_sink_in :=
(x"00000000", "00", '0', '0', '0');
type t_mt_stream_sink_in_array is array(integer range<> ) of t_mt_stream_sink_in;
type t_mt_stream_sink_out_array is array(integer range<> ) of t_mt_stream_sink_out;
type t_rmq_outgoing_slot_config_array is array(integer range<> ) of t_rmq_outgoing_slot_config;
type t_mt_mqueue_slot_config is record
width : integer;
entries : integer;
end record;
type t_wrn_mqueue_slot_config_array is array(integer range<>) of t_wrn_mqueue_slot_config;
type t_mt_mqueue_slot_config_array is array(integer range<>) of t_mt_mqueue_slot_config;
type t_wrn_mqueue_config is record
type t_mt_mqueue_config is record
in_slot_count : integer;
out_slot_count : integer;
in_slot_config : t_wrn_mqueue_slot_config_array(0 to 15);
out_slot_config : t_wrn_mqueue_slot_config_array(0 to 15);
in_slot_config : t_mt_mqueue_slot_config_array(0 to 15);
out_slot_config : t_mt_mqueue_slot_config_array(0 to 15);
end record;
constant c_wrn_default_mqueue_config : t_wrn_mqueue_config :=
constant c_mt_default_mqueue_config : t_mt_mqueue_config :=
(2,
2,
((64, 128), (64, 16),
......@@ -69,7 +152,7 @@ package wrn_mqueue_pkg is
(0, 0), (0, 0),
(0, 0), (0, 0)),
((64, 128), (64, 16),
((128, 16), (128, 16),
(0, 0), (0, 0),
(0, 0), (0, 0),
(0, 0), (0, 0),
......@@ -79,10 +162,10 @@ package wrn_mqueue_pkg is
(0, 0), (0, 0)));
type t_slot_bus_in is record
sel : std_logic;
dat : std_logic_vector(31 downto 0);
adr : std_logic_vector(9 downto 0);
we : std_logic;
sel : std_logic;
dat : std_logic_vector(31 downto 0);
adr : std_logic_vector(9 downto 0);
we : std_logic;
wmask : std_logic_vector(3 downto 0);
end record;
......@@ -94,17 +177,17 @@ package wrn_mqueue_pkg is
full : std_logic;
empty : std_logic;
count : std_logic_vector(7 downto 0);
current_size : std_logic_vector(7 downto 0);
current_size : std_logic_vector(15 downto 0);
ready : std_logic;
commit_mask : std_logic;
commit_mask : std_logic;
end record;
type t_slot_bus_in_array is array(integer range <>) of t_slot_bus_in;
type t_slot_bus_out_array is array(integer range <>) of t_slot_bus_out;
type t_slot_status_out_array is array(integer range <>) of t_slot_status_out;
type t_wrn_irq_config is record
type t_mt_irq_config is record
mask_in : std_logic_vector(15 downto 0);
mask_out : std_logic_vector(15 downto 0);
threshold : std_logic_vector(7 downto 0);
......@@ -112,18 +195,18 @@ package wrn_mqueue_pkg is
end record;
constant c_dummy_status_out : t_slot_status_out := (
'0', '0', x"00", x"00", '0', '0');
'0', '0', x"00", x"0000", '0', '0');
constant c_dummy_slot_bus_in : t_slot_bus_out := (
dat => x"00000000"
);
);
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
component wrn_mqueue_slot
component mt_mqueue_slot
generic (
g_entries : integer;
g_width : integer);
......@@ -135,13 +218,14 @@ package wrn_mqueue_pkg is
inb_o : out t_slot_bus_out;
outb_i : in t_slot_bus_in;
outb_o : out t_slot_bus_out;
out_discard_i : in std_logic := '0');
out_discard_i : in std_logic := '0';
rmq_swrst_o : out std_logic);
end component;
component wrn_mqueue_wishbone_slave
component mt_mqueue_wishbone_slave
generic (
g_with_gcr : boolean;
g_config : t_wrn_mqueue_config);
g_config : t_mt_mqueue_config);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -153,12 +237,12 @@ package wrn_mqueue_pkg is
outgoing_i : in t_slot_bus_out_array(0 to g_config.out_slot_count-1);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irq_config_o : out t_wrn_irq_config);
irq_config_o : out t_mt_irq_config);
end component;
component wrn_mqueue_irq_unit
component mt_mqueue_irq_unit
generic (
g_config : t_wrn_mqueue_config);
g_config : t_mt_mqueue_config);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -168,5 +252,5 @@ package wrn_mqueue_pkg is
end component;
end wrn_mqueue_pkg;
end mt_mqueue_pkg;
hdl/rtl/mqueue/mt_mqueue_remote.vhd 0 → 100644
View file @ f5dbdb5e
This diff is collapsed.
hdl/rtl/wrnc/mqueue/wrn_mqueue_slot.vhd → hdl/rtl/mqueue/mt_mqueue_slot.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_mqueue_slot.vhd
-- File : mt_mqueue_slot.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2016-09-19
-- Last update: 2017-05-15
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -40,9 +40,9 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.mt_mqueue_pkg.all;
entity wrn_mqueue_slot is
entity mt_mqueue_slot is
generic (
g_entries : integer;
......@@ -60,12 +60,14 @@ entity wrn_mqueue_slot is
outb_i : in t_slot_bus_in;
outb_o : out t_slot_bus_out;
rmq_swrst_o : out std_logic;
out_discard_i : in std_logic := '0'
);
end wrn_mqueue_slot;
end mt_mqueue_slot;
architecture rtl of wrn_mqueue_slot is
architecture rtl of mt_mqueue_slot is
constant c_counter_bits : integer := f_log2_size(g_entries);
constant c_slot_offset_bits : integer := f_log2_size(g_width);
......@@ -108,6 +110,8 @@ architecture rtl of wrn_mqueue_slot is
constant c_addr_command : integer := 0;
constant c_addr_status : integer := 1;
signal n_words_last : std_logic_vector(7 downto 0);
signal purge_int : std_logic;
begin -- rtl
......@@ -145,6 +149,18 @@ begin -- rtl
out_discard <= out_discard_i or (out_cmd_wr and outb_i.dat(27));
out_purge <= out_cmd_wr and outb_i.dat(25);
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
purge_int <= '0';
else
purge_int <= out_purge or in_purge;
end if;
end if;
end process;
p_read_status : process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -215,7 +231,7 @@ begin -- rtl
p_write_side : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
if rst_n_i = '0' or purge_int = '1' then
wr_state <= IDLE;
stat_o.commit_mask <= '0';
else
......@@ -260,7 +276,7 @@ begin -- rtl
p_read_side : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
if rst_n_i = '0' or purge_int = '1' then
stat_o.ready <= '0';
rd_state <= IDLE;
else
......@@ -272,7 +288,7 @@ begin -- rtl
when READ_SIZE =>
n_words_last <= mem_rdata_out(7 downto 0);
stat_o.current_size <= mem_rdata_out(7 downto 0);
stat_o.current_size <= x"00" & mem_rdata_out(7 downto 0);
stat_o.ready <= '1';
rd_state <= WAIT_DISCARD;
......@@ -292,7 +308,7 @@ begin -- rtl
p_counters : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' or in_purge = '1' or out_purge = '1' then
if rst_n_i = '0' or purge_int = '1' then
rd_ptr <= (others => '0');
wr_ptr <= (others => '0');
occupied <= (others => '0');
......
hdl/rtl/wrnc/mqueue/wrn_mqueue_wishbone_slave.vhd → hdl/rtl/mqueue/mt_mqueue_wishbone_slave.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Node Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_mqueue_wishbone_slave.vhd
-- File : mt_mqueue_wishbone_slave.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2016-06-06
-- Last update: 2016-11-28
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -40,13 +40,13 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.mt_mqueue_pkg.all;
entity wrn_mqueue_wishbone_slave is
entity mt_mqueue_wishbone_slave is
generic (
g_with_gcr : boolean;
g_config : t_wrn_mqueue_config
g_config : t_mt_mqueue_config
);
port (
clk_i : in std_logic;
......@@ -64,12 +64,13 @@ entity wrn_mqueue_wishbone_slave is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irq_config_o : out t_wrn_irq_config
irq_config_o : out t_mt_irq_config
);
end wrn_mqueue_wishbone_slave;
end mt_mqueue_wishbone_slave;
architecture rtl of wrn_mqueue_wishbone_slave is
architecture rtl of mt_mqueue_wishbone_slave is
constant c_gcr_slot_count : std_logic_vector(3 downto 0) := x"0";
constant c_gcr_slot_status : std_logic_vector(3 downto 0) := x"1";
......@@ -86,7 +87,7 @@ architecture rtl of wrn_mqueue_wishbone_slave is
signal gcr_rd_data : std_logic_vector(31 downto 0) := x"00000000";
signal irq_config : t_wrn_irq_config;
signal irq_config : t_mt_irq_config;
begin -- rtl
......
hdl/rtl/mqueue/mt_rmq_incoming_slot.vhd 0 → 100644
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hdl/rtl/mqueue/mt_rmq_outgoing_slot.vhd 0 → 100644
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hdl/rtl/mqueue/mt_rmq_packet_output.vhd 0 → 100644
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : Mock Turtle Node Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : mt_rmq_packet_output.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2017-05-11
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Packet assembler for the TX path of the RMQ.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.mock_turtle_pkg.all;
use work.mt_mqueue_pkg.all;
use work.genram_pkg.all;
entity mt_rmq_packet_output is
generic (
g_config : t_mt_mqueue_config);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
rmq_swrst_i : in std_logic;
snks_i : in t_mt_stream_sink_in_array(0 to g_config.out_slot_count-1);
snks_o : out t_mt_stream_sink_out_array(0 to g_config.out_slot_count-1);
cfgs_i : in t_rmq_outgoing_slot_config_array(0 to g_config.out_slot_count-1);
tx_req_i : in std_logic_vector(g_config.out_slot_count-1 downto 0);
tx_grant_o : out std_logic_vector(g_config.out_slot_count-1 downto 0);
src_o : out t_mt_stream_source_out;
src_i : in t_mt_stream_source_in;
debug_o : out std_logic_vector(31 downto 0)
);
end mt_rmq_packet_output;
architecture rtl of mt_rmq_packet_output is
component mt_rmq_tx_path is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_mt_stream_sink_in;
snk_o : out t_mt_stream_sink_out;
src_i : in t_mt_stream_source_in;
src_o : out t_mt_stream_source_out;
p_use_udp_i : std_logic;
p_dst_mac_i : in std_logic_vector(47 downto 0);
p_ethertype_i : in std_logic_vector(15 downto 0);
p_src_port_i : in std_logic_vector(15 downto 0);
p_dst_port_i : in std_logic_vector(15 downto 0);
p_src_ip_i : in std_logic_vector(31 downto 0);
p_dst_ip_i : in std_logic_vector(31 downto 0);
p_payload_words_i : in std_logic_vector(15 downto 0));
end component mt_rmq_tx_path;
function f_prio_encode (x : std_logic_vector) return std_logic_vector is
variable rv : std_logic_vector(f_log2_size(x'length) -1 downto 0);
begin
rv := (others => '0');
for i in 0 to x'length-1 loop
if x(i) = '1' then
rv := std_logic_vector(to_unsigned(i, f_log2_size(x'length)));
return rv;
end if;
end loop; -- i
return rv;
end function;
function f_onehot_decode (x : integer; size : integer) return std_logic_vector is
variable rv : std_logic_vector(size-1 downto 0);
begin
rv := (others => '0');
rv(x) := '1';
return rv;
end function;
type t_arb_state is (ARB_IDLE, ARB_SEND);
constant c_slot_index_size : integer := f_log2_size(g_config.out_slot_count);
signal arb_state : t_arb_state;
signal slot_ready : std_logic;
signal slot_sel : std_logic_vector(c_slot_index_size-1 downto 0);
signal slot_done : std_logic;
signal slot_req : std_logic_vector(g_config.out_slot_count-1 downto 0);
signal slot_in : t_slot_bus_out;
signal slot_stat : t_slot_status_out;
signal slot_out : t_slot_bus_in;
signal slot_discard : std_logic;
signal rst_n_int : std_logic;
signal src_out : t_mt_stream_source_out;
signal src_in : t_mt_stream_source_in;
signal config : t_rmq_outgoing_slot_config;
begin -- rtl
process(clk_i)
begin
if rising_edge(clk_i) then
rst_n_int <= rst_n_i and not rmq_swrst_i;
end if;
end process;
gen_slot_status : for i in 0 to g_config.out_slot_count-1 generate
slot_req(i) <= tx_req_i(i);
end generate gen_slot_status;
p_arbitrate_slots : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_int = '0' then
arb_state <= ARB_IDLE;
slot_ready <= '0';
slot_sel <= (others => '0');
tx_grant_o <= (others => '0');
else
case arb_state is
when ARB_IDLE =>
tx_grant_o <= (others => '0');
if unsigned(slot_req) /= 0 then
slot_sel <= f_prio_encode(slot_req);
slot_ready <= '1';
arb_state <= ARB_SEND;
end if;
when ARB_SEND =>
tx_grant_o <= f_onehot_decode(to_integer(unsigned(slot_sel)), tx_grant_o'length);
if(slot_done = '1') then
slot_ready <= '0';
arb_state <= ARB_IDLE;
end if;
end case;
end if;
end if;
end process;
p_pick_slot : process(snks_i, cfgs_i, slot_sel, src_in)
variable idx : integer;
variable tmp : std_logic_vector(g_config.out_slot_count-1 downto 0);
begin
idx := to_integer(unsigned(slot_sel));
src_out <= snks_i(idx);
config <= cfgs_i(idx);
end process;
gen_snk_outs: for i in 0 to g_config.out_slot_count-1 generate
snks_o(i) <= src_in;
end generate gen_snk_outs;
slot_done <= src_out.valid and src_in.ready and src_out.last;
U_TX_Path : mt_rmq_tx_path
port map (
clk_i => clk_i,
rst_n_i => rst_n_int,
snk_i => src_out,
snk_o => src_in,
src_i => src_i,
src_o => src_o,
p_use_udp_i => config.is_udp,
p_dst_mac_i => config.dst_mac,
p_ethertype_i => config.ethertype,
p_src_port_i => config.src_port,
p_dst_port_i => config.dst_port,
p_src_ip_i => config.src_ip,
p_dst_ip_i => config.dst_ip,
p_payload_words_i => config.payload_size);
end rtl;
hdl/rtl/mqueue/mt_rmq_rx_deframer.vhd 0 → 100644
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hdl/rtl/mqueue/mt_rmq_rx_path.vhd 0 → 100644
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hdl/rtl/mqueue/mt_rmq_rx_tlv_demux.vhd 0 → 100644
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hdl/rtl/mqueue/mt_rmq_tx_path.vhd 0 → 100644
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hdl/rtl/mqueue/mt_udp_tx_framer.vhd 0 → 100644
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hdl/rtl/mqueue/mt_wr_sink.vhd 0 → 100644
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hdl/rtl/mqueue/mt_wr_source.vhd 0 → 100644
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hdl/rtl/mt_config_rom.vhd 0 → 100644
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hdl/rtl/wrnc/wb_remapper.vhd → hdl/rtl/mt_wb_remapper.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Node Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wb_remapper.vhd
-- Author : Tomasz Włostowski
......@@ -42,7 +42,7 @@ use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
entity wb_remapper is
entity mt_wb_remapper is
generic (
g_num_ranges : integer := 1;
g_base_in : t_wishbone_address_array;
......@@ -56,9 +56,9 @@ entity wb_remapper is
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out
);
end wb_remapper;
end mt_wb_remapper;
architecture rtl of wb_remapper is
architecture rtl of mt_wb_remapper is
begin
......
hdl/rtl/smem/Manifest.py 0 → 100644
View file @ f5dbdb5e
files = ["mt_shared_mem.vhd"]
\ No newline at end of file
hdl/rtl/wrnc/smem/wrn_shared_mem.vhd → hdl/rtl/smem/mt_shared_mem.vhd
View file @ f5dbdb5e
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-- Title : Mock Turtle Node Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- File : wrn_shared_mem.vhd
-- File : mt_shared_mem.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
......@@ -12,7 +12,7 @@
-------------------------------------------------------------------------------
-- Description:
--
-- WR Node CPU Shared Memory block.
-- Mock Turtle CPU Shared Memory block.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
......@@ -43,7 +43,7 @@ use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
entity wrn_shared_mem is
entity mt_shared_mem is
generic (
g_size : integer := 16384);
......@@ -55,9 +55,9 @@ entity wrn_shared_mem is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end wrn_shared_mem;
end mt_shared_mem;
architecture rtl of wrn_shared_mem is
architecture rtl of mt_shared_mem is
constant c_RANGE_DIRECT : std_logic_vector(2 downto 0) := "000";
constant c_RANGE_ADD : std_logic_vector(2 downto 0) := "001";
......
hdl/rtl/wrnc/Manifest.py deleted 100644 → 0
View file @ 04fa428e
files = [ "wr_node_core.vhd",
"wr_node_pkg.vhd",
"wr_node_core_with_etherbone.vhd",
"wb_remapper.vhd" ]
modules = {
"local" : [ "cpu", "mqueue", "smem" ] }
hdl/rtl/wrnc/cpu/Manifest.py deleted 100644 → 0
View file @ 04fa428e
files = ["wrn_cpu_cb.vhd",
"wrn_cpu_csr_wbgen2_pkg.vhd",
"wrn_cpu_csr_wb.vhd",
"wrn_cpu_iram.vhd",
"wrn_cpu_lr_wbgen2_pkg.vhd",
"wrn_cpu_lr_wb.vhd",
"wrn_lm32_wrapper.vhd",
"wrn_private_pkg.vhd"];
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#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wrn_cpu_csr.html -V wrn_cpu_csr_wb.vhd -p wrn_cpu_csr_wbgen2_pkg.vhd --cstyle defines -C wrn_cpu_csr.h --hstyle record --lang vhdl -K wrn_cpu_csr_regs.vh wrn_cpu_csr.wb
wbgen2 -D ./doc/wrn_cpu_lr.html -V wrn_cpu_lr_wb.vhd -p wrn_cpu_lr_wbgen2_pkg.vhd --cstyle defines -C wrn_cpu_lr.h --hstyle record --lang vhdl wrn_cpu_lr.wb
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files = [ "wrn_mqueue_host.vhd",
"wrn_mqueue_remote.vhd",
"wrn_mqueue_etherbone_output.vhd",
"wrn_mqueue_irq_unit.vhd",
"wrn_mqueue_pkg.vhd",
"wrn_mqueue_slot.vhd",
"wrn_eb_cycle_gen.vhd",
"wrn_mqueue_wishbone_slave.vhd" ];
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files = ["wrn_shared_mem.vhd"]
\ No newline at end of file
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OBJS = debug-test.o
OUTPUT = debug-test
include ../common/wrnode.mk
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`define ADDR_TREVGEN_RM_NEXT_TICK 5'h0
`define ADDR_TREVGEN_LC_NEXT_TICK 5'h4
`define ADDR_TREVGEN_RM_TREV 5'h8
`define ADDR_TREVGEN_LC_TREV 5'hc
`define ADDR_TREVGEN_STROBE_P 5'h10
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