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Mock Turtle
Commits
fdcd610a
Commit
fdcd610a
authored
Mar 19, 2018
by
Dimitris Lampridis
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hdl: eradicate etherbone from MockTurtle
parent
03248832
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5 changed files
with
3 additions
and
20 deletions
+3
-20
.gitmodules
.gitmodules
+0
-3
etherbone-core
hdl/ip_cores/etherbone-core
+0
-1
mock_turtle_core.vhd
hdl/rtl/mock_turtle_core.vhd
+2
-8
mt_mqueue_remote.vhd
hdl/rtl/mqueue/mt_mqueue_remote.vhd
+1
-4
wave.do
hdl/testbench/mock_turtle_core/wave.do
+0
-4
No files found.
.gitmodules
View file @
fdcd610a
...
...
@@ -4,9 +4,6 @@
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
...
...
etherbone-core
@
23903f61
Subproject commit 23903f6123b24b96895d4c04a6fcb237b14fb55f
hdl/rtl/mock_turtle_core.vhd
View file @
fdcd610a
...
...
@@ -244,7 +244,7 @@ architecture rtl of mock_turtle_core is
signal
hac_master_in
:
t_wishbone_master_in_array
(
c_hac_wishbone_masters
-1
downto
0
);
constant
c_si_wishbone_masters
:
integer
:
=
5
;
constant
c_si_wishbone_slaves
:
integer
:
=
g_config
.
cpu_count
+
2
;
constant
c_si_wishbone_slaves
:
integer
:
=
g_config
.
cpu_count
+
1
;
constant
c_si_master_hmq
:
integer
:
=
0
;
constant
c_si_master_rmq
:
integer
:
=
1
;
constant
c_si_master_smem
:
integer
:
=
2
;
...
...
@@ -252,8 +252,7 @@ architecture rtl of mock_turtle_core is
constant
c_si_master_sp
:
integer
:
=
4
;
constant
c_si_slave_hac
:
integer
:
=
0
;
constant
c_si_slave_ebs
:
integer
:
=
1
;
constant
c_si_slave_cpu0
:
integer
:
=
2
;
constant
c_si_slave_cpu0
:
integer
:
=
1
;
constant
c_si_address
:
t_wishbone_address_array
(
c_si_wishbone_masters
-1
downto
0
)
:
=
(
c_si_master_hmq
=>
x"00000000"
,
-- Host MQ
...
...
@@ -424,11 +423,6 @@ begin -- rtl
hac_master_in
(
c_hac_master_si
)
<=
si_slave_out
(
c_si_slave_hac
);
si_slave_in
(
c_si_slave_ebs
)
<=
cc_dummy_slave_in
;
-- fixme: bypass for EB slave
-- si_slave_in(c_si_slave_ebs) <= ebs_slave_i;
-- ebs_slave_o <= si_slave_out(c_si_slave_ebs);
U_CPU_CSR
:
entity
work
.
mt_cpu_csr_wb_slave
port
map
(
...
...
hdl/rtl/mqueue/mt_mqueue_remote.vhd
View file @
fdcd610a
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2018-03-1
3
-- Last update: 2018-03-1
9
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -68,7 +68,6 @@ entity mt_mqueue_remote is
wr_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wr_src_o
:
out
t_wrf_source_out
;
-- software reset for etherbone
rmq_swrst_o
:
out
std_logic
;
rmq_status_o
:
out
std_logic_vector
(
15
downto
0
);
...
...
@@ -236,7 +235,6 @@ begin -- rtl
slave_i
=>
si_slave_i
,
slave_o
=>
si_slave_o
);
-- CB to Etherbone direction (outgoing slots)
gen_outgoing_slots
:
for
i
in
0
to
g_config
.
out_slot_count
-1
generate
U_Out_SlotX
:
mt_rmq_outgoing_slot
...
...
@@ -258,7 +256,6 @@ begin -- rtl
end
generate
gen_outgoing_slots
;
-- Host to CB direction (incoming slots)
gen_incoming_slots
:
for
i
in
0
to
g_config
.
in_slot_count
-1
generate
U_In_SlotX
:
mt_rmq_incoming_slot
...
...
hdl/testbench/mock_turtle_core/wave.do
View file @
fdcd610a
...
...
@@ -7,10 +7,6 @@ add wave -noupdate -group Top /main/DUT/sp_master_o
add wave -noupdate -group Top /main/DUT/sp_master_i
add wave -noupdate -group Top /main/DUT/dp_master_o
add wave -noupdate -group Top /main/DUT/dp_master_i
add wave -noupdate -group Top /main/DUT/ebm_master_o
add wave -noupdate -group Top /main/DUT/ebm_master_i
add wave -noupdate -group Top /main/DUT/ebs_slave_o
add wave -noupdate -group Top /main/DUT/ebs_slave_i
add wave -noupdate -group Top /main/DUT/host_slave_i
add wave -noupdate -group Top /main/DUT/host_slave_o
add wave -noupdate -group Top /main/DUT/clk_ref_i
...
...
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