The Mock Turtle Core
Before you start
The Mock Turtle was initially called The White Rabbit Node Core. We are in the progress of renaming the design and moving it to the repositories in this OHWR project. All the sources can be currently found in the* WR Node Core Project The WRNC project will be progressively moved to the MT project.
Project description
The Mock Turtle (MT) Core is an HDL core of a generic distributed control system node, based on multiple deterministic CPU cores where the users can run any sort of hard real time applications.
White Rabbit Network can be used as the means of communication (through Etherbone protocol) and synchronization, although it is not mandatory.
node_overview.jpg
General concept of the MT Core*
The introductory presentation provides more information on the MT design and explains why we designed it (note the presentation refers to the old name of the MT, the White Rabbit Node Core that we changed as the project is WR-agnostic).
In layman's terms: most of the things we do in bare VHDL or Verilog can be done by a program written in C. MT just provides a simple way of running such programs and interfacing them to your FPGA cores and the host software.
Features
- Up to 8 CPU cores:
- Execute any code the user wishes. Code can be loaded, started and stopped on request.
- User applications are written in bare metal C (using the standard GNU tool set). Assembly may be used if necessary.
- Communication between CPU cores through a dedicated shared memory.
- Have no interrupts to ensure deterministic execution timing.
- Keep code and data in a private memory to ensure deterministic execution timing.
- Application-specific cores and hardware:
- The cores are accessed by the CPUs through a dedicated Wishbone bus and may interface with external hardware of any sort.
- Shared Memory for inter-core communication and process synchronization primitives (mutexes, semaphores, etc.).
- Host Message Queue (HMQ) for exchanging messages between the CPUs and the host system. The HMQ is the primary means of communication between the node and the host software (e.g. FESA). Direct access to shared CPU memory or other resources may be allowed, depending on the needs of the particular application.
- Optional White Rabbit support:
- Remote Message Queue (RMQ), which exchanges messages with remote nodes in the WR network.
- The Etherbone protocol, developed by GSI, is used as the transport layer.
- International Atomic Time (TAI) provided by White Rabbit. The CPUs and user cores in each node in the network have direct access to TAI, with a granularity of 8 nanoseconds. The system clock of the CPUs may be synchronous to the WR reference frequency if necessary.
Project information
- Documentation:
- MT Introduction (slides)
- MT Technical Specification
- Getting-Started - sample 'hello, world'-style application.
- Software
- Developing Distributed Hard-Real Time Software Systems Using FPGAs and Soft Cores, T. Wlostowski et al., 2016
Users
Contacts
- Tomasz Włostowski (CERN)
Status
Date | Event |
19-05-2014 | Initial LIST node design available. |
14-05-2014 | Technical specification available. |
13-05-2014 | Initial VHDL version committed. Capable of communicating with the host and sending Etherbone messages. |
18-04-2014 | First ideas, creation of wr-node-core project. |
08-04-2014 | White Rabbit Node Core Technical Specification document written. |
01-10-2014 | Initial version of gateware & realtime. |
01-02-2015 | Initial version of Node Core & WR Trigger Distribution drivers. |
13 September 2016