The project is an MCH tongue 2 board, which is responsible for clock
generation. In addition to MTCA.4 compatible clock distribution, it is
equipped with timing receiver compatible with WhiteRabbit protocol.
Recovered clock can be used as a source of the clock for individual
slots. All event and timing information are accessible via Ethernet
protocol or PCIe link to the switch on tongue 3.
General board description
The board is divided into two functional parts:
2. Clock/Trigger distribution
The block diagram is presented
WhiteRabbit part consists of digital PLL implementation (DAC + VCOX +
FPGA), which together with firmware blocks executes white rabbit
Clock and Trigger distribution part generates all needed back-plane
clocks and triggers. It is controlled from FPGA.
In addition there is optional DDR3 memory if some more complex functions
will be used (including embedded micro-controller).
The Spartan 6 XC6SLX45T-3FGG484C chip has been selected based on SPEC
and CuteWR OpenHardware projects.
There are several power supplies needed on the board.
- 1.5 V + VREF generation circuit
For Spartan 6:
- 1.2 V for VCCINT
- 2.5 V for VCCAUX
- 3.3 V for VCCO ( for IO components)
- 2.5 V for VCCO ( for IO components / can be the same as for VCCAUX)
- 1.2 V for GTP (generated by local high performance LDO)
WhiteRabbit clocking resources:
- 3.3V with local cleaners implemented as LC filter
For the purpose of power supply distribution two DUAL DC/DC converters
will be used LTM4619 (http://www.linear.com/product/LTM4619). They will
provide 1.2V, 1.5V, 2.5V and 3.3V @ 4A each. 1.5V is optional depending
on DDR3 memory usage.
All power supplies can be configured either as ON or OFF by default.
Serial I2C IO expander is placed on the board for additional control -
the board can be shut down remotely. All clock outputs and triggers to
the back plane are in 'Z' state until request for activation comes. I2C
IO expander must be powered from some kind of Management Power.
Additionally some unique ID chip must be placed on board to provide
serial id and MAC address for the unit.
If possible in addition to I2C some faster interface should be foreseen
for firmware update (for example SPI). If not possible I2C can be used
to boot the board. It should be possible to boot the board even if FPGA
is not initially programmed. Selection of active firmware bank is
possible via I2C and FPGA booting can be externally triggered. Also
Config OK (DONE pin) signal can be read from the board.