
project -new

#project files
#set my_project_dir [get_env MY_PROJECT]
#puts $::argv0
set my_project_dir [ file dirname [ file normalize [ info script ] ] ]
puts $my_project_dir

add_file -vhdl -lib work "$my_project_dir/../src/dualram_512x8.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_package.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_dualram_512x8_clka_rd_clkb_wr.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_cons_bytes_processor.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_cons_outcome.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_consumption.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_rx_deglitcher.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_decr_counter.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_crc.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_rx_deserializer.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_incr_counter.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_rx_osc.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_fd_receiver.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_tx_osc.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_tx_serializer.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_fd_transmitter.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_model_constr_decoder.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_prod_bytes_retriever.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_prod_permit.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_status_bytes_gen.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_production.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_reset_unit.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_wb_controller.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_prod_data_lgth_calc.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_engine_control.vhd"
add_file -vhdl -lib work "$my_project_dir/../src/wf_jtag_controller.vhd"
add_file -vhdl -lib work "$my_project_dir/../top/nanofip.vhd"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology ProASIC3
set_option -part A3P400
set_option -package PQFP208
set_option -speed_grade Std

#compilation/mapping options
set_option -top_module "work.nanofip"

# mapper_options
set_option -frequency 40.000000

# Actel 400K
#set_option -run_prop_extract 1
set_option -disable_io_insertion 0


set_option -maxfan 10
set_option -maxfan_hard 1 
set_option -retiming 0
set_option -resource_sharing 1

set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1


# Actel 500K
#set_option -globalthreshold 50

# Compiler Options



#set result format/file last
project -result_file "$my_project_dir/nanofip.edn"

#design plan options
set_option -nfilter_user_path ""
impl -active "synthesis"


# ###################
# Constraints file
# ##################
add_file -constraint "$my_project_dir/synplify_constraints.sdc"


project -run

