# Microsemi Tcl Script
# libero
# Date: Wed Jul 26 13:49:53 2023
# Directory /home/kblantos/projects/nanofip-gateware/syn
# File /home/kblantos/projects/nanofip-gateware/syn/exported.tcl


new_project \
	-location {./nanofip} \
	-name {nanofip} \
	-project_description {} \
	-block_mode 0 \
	-standalone_peripheral_initialization 0 \
	-instantiate_in_smartdesign 1 \
	-use_enhanced_constraint_flow 0 \
	-hdl {VHDL} \
	-family {ProASIC3} \
	-die {A3P400} \
	-package {208 PQFP} \
	-speed {STD} \
	-die_voltage {1.5} \
	-part_range {COM} \
	-adv_options {IO_DEFT_STD:LVTTL} \
	-adv_options {RESTRICTPROBEPINS:1} \
	-adv_options {RESTRICTSPIPINS:0} \
	-adv_options {TEMPR:IND} \
	-adv_options {VCCI_1.5_VOLTR:COM} \
	-adv_options {VCCI_1.8_VOLTR:COM} \
	-adv_options {VCCI_2.5_VOLTR:COM} \
	-adv_options {VCCI_3.3_VOLTR:COM} \
	-adv_options {VOLTR:IND} 

import_files \
         -convert_EDN_to_HDL 0 \
         -hdl_source {../src/dualram_512x8.vhd} \
         -hdl_source {../src/wf_cons_bytes_processor.vhd} \
         -hdl_source {../src/wf_cons_outcome.vhd} \
         -hdl_source {../src/wf_consumption.vhd} \
         -hdl_source {../src/wf_crc.vhd} \
         -hdl_source {../src/wf_decr_counter.vhd} \
         -hdl_source {../src/wf_dualram_512x8_clka_rd_clkb_wr.vhd} \
         -hdl_source {../src/wf_engine_control.vhd} \
         -hdl_source {../src/wf_fd_receiver.vhd} \
         -hdl_source {../src/wf_fd_transmitter.vhd} \
         -hdl_source {../src/wf_incr_counter.vhd} \
         -hdl_source {../src/wf_jtag_controller.vhd} \
         -hdl_source {../src/wf_model_constr_decoder.vhd} \
         -hdl_source {../src/wf_package.vhd} \
         -hdl_source {../src/wf_prod_bytes_retriever.vhd} \
         -hdl_source {../src/wf_prod_data_lgth_calc.vhd} \
         -hdl_source {../src/wf_prod_permit.vhd} \
         -hdl_source {../src/wf_production.vhd} \
         -hdl_source {../src/wf_reset_unit.vhd} \
         -hdl_source {../src/wf_rx_deglitcher.vhd} \
         -hdl_source {../src/wf_rx_deserializer.vhd} \
         -hdl_source {../src/wf_rx_osc.vhd} \
         -hdl_source {../src/wf_status_bytes_gen.vhd} \
         -hdl_source {../src/wf_tx_osc.vhd} \
         -hdl_source {../src/wf_tx_serializer.vhd} \
         -hdl_source {../src/wf_wb_controller.vhd} \
         -hdl_source {../top/nanofip.vhd}

create_links \
         -convert_EDN_to_HDL 0 \
         -pdc {./Designer_Synpl_Pinout.pdc} \
         -sdc {./Synplify_Constraints.sdc} \
         -sdc {./Designer_Synpl_TimeConstr.sdc} 

save_project

set_root -module {nanofip::work::nanofip} 

organize_tool_files -tool {SYNTHESIZE} \
	-file Designer_Synpl_Pinout.pdc \
	-file Synplify_Constraints.sdc \
	-file Designer_Synpl_TimeConstr.sdc \
	-module {nanofip::work} \
	-input_type {constraint}

organize_tool_files -tool {COMPILE} \
	-file {./Designer_Synpl_Pinout.pdc} \
	-file {./Designer_Synpl_TimeConstr.sdc} \
	-file {./Synplify_Constraints.sdc} \
	-module {nanofip::work::nanofip} \
	-input_type {constraint} 

update_and_run_tool -name {PLACEROUTE} 
run_tool -name {VERIFYTIMING}
run_tool -name {EXPORTPROGRAMMINGFILE} 
run_tool -name {EXPORTPROGRAMMINGFILE} 

