wf_rx_deglitcher.vhd 9.19 KB
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--_________________________________________________________________________________________________
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--                                                                                                |
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--                                         |The nanoFIP|                                          |
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--                                                                                                |
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--                                         CERN,BE/CO-HT                                          |
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--________________________________________________________________________________________________|
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---------------------------------------------------------------------------------------------------
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--                                                                                                |
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--                                        wf_rx_deglitcher                                        |
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--                                                                                                |
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---------------------------------------------------------------------------------------------------
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-- File         wf_rx_deglitcher.vhd                                                              |
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--                                                                                                |
-- Description  The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD.           |
--              It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.    |
--                                                                                                |
-- Authors      Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             |
--              Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)                                 |
-- Date         14/02/2011                                                                        |
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---------------------------------------------------------------------------------------------------

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---------------------------------------------------------------------------------------------------
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--                                      SOLDERPAD LICENSE                                         |
--                                   Copyright CERN 2014-2018                                     |
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--                              ------------------------------------                              |
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-- Copyright and related rights are licensed under the Solderpad Hardware License, Version 2.0    |
-- (the "License"); you may not use this file except in compliance with the License.              |
-- You may obtain a copy of the License at http://solderpad.org/licenses/SHL-2.0.                 |
-- Unless required by applicable law or agreed to in writing, software, hardware and materials    |
-- distributed under this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR       |
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language   |
-- governing permissions and limitations under the License.                                       |
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---------------------------------------------------------------------------------------------------



--=================================================================================================
--                                       Libraries & Packages
--=================================================================================================

-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all;    -- conversion functions
-- Specific library
library work;
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use work.WF_PACKAGE.all;     -- definitions of types, constants, entities
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--=================================================================================================
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--                             Entity declaration for wf_rx_deglitcher
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--=================================================================================================
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entity wf_rx_deglitcher is port(
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  -- INPUTS
    -- nanoFIP User Interface general signal
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    uclk_i                 : in std_logic;  -- 40 MHz clock
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    -- Signal from the wf_reset_unit
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    nfip_rst_i             : in std_logic;  -- nanoFIP internal reset
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    -- nanoFIP FIELDRIVE (synchronized with uclk)
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    fd_rxd_a_i             : in std_logic;  -- receiver data
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  -- OUTPUTS
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    -- Signals to the wf_rx_deserializer unit
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    fd_rxd_filt_o          : out std_logic; -- filtered output signal
    fd_rxd_filt_edge_p_o   : out std_logic; -- indicates an edge on the filtered signal
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    fd_rxd_filt_f_edge_p_o : out std_logic);-- indicates a falling edge on the filtered signal

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end wf_rx_deglitcher;
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--=================================================================================================
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--                                    architecture declaration
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--=================================================================================================
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architecture rtl of wf_rx_deglitcher is
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  signal s_fd_rxd_synch                                 : std_logic_vector (1 downto 0);
  signal s_fd_rxd_filt, s_fd_rxd_filt_d1                : std_logic;
  signal s_fd_rxd_filt_r_edge_p, s_fd_rxd_filt_f_edge_p : std_logic;
  signal s_filt_c                                       : unsigned (3 downto 0);
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--=================================================================================================
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--                                       architecture begin
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--=================================================================================================
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begin

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---------------------------------------------------------------------------------------------------
--                                     FD_RXD synchronization                                    --
---------------------------------------------------------------------------------------------------

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-- Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input
-- FD_RXD to the uclk, using a set of 2 registers.
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  FD_RXD_synchronizer: process (uclk_i)
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  begin
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    if rising_edge (uclk_i) then
      if nfip_rst_i = '1' then
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       s_fd_rxd_synch <= (others => '0');
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      else
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       s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i;
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      end if;
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    end if;
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  end process;
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--                                          Deglitching                                          --
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---------------------------------------------------------------------------------------------------

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
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-- Synchronous process FD_RXD_deglitcher: the output signal s_fd_rxd_filt is updated only
-- after the accumulation of a sufficient (c_DEGLITCH_THRESHOLD + 1) amount of identical bits.
-- The signal is therefore cleaned of any glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
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  FD_RXD_deglitcher: process (uclk_i)
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  begin
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    if rising_edge (uclk_i) then
      if nfip_rst_i = '1' then
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        s_filt_c          <= to_unsigned (c_DEGLITCH_THRESHOLD, s_filt_c'length) srl 1;-- middle value
        s_fd_rxd_filt     <= '0';
        s_fd_rxd_filt_d1  <= '0';
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      else
        --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
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        if s_fd_rxd_synch(1) = '0' then     -- arrival of a '0'
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          if s_filt_c /= 0 then             -- counter updated
            s_filt_c      <= s_filt_c - 1;
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          else
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            s_fd_rxd_filt <= '0';           -- output updated
          end if;                           -- if counter = 0
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        --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
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        elsif s_fd_rxd_synch(1) = '1' then  -- arrival of a '1'
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          if s_filt_c /= c_DEGLITCH_THRESHOLD then
            s_filt_c      <= s_filt_c + 1;  -- counter updated
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          else
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            s_fd_rxd_filt <= '1';           -- output updated
          end if;                           -- if counter = c_DEGLITCH_THRESHOLD
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        end if;
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        s_fd_rxd_filt_d1  <= s_fd_rxd_filt; -- used for the edges detection
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      end if;
    end if;
  end process;

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  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
  -- Concurrent signal assignments

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  s_fd_rxd_filt_r_edge_p  <= (not s_fd_rxd_filt_d1) and s_fd_rxd_filt; -- pulse upon detection
                                                                       -- of a falling edge
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  s_fd_rxd_filt_f_edge_p  <= s_fd_rxd_filt_d1 and (not s_fd_rxd_filt); -- pulse upon detection
                                                                       -- of a rising edge
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  fd_rxd_filt_edge_p_o    <= s_fd_rxd_filt_f_edge_p or s_fd_rxd_filt_r_edge_p;
  fd_rxd_filt_f_edge_p_o  <= s_fd_rxd_filt_f_edge_p;
  fd_rxd_filt_o           <= s_fd_rxd_filt;
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end rtl;
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--=================================================================================================
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--                                        architecture end
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--=================================================================================================
---------------------------------------------------------------------------------------------------
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--                                      E N D   O F   F I L E
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