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nanoFIP - Gateware
Commit 11d339ce authored by egousiou's avatar egousiou
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engine_control separe the bytes counting when producing and consuming 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@85 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 643090f8
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Showing with 96 additions and 67 deletions
nanofip.vhd
View file @ 11d339ce
......@@ -98,22 +98,23 @@ entity nanofip is
-- WorldFIP settings
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- FIELDRIVE connections
fd_rstn_o : out std_logic; --! Initialisation control, active low
fx_rxa_i : in std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fx_txd_o : out std_logic; --! Transmitter data
fx_rxa_i : in std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
fd_rstn_o : out std_logic; --! Initialisation control, active low
-- USER INTERFACE, General signals
......@@ -121,35 +122,34 @@ entity nanofip is
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! No NanoFIP status transmission
rstin_i : in std_logic; --! Initialisation control, active low
rston_o : out std_logic; --! Reset output, active low
-- USER INTERFACE, non WISHBONE
var1_rdy_o: out std_logic; --! Variable 1 ready
var1_acc_i: in std_logic; --! Variable 1 access
var2_rdy_o: out std_logic; --! Variable 2 ready
var2_acc_i: in std_logic; --! Variable 2 access
var3_rdy_o: out std_logic; --! Variable 3 ready
var3_acc_i: in std_logic; --! Variable 3 access
var1_rdy_o: out std_logic; --! Variable 1 ready
var2_rdy_o: out std_logic; --! Variable 2 ready
var3_rdy_o: out std_logic; --! Variable 3 ready
-- USER INTERFACE, WISHBONE SLAVE
wclk_i : in std_logic; --! WISHBONE clock. May be independent of UCLK.
dat_i : in std_logic_vector (15 downto 0); --! Data in
dat_o : out std_logic_vector (15 downto 0); --! Data out
adr_i : in std_logic_vector ( 9 downto 0); --! Address
rst_i : in std_logic; --! WISHBONE reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
ack_o : out std_logic; --! Acknowledge
cyc_i : in std_logic;
we_i : in std_logic --! Write enable
we_i : in std_logic; --! Write enable
adr_i : in std_logic_vector ( 9 downto 0); --! Address
dat_i : in std_logic_vector (15 downto 0); --! Data in
dat_o : out std_logic_vector (15 downto 0); --! Data out
ack_o : out std_logic --! Acknowledge
);
......
wf_engine_control.vhd
View file @ 11d339ce
......@@ -166,7 +166,8 @@ architecture rtl of wf_engine_control is
signal s_time_c, s_time_counter_top: signed(14 downto 0);
signal s_response_time, s_silence_time : signed(14 downto 0);
signal s_produce_or_consume : std_logic_vector (1 downto 0);
signal s_enble_load_temp_var, s_reset_rx_unit : std_logic;
signal s_enble_load_temp_var : std_logic;
signal s_reset_rx_unit : std_logic;
signal s_enble_bytes_counter, s_start_producing, s_enble_tx, s_enble_rx : std_logic;
......@@ -238,7 +239,7 @@ begin
if (rx_byte_ready_p_i = '1') and (s_var_aux_concurr /= var_whatever) then
nx_control_st <= id_dat_subs_byte;
elsif (rx_byte_ready_p_i = '1') and (s_var_aux_concurr = var_whatever) then
elsif (rx_byte_ready_p_i = '1') then
nx_control_st <= idle;
else
......@@ -336,12 +337,16 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Central_Control_FSM_Comb_Output_Signals:
Central_Control_FSM_Comb_Output_Signals: process (control_st)
Central_Control_FSM_Comb_Output_Signals: process (control_st, s_tx_rx_bytes_c,
tx_request_byte_p_i,
rx_byte_ready_p_i)
begin
case control_st is
when idle =>
s_inc_tx_rx_bytes_counter <= '0';
tx_rx_byte_index_o <= (others => '0');
s_reset_rx_unit <= '1';
s_rst_time_c <= '1';
s_enble_bytes_counter <= '0';
......@@ -352,8 +357,9 @@ begin
s_enble_rx <= '0';
s_enble_tx <= '0';
when id_dat_control_byte =>
s_inc_tx_rx_bytes_counter <= '0';
tx_rx_byte_index_o <= (others => '0');
s_reset_rx_unit <= '0';
s_rst_time_c <= '1';
s_enble_bytes_counter <= '0';
......@@ -366,6 +372,8 @@ begin
when id_dat_var_byte =>
s_inc_tx_rx_bytes_counter <= '0';
tx_rx_byte_index_o <= (others => '0');
s_reset_rx_unit <= '0';
s_rst_time_c <= '1';
s_enble_bytes_counter <= '0';
......@@ -378,6 +386,8 @@ begin
when id_dat_subs_byte =>
s_inc_tx_rx_bytes_counter <= '0';
tx_rx_byte_index_o <= (others => '0');
s_reset_rx_unit <= '0';
s_rst_time_c <= '1';
s_enble_bytes_counter <= '0';
......@@ -390,6 +400,8 @@ begin
when id_dat_frame_ok =>
s_inc_tx_rx_bytes_counter <= rx_byte_ready_p_i;
tx_rx_byte_index_o <= (others => '0');
s_reset_rx_unit <= '0';
s_rst_time_c <= '1';
s_enble_bytes_counter <= '1';
......@@ -402,6 +414,8 @@ begin
when produce_wait_respon_time =>
s_inc_tx_rx_bytes_counter <= '0';
tx_rx_byte_index_o <= (others => '0');
s_reset_rx_unit <= '0';
s_rst_time_c <= '0';
s_enble_bytes_counter <= '0';
......@@ -415,6 +429,8 @@ begin
when consume_wait_FSS =>
s_inc_tx_rx_bytes_counter <= '0';
tx_rx_byte_index_o <= (others => '0');
s_reset_rx_unit <= '0';
s_rst_time_c <= '0';
s_enble_bytes_counter <= '0';
......@@ -428,6 +444,8 @@ begin
when consume =>
s_inc_tx_rx_bytes_counter <= rx_byte_ready_p_i;
tx_rx_byte_index_o <= std_logic_vector (resize(s_tx_rx_bytes_c,tx_rx_byte_index_o'length));
s_reset_rx_unit <= '0';
s_rst_time_c <= '1';
s_enble_bytes_counter <= '1';
......@@ -441,6 +459,8 @@ begin
when produce =>
s_inc_tx_rx_bytes_counter <= tx_request_byte_p_i;
tx_rx_byte_index_o <= std_logic_vector (resize(s_tx_rx_bytes_c, tx_rx_byte_index_o'length));
s_reset_rx_unit <= '0';
s_rst_time_c <= '1';
s_enble_bytes_counter <= '1';
......@@ -452,7 +472,9 @@ begin
s_enble_tx <= '1';
when others =>
when others =>
s_inc_tx_rx_bytes_counter <= '0';
tx_rx_byte_index_o <= (others => '0');
s_reset_rx_unit <= '0';
s_rst_time_c <= '1';
s_enble_bytes_counter <= '0';
......@@ -463,6 +485,7 @@ begin
s_enble_rx <= '0';
s_enble_tx <= '0';
end case;
end process;
......@@ -474,16 +497,18 @@ begin
rx_byte_ready_p_o <= s_enble_rx and rx_byte_ready_p_i;
s_tx_last_byte_p <= s_enble_tx and s_tx_data_length_match and tx_request_byte_p_i;
reset_status_bytes_o <= s_enble_tx and s_tx_byte_ready_p_d2 and tx_sending_mps_i;
s_inc_tx_rx_bytes_counter <= s_enble_bytes_counter and (tx_request_byte_p_i or rx_byte_ready_p_i);
--s_inc_tx_rx_bytes_counter <= s_enble_bytes_counter and (tx_request_byte_p_i or rx_byte_ready_p_i);
s_tx_byte_ready_p <= s_enble_tx and (tx_request_byte_p_i or s_tx_start_produce_p_d1);
tx_rx_byte_index_o <= std_logic_vector (resize(s_tx_rx_bytes_c, tx_rx_byte_index_o'length))
when s_enble_tx ='1' or s_enble_rx = '1'
else (others => '0');
--tx_rx_byte_index_o <= std_logic_vector (s_tx_rx_bytes_c) when (s_enble_tx ='1' or s_enble_rx = '1')
-- else (others => '0');
s_tx_start_produce_p <= s_start_producing and s_time_c_is_zero;
--------------------------------------------------------------------------------------------------
--! The following two processes: id_dat_var_concurrent and id_dat_var_specific_moments manage the
--! signals s_var_aux_concurr, s_var_aux and s_var. All of them are used to keep the value of the
......@@ -573,10 +598,9 @@ begin
--! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation
data_length_calcul_produce: process ( s_var, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i )
variable v_nostat : std_logic_vector (1 downto 0);
begin
s_tx_data_length <= (others => '0');
s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
case s_var is
......@@ -623,21 +647,25 @@ begin
else
if nostat_i = '0' then
s_tx_data_length <= s_p3_length_decoded + 4; -- (bytes counting starts from 0)
-- if nostat_i = '0' then
-- s_tx_data_length <= s_p3_length_decoded + 4; -- (bytes counting starts from 0)
else
-- else
s_tx_data_length <= s_p3_length_decoded + 3; -- (bytes counting starts from 0)
end if;
-- end if;
end if;
when var_1 =>
s_tx_data_length <= (others => '0');
when var_2 =>
s_tx_data_length <= (others => '0');
when reset_var =>
s_tx_data_length <= (others => '0');
when others =>
s_tx_data_length <= (others => '0');
end case;
end process;
......@@ -706,53 +734,54 @@ begin
--! the Ctrl, PDU and Length bytes of an rp_dat. At the end of the rp_dat frame, the signal
--! s_cons_frame_ok_p indicates if those bytes, along with the CRC and the FES were correct and enables
--! the signals var1_rdy or var2_rdy (VAR_RDY_Generation process)
process(uclk_i)
process(s_var, rx_CRC_FES_ok_p_i, s_tx_rx_bytes_c, rx_PDU_byte_i, rx_Ctrl_byte_i, rx_Length_byte_i)
begin
if rising_edge(uclk_i) then
if s_var = var_1 or s_var = var_2 then
if s_var = var_1 or s_var = var_2 then
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_Ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_rx_ctrl_byte_ok <= '1'; -- RP_DAt_CTRL byte
else
s_rx_ctrl_byte_ok <= '0';
end if;
if rx_Ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_rx_ctrl_byte_ok <= '1'; -- RP_DAt_CTRL byte
else
s_rx_ctrl_byte_ok <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_PDU_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_rx_PDU_byte_ok <= '1'; -- PDU_TYPE byte
else
s_rx_PDU_byte_ok <= '0' ;
end if;
if rx_PDU_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_rx_PDU_byte_ok <= '1'; -- PDU_TYPE byte
else
s_rx_PDU_byte_ok <= '0' ;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_CRC_FES_ok_p_i = '1' then -- checking the rp_dat.Data.Length
if rx_CRC_FES_ok_p_i = '1' then -- checking the rp_dat.Data.Length
-- byte, when the end of frame
-- arrives correctly
if s_tx_rx_bytes_c = (unsigned(rx_Length_byte_i) + 5) then
s_rx_length_byte_ok <= '1'; -- s_tx_rx_bytes_c starts counting
-- from 0 and apart from the user-data
else -- bytes, also counts ctrl, PDU,
s_rx_length_byte_ok <= '0'; -- Length, 2 crc and FES bytes
end if;
if s_tx_rx_bytes_c = (unsigned(rx_Length_byte_i) + 5) then -- s_tx_rx_bytes_c starts counting
s_rx_length_byte_ok <= '1'; -- from 0 and apart from the user-data
-- bytes, also counts ctrl, PDU,
else -- Length, 2 crc and FES bytes
s_rx_length_byte_ok <= '0';
end if;
else
s_rx_length_byte_ok <= '0';
end if;
else
s_rx_length_byte_ok <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
else
s_rx_ctrl_byte_ok <= '0';
s_rx_PDU_byte_ok <= '0';
s_rx_length_byte_ok <= '0';
end if;
end if;
else
s_rx_ctrl_byte_ok <= '0';
s_rx_PDU_byte_ok <= '0';
s_rx_length_byte_ok <= '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
s_cons_frame_ok_p <= s_rx_length_byte_ok and s_rx_ctrl_byte_ok and s_rx_PDU_byte_ok;
s_cons_frame_ok_p <= rx_CRC_FES_ok_p_i and s_rx_length_byte_ok and s_rx_ctrl_byte_ok and s_rx_PDU_byte_ok;
......
wf_package.vhd
View file @ 11d339ce
......@@ -84,7 +84,7 @@ package wf_package is
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000000" -- reserved
others => "00000010" -- reserved ----------!!!!!!!!!!
);
......
wf_produced_vars.vhd
View file @ 11d339ce
......@@ -391,13 +391,13 @@ architecture rtl of wf_produced_vars is
-- The one but last byte if the input nostat_i is negated is the nanoFIP status byte
-- (if nostat_i is not negated, the "else" condition takes place)
elsif unsigned(s_byte_index) = (unsigned(data_length_i)-1 ) and nostat_i = '0' then
byte_o <= nFIP_status_byte_i;
sending_mps_o <= '0';
-- elsif unsigned(s_byte_index) = (unsigned(data_length_i)-1 ) and nostat_i = '0' then !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- byte_o <= nFIP_status_byte_i;
-- sending_mps_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The last byte is the MPS status
elsif s_byte_index = (data_length_i)then
elsif s_byte_index = (data_length_i) then
byte_o <= mps_status_byte_i;
sending_mps_o <= '1'; -- indication: MPS byte is being sent
......
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