wf_engine_control: mistake when id_dat with wrong crc arrives corrected

aesthetics: trailing whitespaces deleted from all the units git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@173 7f0067c9-7624-46c7-bd39-3fb5400c0213

wf_engine_control: mistake when id_dat with wrong crc arrives corrected
aesthetics: trailing whitespaces deleted from all the units git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@173 7f0067c9-7624-46c7-bd39-3fb5400c0213
297713da · egousiou · c2a427ea · 297713da · 297713da · 297713da
Commit 297713da authored Mar 01, 2011 by egousiou
27 changed files
--- a/DualClkRAM.vhd
+++ b/DualClkRAM.vhd
--- a/nanofip.vhd
+++ b/nanofip.vhd
@@ -219,7 +219,7 @@ entity nanofip is

  nostat_i   : in std_logic;                     --! No NanoFIP status with produced data

-  rstin_i    : in std_logic;                     --! Initialisation control, active low
+  rstin_i    : in std_logic;                     --! Initialization control, active low
                                                 --! Resets nanoFIP & the FIELDRIVE

  rstpon_i   : in std_logic;                     --! Power On Reset, active low
@@ -259,7 +259,7 @@ entity nanofip is

  --  FIELDRIVE

-  fd_rstn_o  : out std_logic;                    --! Initialisation control, active low
+  fd_rstn_o  : out std_logic;                    --! Initialization control, active low
  fd_txck_o  : out std_logic;                    --! Line driver half bit clock
  fd_txd_o   : out std_logic;                    --! Transmitter data
  fd_txena_o : out std_logic;                    --! Transmitter enable
@@ -344,10 +344,9 @@ begin
      uclk_i                => uclk_i,
      wb_clk_i              => wclk_i,
      rstin_a_i             => rstin_i,
-      rstpon_i              => rstpon_i,
+      rstpon_a_i            => rstpon_i,
      rate_i                => rate_i,
      rst_i                 => rst_i,
-      var_i                 => s_var_from_control,
      rst_nFIP_and_FD_p_i   => s_reset_nFIP_and_FD_p,
      assert_RSTON_p_i      => s_assert_RSTON_p,
    ---------------------------------------------------------

--- a/wf_DualClkRAM_clka_rd_clkb_wr.vhd
+++ b/wf_DualClkRAM_clka_rd_clkb_wr.vhd
--- a/wf_bits_to_txd.vhd
+++ b/wf_bits_to_txd.vhd
--- a/wf_cons_bytes_processor.vhd
+++ b/wf_cons_bytes_processor.vhd
@@ -99,8 +99,6 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --
 --! @todo
--!   --> separate unit for the wb_ack treatment
--!   --> two constant!
 --
 ---------------------------------------------------------------------------------------------------

@@ -160,7 +158,6 @@ architecture rtl of WF_cons_bytes_processor is
  signal s_addr                           : std_logic_vector (8 downto 0);
  signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
  signal s_slone_write_byte_p             : std_logic_vector (1 downto 0);
-  signal two                              : unsigned (7 downto 0);
  signal s_base_addr                      : unsigned (8 downto 0);
  signal s_write_byte_to_mem_p            : std_logic;

@@ -170,7 +167,6 @@ architecture rtl of WF_cons_bytes_processor is
 --=================================================================================================
 begin

-  two <= to_unsigned (2, two'length);

 ---------------------------------------------------------------------------------------------------
 --                               Consumed & Consumed Broadcast RAM                               --
@@ -277,7 +273,7 @@ begin
                                                                          -- (-1 bc the Ctrl
                                                                          -- byte is not written)

-  Bytes_Processing: process (var_i,byte_index_i,slone_i, byte_i,two,byte_ready_p_i,s_cons_lgth_byte)
+  Bytes_Processing: process (var_i,byte_index_i,slone_i, byte_i, byte_ready_p_i,s_cons_lgth_byte)


  begin
@@ -303,7 +299,7 @@ begin

                if byte_index_i > c_LGTH_BYTE_INDEX then                    -- after the reception
                                                                            -- of the Length byte
-                  if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two  then -- less or eq
+                  if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2  then -- less or eq
                    s_write_byte_to_mem_p <= byte_ready_p_i;                -- "Length" amount of
                                                                            -- bytes are written
                                                                            --(to avoid writing CRC!)
@@ -354,7 +350,7 @@ begin

                if byte_index_i > c_LGTH_BYTE_INDEX then

-                  if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two  then
+                  if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2  then
                    s_write_byte_to_mem_p <= byte_ready_p_i;

                  else

--- a/wf_cons_outcome.vhd
+++ b/wf_cons_outcome.vhd
--- a/wf_consumption.vhd
+++ b/wf_consumption.vhd
--- a/wf_crc.vhd
+++ b/wf_crc.vhd
@@ -95,7 +95,7 @@ entity WF_crc is
    crc_ok_p_o         : out std_logic;             --! signals a correct received CRC syndrome

    -- Signal to the WF_tx_serializer unit
-    crc_o              : out  std_logic_vector (c_CRC_GENER_POLY_LGTH-1 downto 0)--!calculated CRC
+    crc_o              : out  std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)--!calculated CRC
     );

 end entity WF_crc;
@@ -106,7 +106,7 @@ end entity WF_crc;
 --=================================================================================================
 architecture rtl of WF_crc is

-  signal s_q, s_q_nx, s_q_check_mask       : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0);
+  signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);


 --=================================================================================================
@@ -161,14 +161,14 @@ begin
 ---------------------------------------------------------------------------------------------------
 --!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
 --! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_CRC_VERIFIC_MASK. When the CRC calculated from the received data matches the
--! c_CRC_VERIFIC_MASK, it is implied that a correct CRC word has been received for the preceded
+--! predefined c_CRC_VERIF_POLY. When the CRC calculated from the received data matches the
+--! c_CRC_VERIF_POLY, it is implied that a correct CRC word has been received for the preceded
 --! data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.

  Syndrome_Verification: process (s_q, data_bit_ready_p_i)
  begin

-    if s_q = not c_CRC_VERIFIC_MASK then 
+    if s_q = not c_CRC_VERIF_POLY then

      crc_ok_p_o <= data_bit_ready_p_i;


--- a/wf_decr_counter.vhd
+++ b/wf_decr_counter.vhd
--- a/wf_engine_control.vhd
+++ b/wf_engine_control.vhd
@@ -7,7 +7,7 @@
 --________________________________________________________________________________________________|

 ---------------------------------------------------------------------------------------------------
--! @file WF_engine_control.vhd                                                                  
+--! @file WF_engine_control.vhd                                                                   |
 ---------------------------------------------------------------------------------------------------

 --! Standard library
@@ -96,6 +96,8 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 --!                         assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and
 --!                         rx_byte_ready_p_o removed cleaning-up+commenting
 --!     02/2011  v0.05  EG  Independant timeout counter added; time counter 18 digits instead of 15
+--!                         id_dat_frame_ok: corrected mistake if rx_fss_crc_fes_manch_ok_p not
+--!                         activated
 --
 ---------------------------------------------------------------------------------------------------
 --
@@ -359,9 +361,9 @@ begin
        elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_prod_or_cons = "01") then
          nx_control_st <= consume_wait_FSS;         -- CRC & FES check ok! station has to consume

-        elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_rx_bytes_c > 2)  then
-          nx_control_st <= idle;                     -- 3 bytes after the arrival of the subscriber
-                                                     -- byte, a FES has not been detected
+        elsif (s_rx_bytes_c > 2)  then               -- 3 bytes after the arrival of the subscriber
+          nx_control_st <= idle;                     -- byte, a FES has not been detected
+
        elsif (s_session_timedout = '1') then
          nx_control_st <= idle;


--- a/wf_fd_receiver.vhd
+++ b/wf_fd_receiver.vhd
--- a/wf_fd_transmitter.vhd
+++ b/wf_fd_transmitter.vhd
--- a/wf_incr_counter.vhd
+++ b/wf_incr_counter.vhd
@@ -75,7 +75,7 @@ entity WF_incr_counter is

  -- OUTPUT
    -- Signal to any unit
-   counter_o         : out unsigned(g_counter_lgth-1 downto 0); --! counter
+   counter_o         : out unsigned (g_counter_lgth-1 downto 0); --! counter
   counter_is_full_o : out std_logic                             --! counter full indication
      );                                                         --! (all bits to '1')

@@ -90,7 +90,6 @@ architecture rtl of WF_incr_counter is
 constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
 signal   s_counter      : unsigned (g_counter_lgth-1 downto 0);

-
 --=================================================================================================
 --                                        architecture begin
 --=================================================================================================

--- a/wf_manch_code_viol_check.vhd
+++ b/wf_manch_code_viol_check.vhd
--- a/wf_model_constr_decoder.vhd
+++ b/wf_model_constr_decoder.vhd
--- a/wf_package.vhd
+++ b/wf_package.vhd
@@ -79,12 +79,9 @@ package WF_package is
 ---------------------------------------------------------------------------------------------------
 --                            Constants regarding the CRC calculation                            --
 ---------------------------------------------------------------------------------------------------
-  constant c_CRC_GENER_POLY_LGTH : natural                                               := 16;
-  constant c_CRC_GENER_POLY      : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0) :=
-                                                                                "0001110111001111";
-  constant c_CRC_VERIFIC_MASK    : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0) := 
-                                                                                "0001110001101011";
-
+  constant c_CRC_POLY_LGTH  : natural                                         := 16;
+  constant c_CRC_GENER_POLY : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0) := "0001110111001111";
+  constant c_CRC_VERIF_POLY : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0) := "0001110001101011";


 ---------------------------------------------------------------------------------------------------
@@ -629,10 +626,9 @@ end component WF_rx_osc;
    uclk_i              : in std_logic;
    wb_clk_i            : in std_logic;
    rstin_a_i           : in std_logic;
-    rstpon_i            : in std_logic;
+    rstpon_a_i          : in std_logic;
    rate_i              : in std_logic_vector (1 downto 0);
    rst_i               : in std_logic;
-    var_i               : in t_var;    
    rst_nFIP_and_FD_p_i : in std_logic;
    assert_RSTON_p_i    : in std_logic;
  -----------------------------------------------------------------
@@ -693,7 +689,7 @@ end component WF_rx_osc;
    data_bit_ready_p_i : in std_logic;
  -----------------------------------------------------------------
    crc_ok_p_o         : out std_logic;
-    crc_o              : out std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0));
+    crc_o              : out std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0));
  -----------------------------------------------------------------
  end component WF_crc;


--- a/wf_prod_bytes_retriever.vhd
+++ b/wf_prod_bytes_retriever.vhd
--- a/wf_prod_data_lgth_calc.vhd
+++ b/wf_prod_data_lgth_calc.vhd
--- a/wf_prod_permit.vhd
+++ b/wf_prod_permit.vhd
--- a/wf_production.vhd
+++ b/wf_production.vhd
--- a/wf_reset_unit.vhd
+++ b/wf_reset_unit.vhd
--- a/wf_rx_deglitcher.vhd
+++ b/wf_rx_deglitcher.vhd
--- a/wf_rx_deserializer.vhd
+++ b/wf_rx_deserializer.vhd
--- a/wf_rx_osc.vhd
+++ b/wf_rx_osc.vhd
--- a/wf_status_bytes_gen.vhd
+++ b/wf_status_bytes_gen.vhd
@@ -305,7 +305,7 @@ end process;

      else
        --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-        -- reinitialisation after the transmission of a produced variable
+        -- reinitialization after the transmission of a produced variable
        if rst_status_bytes_p_i = '1' then                          -- bits 0 to 5 reinitialised
          s_nFIP_status_byte(5 downto 0)        <= (others => '0'); -- after having been delivered
                                                                    -- bits 6 and 7 are only reset

--- a/wf_tx_osc.vhd
+++ b/wf_tx_osc.vhd
--- a/wf_tx_serializer.vhd
+++ b/wf_tx_serializer.vhd
@@ -149,7 +149,7 @@ architecture rtl of WF_tx_serializer is
  signal s_session_timedout : std_logic;
  signal s_prepare_to_produce, s_sending_fss, s_sending_data, s_sending_crc        : std_logic;
  signal s_sending_fes, s_stop_transmission, s_start_crc_p, s_data_bit_to_crc_p    : std_logic;
-  signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero, s_tx_enable : std_logic;
+  signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero              : std_logic;
  signal s_bit_index, s_bit_index_top                                   : unsigned (4 downto 0);
  signal s_byte                                                : std_logic_vector  (7 downto 0);
  signal s_crc_bytes_manch                                     : std_logic_vector (31 downto 0);
@@ -199,7 +199,7 @@ begin
 --! follow.

 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
--!@brief synchronous process Serializer_FSM_Sync:
+--!@brief Synchronous process Serializer_FSM_Sync:

  Serializer_FSM_Sync: process (uclk_i)
  begin
@@ -213,8 +213,7 @@ begin
  end process;

 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
--!@brief combinatorial process Serializer_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM
+--!@brief Combinatorial process Serializer_FSM_Comb_State_Transitions

  Serializer_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
                                                  s_session_timedout,tx_start_p_i, tx_clk_p_buff_i)
@@ -313,8 +312,7 @@ begin


 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
--!@brief combinatorial process Serializer_FSM_Comb_Output_Signals: definition of the output
--! signals of the FSM
+--!@brief Combinatorial process Serializer_FSM_Comb_Output_Signals

  Serializer_FSM_Comb_Output_Signals:  process ( tx_state )
  begin
@@ -558,7 +556,7 @@ Input_Byte_Retrieval: process (uclk_i)
    tx_clk_p_i          => tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-3),
   ---------------------------------------------
    txd_o               => s_txd,
-    tx_enable_o         => s_tx_enable);
+    tx_enable_o         => tx_enable_o);
   ---------------------------------------------


@@ -592,8 +590,6 @@ Input_Byte_Retrieval: process (uclk_i)

  tx_data_o           <= s_txd;

-  tx_enable_o         <= s_tx_enable;
-
  tx_osc_rst_p_o      <= s_session_timedout;

  byte_request_p_o    <= s_sending_data and s_bit_index_is_zero and  tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);