major changes in wf_reset_unit

PoR input pin added git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@109 7f0067c9-7624-46c7-bd39-3fb5400c0213

major changes in wf_reset_unit
PoR input pin added git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@109 7f0067c9-7624-46c7-bd39-3fb5400c0213
35b7480e · egousiou · 8994c7c1 · 35b7480e · 8994c7c1 · 35b7480e
Commit 35b7480e authored Jan 18, 2011 by egousiou
27 changed files
--- a/DualClkRAM.vhd
+++ b/DualClkRAM.vhd
@@ -136,7 +136,6 @@ architecture RAM4K9 of  DualClkRAM is
 --! A Low on this signal makes the output retain data from the previous Read. A High indicates a 
 --! pass-through behavior where the data being written will appear on the output immediately.
  component RAM4K9
    generic (MEMORYFILE:string := "");

--- a/nanofip.vhd
+++ b/nanofip.vhd
--_________________________________________________________________________________________________
--                                                                                                |
--                                        |The nanoFIP|                                           |
--                                                                                                |
--                                        CERN,BE/CO-HT                                           |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file nanofip.vhd
---------------------------------------------------------------------------------------------------
--! standard library
-library IEEE;
--! standard packages
-use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
-use IEEE.NUMERIC_STD.all;     --! conversion functions
--! specific packages
-use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
-- library synplify;
-- use synplify.attributes.all;
-- syn_translate on;
-- library synplify;
-- syn_translate off;
--------------------------------------------------------------------------------------------------- 
--                                                                                               --
--                                              nanoFIP                                          --
--                                                                                               --
--------------------------------------------------------------------------------------------------- 
--
--
--! The nanoFIP is an FPGA component implementing the WorldFIP protocol that can be used in field
--! devices able to communicate at the three standard speeds. The nanoFIP, that is developed as
--! part of the WorldFIP insourcing project, is designed to be radiation tolerant by using
--! different single event upset mitigation techniques such as triple module redundancy. The
--! nanoFIP design is to be implemented in an Actel ProASIC3 Flash family FPGA that is not loosing
--! its configuration and has high tolerance to total dose radiation effects. The device is used in
--! conjunction with a FIELDRIVER chip and FieldTR insulating transformer, both available from the
--! company ALSTOM.
--!
--! NanoFIP is handling the following variables addresses by:
--!   o ID_DAT = ..14xyh: for the presence variable
--!   o ID_DAT = ..10xyh: for the identification variable
--!   o ID_DAT = ..05xyh: for the consumed variable of any length up to 124 bytes
--!   o ID_DAT = ..91..h: for the broadcast consumed variable of any length up to 124 bytes
--!   o ID_DAT = ..06xyh: for the produced variable of a user-settable length 
--!   o ID_DAT = ..E0..h: for the broadcast consumed reset variable 
--!
--! Regarding the interface with the user, nanoFIP provides:
--!   o variable data transfer over an integrated memory accessible with an 8-bit WISHBONE
--!     System-On-Chip interconnection
--!   o possibility of stand-alone mode with 16 input and 16 output  lines without the need to
--!     transfer data to or from the memory
--!   o separate data valid outputs for each variable (consumed and produced)
--!
--! nanoFIP provides several reset possibilities:
--!  o External reset pin, RSTIN, for the user logic and the FIELDRIVE
--!  o External reset pin, RST_I, for the WISHBONE logic
--!  o addressed reset by the reset broadcast consumed variable (E0..h)
--!    validated by station address as data, for the user logic and the FIELDRIVE
--!  o Reset output available to external logic
--! 
--!   _____________     __________________________     _____________
--!  |             |   |                          |   |             |
--!  |             |   |      WF_tx_rx_osc        |   |             |
--!  |             |   |                          |   |             |
--!  |             |   |__________________________|   |             |
--!  |             |                                  |             |
--!  | WF_inputs_  |    ___________   ____________    |
--!  | synchroniser|   |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |             |   |           | |            |   |  WF_engine  |
--!  |_____________|   |           | |            |   |  _control   |
--!                    |           | |            |   |             |
--!   _____________    |           | |            |   |             |
--!  |             |   |    WF_    | |     WF_    |   |             |
--!  |             |   |consumption| | production |   |             |
--!  |   WF_reset  |   |           | |            |   |             |
--!  |   _unit     |   |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |_____________|   |           | |            |   |             |
--!                    |           | |            |   |             |
--!   _____________    |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |  WF_model_  |   |           | |            |   |             |
--!  | constr_dec  |   |           | |            |   |             |
--!  |             |   |           | |            |   |             |
--!  |_____________|   |___________| |____________|   |_____________|
--! <HR>
--! @section more_sec More information
--! This design is based on the <em>NanoFIP functional specification v1.2</em> 
--! http://www.ohwr.org/twiki/pub/OHR/CernFIP/WP3/cernfip_fspec1_2.pdf
--!
--! Complete information about this project at 
--! http://www.ohwr.org/twiki/bin/view/OHR/CernFIP/ \n\n
--! 
--! <HR>
--! @image html nanofip_image_1s.gif "Block diagram of the NanoFIP design"
--!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--
--! @date 07/07/2009
--
--! @version v0.1
--
--! @details 
--!
--! <b>Dependencies:</b>\n
--! 
--!
--! <b>References:</b>\n
--! 
--! 
--!
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
--------------------------------------------------------------------------------------------------- 
--! \n\n<b>Last changes:</b>\n
--! 30/06/2009  v0.010  EB  First version \n
--! 06/07/2009  v0.011  EB  Dummy blocks  \n
--! 07/07/2009  v0.011  EB  Comments      \n
--!
--------------------------------------------------------------------------------------------------- 
--! @todo Create entity \n
--
--------------------------------------------------------------------------------------------------- 
--! @brief Top level design file of nanofip
--=================================================================================================
--!                           Entity declaration for nanoFIP
--=================================================================================================
-entity nanofip is
-  port (
--INPUTS
-  -- WorldFIP settings
-  c_id_i     : in  std_logic_vector (3 downto 0); --! Constructor identification settings
-  m_id_i     : in  std_logic_vector (3 downto 0); --! Model identification settings
-  p3_lgth_i  : in  std_logic_vector (2 downto 0); --! Produced variable data length
-  rate_i     : in  std_logic_vector (1 downto 0); --! Bit rate
-  subs_i     : in  std_logic_vector (7 downto 0); --! Subscriber number coding
-  --  FIELDRIVE 
-  fd_rxcdn_i : in  std_logic; --! Reception activity detection
-  fd_rxd_i   : in  std_logic; --! Receiver data
-  fd_txer_i  : in  std_logic; --! Transmitter error
-  fd_wdgn_i  : in  std_logic; --! Watchdog on transmitter
-  --  User Interface, General signals
-  nostat_i   : in  std_logic; --! No NanoFIP status transmission
-  rstin_i    : in  std_logic; --! Initialisation control, active low
-  slone_i    : in  std_logic; --! Stand-alone mode
-  uclk_i     : in  std_logic; --! 40 MHz clock
-  --  User Interface, NON-WISHBONE
-  var1_acc_i : in  std_logic; --! Variable 1 access
-  var2_acc_i : in  std_logic; --! Variable 2 access
-  var3_acc_i : in  std_logic; --! Variable 3 access
-  --  User Interface, WISHBONE Slave
-  we_i       : in  std_logic;  --! Write enable
-  adr_i      : in  std_logic_vector ( 9 downto 0); --! Address
-  cyc_i      : in std_logic;
-  dat_i      : in  std_logic_vector (15 downto 0); --! Data in
-  rst_i      : in  std_logic;  --! WISHBONE reset. Does not reset other internal logic.
-  stb_i      : in  std_logic;  --! Strobe
-  wclk_i     : in  std_logic;  --! WISHBONE clock. May be independent of UCLK.
-- OUTUTS
-  -- WorldFIP settings
-  s_id_o     : out std_logic_vector (1 downto 0); --! Identification selection
-  --  FIELDRIVE
-  fd_rstn_o  : out std_logic; --! Initialisation control, active low
-  fd_txck_o  : out std_logic; --! Line driver half bit clock
-  fd_txd_o   : out std_logic; --! Transmitter data
-  fd_txena_o:  out std_logic; --! Transmitter enable
-  --  User Interface, General signals
-  rston_o    : out std_logic; --! Reset output, active low
-  --  User Interface, NON-WISHBONE
-  r_fcser_o  : out std_logic; --! nanoFIP status byte, bit 5
-  r_tler_o   : out std_logic; --! nanoFIP status byte, bit 4
-  u_cacer_o  : out std_logic; --! nanoFIP status byte, bit 2
-  u_pacer_o  : out std_logic; --! nanoFIP status byte, bit 3
-  var1_rdy_o : out std_logic; --! Variable 1 ready
-  var2_rdy_o : out std_logic; --! Variable 2 ready
-  var3_rdy_o : out std_logic; --! Variable 3 ready
-  --  User Interface, WISHBONE Slave
-  dat_o      : out std_logic_vector (15 downto 0); --! Data out
-  ack_o      : out std_logic --! Acknowledge
-    );
-  -- attribute syn_insert_buffer : string;  
-  -- attribute syn_insert_buffer of wb_clk_i : signal is "GL25";
-end entity nanofip;
--=================================================================================================
-- end of entity declaration
--=================================================================================================
--=================================================================================================
--!                                  architecture declaration
--=================================================================================================
--! Architecture contains only connectivity
-architecture struc of nanofip is
--=================================================================================================
-- Triple Module Redundancy
- attribute syn_radhardlevel          : string;
- attribute syn_radhardlevel of struc : architecture is "tmr";
--=================================================================================================
-  component CLKBUF
-    port (PAD : in std_logic;
-          Y   : out std_logic);
-  end component;
-  signal s_data_length_from_control :  std_logic_vector (7 downto 0);
-  signal s_rst, s_rx_byte_ready : std_logic;
-  signal s_start_prod_p, s_rst_rx_osc : std_logic;
-  signal s_prod_request_byte_p : std_logic;
-  signal s_prod_byte_ready_p : std_logic;
-  signal s_prod_last_byte_p : std_logic;
-  signal s_rx_byte : std_logic_vector (7 downto 0);
-  signal s_var_from_control : t_var;
-  signal s_cons_prod_byte_index_from_control : std_logic_vector (7 downto 0);
-  signal s_fss_crc_fes_manch_ok_p, s_urst_r_edge : std_logic;
-  signal s_cons_fss_decoded_p, s_assert_RSTON_p : std_logic;
-  signal s_prod_ack, s_wb_ack_cons, s_ack_o: std_logic;
-  signal s_crc_wrong_p, s_reset_nFIP_and_FD_p  : std_logic;
-  signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic;
-  signal s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);  
-  signal s_rst_rx_unit_p, s_nfip_status_r_tler, s_signif_edge_window, s_adjac_bits_window, s_rx_bit_clk_p, s_rx_manch_clk_p : std_logic;
-  signal s_urst_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch: std_logic;
-  signal s_fd_rxd_synch, s_fd_rxd_edge_p, s_fd_rxd_r_edge_p, s_fd_rxd_f_edge_p, s_wb_cyc_synch: std_logic;
-  signal s_wb_we_synch, s_wb_stb_synch, s_wb_stb_r_edge: std_logic; 
-  signal s_wb_dati_synch: std_logic_vector(7 downto 0);
-  signal s_wb_adri_synch: std_logic_vector(9 downto 0);
-  signal s_var1_access_synch, s_var2_access_synch, s_var3_access_synch: std_logic;
-  signal s_slone_dati_synch: std_logic_vector(15 downto 0);
-  signal s_rate_synch: std_logic_vector(1 downto 0);
-  signal s_subs_synch : std_logic_vector(7 downto 0);
-  signal s_m_id_synch, s_c_id_synch : std_logic_vector(3 downto 0);
-  signal s_p3_lgth_synch : std_logic_vector(2 downto 0);
-  signal s_tx_clk_p_buff                   : std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
--=================================================================================================
--                                      architecture begin
--=================================================================================================  
-begin
---------------------------------------------------------------------------------------------------
-  reset_unit : WF_reset_unit 
-    port map(
-      uclk_i                => uclk_i,
-      urst_i                => s_urst_synch,
-      rate_i                => s_rate_synch,--------------------
-      urst_r_edge_i         => s_urst_r_edge,
-      var_i                 => s_var_from_control,
-      subs_i                => s_subs_synch,--------------------
-      rst_nFIP_and_FD_p_i   => s_reset_nFIP_and_FD_p,
-      assert_RSTON_p_i      => s_assert_RSTON_p,
-      rston_o               => rston_o,
-      nFIP_rst_o            => s_rst, 
-      fd_rstn_o             => fd_rstn_o  
-      );
---------------------------------------------------------------------------------------------------
-  engine_control : WF_engine_control 
-    generic map( c_QUARTZ_PERIOD => c_QUARTZ_PERIOD)
-    port map(
-      uclk_i                  => uclk_i,
-      nfip_urst_i             => s_rst, 
-      tx_request_byte_p_i     => s_prod_request_byte_p, 
-      rx_fss_received_p_i     => s_cons_fss_decoded_p,   
-      rx_byte_i               => s_rx_byte, 
-      rx_byte_ready_p_i       => s_rx_byte_ready,
-      rx_fss_crc_fes_manch_ok_p_i  => s_fss_crc_fes_manch_ok_p,
-      rx_crc_wrong_p_i        => s_crc_wrong_p,
-      rate_i                  => s_rate_synch,---------------- 
-      subs_i                  => s_subs_synch,----------------
-      p3_lgth_i               => s_p3_lgth_synch, ----------------------
-      slone_i                 => s_slone_synch, 
-      nostat_i                => s_nostat_synch, 
-      var_o                   => s_var_from_control,
-      tx_start_prod_p_o       => s_start_prod_p , 
-      tx_byte_ready_p_o       => s_prod_byte_ready_p, 
-      tx_last_byte_p_o        => s_prod_last_byte_p, 
-      prod_cons_byte_index_o  => s_cons_prod_byte_index_from_control,
-      prod_data_length_o      => s_data_length_from_control,
-      rst_rx_unit_p_o         => s_rst_rx_unit_p
-      );
-      var1_rdy_o <= s_var1_rdy; 
-      var2_rdy_o <= s_var2_rdy; 
-      var3_rdy_o <= s_var3_rdy;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-  Consumption: WF_consumption
-  port map(
-    uclk_i                  => uclk_i,
-    slone_i                 => slone_i,
-    nfip_urst_i             => s_rst,
-    subs_i                  => s_subs_synch,
-    fd_rxd_i                => s_fd_rxd_synch,
-    fd_rxd_r_edge_p_i       => s_fd_rxd_r_edge_p,
-    fd_rxd_f_edge_p_i       => s_fd_rxd_f_edge_p,
-    wb_clk_i                => wclk_i,
-    wb_adr_i                => s_wb_adri_synch,
-    wb_stb_r_edge_p_i       => s_wb_stb_r_edge,
-    wb_cyc_i                => s_wb_cyc_synch,
-    var_i                   => s_var_from_control,
-    byte_index_i            => s_cons_prod_byte_index_from_control,
-    rst_rx_unit_p_i         => s_rst_rx_unit_p,
-    signif_edge_window_i    => s_signif_edge_window,
-    adjac_bits_window_i     => s_adjac_bits_window,
-    sample_bit_p_i          => s_rx_bit_clk_p,
-    sample_manch_bit_p_i    => s_rx_manch_clk_p,
-    ---------------------------------------------------------------
-    var1_rdy_o              => s_var1_rdy,
-    var2_rdy_o              => s_var2_rdy,
-    data_o                  => dat_o,
-    wb_ack_cons_p_o         => s_wb_ack_cons,
-    byte_o                  => s_rx_byte,
-    byte_ready_p_o          => s_rx_byte_ready,
-    fss_received_p_o        => s_cons_fss_decoded_p, 
-    crc_wrong_p_o           => s_crc_wrong_p,
-    fss_crc_fes_manch_ok_p_o => s_fss_crc_fes_manch_ok_p,
-    nfip_status_r_tler_o    => s_nfip_status_r_tler,
-    assert_rston_p_o        => s_assert_RSTON_p,
-    rst_nfip_and_fd_p_o     => s_reset_nFIP_and_FD_p,
-    rst_rx_osc_o            => s_rst_rx_osc
-    ---------------------------------------------------------------
-       );
---------------------------------------------------------------------------------------------------
-  rx_tx_osc :WF_rx_tx_osc
-    generic map(C_PERIODS_COUNTER_LENGTH => 11,
-                c_TX_CLK_BUFF_LGTH       => 4)
-    port map(
-      uclk_i                  => uclk_i,
-      nfip_urst_i             => s_rst, 
-      rxd_edge_i              => s_fd_rxd_edge_p,      
-      rst_rx_osc_i            => s_rst_rx_osc, 
-      rate_i                  => s_rate_synch,  
-      tx_clk_p_buff_o         => s_tx_clk_p_buff,
-      tx_clk_o                => fd_txck_o,
-      rx_manch_clk_p_o        => s_rx_manch_clk_p,
-      rx_bit_clk_p_o          => s_rx_bit_clk_p, 
-      rx_signif_edge_window_o => s_signif_edge_window,
-      rx_adjac_bits_window_o  => s_adjac_bits_window
-      );
---------------------------------------------------------------------------------------------------
-  Production: WF_production
-  port map(
-    uclk_i                  => uclk_i,
-    slone_i                 => slone_i,
-    nostat_i                => nostat_i,
-    nfip_urst_i             => s_rst,
-    wb_clk_i                => wclk_i,
-    wb_data_i               => s_wb_dati_synch,
-    wb_adr_i                => s_wb_adri_synch,
-    wb_stb_r_edge_p_i       => s_wb_stb_r_edge,
-    wb_we_i                 => s_wb_we_synch,
-    wb_cyc_i                => s_wb_cyc_synch,
-    slone_data_i            => s_slone_dati_synch,
-    var1_acc_i              => s_var1_access_synch,
-    var2_acc_i              => s_var2_access_synch,
-    var3_acc_i              => s_var3_access_synch,
-    fd_txer_i               => s_fd_txer_synch,
-    fd_wdgn_i               => s_fd_wdgn_synch,
-    var_i                   => s_var_from_control,
-    data_length_i           => s_data_length_from_control,
-    byte_index_i            => s_cons_prod_byte_index_from_control,
-    start_prod_p_i          => s_start_prod_p,
-    byte_ready_p_i          => s_prod_byte_ready_p,
-    last_byte_p_i           => s_prod_last_byte_p,
-    nfip_status_r_tler_i    => s_nfip_status_r_tler,
-    nfip_status_r_fcser_p_i => s_crc_wrong_p,
-    var1_rdy_i              => s_var1_rdy,
-    var2_rdy_i              => s_var2_rdy,
-    tx_clk_p_buff_i         => s_tx_clk_p_buff,
-    model_id_dec_i          => s_model_id_dec,
-    constr_id_dec_i         => s_constr_id_dec,
-    --------------------------------------------------------------------------
-    request_byte_p_o        => s_prod_request_byte_p,
-    tx_data_o               => fd_txd_o,
-    tx_enable_o             => fd_txena_o,
-    u_cacer_o               => u_cacer_o,
-    u_pacer_o               => u_pacer_o,
-    r_tler_o                => r_tler_o,
-    r_fcser_o               => r_fcser_o,
-    var3_rdy_o              => s_var3_rdy,
-    wb_ack_prod_p_o         => s_prod_ack
-    --------------------------------------------------------------------------
-       );
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
- model_constr_decoder : WF_model_constr_decoder 
-  port map(
-    uclk_i          => uclk_i,
-    nfip_urst_i     => s_rst,
-    model_id_i      => s_m_id_synch,--------------
-    constr_id_i     => s_c_id_synch,
-    select_id_o     => s_id_o,
-    model_id_dec_o  => s_model_id_dec,
-    constr_id_dec_o => s_constr_id_dec
-    );
---------------------------------------------------------------------------------------------------
-  synchronizer: WF_inputs_synchronizer
-  port map(
-    uclk_i            => uclk_i,
-    wb_clk_i          => wclk_i,
-    nfip_urst_i       => s_rst, 
-    rstin_a_i         => rstin_i,
-    wb_rst_a_i        => rst_i,
-    slone_a_i         => slone_i,
-    nostat_a_i        => nostat_i,
-    fd_wdgn_a_i       => fd_wdgn_i,
-    fd_txer_a_i       => fd_txer_i,
-    fd_rxd_a_i        => fd_rxd_i,
-    fd_rxcdn_a_i      => fd_rxcdn_i, 
-    wb_cyc_a_i        => cyc_i,
-    wb_we_a_i         => we_i,
-    wb_stb_a_i        => stb_i,
-    wb_adr_a_i        => adr_i,
-    var1_access_a_i   => var1_acc_i,
-    var2_access_a_i   => var2_acc_i,
-    var3_access_a_i   => var3_acc_i,
-    dat_a_i           => dat_i,
-    rate_a_i          => rate_i,
-    subs_a_i          => subs_i,
-    m_id_a_i          => m_id_i,
-    c_id_a_i          => c_id_i,
-    p3_lgth_a_i       => p3_lgth_i,
-    rsti_o            => s_urst_synch,
-    urst_r_edge_o     => s_urst_r_edge,
-    slone_o           => s_slone_synch,
-    nostat_o          => s_nostat_synch,
-    fd_wdgn_o         => s_fd_wdgn_synch,
-    fd_txer_o         => s_fd_txer_synch,
-    fd_rxd_o          => s_fd_rxd_synch,
-    fd_rxd_edge_p_o   => s_fd_rxd_edge_p,
-    fd_rxd_r_edge_p_o => s_fd_rxd_r_edge_p,
-    fd_rxd_f_edge_p_o => s_fd_rxd_f_edge_p, 
-    wb_cyc_o          => s_wb_cyc_synch,
-    wb_we_o           => s_wb_we_synch,
-    wb_stb_o          => s_wb_stb_synch,
-    wb_stb_r_edge_o   => s_wb_stb_r_edge,
-    wb_dati_o         => s_wb_dati_synch,
-    wb_adri_o         => s_wb_adri_synch,
-    var1_access_o     => s_var1_access_synch,
-    var2_access_o     => s_var2_access_synch,
-    var3_access_o     => s_var3_access_synch,
-    slone_dati_o      => s_slone_dati_synch,
-    rate_o            => s_rate_synch,
-    subs_o            => s_subs_synch,
-    m_id_o            => s_m_id_synch,
-    c_id_o            => s_c_id_synch,
-    p3_lgth_o         => s_p3_lgth_synch
-      );
---------------------------------------------------------------------------------------------------
-  ack_o   <= (s_prod_ack or s_wb_ack_cons); --and stb_i;  
-  s_ack_o <= s_prod_ack or s_wb_ack_cons;
---------------------------------------------------------------------------------------------------
-end architecture struc;
--=================================================================================================
--                                      architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
--                                    E N D   O F   F I L E
---------------------------------------------------------------------------------------------------=========================
\ No newline at end of file
--- a/wf_DualClkRAM_clka_rd_clkb_wr.vhd
+++ b/wf_DualClkRAM_clka_rd_clkb_wr.vhd
@@ -64,7 +64,7 @@ use IEEE.NUMERIC_STD.all;     --! conversion functions
 --------------------------------------------------------------------------------------------------- 
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -104,6 +104,7 @@ architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
 ---------------------------------------------------------------------------------------------------
 --!@brief: component DualClkRam declaration
  component DualClkRam is 
    port(
    CLKA   : in std_logic; 

--- a/wf_bits_to_txd.vhd
+++ b/wf_bits_to_txd.vhd
@@ -71,7 +71,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --------------------------------------------------------------------------------------------------- 
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                                    Sunplify Premier Warnings                                  --
+--                                    Synplify Premier Warnings                                  --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------

--- a/wf_cons_bytes_processor.vhd
+++ b/wf_cons_bytes_processor.vhd
@@ -29,7 +29,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 -- unit name:  WF_cons_bytes_processor
 --
 --! @brief     The unit is consuming the data bytes that are arriving from the WF_rx_deserializer,
--!            according to the following rules:
+--!            according to the following:
 --!
 --!            o If the consumed variable had been a var_1 or a var_2:
 --!
@@ -43,7 +43,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --!              identified and sent to the WF_reset_unit.
 --!
 --!            ------------------------------------------------------------------------------------
--!            Small Reminder:
+--!            Reminder:
 --!
 --!            Consumed RP_DAT frame structure :
 --!             ___________ ______  _______ ________ ________________ _______  ___________ _______
@@ -99,7 +99,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                                    Sunplify Premier Warnings                                  --
+--                                    Synplify Premier Warnings                                  --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -119,7 +119,7 @@ port (
    -- Signal from the WF_reset_unit
    nfip_urst_i           : in std_logic;                      --! nanoFIP internal reset
-    -- nanoFIP User Interface, WISHBONE Slave
+    -- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
    wb_clk_i              : in std_logic;                      --! WISHBONE clock
    wb_adr_i              : in  std_logic_vector (9 downto 0); --! WISHBONE address to memory
    wb_cyc_i              : in std_logic;                      --! WISHBONE cycle
@@ -178,7 +178,10 @@ begin
  two    <= to_unsigned (2, two'length);
---------------------------------------------------------------------------------------------------  
+---------------------------------------------------------------------------------------------------
+--                                  Consumed & Consumed Broadcast RAM                            --
+--                    Storage (by the unit) & retreival (by the user) of consumed bytes          --
+--------------------------------------------------------------------------------------------------- 
 -- !@brief Instantiation of a Dual Port Consumed RAM
 --! (for both the consumed and consumed broadcast variables)
@@ -213,38 +216,64 @@ begin
                                          else '0';
 ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Bytes_Consumption: Data bytes are consumed according to the
+--                                      Consumed bytes to DAT_O                                  --
--! variable type they belong.
+---------------------------------------------------------------------------------------------------
+--! @brief Instantiation of the unit responsible for the transfering of 2 de-serialized data bytes
+--! to DAT_O;
+  Consumed_Bytes_To_DATO: WF_cons_bytes_to_dato
+  port map(
+    uclk_i            => uclk_i, 
+    nfip_urst_i       => nfip_urst_i, 
+    transfer_byte_p_i => s_slone_write_byte_p,
+    byte_i            => byte_i,
+    ------------------------------------------
+    slone_data_o      => s_slone_data);
+    ------------------------------------------
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- -- -- --
+  -- In stand-alone mode the 16 bits DAT_O fills up with the output of the WF_cons_bytes_to_dato
+  -- unit.In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory
+   data_o <= s_slone_data when slone_i = '1'
+        else "00000000" & s_mem_data_out;  
--! In memory mode the treatment of a var1 is identical to the one of a var2; only the base address
+---------------------------------------------------------------------------------------------------
+--                                        Bytes Processing                                       --
+---------------------------------------------------------------------------------------------------
+--!@brief Combinatorial process Bytes_Processing: Data bytes are consumed according to the
+--! variable type (var_1, var_2, var_rst) they belong.
+--! In memory mode the treatment of a var_1 is identical to the one of a var2; only the base address
 --! of the memory differs.
--! Bytes are consumed even if the Control, PDU_TYPE, Length, CRC & FES bytes or the manch.
+--! Bytes are consumed even if any of the Control, PDU_TYPE, Length, CRC & FES byte or the manch.
 --! encoding of the consumed frame are incorrect.
 --! It is the VAR_RDY signal that signals the user for the validity of the consumed data.
 --! In memory mode, the incoming bytes (byte_i) after the Control byte and before the CRC bytes,
 --! are written in the memory one by one as they arrive, on the moments when the signal
 --! byte_ready_p_i is active.
--! The signals byte_index_i and Length (s_cons_lgth_byte) are used to coordinate which bytes are
+--! The signals byte_index_i and Length (s_cons_lgth_byte) are used to distinguish the Control and
--! written and which are not:
+--! CRC bytes from hte rest:
--! the Control byte, that arrives when byte_index_i = 0, is not written
+--!   o the Control byte arrives when byte_index_i = 0
--! and the CRC bytes are not written by checking the amount of bytes indicated by the Length byte.
+--!   o the CRC bytes arrive $Length bytes after the Length byte
+--! The byte_index_i signal is counting each byte after the FSS and before the FES.
--! The byte_index_i signal is counting each byte after the FSS and before the FES (therefore,
+--! The Length byte (s_cons_lgth_byte) is received from the WF_rx_deserializer when byte_index_i is
--! apart from all the pure data-bytes,it also includes the Control, PDU, Length, MPS & CRC bytes).
+--! equal to 3 and indicates the amount of bytes in the frame after the Control, PDU_TYPE and itself and
--! The Length byte (s_cons_lgth_byte) is received from the WF_rx_deserializer when byte_index_i is equal to 3
--! and indicates the amount of bytes in the frame after the Control, PDU_TYPE and itself and
 --! before the CRC.
 --! In stand-alone mode, in total two bytes of data have to be transferred to the data out bus. The
--! process manages the signal slone_write_byte_p which indicates which of the bytes of the bus
+--! process manages the signal slone_write_byte_p which indicates on which one of the bytes of the
--! (msb: 15 downto 8 or lsb: 7 downto 0) have to be written.
+--! bus (msb: 15 downto 8 or lsb: 7 downto 0) the new incoming byte has to be written.
 --! If the consumed variable is the reset one the process latches the first and second data bytes.
-Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
+Bytes_Processing: process (var_i, byte_index_i, slone_i, byte_i, two,
                            byte_ready_p_i, s_base_addr, s_cons_lgth_byte)
  begin
@@ -396,31 +425,14 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
 end process;
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the unit responsible for the transfering of 2 de-serialized data bytes
--! to DAT_O;
-  Consumed_Bytes_To_DATO: WF_cons_bytes_to_dato
-  port map(
-    uclk_i            => uclk_i, 
-    nfip_urst_i       => nfip_urst_i, 
-    transfer_byte_p_i => s_slone_write_byte_p,
-    byte_i            => byte_i,
-    ------------------------------------------
-    slone_data_o      => s_slone_data);
-    ------------------------------------------
--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- -- -- --
-  -- In stand-alone mode the 16 bits DAT_O fills up with the output of the WF_cons_bytes_to_dato
-  -- unit.In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory 
-   data_o <= s_slone_data when slone_i = '1'
-        else "00000000" & s_mem_data_out;  
+---------------------------------------------------------------------------------------------------
+--                                 Control, PDU_TYPE, Length bytes                               --
 ---------------------------------------------------------------------------------------------------
 --!@brief Synchronous process Buffer_Ctrl_PDU_Length_bytes: Storage of the Control, PDU_TYPE
--! and Length bytes of an incoming RP_DAT frame. The bytes are sent to the WF_cons_outcome
+--! and Length bytes of an incoming RP_DAT frame. The bytes are sent to the WF_cons_frame_validator
--! unit that accordingly enables or not the signals VAR1_RDY (for a var1), VAR2_RDY (for a var2),
+--! unit that validates them and accordingly signals the WF_outcome unit for the activation of the
--! assert_rston_p and rst_nfip_and_fd_p (for a var_rst).
+--! VAR1_RDY(for a var_1), VAR2_RDY(for a var_2), assert_rston_p & rst_nfip_and_fd_p(for a var_rst).
 Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
  begin                                               

--- a/wf_cons_bytes_to_dato.vhd
+++ b/wf_cons_bytes_to_dato.vhd
@@ -28,14 +28,14 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --
 --
 --! @brief     In stand-alone mode, after the reception of a consumed or consumed broadcast
--!            variable, the unit is responsible for transering the two data-bytes of the variable
+--!            variable, the unit is responsible for transering the two pure-data bytes to the
--!            to the 2-bytes long bus DAT_O.
+--!            2-bytes long bus DAT_O.
 --!            The bytes are put in the bus one by one as they arrive, as the signal 
 --!            transfer_byte_p_i indicates.
 --!
 --!            Note: The validity of these transfered bytes is indicated by the "nanoFIP
--!            User Interface, NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY which arrive after
+--!            User Interface, NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY which arrive later, after
--!            the reception of the FCS and FES bytes.  
+--!            the end of the reception of the consumed frame.  
 --
 --
 --! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
@@ -122,6 +122,7 @@ begin
 --!@brief synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, accrording to the signal
 --! transfer_byte_p_i, the first or second byte of the user interface bus DAT_O takes the
 --! incoming byte byte_i.
 Data_Transfer_To_Dat_o: process (uclk_i) 
  begin
    if rising_edge (uclk_i) then

--- a/wf_cons_frame_validator.vhd
+++ b/wf_cons_frame_validator.vhd
@@ -74,7 +74,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --------------------------------------------------------------------------------------------------- 
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 -- "W CL246  Input port bits 0, 2, 5, 6 of var_i(0 to 6) are unused"                             --
 -- var_i is one-hot encoded and has 7 values.                                                    -- 
@@ -130,11 +130,11 @@ begin
 --------------------------------------------------------------------------------------------------- 
 --!@brief Combinatorial process Consumed_Frame_Validator: validation of an RP_DAT 
--! frame with respect to: Ctrl, PDU, Length bytes as well as CRC, FSS, FES and code violations.
+--! frame with respect to the Ctrl, PDU_TYPE and Length bytes as well as to the CRC, FSS, FES and
--! The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that arrive at the beginning of a
+--! to the manchester encoding. The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that
--! frame, have been registered and keep their values until the end of a frame.
+--! arrive at the beginning of a frame, have been registered and keep their values until the end
--! The signal rx_fss_crc_fes_manch_ok_p_i, is a pulse at the end of the FES that combines
+--! of it. The signal rx_fss_crc_fes_manch_ok_p_i, is a pulse at the end of the FES that combines
--! the check of the FSS, CRC, FES and the code violations. 
+--! the checks of the FSS, CRC, FES and of the manch. encoding. 
 Consumed_Frame_Validator: process (var_i, cons_ctrl_byte_i, rx_byte_index_i, cons_pdu_byte_i,
                                    rx_fss_crc_fes_manch_ok_p_i, cons_lgth_byte_i)
@@ -191,8 +191,10 @@ begin
 end process;            
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- -- -
-  -- Concurrent signal assignment for the output signals
+  -- Concurrent signal assignments 
  cons_frame_ok_p_o          <= rx_fss_crc_fes_manch_ok_p_i and
                                s_cons_lgth_byte_ok         and
                                s_cons_ctrl_byte_ok         and
@@ -202,6 +204,7 @@ end process;
                                s_cons_ctrl_byte_ok         and
                                s_cons_pdu_byte_ok;
 end architecture rtl;
 --=================================================================================================
 --                                      architecture end

--- a/wf_cons_outcome.vhd
+++ b/wf_cons_outcome.vhd
@@ -28,14 +28,10 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --
 --
 --! @brief     According to the consumed variable that has been received (var_1, var_2, var_rst)
--!            the unit generates the signals:
+--!            and the outcome of the WF_cons_frame_VALIDATOR, the unit generates the signals:
 --!
 --!              o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY,
--!                according to the variable that is being treated (var_i) and to the
+--!              o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the WF_reset_unit.    
--!                "correct frame" indicator, cons_frame_ok_p_i.
--!
--!              o rst_nFIP_and_FD_p and assert_RSTON_p, according to the data bytes received and to
--!                the "correct frame" indicator, cons_frame_ok_p_i.    
 --
 --
 --! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
@@ -69,7 +65,6 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --------------------------------------------------------------------------------------------------- 
 --
 --! @todo 
--!   -> rename the unit to include actions for var reset. 
 --
 --------------------------------------------------------------------------------------------------- 
@@ -146,37 +141,35 @@ begin
 --! Memory Mode:
  --! Since the three memories (consumed, consumed broadcast, produced) are independant, when a
-  --! produced var is being sent, the user can read form the consumed memories; similarly, when a
+  --! produced var. is being sent, the user can read form the consumed memories; similarly, when a
-  --! consumed variable is being received the user can write to the produced momory.
+  --! consumed var. is being received the user can read from the consumed broadcast memory.
-  --! VAR1_RDY (for consumed vars): signals that the user can safely read from the consumed
+  --! VAR1_RDY (for consumed vars): signals that the user can safely read from the consumed memory.
-  --! variable memory. The signal is asserted only after the reception of a correct RP_DAT frame.
+  --! The signal is asserted only after the reception of a correct RP_DAT frame.
-  --! It is de-asserted after the reception of a correct var1 ID_DAT frame. 
+  --! It is de-asserted after the reception of a correct var_1 ID_DAT frame. 
  --! VAR2_RDY (for broadcast consumed vars): signals that the user can safely read from the
-  --! consumed broadcast variable memory. The signal is asserted only after the reception of a 
+  --! consumed broadcast memory. The signal is asserted only after the reception of a correct
-  --! correct consumed broadcast RP_DAT frame. It is de-asserted after the reception of a correct
+  --! consumed broadcast RP_DAT frame. It is de-asserted after the reception of a correct var_2
-  --! var2 ID_DAT frame. 
+  --! ID_DAT frame. 
 --! Stand-alone Mode:
-  --! In stand-alone mode, the DAT_I and DAT_O buses for the produced and the consumed bytes 
+  --! Similarly, in stand-alone mode, the DAT_I and DAT_O buses for the produced and the consumed 
-  --! are independant. Stand-alone mode does not treat the consumed broadcast variable.
+  --! bytes are independant. Stand-alone mode though does not treat the consumed broadcast variable.
  --! VAR1_RDY (for consumed vars): signals that the user can safely retreive data from the DAT_O
  --! bus. The signal is asserted only after the reception of a correct RP_DAT frame.
-  --! It is de-asserted after the reception of a correct var1 ID_DAT frame(same as in memory mode).
+  --! It is de-asserted after the reception of a correct var_1 ID_DAT frame(same as in memory mode).
  --! VAR2_RDY (for broadcast consumed vars): stays always deasserted.
 --! Note: A correct consumed RP_DAT frame is signaled by the cons_frame_ok_p_i, whereas a correct
 --! ID_DAT frame along with the variable it contained is signaled by the var_i.
--! For consumed variables, var_i gets its value (var1, var2, var_rst) after the reception of a
+--! For consumed variables, var_i gets its value (var_1, var_2, var_rst) after the reception of a
 --! correct ID_DAT frame and of a correct FSS of the corresponding RP_DAT frame and it retains it
 --! unitl the end of the reception.
  VAR_RDY_Generation: process (uclk_i) 
  begin
    if rising_edge (uclk_i) then
@@ -192,7 +185,7 @@ begin
        when var_1 =>                              -- nanoFIP consuming
                                                   --------------------   
-          var1_rdy_o        <= '0';                -- while consuming a var1, VAR1_RDY is 0
+          var1_rdy_o        <= '0';                -- while consuming a var_1, VAR1_RDY is 0
          var2_rdy_o        <= s_var2_received;    -- VAR2_RDY retains its value
@@ -208,7 +201,7 @@ begin
      --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --
        when var_2 =>                             -- nanoFIP consuming broadcast     
                                                  ------------------------------ 
-          var2_rdy_o        <= '0';               -- while consuming a var2, VAR2_RDY is 0
+          var2_rdy_o        <= '0';               -- while consuming a var_2, VAR2_RDY is 0
          var1_rdy_o        <= s_var1_received;   -- VAR1_RDY retains its value
          if slone_i = '0' and cons_frame_ok_p_d1 = '1' then        
@@ -250,14 +243,14 @@ begin
    end if;
  end process;
---------------------------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------------------------
 --!@ brief: Generation of the signals s_rst_nfip_and_fd : signals that the 1st byte of a consumed 
 --!                                                        reset var contains the station address   
 --!                                  and s_assert_rston : signals that the 2nd byte of a consumed
 --!                                                        reset var contains the station address 
-  Reset_Signals: process (uclk_i) 
+  Cons_Reset_Signals: process (uclk_i) 
  begin
    if rising_edge (uclk_i) then

--- a/wf_consumption.vhd
+++ b/wf_consumption.vhd
@@ -27,7 +27,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     The unit gathers the main nanoFIP actions with respect to data consumption.
+--! @brief     The unit gathers the main actions that regard data consumption.
 --!            It instantiates the units:
 --!
 --!              o WF_rx_deglitcher        : for the filtering of the "nanoFIP FIELDRIVE"
@@ -36,41 +36,42 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --!              o WF_cons_bytes_processor : for the manipulation of the data as they arrive (mainly
 --!                                          registering them to the RAM or putting them to DAT_O)
 --!              o WF_cons_frame_validator : for the validation of the consumed frame, at the end of
--!                                          of its arrival (checking mainly the CRC & manch. encoding)
+--!                                          of its arrival (in terms of FSS, Ctrl, PDU_TYPE, Lgth,
--!              o WF_cons_outcome         : for the treatment of the "nanoFIP User Interface, NON-
+--!                                          CRC bytes & manch. encoding)
+--!              o WF_cons_outcome         : for the generation of the "nanoFIP User Interface, NON-
 --!                                          WISHBONE" outputs VAR1_RDY and VAR2_RDY (for var_1, var_2)
 --!                                          or of the internal signals for the nanoFIP and FIELDRIVE
 --!                                          resets (for a var_rst)  
 --!
--!                            _________________________________
+--!                                __       _________________________________
--!                           |                                 | 
+--!                               |        |                                 | 
--!                           |         WF_cons_outcome         | 
+--!                               |        |         WF_cons_outcome         | 
--!                           |_________________________________|
+--!                               |        |_________________________________|
--!                                           ^
+--!                           Level 2                       ^
--!                            _________________________________
+--!                               |         _________________________________
--!                           |                                 | 
+--!                               |        |                                 | 
--!                           |     WF_cons_frame_validator     | 
+--!                               |        |     WF_cons_frame_validator     | 
--!                           |_________________________________|
+--!                               |__      |_________________________________|
--!                                            ^
+--!                                                         ^
--!                            _________________________________
+--!                                __       _________________________________
--!                           |                                 | 
+--!                               |        |                                 | 
--!                           |      WF_cons_bytes_processor    |
+--!                           Level 1      |      WF_cons_bytes_processor    |
--!                           |                                 | 
+--!                               |        |                                 | 
--!                           |_________________________________|
+--!                               |__      |_________________________________|
--!                                            ^
+--!                                                         ^
--!                            _________________________________
+--!                                __       _________________________________
--!                           |                                 | 
+--!                               |        |                                 | 
--!                           |        WF_rx_deserializer       |
+--!                               |        |        WF_rx_deserializer       |
--!                           |                                 | 
+--!                               |        |                                 | 
--!                           |_________________________________|
+--!                               |        |_________________________________|
--!                                            ^
+--!                            Level 0                      ^
--!                            _________________________________
+--!                               |         _________________________________
--!                           |                                 | 
+--!                               |        |                                 | 
--!                           |         WF_rx_deglitcher        |
+--!                               |        |         WF_rx_deglitcher        |
--!                           |_________________________________|
+--!                               |__      |_________________________________|
--!
+--! 
--!             _______________________________________________________________
+--!                          _______________________________________________________________
--!            0__________________________FIELDBUS____________________________O    
+--!                         0__________________________FIELDBUS____________________________O    
 --1
 --!
 --!            Note: In the entity declaration of this unit, below each input signal, we mark
@@ -112,7 +113,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --------------------------------------------------------------------------------------------------- 
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings!                                          --
 ---------------------------------------------------------------------------------------------------
@@ -253,7 +254,8 @@ begin
 --                               Consumption Level 0: Deglitcher                                 --
 ---------------------------------------------------------------------------------------------------
 --! @brief Instantiation of the WF_rx_deglitcher unit that applies a glitch filter to the "nanoFIP
--! FIELDRIVE" input signal fd_rxd
+--! FIELDRIVE" input signal fd_rxd.
  Consumption_Level_0_Deglitcher : WF_rx_deglitcher 
  generic map (c_DEGLITCH_LGTH => 10)
  port map(
@@ -275,6 +277,7 @@ begin
 --------------------------------------------------------------------------------------------------- 
 --! @brief Instantiation of the WF_rx_deserializer unit that deserializes the deglitched fd_rxd
 --! and constructs bytes of data.
  Consumption_Level_0_Deserializer: WF_rx_deserializer 
  port map (
    uclk_i                   => uclk_i,
@@ -304,6 +307,7 @@ begin
 --! @brief Instantiation of the WF_cons_bytes_processor unit that is "consuming" data bytes
 --! arriving from the WF_rx_deserializer, by registering them to the Consumed memories or by
 --! transferring them to the "nanoFIP User Interface, NON_WISHBONE" output bus DAT_O.
  Consumption_Level_1_bytes_processor : WF_cons_bytes_processor 
  port map(
    uclk_i                => uclk_i,
@@ -334,6 +338,7 @@ begin
 --! @brief Instantiation of the WF_cons_frame_validator unit, responsible for the validation of a
 --! received RP_DAT frame with respect to the correctness of the Control, PDU_TYPE and Length
 --! bytes of the Manchester encoding.
  Consumption_Level_2_Frame_Validator: WF_cons_frame_validator
  port map(
    cons_ctrl_byte_i            => s_cons_ctrl_byte, 
@@ -354,7 +359,8 @@ begin
 --------------------------------------------------------------------------------------------------- 
 --! @brief Instantiation of the WF_cons_outcome unit that is generating :
 --! the "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY & VAR2_RDY (for a var_1/2)
--! or the nanoFIP internal signals rst_nFIP_and_FD_p and assert_RSTON_p          (for a var_rst)
+--! or the nanoFIP internal signals rst_nFIP_and_FD_p and assert_RSTON_p          (for a var_rst).
  Consumption_Level_2_Outcome : WF_cons_outcome
  port map (
    uclk_i                => uclk_i,

--- a/wf_crc.vhd
+++ b/wf_crc.vhd
@@ -27,8 +27,9 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     The unit includes the modules for the generation of the CRC of serial data,
+--! @brief     The unit creates the modules:
--!            as well as for the verification of an incoming CRC syndrome.
+--!              o for the generation of the CRC of serial data,
+--!              o for the verification of an incoming CRC syndrome.
 --
 --
 --! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
@@ -68,7 +69,7 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -78,7 +79,7 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 --!                                 Entity declaration for WF_crc
 --=================================================================================================
 entity WF_crc is
-generic (c_GENERATOR_POLY_length : natural := 16);   --! default value
+generic (c_GENERATOR_POLY_length : natural := 16);  --! default value
 port (
  -- INPUTS 
    -- nanoFIP User Interface, General signals
@@ -89,13 +90,13 @@ port (
    -- Signals from the WF_rx_deserializer/ WF_tx_serializer units
    data_bit_i         : in std_logic;              --! incoming data bit stream
-    data_bit_ready_p_i : in std_logic;              --! indicator of sampling time for data_bit_i
+    data_bit_ready_p_i : in std_logic;              --! indicates the sampling moment of data_bit_i
    start_crc_p_i      : in std_logic;              --! beginning of the CRC calculation
  -- OUTPUTS 
    -- Signal to the WF_rx_deserializer unit
-    crc_ok_p           : out std_logic;             --! signaling of a correct received CRC syndrome
+    crc_ok_p           : out std_logic;             --! signals a correct received CRC syndrome
    -- Signal to the WF_tx_serializer unit
    crc_o              : out  std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
@@ -172,8 +173,8 @@ crc_o <= not s_q;
 --!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
 --! calculated as data is arriving (same as in the transmission) and it is being compared to the
 --! predefined c_VERIFICATION_MASK. When the CRC calculated from the received data matches the
--! c_VERIFICATION_MASK, it is implied that a correct CRC word has been received and the signal
+--! c_VERIFICATION_MASK, it is implied that a correct CRC word has been received for the preceded
--! crc_ok_p gives a pulse. 
+--! data and the signal crc_ok_p gives a pulse. 
 Syndrome_Verification: process (s_q, s_crc_bit_ready_p)

--- a/wf_decr_counter.vhd
+++ b/wf_decr_counter.vhd
@@ -57,7 +57,7 @@ use IEEE.NUMERIC_STD.all;     --! conversion functions
 --------------------------------------------------------------------------------------------------- 
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -105,6 +105,7 @@ begin
 ---------------------------------------------------------------------------------------------------
  -- Synchronous process Decr_Counter
  Decr_Counter: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
@@ -124,8 +125,10 @@ begin
    end if;
  end process;
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
  -- Concurrent assignments for output signals
  counter_o         <= s_counter;
  counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';

--- a/wf_engine_control.vhd
+++ b/wf_engine_control.vhd
@@ -27,33 +27,29 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     The WF_engine_control is the coordinator of the main units: WF_consumption,
+--! @brief     The WF_engine_control is following the reception of an incoming ID_DAT frame and
--!            WF_production and WF_reset_unit. It follows the reception of an incoming ID_DAT
+--!              o identifies the variable to be treated
--!            frame and accordingly can activate the transmitter WF_tx_serializer (if a frame has
+--!              o signals accordingly the WF_production and WF_consumption units.
--!            to be produced) or reset the receiver WF_rx_deserializer (if the reception has to
--!            be reinitialized) or inform the WF_reset_unit to reset the nanoFIP or the FIELDRIVE
--!            (if a consumed reset variable has arrived). Therefore, it is responsible for all 
--!            information traffic between the WF_consumption unit and the units WF_production and
--!            WF_reset_unit (in detail it provides all the information to the WF_production for
--!            the nanoFIP status byte and to the WF_reset_unit it provides the signals
--!            assert_rston_p and rst_nfip_and_fd_p).
 --!            Its main output var_i is crucial for the units WF_cons_bytes_processor and
 --!            WF_prod_bytes_retriever as it defines the structure of the frames that are expected
--!            to arrive or to be produced.   
+--!            to arrive or to be produced.
--!            Finally it is in charge of generation of the nanoFIP User Interface, NON_WISHBONE
--!            VAR_RDY signals.
 --!
 --!            ------------------------------------------------------------------------------------
--!            Few Reminders
+--!            Reminder
 --!
 --!            ID_DAT frame structure :
 --!             ___________ ______  _______ ______  ___________ _______
 --!            |____FSS____|_Ctrl_||__Var__|_Subs_||____FCS____|__FES__|
 --! 
 --!
--!            RP_DAT frame structure :
+--!            Produced RP_DAT frame structure :
--!             ___________ ______  _______ ________ _________________ ____________ _______  ___________ _______
+--!             ___________ ______  _______ ______ _________________ _______ _______  ___________ _______
--!            |____FSS____|_Ctrl_||__PDU__|__LGTH__|__..User-Data..__|_nFIPstatus_|__MPS__||____FCS____|__FES__|
+--!            |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
+--!
+--!
+--!            Consumed RP_DAT frame structure :
+--!             ___________ ______  _______ ______ _________________________ _______  ___________ _______
+--!            |____FSS____|_Ctrl_||__PDU__|_LGTH_|______..Pure-Data..______|__MPS__||____FCS____|__FES__|
 --!
 --!
 --!            Turnaround time : Time between the end of the reception of an ID_DAT frame
@@ -93,13 +89,9 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 --!                         state consume_wait_FSS, for the correct use of the silence time(time
 --!                         stops counting when an RP_DAT frame has started)
 --!                         
--!     12/2010  v0.03  EG  removed check on slone mode for #bytes>4;
+--!     12/2010  v0.02  EG  removed check on slone mode for #bytes>4;
 --!                         in slone no broadcast
--!     01/2011  v0.04  EG  signals named according to their origin
+--!     01/2011  v0.03  EG  signals named according to their origin; signals removed....
--!                         signals removed for simplification; they were added to the
--!                         WF_consumption & WF_production units: var1,2,3_rdy, assert_rston,
--!                         rst_nfip_and_fd, nfip_status_r_tler, nfip_status_fcser,rst-status_bytes
--!                         rx_byte_ready_p.
 --
 ---------------------------------------------------------------------------------------------------
 --
@@ -108,7 +100,7 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -215,25 +207,17 @@ architecture rtl of WF_engine_control is
  signal control_st, nx_control_st  : control_st_t;
  signal s_var_aux, s_var, s_var_id : t_var;
+  signal s_time_c_is_zero, s_broadcast_var, s_tx_start_prod_p, s_inc_rx_bytes_counter  : std_logic;
-  signal s_tx_byte_ready_p_d1 :           std_logic;
+  signal s_producing, s_consuming, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter  : std_logic;
-  signal s_load_time_counter, s_tx_byte_ready_p_d2 :        std_logic;
+  signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_cons_wait_FSS          : std_logic;
-  signal s_tx_start_prod_p :               std_logic;
+  signal s_prod_data_length_match, s_tx_byte_ready_p, s_prod_wait_turnar_time          : std_logic;
-  signal s_time_c_is_zero, s_broadcast_var :                           std_logic;
+  signal s_tx_byte_ready_p_d1, s_load_time_counter, s_tx_byte_ready_p_d2               : std_logic;
-  signal s_inc_rx_bytes_counter, s_tx_last_byte_p :std_logic;
+  signal s_rst_rx_bytes_counter, s_tx_last_byte_p_d, s_tx_last_byte_p                  : std_logic;
-  signal s_prod_data_length_match, s_tx_byte_ready_p :std_logic;
+  signal s_id_dat_subs_byte, s_id_dat_frame_ok                                         : std_logic;
-  signal s_rx_bytes_c, s_prod_bytes_c :  unsigned(7 downto 0);
+  signal s_rx_bytes_c, s_prod_bytes_c                                      : unsigned (7 downto 0);
-  signal s_prod_data_length :      std_logic_vector(7 downto 0);
+  signal s_time_counter_top, s_time_c, s_turnaround_time, s_silence_time   : unsigned(14 downto 0);
-  signal s_time_counter_top, s_time_c:                                 unsigned(14 downto 0); 
+  signal s_prod_data_length, s_tx_byte_index, s_rx_byte_index      : std_logic_vector (7 downto 0);
-  signal s_turnaround_time, s_silence_time :                             unsigned(14 downto 0);
+  signal s_produce_or_consume                                      : std_logic_vector (1 downto 0);
-  signal s_produce_or_consume :                                        std_logic_vector (1 downto 0);
-  signal s_id_dat_subs_byte, s_id_dat_frame_ok : std_logic;
-  signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_cons_wait_FSS: std_logic;
-  signal s_prod_wait_turnar_time, s_producing, s_consuming :                                  std_logic;
-  signal s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
-  signal s_rst_rx_bytes_counter, s_tx_last_byte_p_d: std_logic;
-  signal s_tx_byte_index, s_rx_byte_index :        std_logic_vector (7 downto 0);
 --=================================================================================================
@@ -576,7 +560,8 @@ begin
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
 --! @brief Instantiation of the WF_prod_data_lgth_calc unit that calculates the total amount of
 --! data-bytes that have to be transferred when a variable is produced (including the
--! RP_DAT.Control, RP_DAT.Data.MPS_status and RP_DAT.Data.nanoFIP_status bytes)
+--! RP_DAT.Control, RP_DAT.Data.MPS_status and RP_DAT.Data.nanoFIP_status bytes).
  Produced_Data_Length_Calculator: WF_prod_data_lgth_calc
  port map(
    slone_i            => slone_i,             
@@ -592,6 +577,7 @@ begin
 --! @brief Instantiation of a WF_incr_counter for the counting of the number of the bytes that are
 --! being produced. The counter is reset at the "produce_wait_turnar_time" state of the FSM and
 --! counts bytes following the "tx_request_byte_p_i" pulse in the "produce" state.
  Produced_Bytes_Counter: WF_incr_counter
  generic map(g_counter_lgth => 8)
  port map(
@@ -621,6 +607,7 @@ begin
 --! following the "rx_byte_ready_p_i" pulse in the "id_dat_frame_ok" state.
 --! Regarding a RP_DAT frame  : the counter is reset at the "consume_wait_FSS" state and counts
 --! bytes following the "rx_byte_ready_p_i" pulse in the "consume" state.
  Rx_Bytes_Counter: WF_incr_counter
  generic map(g_counter_lgth => 8)
  port map(
@@ -638,6 +625,7 @@ begin
 --! @brief Combinatorial process Arguments_For_Both_Bytes_Counters: The process gives values to
 --! the signals reinit_counter_i and incr_counter_i of the Produced_Bytes_Counter and 
 --! Rx_Bytes_Counter according to the state of the FSM.
  Arguments_For_Both_Bytes_Counters: process (s_id_dat_frame_ok, s_consuming, tx_request_byte_p_i,
                                     s_producing, rx_byte_ready_p_i, s_rx_bytes_c, s_prod_bytes_c)
  begin
@@ -696,6 +684,7 @@ begin
 --! the identified variable is a produced one the counter loads to the turnaround time, whereas if
 --! it had been a consumed variable it loads to the silence. The counting takes place during the
 --! states "produce_wait_turnar_time" and "consume_wait_FSS" respectively.
  Turnaround_and_Silence_Time_Counter: WF_decr_counter
  generic map(g_counter_lgth => 15)
  port map(
@@ -723,6 +712,7 @@ begin
 --! @brief Combinatorial process Turnaround_and_Silence_Time_Counter_Arg: The process gives values
 --! to the counter_top and counter_load_i inputs of the Turnaround_and_Silence_Time_Counter,
 --! according to the state of the FSM and the type of received variable (s_produce_or_consume).
  Turnaround_and_Silence_Time_Counter_Arg: process (s_prod_wait_turnar_time, s_turnaround_time,
                                                    s_id_dat_frame_ok, s_produce_or_consume,
                                                    s_cons_wait_FSS, s_silence_time)
@@ -812,6 +802,7 @@ begin
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
 --!@brief: Combinatorial process Var_Characteristics: management of the signals
 --! s_produce_or_consume and s_broadcast_var, according to the value of s_var_aux.
  Var_Characteristics: process (s_var_aux)
  begin
    s_produce_or_consume       <= "00";

--- a/wf_incr_counter.vhd
+++ b/wf_incr_counter.vhd
@@ -102,6 +102,7 @@ begin
 --------------------------------------------------------------------------------------------------- 
  -- Synchronous process Incr_Counter
  Incr_Counter: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
@@ -119,8 +120,10 @@ begin
    end if;
  end process;
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
  -- Concurrent assignments for output signals
  counter_o         <= s_counter;
  counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';

--- a/wf_inputs_synchronizer.vhd
+++ b/wf_inputs_synchronizer.vhd
@@ -69,7 +69,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --------------------------------------------------------------------------------------------------- 
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -99,7 +99,7 @@ entity WF_inputs_synchronizer is
    rate_a_i          : in std_logic_vector(1 downto 0);
    subs_a_i          : in std_logic_vector(7 downto 0);
-    -- nanoFIP User Interface, WISHBONE Slave 
+    -- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk) 
    wb_clk_i          : in std_logic;                   --! WISHBONE clock
    dat_a_i           : in std_logic_vector(15 downto 0);
    wb_adr_a_i        : in std_logic_vector(9 downto 0);
@@ -134,7 +134,7 @@ entity WF_inputs_synchronizer is
    rate_o            : out std_logic_vector(1 downto 0);
    subs_o            : out std_logic_vector(7 downto 0);
-    -- nanoFIP User Interface, WISHBONE Slave 
+    -- nanoFIP User Interface, WISHBONE Slave
    wb_adri_o         : out std_logic_vector(9 downto 0);
    wb_cyc_o          : out std_logic;
    wb_dati_o         : out std_logic_vector(7 downto 0);
@@ -417,7 +417,6 @@ begin
  p3_lgth_o         <= s_p3_lgth_d3;
--------------------------------------------------------------------------------------------------
 end architecture rtl;
 --=================================================================================================

--- a/wf_manch_code_viol_check.vhd
+++ b/wf_manch_code_viol_check.vhd
@@ -7,7 +7,7 @@
 --________________________________________________________________________________________________|
 ---------------------------------------------------------------------------------------------------
--! @file WF_rx_manch_code_check.vhd                                                            |
+--! @file WF_rx_manch_code_check.vhd                                                              |
 ---------------------------------------------------------------------------------------------------
 --! standard library
@@ -31,15 +31,22 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --!            Manchester 2 (manch.) code violation is detected.
 --!            It is assumed that a violation happens if after a half-bit-clock period (plus 2 uclk
 --!            periods), the incoming signal has not had a transition.
--!            Note: the term sample_manch_bit_p refers to the moments when a manch. encoded bit
+--!
--!            should be sampled (before and after a significant edge), whereas the 
+--!            Remark: We refer to
--!            sample_bit_p includes only the sampling of the 1st part, before the transition. 
+--!              o a significant edge                : for the edge of a manch. encoded bit
--!            Example:
+--!                (bit 0: __|--, bit 1: --|__)
--!                    bit                : 0 
+--!              o the sampling of a manch. bit      : for the moments when a manch. encoded bit
--!                    manch. encoded     : _|-
+--!                should be sampled, before and after a significant edge. The period of this
--!                    sample_manch_bit_p : ^ ^
+--!                sampling is that of the half-bit-clock.
--!                    sample_bit_p       : ^    (this sampling will give the 0)
+--!              o the sampling of a bit             : for the sampling of only the 1st part,
+--!                before the transition (the period is the double of the manch. sampling) 
+--!
+--!                Example:
+--!                  bits               :   0     1 
+--!                  manch. encoded     : __|-- --|__
+--!                  significant edge   :  ^     ^
+--!                  sample_manch_bit_p :  ^ ^   ^ ^ 
+--!                  sample_bit_p       :  ^     ^   (this sampling will give the 0 and the 1)
 --
 --
 --! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
@@ -116,8 +123,7 @@ begin
 ---------------------------------------------------------------------------------------------------
 --!@brief Synchronous process Check_Code_Violations: in order to check for code violations, the
 --! input signal is delayed by half-bit-clock period (serial_input_signal_d).
--! The signal check_code_viol_p is a pulse occuring 2 uclk periods after a manch. transition is
+--! The signal check_code_viol_p is a pulse occuring 2 uclk periods after a manch. edge is expected.
--! expected.
 --! As the following drawing roughly indicates, a violation exists if the signal and its delayed
 --! version are identical on the check_code_viol_p moments.
@@ -150,6 +156,7 @@ begin
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
  -- Concurrent signal assignment
  manch_code_viol_p_o                <= s_check_code_viol_p and 
                                        (not (serial_input_signal_i xor s_serial_input_signal_d));

--- a/wf_manch_encoder.vhd
+++ b/wf_manch_encoder.vhd
@@ -64,7 +64,7 @@ use IEEE.NUMERIC_STD.all;     --! conversion functions
 --------------------------------------------------------------------------------------------------- 
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------

--- a/wf_model_constr_decoder.vhd
+++ b/wf_model_constr_decoder.vhd
@@ -77,7 +77,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -141,7 +141,6 @@ begin
 --! s_constr_stage1. On a third uclk tick the loaded odd and even values are combined to give
 --! the decoded outputs (model_id_dec_o & constr_id_dec_o).
  Model_Constructor_Decoder: process (uclk_i)
  begin
    if rising_edge (uclk_i) then                    -- initializations
@@ -178,8 +177,10 @@ begin
    end if;
  end process;
 ---------------------------------------------------------------------------------------------------
 --!@brief Instantiation of a counter WF_incr_counter
  Free_Counter: WF_incr_counter
  generic map(g_counter_lgth => 2)
  port map(
@@ -195,6 +196,7 @@ begin
 ---------------------------------------------------------------------------------------------------
 --!@brief Concurrent signal assignment for the output select_id_o
  select_id_o <=  ((not s_counter(0)) & s_counter(0)); -- 2 opposite clocks generated using
                                                       -- the LSB of the counter 
                                                       -- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_

--- a/wf_package.vhd
+++ b/wf_package.vhd
@@ -179,9 +179,9 @@ package WF_package is
  constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned := 
                          to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
-  constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
+  constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned    :=
                          to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
-  constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned :=
+  constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned  :=
                          to_unsigned((400 /integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
  -- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
@@ -193,6 +193,9 @@ package WF_package is
                           2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
                           3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
+  constant c_2_PERIODS_COUNTER_LENGTH : natural := 12;-- length of a counter counting 4 reception/
+                                                      -- transmission period
 ---------------------------------------------------------------------------------------------------
 --                     Constants & Types regarding the turnaround and silence times              --
@@ -678,11 +681,11 @@ end component WF_production;
  component WF_reset_unit 
  port (
    uclk_i              : in std_logic; 
-    urst_i              : in  std_logic; 
+    rstin_i             : in std_logic; 
-    rate_i              : in std_logic_vector (1 downto 0);
    urst_r_edge_i       : in std_logic;
+    rstpon_i            : in std_logic;
+    rate_i              : in std_logic_vector (1 downto 0);
    var_i               : in t_var;    
-    subs_i              : in  std_logic_vector (7 downto 0);
    rst_nFIP_and_FD_p_i : in std_logic;
    assert_RSTON_p_i    : in std_logic;
    ---------------------------------------------------------------

--- a/wf_prod_bytes_retriever.vhd
+++ b/wf_prod_bytes_retriever.vhd
@@ -447,6 +447,7 @@ begin
 --!@brief Synchronous process Delay_mem_wr_en: since the input buses wb_data_i and wb_addr_i are
 --! the triply buffered versions of the DAT_I and ADR_I, the signal write_en_portb_i has to be delayed
 --! too. As write_en_portb_i we use the wb_ack_prod_p signal.
  Delay_mem_wr_en: process (wb_clk_i) 
  begin
    if rising_edge (wb_clk_i) then

--- a/wf_prod_data_lgth_calc.vhd
+++ b/wf_prod_data_lgth_calc.vhd
@@ -27,13 +27,25 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     Calculation of the total amount of data bytes that have to be transferreed when a
+--! @brief     Calculation of the total amount of bytes, after the FSS and before the FCS, that
--!            variable is produced (including the RP_DAT.Control, RP_DAT.Data.MPS_status and
+--!            have to be transferreed when a variable is produced. In detail, the calculation
--!            RP_DAT.Data.nanoFIP_status bytes)
+--!            takes into account the: RP_DAT.Control, RP_DAT.Data.PDU_TYPE, RP_DAT.Data.Length,
--
+--!            RP_DAT.Data.MPS_status, RP_DAT.Data.nanoFIP_status bytes as well as the user-data
--
+--!            bytes described by the P3_LGTH.
--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--!
--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)
+--!            ------------------------------------------------------------------------------------
+--!            Reminder
+--!
+--!            Produced RP_DAT frame structure :
+--!             ___________ ______  _______ ______ _________________ _______ _______  ___________ _______
+--!            |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
+--!
+--!                                               |-----P3_LGTH-----|
+--!
+--
+--
+--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
+--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)     \n
 --
 --
 --! @date      09/12/2010
@@ -66,7 +78,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --------------------------------------------------------------------------------------------------- 
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -112,11 +124,11 @@ signal s_prod_data_length, s_p3_length_decoded : unsigned(7 downto 0);
 begin
 ---------------------------------------------------------------------------------------------------
--!@brief: Combinatorial process data_length_calcul: calculation of the total amount of data
+--!@brief: Combinatorial process data_length_calcul: calculation of the amount of bytes, after the
--! bytes that have to be transferreed when a variable is produced, including the RP_DAT.Control as
+--! FSS and before the FCS, that have to be transferreed when a variable is produced. In the case  
--! well as the RP_DAT.Data.MPS_status and RP_DAT.Data.nanoFIP_status bytes. In the case of the 
+--! of the presence and the identification variables, the data length is predefined in the WF_package.
--! presence and the identification variables, the data length is predefined in the WF_package.
+--! In the case of a var3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation.
--! In the case of a var3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation. 
  data_length_calcul: process (var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i)
  begin
@@ -142,15 +154,15 @@ begin
      -- data length calculation according to the operational mode (memory or stand-alone)
      -- in slone mode                   2 bytes of user-data are produced(independantly of p3_lgth)
-      -- to these there should be added: 1 byte RP_DAT.Control
+      -- to these there should be added: 1 byte Control
-      --                                 1 byte PDU
+      --                                 1 byte PDU_TYPE
      --                                 1 byte Length
      --                                 1 byte MPS status
      --                      optionally 1 byte nFIP status
      -- in memory mode the signal      "s_p3_length_decoded" indicates the amount of user-data
-      -- to these, there should be added 1 byte RP_DAT.Control
+      -- to these, there should be added 1 byte Control
-      --                                 1 byte PDU
+      --                                 1 byte PDU_TYPE
      --                                 1 byte Length
      --                                 1 byte MPS status
      --                      optionally 1 byte nFIP status  

--- a/wf_prod_permit.vhd
+++ b/wf_prod_permit.vhd
@@ -22,7 +22,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --                                                                                               --
--                                          WF_prod_permit                                       --
+--                                        WF_prod_permit                                         --
 --                                                                                               --
 ---------------------------------------------------------------------------------------------------
 --
@@ -112,7 +112,7 @@ begin
 --! VAR3_RDY (for produced vars): signals that the user can safely write to the produced variable
 --! memory or access the DAT_I bus. It is deasserted right after the end of the reception of a
--! correct var3 ID_DAT frame and stays de-asserted until the end of the transmission of the
+--! correct var_3 ID_DAT frame and stays de-asserted until the end of the transmission of the
 --! corresponding RP_DAT from nanoFIP.
 --! Note: A correct ID_DAT frame along with the variable it contained is signaled by the var_i.
@@ -148,7 +148,6 @@ begin
  end process;
 end architecture rtl;
 --=================================================================================================
 --                                      architecture end

--- a/wf_production.vhd
+++ b/wf_production.vhd
@@ -117,7 +117,7 @@ entity WF_production is
      var3_acc_i              : in std_logic;
 	--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-    -- nanoFIP FIELDRIVE
+    -- nanoFIP FIELDRIVE (synchronized with uclk)
      --! WF_status_bytes_gen : for the nanoFIP status byte, bits 6, 7
      fd_txer_i               : in  std_logic;
@@ -178,7 +178,7 @@ entity WF_production is
      var3_rdy_o              : out std_logic; --! signals the user that data can safely be written
 	--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-    -- nanoFIP User Interface, WISHBONE Slave output
+    -- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk) output
      wb_ack_prod_p_o         : out std_logic  --! WISHBONE acknowledge
      );

--- a/wf_reset_unit.vhd
+++ b/wf_reset_unit.vhd
+--_________________________________________________________________________________________________
+--                                                                                                |
+--                                        |The nanoFIP|                                           |
+--                                                                                                |
+--                                        CERN,BE/CO-HT                                           |
+--________________________________________________________________________________________________|
+--________________________________________________________________________________________________|
 ---------------------------------------------------------------------------------------------------
--! @file WF_reset_unit.vhd
+--! @file WF_reset_unit.vhd                                                                       |
 ---------------------------------------------------------------------------------------------------
--! standard library
+--! Standard library
 library IEEE;
--! standard packages
+--! Standard packages
-use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
+use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
-use IEEE.NUMERIC_STD.all;     --! conversion functions
+use IEEE.NUMERIC_STD.all;    --! conversion functions
--! specific packages
+use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
-use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 --                                                                                               --
 --                                        WF_reset_unit                                          --
 --                                                                                               --
--                                        CERN, BE/CO/HT                                         --
--                                                                                               --
 ---------------------------------------------------------------------------------------------------
 --
-- unit name: WF_reset_unit
 --
--! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset
+--! @brief     The unit is responsible for the generation of the:
--! and user interface reset (RSTON)
+--!
+--!              o nanoFIP internal reset
+--!                  after the activation of the "nanoFIP User Interface General signal" RSTIN, or
+--!                  after the reception of a valid var_rst with its 1st data byte containing the
+--!                  station's address. In those cases, the signal stays active for 2 uclk cycles.
+--!                  After the activation of the "nanoFIP User Interface General signal" RSTPON.
+--!                  In this case the signal stays active for as long as the RSTPON is active.
+--!
+--!              o FIELDRIVE reset (nanoFIP FIELDRIVE output FD_RSTN)
+--!                  after the activation of the "nanoFIP User Interface General signal" RSTIN, or
+--!                  after the reception of a valid var_rst with its 1st data byte containing the
+--!                  station's address. The signal stays active for 4 FD_TXCK cycles.
+--!
+--!              o reset to the external logic (nanoFIP User Interface, General signal RSTON) 
+--!                  after the reception of a valid var_rst with its 2nd data byte containing the
+--!                  station's address. The signal stays active for 8 uclk cycles.
+--!
+--!            The input signal RSTIN is considered only if it has been active for > 8 uclk cycles.
+--!            The input signals rst_nFIP_and_FD_p and assert_RSTON_p come from the
+--!            WF_cons_outcome unit and are activated only after the sucessful validation of the
+--!            frame structure and data-bytes of a var_rst; therefore in this unit they are used
+--!            directly, without any handling.
+--!            The Power On Reset signal is used directly, without any handling.
+--!
+--!            The unit implements 2 state machines: one for resets coming from RSTIN
+--!                                                  and one for resets coming from a var_rst.
+--!                       __________
+--!               RSTIN  |          |       \ \
+--!              ________|   FSM    |_______ \ \
+--!                      |  RSTIN   |         \  \
+--!                      |__________|          \  \
+--!                       __________            |  \
+--!   rst_nFIP_and_FD_p  |          |           |   |      nFIP_rst
+--!              ________|   FSM    |________   |OR |  _______________ 
+--!                      |  var_rst |           |   |
+--!                      |__________|           |  /
+--!                                            /  /
+--!              RSTPON                       /  /
+--!              __________________________  / /
+--!                                         / / 
+--!
+--!
+--!                       __________
+--!               RSTIN  |          |       \ \
+--!              ________|   FSM    |_______ \  \
+--!                      |  RSTIN   |         \  \
+--!                      |__________|          \   \
+--!                                             |   \     FD_RSTN
+--!                       __________            |   |  _______________    
+--!   rst_nFIP_and_FD_p  |          |           |OR |     
+--!              ________|   FSM    |________   |   |   
+--!                      |  var_rst |          /   /
+--!                      |__________|         /  /
+--!                                          /  /
+--!                                         / / 
+--!
+--!                       __________            
+--!        assert_RSTON  |          |                       RSTON   
+--!              ________|   FSM    |_________________________________   
+--!                      |  var_rst |          
+--!                      |__________| 
+--!
 --
 --
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
+--! @author    Erik van der Bij      (Erik.van.der.Bij@cern.ch)      \n
--!         Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--!            Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--!         Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
+--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)     \n
 --
 --
--! @date 08/2010
+--! @date      18/01/2011
 --
 --
--! @version v0.02
+--! @version   v0.03
 --
 --
 --! @details 
 --
--!   \n<b>Dependencies:</b>    \n
+--!   \n<b>Dependencies:</b>           \n
--!     WF_cons_bytes_processor \n
+--!            WF_cons_bytes_processor \n
 -- 
 --
--!   \n<b>Modified by:</b>\n
+--!   \n<b>Modified by:</b>          \n
--!     Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
+--!            Pablo Alvarez Sanchez \n
--!     Evangelia Gousiou (Evangelia.Gousiou@cern.ch)         \n
+--!            Evangelia Gousiou     \n
 --
 ---------------------------------------------------------------------------------------------------
 --
 --!   \n\n<b>Last changes:</b>\n
 --!     07/2009  v0.01  EB  First version \n
--!     08/2010  v0.02  EG  checking of bytes1 and2 of reset var added \n
+--!     08/2010  v0.02  EG  checking of bytes1 and 2 of reset var added \n
--!                         fd_rstn_o, nFIP_rst_o enabled only if rstin has been active for > 16 uclk \n
+--!                         fd_rstn_o, nFIP_rst_o enabled only if rstin has been active for>4 uclk
+--!     01/2011  v0.03  EG  PoR added; signals assert_RSTON_p_i & rst_nFIP_and_FD_p_i are inputs
+--!                         treated in the wf_cons_outcome; 2 state machines created; clean-up
 --
 ---------------------------------------------------------------------------------------------------
 --
@@ -69,30 +136,35 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 entity WF_reset_unit is
  port (
  -- INPUTS
-    -- nanoFIP User Interface, General signals (synchronized with uclk) (after synchronization)
+    -- nanoFIP User Interface General signals (synchronized with uclk)
-    uclk_i :              in std_logic;                     --! 40 MHz clock
+    uclk_i              : in std_logic;     --! 40 MHz clock
-    urst_i :              in std_logic;                     --! initialisation control, active low
+    rstin_i             : in std_logic;     --! initialisation control, active low
-    urst_r_edge_i :       in std_logic;
+    rstpon_i            : in std_logic;     --! Power On Reset, active low
+    urst_r_edge_i       : in std_logic;     --! rising edge on RSTIN
-    -- nanoFIP WorldFIP Settings (synchronized with uclk) 
+    rate_i              : in  std_logic_vector (1 downto 0); --! WorldFIP bit rate 
-    subs_i :              in std_logic_vector (7 downto 0); --! subscriber number coding
-    rate_i :              in std_logic_vector (1 downto 0); --! WorldFIP bit rate
    -- Signal from the WF_engine_control unit
-    var_i :               in t_var;                         --! variable type that is being treated
+    var_i               : in t_var;         --! variable type that is being treated
-    rst_nFIP_and_FD_p_i : in std_logic;
-    assert_RSTON_p_i :    in std_logic;
+    -- Signal from the WF_consumption unit
+    rst_nFIP_and_FD_p_i : in std_logic;     --! indicates that a var_rst with its 1st byte
+                                            --! containing the station's address has been
+                                            --! correctly received
+    assert_RSTON_p_i    : in std_logic;     --! indicates that a var_rst with its 2nd byte
+                                            --! containing the station's address has been
+                                            --! correctly received
  -- OUTPUTS
-    -- nanoFIP internal reset
+    -- nanoFIP internal reset, to all the units
-    nFIP_rst_o :          out std_logic;                    --! nanoFIP internal reset, active high
+    nFIP_rst_o          : out std_logic;    --! nanoFIP internal reset, active high
-    -- nanoFIP User Interface output 
+    -- nanoFIP User Interface General signal output 
-    rston_o :             out std_logic;                    --! reset output, active low
+    rston_o             : out std_logic;    --! reset output, active low
    -- nanoFIP FIELDRIVE output
-    fd_rstn_o :           out std_logic                     --! FIELDRIVE reset, active low
+    fd_rstn_o           : out std_logic     --! FIELDRIVE reset, active low
       );
 end entity WF_reset_unit;
@@ -102,77 +174,448 @@ end entity WF_reset_unit;
 --=================================================================================================
 architecture rtl of WF_reset_unit is
-  signal s_rst  : std_logic;
+  signal s_counter_is_four, s_reinit_counter, s_rston, s_FD_rst_from_var_rst, s_por    : std_logic;
-  signal s_rstin_c :                                  unsigned(4 downto 0) := (others=>'0'); 
+  signal s_intern_rst_from_RSTIN, s_intern_rst_from_var_rst, s_fd_rst_from_RSTIN       : std_logic;
-                                                      -- counter init for simulation purpuses
+  signal s_counter_is_ten, s_counter_is_full, s_counter_full                           : std_logic;
+  signal s_var_rst_counter_is_eight, s_var_rst_counter_is_two                          : std_logic;
+  signal s_var_rst_reinit_counter, s_var_rst_counter_is_full, s_var_rst_counter_full   : std_logic;
+  signal s_transm_period                        : unsigned   (c_PERIODS_COUNTER_LENGTH-1 downto 0);
+  signal s_c, s_var_rst_c, s_txck_four_periods  : unsigned (c_2_PERIODS_COUNTER_LENGTH-1 downto 0);
+  type rstin_st_t        is (idle, rstin_eval, intern_rst_ON_FD_rst_ON,intern_rst_OFF_FD_rst_ON);
+  type after_a_var_rst_t is (after_a_var_rst_idle, after_a_var_rst_rston_ON,
+                             after_a_var_rst_nFIP_ON_fd_ON_rston_ON,
+                             after_a_var_rst_nFIP_OFF_fd_ON_rston_ON,
+                             after_a_var_rst_nFIP_ON_fd_ON,
+                             after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF);
+  signal after_a_var_rst_st, nx_after_a_var_rst_st : after_a_var_rst_t;
+  signal rstin_st, nx_rstin_st                     : rstin_st_t;
 --=================================================================================================
 --                                      architecture begin
 --================================================================================================= 
 begin
+  s_por               <= not rstpon_i;
+  s_transm_period     <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks of a
+                                                                             -- transmission period
+  s_txck_four_periods <= resize(s_transm_period, s_txck_four_periods'length) sll 1;-- # uclk ticks
+                                                                                   -- of 2 transm.
+                                                                                   -- periods = 4
+                                                                                   -- FD_TXCK periods
+  s_counter_full         <= '1' when s_c         = s_txck_four_periods else '0';                   
+  s_var_rst_counter_full <= '1' when s_var_rst_c = s_txck_four_periods else '0';
 ---------------------------------------------------------------------------------------------------
--!@brief Synchronous process s_rst_creation: the process follows the (buffered) input signal rstin 
+--                                            RSTIN                                              --
--! and confirms that it stays active for more than 16 uclk cycles;
+---------------------------------------------------------------------------------------------------
--! if so, it enables the signal s_rst to follow it.
+--!@brief RSTIN FSM: the state machine is divided in three parts (a clocked process
+--! to store the current state, a combinatorial process to manage state transitions and finally a
+--! combinatorial process to manage the output signals), which are the three processes that follow.
+--! The FSM is following the "User Interface, General signal" RSTIN (after synchronization) and
+--! checks weather it stays active for more than 4 uclk cycles; if so, it enables the nanoFIP
+--! internal reset (s_intern_rst_from_RSTIN) and the FIELDRIVE reset (s_FD_rst_from_RSTIN). The
+--! nanoFIP internal reset stays active for 2 uclk cycles and the  FIELDRIVE for 4 FD_TXCK cycles.
+--! The same counter is used for the evaluation of the RSTIN (if it is > 4 uclk) and for the
+--! generation of the two reset signals.
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  
+--!@brief synchronous process RSTIN_FSM_Sync: Storage of the current state of the FSM.
+--! The state machine can be reset by the Power On Reset and the variable reset.
+   RSTIN_FSM_Sync: process (uclk_i)
+    begin
+      if rising_edge (uclk_i) then
+        if s_por = '1' or rst_nFIP_and_FD_p_i = '1' then
+          rstin_st <= idle; 
+        else
+          rstin_st <= nx_rstin_st;
+        end if;
+      end if;
+  end process;
-  s_rst_creation: process (uclk_i)
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
+--!@brief Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
+--! transitions of the FSM.
+  RSTIN_FSM_Comb_State_Transitions: process (rstin_st,urst_r_edge_i,
+                                             s_counter_is_ten,rstin_i,s_counter_is_four,
+                                             s_counter_is_full)
  begin
-    if rising_edge (uclk_i) then
+  case rstin_st is 
+    when idle =>                                                        
+                        if urst_r_edge_i = '1' then       -- rising edges of RSTIN move the FSM to
+                          nx_rstin_st   <= rstin_eval;    -- the next state, so as not to be getting
+                                                          -- stuck if the RSTIN is stuck
+                        else 
+                          nx_rstin_st   <= idle;
+                        end if;
+    when rstin_eval => 
+                        if rstin_i = '0' then             -- RSTIN deactivated before the 8 cycles
+                          nx_rstin_st   <= idle;
+                        else
+                          if s_counter_is_four = '1' then          -- counting the uclk cycles that 
+                            nx_rstin_st <= intern_rst_ON_fd_rst_ON;-- RSTIN is active 
+                          else 
+                            nx_rstin_st <= rstin_eval;
+                          end if;	
+                        end if;  
+    when intern_rst_ON_fd_rst_ON =>                   
+                        if s_counter_is_ten = '1' then             -- nanoFIP internal reset and             
+                          nx_rstin_st <= intern_rst_OFF_fd_rst_ON; -- FIELDRIVE reset active for
+                                                                   -- 2 uclk cycles
+                        else
+                          nx_rstin_st <= intern_rst_ON_fd_rst_ON;
+                        end if;
+    when intern_rst_OFF_fd_rst_ON =>                              
+                                                          -- nanoFIP internal reset deactivated
+                        if s_counter_is_full = '1' then   -- FIELDRIVE reset continues being active
+                           nx_rstin_st <= idle;           -- unitl 4 FD_TXCK cycles have passed
+                        else
+                           nx_rstin_st <= intern_rst_OFF_FD_rst_ON;
+                        end if;
+    when others => 
+                        nx_rstin_st <= idle;
+  end case;	
+  end process;
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
+--!@brief combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
+--! the FSM. The process is managing the signals for the nanoFIP internal reset
+--! (s_intern_rst_from_RSTIN) and the FIELDRIVE reset (s_FD_rst_from_RSTIN), as well as the inputs
+--! of the RSTIN_free_counter.
+  RSTIN_FSM_Comb_Output_Signals: process (rstin_st)
+  begin
+    case rstin_st is 
+    when idle =>           
+                  s_reinit_counter        <= '1';    -- counter initialized
+                  s_intern_rst_from_RSTIN <= '0'; 
+                  s_FD_rst_from_RSTIN     <= '0';  
-      if (urst_i = '1')  then                       -- when the rstin in ON
-        if (s_rstin_c(s_rstin_c'left) = '0')  then  -- counter counts until 16 (then stays at 16)
+    when rstin_eval => 
-          s_rstin_c <= s_rstin_c+1;
+                  s_reinit_counter        <= '0';    -- counting until 4
-        end if;
+                                                     -- if rstin_i is active
+                  s_intern_rst_from_RSTIN <= '0';  
+                  s_FD_rst_from_RSTIN     <= '0';
+    when intern_rst_ON_fd_rst_ON =>
+                  s_reinit_counter        <= '0';    -- free counter counting 2 uclk cycles
+                 ------------------------------------- 
+                  s_FD_rst_from_RSTIN     <= '1';    -- FIELDRIVE     active 
+                  s_intern_rst_from_RSTIN <= '1';    -- nFIP internal active  
+                 ------------------------------------- 
+    when intern_rst_OFF_fd_rst_ON =>
+                  s_reinit_counter        <= '0';    -- free counter counting 4 FD_TXCK cycles
+                  s_intern_rst_from_RSTIN <= '0';
+                 ------------------------------------- 
+                  s_FD_rst_from_RSTIN     <= '1';    -- FIELDRIVE     active 
+                 ------------------------------------- 
+    when others =>
+                  s_reinit_counter        <= '1';    -- no counting
+                  s_FD_rst_from_RSTIN     <= '0'; 
+                  s_intern_rst_from_RSTIN <= '0';
-      else                                          -- when the reset is OFF
-        s_rstin_c <= (others => '0');               -- counter reinitialised
-      end if;
-------------------------------------------------
+    end case;	
+  end process;
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+--!@brief Instantiation of a WF_incr_counter: the counter counts from 0 to 4 FD_TXCK.
-      if (s_rstin_c(s_rstin_c'left) = '1')  then    -- if rstin was ON for at least 16 uclk ticks
+RSTIN_free_counter: WF_incr_counter
-        s_rst <= urst_i;                            -- the signal s_rst starts following rstin
+  generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LENGTH)
+  port map(
+    uclk_i            => uclk_i,        
+    nfip_urst_i       => s_por, --or rst_nFIP_and_FD_p_i,
+    reinit_counter_i  => s_reinit_counter,
+    incr_counter_i    => '1',
+    counter_o         => s_c,
+    counter_is_full_o => open);
-      else                                          
+  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
-        s_rst <= '0';                               -- otherwise it stays to 0
+  s_counter_is_four  <= '1' when s_c = to_unsigned(4, s_c'length)  else '0'; 
+  s_counter_is_ten   <= '1' when s_c = to_unsigned(10, s_c'length) else '0'; 
+  s_counter_is_full  <= s_counter_full;
+---------------------------------------------------------------------------------------------------
+--                                              var_rst                                          --
+---------------------------------------------------------------------------------------------------
+--!@brief Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
+--! to store the current state, a combinatorial process to manage state transitions and finally a
+--! combinatorial process to manage the output signals), which are the three processes that follow.
+--! If after the reception or a var_rst the signal assert_RSTON_p_i is asserted, the FSM
+--! asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
+--! If after the reception or a var_rst the signal rst_nFIP_and_FD_p_i is asserted, the FSM
+--! asserts the nanoFIP internal reset (s_intern_rst_from_var_rst) for 2 uclk cycles and the
+--! "nanoFIP FIELDRIVE" output (s_FD_rst_from_var_rst) for 4 FD_TXCK cycles.
+--! If after the reception or a var_rst both assert_RSTON_p_i and rst_nFIP_and_FD_p_i
+--! are asserted, the FSM asserts the s_intern_rst_from_var_rst for 2 uclk cycles, the RSTON for 8
+--! uclk cycles and the s_FD_rst_from_var_rst for 4 FD_TXCK cycles.
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  
+--!@brief Synchronous process Resets_after_a_var_rst_synch: Storage of the current state of the FSM
+--! The state machine can be reset by the Power On Reset and the nanoFIP internal reset from RSTIN.
+   Resets_after_a_var_rst_synch: process (uclk_i)
+    begin
+      if rising_edge (uclk_i) then
+        if s_por = '1' or s_intern_rst_from_RSTIN = '1' then
+          after_a_var_rst_st <= after_a_var_rst_idle; 
+        else
+          after_a_var_rst_st <= nx_after_a_var_rst_st;
+        end if;
      end if;
+  end process;
-    end if;
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
+--!@brief Combinatorial process Resets_after_a_var_rst_Comb_State_Transitions: definition of the 
+--! state transitions of the FSM.
+  Resets_after_a_var_rst_Comb_State_Transitions: process (after_a_var_rst_st,var_i,rst_nFIP_and_FD_p_i,
+                                                          assert_RSTON_p_i, s_var_rst_counter_is_two,
+                                                          s_var_rst_counter_is_eight,
+                                                          s_var_rst_counter_is_full)
+  begin
-end process;
+  case after_a_var_rst_st is 
+    when after_a_var_rst_idle =>      
+                        if (var_i = var_rst) and (assert_RSTON_p_i = '1')      -- re-check of var_i
+                                             and (rst_nFIP_and_FD_p_i = '1') then   -- just in case  
+                          nx_after_a_var_rst_st   <= after_a_var_rst_nFIP_ON_fd_ON_rston_ON; 
+                        elsif (var_i = var_rst) and (assert_RSTON_p_i = '1') then
+                          nx_after_a_var_rst_st   <= after_a_var_rst_rston_ON;   
+                        elsif (var_i = var_rst) and (rst_nFIP_and_FD_p_i = '1') then
+                          nx_after_a_var_rst_st   <= after_a_var_rst_nFIP_ON_fd_ON;                            
+                        else 
+                          nx_after_a_var_rst_st   <= after_a_var_rst_idle;
+                        end if;
+    when after_a_var_rst_rston_ON =>                              -- here for 8 uclk cycles
+                        if s_var_rst_counter_is_eight = '1' then 
+                          nx_after_a_var_rst_st   <= after_a_var_rst_idle;
+                        else
+                          nx_after_a_var_rst_st <= after_a_var_rst_rston_ON;
+                        end if;  
+    when after_a_var_rst_nFIP_ON_fd_ON_rston_ON =>                -- here for 2 uclk cycles
+                        if s_var_rst_counter_is_two = '1' then          
+                          nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_ON;
+                        else
+                          nx_after_a_var_rst_st <= after_a_var_rst_nFIP_ON_fd_ON_rston_ON;
+                        end if;
+    when after_a_var_rst_nFIP_OFF_fd_ON_rston_ON =>              -- here for 6 uclk cycles  
+                        if s_var_rst_counter_is_eight = '1' then          
+                          nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF;
+                        else
+                          nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_ON;
+                        end if;
+    when after_a_var_rst_nFIP_ON_fd_ON =>                        -- here for 2 uclk cycles   
+                        if s_var_rst_counter_is_two = '1' then          
+                          nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF;
+                        else
+                          nx_after_a_var_rst_st <= after_a_var_rst_nFIP_ON_fd_ON;
+                        end if;
+    when after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF =>             -- here for 4 fd_txck cycles 
+                        if s_var_rst_counter_is_full = '1' then  
+                           nx_after_a_var_rst_st <= after_a_var_rst_idle;
+                        else
+                           nx_after_a_var_rst_st <= after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF;
+                        end if;
+    when others => 
+                        nx_after_a_var_rst_st <= after_a_var_rst_idle;
+  end case;	
+  end process;
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
+--!@brief combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
+--! the FSM. The process is managing the signals for the nanoFIP internal reset and the FIELDRIVE
+--! reset, as well as the arguments of the counter.
+  rst_var_FSM_Comb_Output_Signals: process (after_a_var_rst_st)
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Reset_Outputs: definitions of the three reset outputs: 
--! rston_o: user interface reset, active low; active when a reset variable is received and the 2nd
--! byte contains the station address.
--! The signal reset_RSTON stays asserted until the end of the transmission of the RP_DAT frame
--! nFIP_rst_o: nanoFIP internal reset, active high;active when rstin is active or when a reset variable
--! is received and the 1st byte contains the station address.
--!The signal reset_nFIP_and_FD stays asserted until the end of the transmission of the RP_DAT frame
--! fd_rstn_o: FIELDRIVE reset, active low; active when a reset variable is received and the 1st
--! byte contains the station address.
--! The signal reset_nFIP_and_FD_i stays asserted until a new variable for this station is received
-  Reset_Outputs: process (uclk_i)
  begin
-    if rising_edge (uclk_i) then
+    case after_a_var_rst_st is 
+    when after_a_var_rst_idle =>  
+                                     s_var_rst_reinit_counter  <= '1';    -- counter initialized
+                                     s_rston                   <= '0';
+                                     s_intern_rst_from_var_rst <= '0'; 
+                                     s_FD_rst_from_var_rst     <= '0';  
+    when after_a_var_rst_rston_ON => 
+                                     s_var_rst_reinit_counter  <= '0';    -- counting 8 uclk cycles
+                                    -------------------------------------
+                                     s_rston                   <= '1';    -- RSTON         active
+                                    -------------------------------------
+                                     s_intern_rst_from_var_rst <= '0';  
+                                     s_FD_rst_from_var_rst     <= '0';
+    when after_a_var_rst_nFIP_ON_fd_ON_rston_ON =>
+                                     s_var_rst_reinit_counter  <= '0';    -- counting 2 uclk cycles
+                                    -------------------------------------
+                                     s_rston                   <= '1';    -- RSTON         active
+                                     s_intern_rst_from_var_rst <= '1';    -- nFIP internal active
+                                     s_FD_rst_from_var_rst     <= '1';    -- FIELDRIVE     active
+                                    -------------------------------------
+    when after_a_var_rst_nFIP_OFF_fd_ON_rston_ON =>
+                                     s_var_rst_reinit_counter  <= '0';    -- counting 6 uclk cycles
+                                     s_intern_rst_from_var_rst <= '0'; 
+                                    -------------------------------------
+                                     s_rston                   <= '1';    -- RSTON         active
+                                     s_FD_rst_from_var_rst     <= '1';    -- FIELDRIVE     active
+                                    -------------------------------------
+    when after_a_var_rst_nFIP_ON_fd_ON =>
+                                     s_var_rst_reinit_counter  <= '0';    -- counting 2 uclk cycles 
+                                     s_rston                   <= '0';
+                                    ------------------------------------- 
+                                     s_intern_rst_from_var_rst <= '1';    -- nFIP internal active
+                                     s_FD_rst_from_var_rst     <= '1';    -- FIELDRIVE     active
+                                    ------------------------------------- 
-      rston_o    <= not assert_RSTON_p_i; 
-      nFIP_rst_o <= s_rst or rst_nFIP_and_FD_p_i;
+    when after_a_var_rst_nFIP_OFF_fd_ON_rston_OFF =>
-      fd_rstn_o  <= not (s_rst or rst_nFIP_and_FD_p_i);                                                       
+                                     s_var_rst_reinit_counter  <= '0';    -- counting 4 FD_TXCK cycles
+                                     s_rston                   <= '0';   
+                                     s_intern_rst_from_var_rst <= '0';
+                                    -------------------------------------  
+                                    s_FD_rst_from_var_rst      <= '1';    -- FIELDRIVE     active
+                                    -------------------------------------    
+    when others =>
+                                     s_var_rst_reinit_counter  <= '1';    -- no counting
+                                     s_rston                   <= '0';   
+                                     s_intern_rst_from_var_rst <= '0'; 
+                                     s_FD_rst_from_var_rst     <= '0';   
-   end if;
+    end case;	
  end process;
-end architecture rtl;
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+--!@brief Instantiation of a WF_incr_counter:
+--! the counter counts from 0 to 8, if only assert_RSTON_p has been activated, or
+--!                    from 0 to 4 * FD_TXCK, if rst_nFIP_and_FD_p has been activated.
+free_counter: WF_incr_counter
+  generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LENGTH)
+  port map(
+    uclk_i            => uclk_i,        
+    nfip_urst_i       => s_por,-- or s_intern_rst_from_RSTIN,
+    reinit_counter_i  => s_var_rst_reinit_counter,
+    incr_counter_i    => '1',
+    counter_o         => s_var_rst_c,
+    counter_is_full_o => open);
+  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
+  s_var_rst_counter_is_eight <= '1' when s_var_rst_c = to_unsigned(8, s_var_rst_c'length)  else '0'; 
+  s_var_rst_counter_is_two   <= '1' when s_var_rst_c = to_unsigned(10, s_var_rst_c'length) else '0'; 
+  s_var_rst_counter_is_full  <= s_var_rst_counter_full;
+---------------------------------------------------------------------------------------------------
+--                                         Output Signals                                        --
+---------------------------------------------------------------------------------------------------
+  nFIP_rst_o <= s_intern_rst_from_RSTIN or s_intern_rst_from_var_rst or s_por;
+  Outputs_Buffering: process (uclk_i)
+  begin
+    if rising_edge (uclk_i) then
+      if (s_por = '1') or (s_intern_rst_from_RSTIN = '1') or (s_intern_rst_from_var_rst = '1') then     
+        fd_rstn_o  <= '1'; -- active low     
+        rston_o    <= '1'; -- active low   
+      else
+        fd_rstn_o  <= (not s_FD_rst_from_RSTIN) or (not s_FD_rst_from_var_rst);      
+        rston_o    <=  not s_rston; 
+      end if;
+    end if;
+  end process;
+end architecture rtl;
 --=================================================================================================
 --                                      architecture end
 --=================================================================================================

--- a/wf_rx_deglitcher.vhd
+++ b/wf_rx_deglitcher.vhd
@@ -25,18 +25,25 @@ use IEEE.NUMERIC_STD.all;    --! conversion functions
 ---------------------------------------------------------------------------------------------------
 --
 --
--! @brief     The unit applies a glitch filter; it follows each manchester bit of the "nanoFIP
+--! @brief     The unit applies a glitch filter; it follows each Manchester 2 encoded bit (manch.)
--!            FIELDRIVE" input signal fd_rxd (synchronized with uclk), counts the number of zeros
+--!            of the "nanoFIP FIELDRIVE" input signal fd_rxd (synchronized with uclk), counts the 
--!            and ones throughout its duration and finally outputs the majority. The output
+--!            number of zeros and ones throughout its duration and finally outputs the majority. 
--!            deglitched signal is one half-bit-clock period later than the input.
+--!            The output deglitched signal is one half-bit-clock period later than the input.
--!            Note: the term sample_manch_bit_p refers to the moments when a manch. encoded bit
+--!
--!            should be sampled (before and after a significant edge), whereas the 
+--!            Remark: We refer to
--!            sample_bit_p includes only the sampling of the 1st part, before the transition. 
+--!              o a significant edge                : for the edge of a manch. encoded bit
--!            Example:
+--!                (bit 0: _|-, bit 1: -|_)
--!                    bit                : 0 
+--!              o the sampling of a manch. bit      : for the moments when a manch. encoded bit
--!                    manch. encoded     : _|-
+--!                should be sampled, before and after a significant edge
--!                    sample_manch_bit_p : ^ ^
+--!              o the sampling of a bit             : for the sampling of only the 1st part,
--!                    sample_bit_p       : ^    (this sampling will give the 0)
+--!                before the transition. 
+--!
+--!                Example:
+--!                  bits               :  0   1 
+--!                  manch. encoded     : _|- -|_
+--!                  significant edge   :  ^   ^
+--!                  sample_manch_bit_p : ^ ^ ^ ^ 
+--!                  sample_bit_p       : ^   ^   (this sampling will give the 0 and the 1)
 --
 --
 --! @author	   Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
@@ -126,9 +133,9 @@ begin
 ---------------------------------------------------------------------------------------------------
--! Synchronous process: Zeros_and_Ones_counter: For each manchester bit (between two
+--! Synchronous process: Zeros_and_Ones_counter: For each manch. encoded bit (between two
--! sample_manch_bit_p_i pulses) at each uclk tick, the signed counter decreases by one if rxd is
+--! sample_manch_bit_p_i pulses) at each uclk tick, the signed counter decreases by one if rxd_i
--! one or increases by one if rxd is zero.
+--! is "1" and increases by one if rxd_i is "0".
 Zeros_and_Ones_counter: process (uclk_i)
  begin
@@ -150,12 +157,12 @@ Zeros_and_Ones_counter: process (uclk_i)
  end if;
 end process;
 ---------------------------------------------------------------------------------------------------
--! Synchronous process Filtering: On the arrival of a new manchester bit, if the number of ones 
+--! Synchronous process Filtering: On the arrival of a new manch. bit, if the number of ones 
 --! that has been measured (for the bit that has already passed) is more than the number of zeros,
--! the filtered output signal is zero (until the new manchester bit), otherwise one. 
+--! the filtered output is set to zero (until the new manch. bit), otherwise to one. 
--! The filtered signal is one half-bit-clock cycle (+2 uclk cycles) late with respect to the
+--! The filtered signal is one half-bit-clock cycle (+2 uclk cycles) late with respect to its input.
--! synchronized fd_rxd.
 Filtering: process (uclk_i)
  begin
@@ -176,9 +183,10 @@ Filtering: process (uclk_i)
  end if;
 end process;
 ---------------------------------------------------------------------------------------------------
--!@brief synchronous process Detect_f_edge_rxd_filtered: detection of a falling edge on the 
+--!@brief Synchronous process Detect_f_edge_rxd_filtered: detection of a falling edge on the 
--! deglitched input signal(rxd_filtered). A buffer is used to store the last 2 bits of the signal.
+--! deglitched input signal (rxd_filtered).
 Detect_f_edge_rxd_filtered: process (uclk_i)
  begin
@@ -193,8 +201,10 @@ Detect_f_edge_rxd_filtered: process (uclk_i)
    end if;
  end process;
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- Concurrent signals assignments
+ --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+-- Concurrent signal assignments
  rxd_filtered_f_edge_p_o   <= s_rxd_filtered_buff(1) and (not s_rxd_filtered_buff(0));
  rxd_filtered_o            <= s_rxd_filtered_d;
  sample_bit_p_o            <= sample_bit_p_i;

--- a/wf_rx_deserializer.vhd
+++ b/wf_rx_deserializer.vhd
@@ -53,6 +53,15 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --!                  transition         :    ^
 --!                  sample_manch_bit_p : ^ ^ ^ ^ 
 --!                  sample_bit_p       : ^   ^   (this sampling will give the 0 and the 1)
+--!
+--!            ------------------------------------------------------------------------------------
+--!            Reminder:
+--!
+--!            Consumed RP_DAT frame structure :
+--!             _______ _______ ______  _______ ______ ______________ _______  ___________ _______
+--!            |__PRE__|__FSD__|_Ctrl_||__PDU__|_LGTH_|_..PureData.._|__MPS__||____FCS____|__FES__|
+--!
+--!            ------------------------------------------------------------------------------------
 --
 --
 --! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
@@ -67,17 +76,17 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --
 --! @details \n 
 --
--!   \n<b>Dependencies:</b>  \n
+--!   \n<b>Dependencies:</b>         \n
--!     WF_reset_unit         \n
+--!            WF_reset_unit         \n
--!     WF_rx_tx_osc          \n
+--!            WF_rx_tx_osc          \n
--!     WF_rx_deglitcher      \n
+--!            WF_rx_deglitcher      \n
--!     WF_engine_control     \n
+--!            WF_engine_control     \n
--!     WF_inputs_synchronizer\n
+--!            WF_inputs_synchronizer\n
 -- 
 -- 
--!   \n<b>Modified by:</b>   \n
+--!   \n<b>Modified by:</b>          \n
--!     Pablo Alvarez Sanchez \n
+--!            Pablo Alvarez Sanchez \n
--!     Evangelia Gousiou     \n
+--!             Evangelia Gousiou    \n
 --
 --------------------------------------------------------------------------------------------------- 
 --
@@ -89,7 +98,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --!                          units WF_rx_manch_code_check and Incoming_Bits_Index created;
 --!                          each manch bit of FES checked (bf was just each bit, so any D5 was FES) 
 --!                          code cleaned-up + commented.\n
--!     -> 12/2010 v0.03 EG  CRC_ok pulse transfered 16 bits later to match the FES;
+--!     -> 12/2010 v0.02 EG  CRC_ok pulse transfered 16 bits later to match the FES;
 --!                          like this we confirm that the CRC_ok_p arrived just before the FES,
 --!                          and any 2 bytes that could by chanche be seen as CRC, are neglected.  
 --!                          FSM data_field_byte state: redundant code removed:
@@ -104,7 +113,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -177,10 +186,10 @@ architecture rtl of WF_rx_deserializer is
                    fsd_field, switch_to_deglitched, data_fcs_fes_fields);
  signal rx_st, nx_rx_st                                          : rx_st_t;
-  signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok_p_d16          : std_logic;
+  signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok_p_d16             : std_logic;
  signal s_fsd_last_bit, s_fes_wrong_bit, s_sample_manch_bit_p_d1 : std_logic;
  signal s_fes_detected_p, s_fes_detection_window                 : std_logic;
-  signal s_manch_not_ok, s_switching_to_deglitched                : std_logic;
+  signal s_manch_not_ok, s_switching_to_deglitched       : std_logic;
  signal s_receiving_fsd, s_receiving_bytes, s_receiving_pre      : std_logic;
  signal s_decr_manch_bit_index_p, s_manch_bit_index_load         : std_logic;
  signal s_manch_bit_index_is_zero, s_edge_outside_manch_window_p : std_logic;
@@ -424,13 +433,14 @@ architecture rtl of WF_rx_deserializer is
 ---------------------------------------------------------------------------------------------------
--                                          Bytes Creation                                       --
+--                                          Creating Bytes                                       --
 ---------------------------------------------------------------------------------------------------
 --!@brief Synchronous process Append_Bit_To_Byte: creation of bytes of data.
 --! A new bit of the (deglitched) input signal is appended to the output byte that is being formed
 --! when the Deserializer's FSM is in the "data_fcs_fes_fields" state, on the "sampling of a bit"
 --! moments.
  Append_Bit_To_Byte: process (uclk_i)
    begin
      if rising_edge (uclk_i) then
@@ -460,7 +470,8 @@ architecture rtl of WF_rx_deserializer is
 ---------------------------------------------------------------------------------------------------
 --!@brief Instantiation of a counter that manages the position of an incoming deglitched bit
--! inside a manch. encoded byte (16 bits).  
+--! inside a manch. encoded byte (16 bits).
  Incoming_Bits_Index: WF_decr_counter
  generic map(g_counter_lgth => 4)
  port map(
@@ -476,11 +487,13 @@ architecture rtl of WF_rx_deserializer is
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
  -- FSD aux signals concurrent assignments:
  s_fsd_bit        <= s_receiving_fsd   and FSD (to_integer(s_manch_bit_index));  
  s_fsd_last_bit   <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
  s_fsd_wrong_bit  <= (s_fsd_bit xor rxd_filtered_i) and sample_manch_bit_p_i; 
  -- FES aux signals concurrent assignments :
  s_fes_bit        <= s_receiving_bytes and FES (to_integer(s_manch_bit_index));
  s_fes_wrong_bit  <= (s_fes_bit xor rxd_filtered_i) and sample_manch_bit_p_i;   
  s_fes_detected_p <=s_fes_detection_window and sample_manch_bit_p_i and s_manch_bit_index_is_zero;     
@@ -488,6 +501,7 @@ architecture rtl of WF_rx_deserializer is
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
 --!@brief Combinatorial process that according to the state of the FSM sets values to the
 --! Incoming_Bits_Index inputs.
  Bit_Index: process (s_idle,s_receiving_pre, s_switching_to_deglitched, s_receiving_fsd,
                      s_receiving_bytes, s_manch_bit_index_is_zero,sample_manch_bit_p_i)
  begin
@@ -527,7 +541,8 @@ architecture rtl of WF_rx_deserializer is
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
 --!@brief Synchronous process FES_Detector: creation of a window that is activated at the 
--! beginning of an incoming byte and stays active as long as 16 incoming manch. bits match the FES. 
+--! beginning of an incoming byte and stays active as long as 16 incoming manch. bits match the FES.
  FES_Detector: process (uclk_i)
    begin
      if rising_edge (uclk_i) then
@@ -553,6 +568,7 @@ architecture rtl of WF_rx_deserializer is
 ---------------------------------------------------------------------------------------------------
 --!@brief Instantiation of the CRC calculator unit that verifies the received FCS field.
  CRC_Verification : WF_crc 
  generic map(c_GENERATOR_POLY_length => 16) 
  port map(
@@ -568,6 +584,7 @@ architecture rtl of WF_rx_deserializer is
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
 --!@brief Instantiation of the WF_rx_manch_code_check unit that checks for manch. code violations.
  Manch_Encoding_Verification: WF_rx_manch_code_check
  port map(
    uclk_i                => uclk_i,
@@ -583,6 +600,7 @@ architecture rtl of WF_rx_deserializer is
 --!@brief Synchronous process that manages the s_manch_code_viol_p signal: If at any point after
 --! the FSS and before the FES a code violation appears, the signal s_manch_not_ok stays
 --! asserted until the end of the corresponding frame.    
  Code_viol: process (uclk_i)
    begin
      if rising_edge (uclk_i) then
@@ -611,6 +629,7 @@ architecture rtl of WF_rx_deserializer is
 --! calculator unit is delayed for 16 manch. encoded bits. The matching of this delayed pulse with
 --! the FES pulse (s_fes_detected_p), would confirm that the two last bytes received before the
 --! FES were the correct CRC.
  CRC_OK_pulse_delay: process (uclk_i)
    begin
      if rising_edge (uclk_i) then
@@ -648,6 +667,7 @@ architecture rtl of WF_rx_deserializer is
 --                                   Concurrent signal assignments                               --
 ---------------------------------------------------------------------------------------------------
 -- aux signals concurrent assignments :
  s_manch_r_edge_p              <= signif_edge_window_i and rxd_r_edge_p_i;
  s_manch_f_edge_p              <= signif_edge_window_i and rxd_f_edge_p_i;
  s_bit_r_edge_p                <= adjac_bits_window_i and ( rxd_r_edge_p_i);
@@ -656,6 +676,7 @@ architecture rtl of WF_rx_deserializer is
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- 
  -- output signals concurrent assignments :
  byte_o                        <= s_byte; 
  rst_rx_osc_o                  <= s_idle;
  fss_received_p_o              <= s_receiving_fsd and s_fsd_last_bit;

--- a/wf_rx_tx_osc.vhd
+++ b/wf_rx_tx_osc.vhd
@@ -88,7 +88,7 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 --                                         No Warnings                                           --
 ---------------------------------------------------------------------------------------------------
@@ -237,6 +237,7 @@ begin
    end if;
  end process;
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
 -- Concurrent signal assignments concerning the receiver:
 -- creation of the windows where "significant edges" and "adjacent bits transitions" are expected
@@ -276,7 +277,6 @@ begin
  -- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
  -- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
 rx_clk: process (uclk_i)
    begin
@@ -384,6 +384,7 @@ begin
    end if;
  end process;
 ---------------------------------------------------------------------------------------------------
 -- Concurrent signal assignments concerning the transmitter:
@@ -404,6 +405,10 @@ begin
                                              -- not s_tx_clk_d1       : ----|_____|-----|_____|---
                                              -- s_tx_clk_p            : __|-|___|-|___|-|___|-|___
+---------------------------------------------------------------------------------------------------
+--                                           Output signals                                      --
 ---------------------------------------------------------------------------------------------------
 -- Output signals construction:

--- a/wf_status_bytes_gen.vhd
+++ b/wf_status_bytes_gen.vhd
@@ -48,8 +48,8 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --!            having been sent.            
 --
 --
--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)
+--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)     \n
 --
 --
 --! @date 10/01/2011
@@ -61,10 +61,10 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --! @details\n 
 --
 --!   \n<b>Dependencies:</b>\n
--!     data_if             \n
+--!     WF_consumption      \n
--!     tx_engine           \n
+--!     WF_bytes_retriever  \n
--!     WF_tx_rx            \n
+--!     WF_prod_permit      \n
--!     reset_logic         \n
+--!     WF_reset_unit       \n
 --
 --
 --!   \n<b>Modified by:</b>\n
@@ -88,7 +88,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 ---------------------------------------------------------------------------------------------------
 ---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
--                               Sunplify Premier D-2009.12 Warnings                             --
+--                               Synplify Premier D-2009.12 Warnings                             --
 -- -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
 -- "W CL189	Register bits s_nFIP_status_byte(0), s_nFIP_status_byte(1) are always 0, optimizing" --
 -- "W CL260	Pruning Register bits 0 and 1 of s_nFIP_status_byte(7 downto 0)"                     --
@@ -110,7 +110,7 @@ port (
    -- Signal from the WF_reset_unit
    nfip_urst_i             : in std_logic;  --! nanaoFIP internal reset
-    -- nanoFIP FIELDRIVE  
+    -- nanoFIP FIELDRIVE (synchronized with uclk)
    fd_txer_i               : in  std_logic; --! transmitter error
    fd_wdgn_i               : in  std_logic; --! watchdog on transmitter
@@ -206,16 +206,16 @@ begin
          --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-          -- t_txer
+          -- t_wder
          if (fd_wdgn_i = '0') then                              -- FIELDRIVE transmission error 
-            s_nFIP_status_byte(c_T_TXER_INDEX)  <= '1';
+            s_nFIP_status_byte(c_T_WDER_INDEX)  <= '1';
          end if;
          --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-          -- t_wder
+          -- t_rxer
          if (fd_txer_i = '1') then                              -- FIELDRIVE watchdog timer problem
-            s_nFIP_status_byte(c_T_WDER_INDEX)  <= '1';
+            s_nFIP_status_byte(c_T_TXER_INDEX)  <= '1';
          end if;
@@ -311,7 +311,7 @@ begin
        s_refreshment   <= '0';
      else
-        if rst_status_bytes_p_i = '1' then          -- the bit is reinitialized
+        if rst_status_bytes_p_i = '1' then          -- bit reinitialized after a var production
          s_refreshment <= '0';  
        elsif (var3_acc_i = '1') then               -- indication that the memory has been accessed