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nanoFIP - Gateware
Commit 40153778 authored by egousiou's avatar egousiou
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"cosmetics" in package+engine 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@105 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 3c37fd5f
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Showing with 550 additions and 446 deletions
nanofip.vhd
View file @ 40153778
......@@ -252,14 +252,14 @@ begin
rx_FSS_received_p_i => s_cons_fss_decoded_p,
rx_byte_ready_p_i => s_cons_byte_ready_p,
rx_byte_i => s_cons_byte,
rx_CRC_FES_ok_p_i => s_fss_crc_fes_viol_ok_p,
produce_wait_turnar_time => s_fss_crc_fes_viol_ok_p,
rx_crc_wrong_p_i => s_cons_crc_wrong_p,
tx_sending_mps_i => s_prod_sending_mps,
rx_ctrl_byte_i => s_cons_ctrl_byte,
rx_pdu_byte_i => s_cons_PDU_byte,
rx_length_byte_i => s_cons_lgth_byte,
rx_var_rst_byte_1_i => s_cons_var_rst_byte_1,
rx_var_rst_byte_2_i => s_cons_var_rst_byte_2,
prod_sending_mps_i => s_prod_sending_mps,
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_PDU_byte,
cons_lgth_byte_i => s_cons_lgth_byte,
cons_var_rst_byte_1_i => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_i => s_cons_var_rst_byte_2,
rate_i => s_rate_synch,----------------
subs_i => s_subs_synch,----------------
p3_lgth_i => s_p3_lgth_synch, ----------------------
......@@ -269,12 +269,12 @@ begin
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
tx_start_produce_p_o => s_start_prod_p ,
tx_start_prod_p_o => s_start_prod_p ,
tx_byte_ready_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
tx_rx_byte_index_o => s_cons_prod_byte_index_from_control,
tx_data_length_o => s_data_length_from_control,
rx_byte_ready_p_o => s_cons_byte_ready_from_control,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control,
prod_data_length_o => s_data_length_from_control,
cons_byte_ready_p_o => s_cons_byte_ready_from_control,
rst_rx_unit_p_o => s_rst_rx_unit_p,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p,
......
wf_VAR_RDY_generator.vhd
View file @ 40153778
......@@ -86,31 +86,31 @@ entity WF_var_rdy_generator is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
subs_i : in std_logic_vector (7 downto 0); --! Station address
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
subs_i : in std_logic_vector (7 downto 0); --! Station address
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_cons_frame_validator
cons_frame_ok_p_i : in std_logic; --! pulse after a correct consumed frame
var_i : in t_var; --! variable type that is being treated
cons_frame_ok_p_i : in std_logic; --! pulse after a correct cons frame
var_i : in t_var; --! variable type that is being treated
-- Signals from the wf_cons_bytes_processor
rx_var_rst_byte_1_i : in std_logic_vector(7 downto 0); --! first & second data bytes of a
rx_var_rst_byte_2_i : in std_logic_vector(7 downto 0); --! reset variable
cons_var_rst_byte_1_i : in std_logic_vector(7 downto 0);--! first & second data bytes of a
cons_var_rst_byte_2_i : in std_logic_vector(7 downto 0);--! reset variable
-- OUTPUT
-- nanoFIP User Interface, NON-WISHBONE outputs
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
-- Signals for the WF_reset_unit
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
);
end entity WF_var_rdy_generator;
......@@ -275,12 +275,12 @@ begin
if var_i = var_rst then
if rx_var_rst_byte_1_i = subs_i then
if cons_var_rst_byte_1_i = subs_i then
s_rst_nfip_and_fd <= '1'; -- rst_nFIP_and_FD_o stays asserted until
end if; -- the end of the current RP_DAT frame
if rx_var_rst_byte_2_i = subs_i then
if cons_var_rst_byte_2_i = subs_i then
s_assert_rston <= '1'; -- assert_RSTON_o stays asserted until
end if; -- the end of the current RP_DAT frame
......
wf_cons_bytes_processor.vhd
View file @ 40153778
......@@ -145,7 +145,7 @@ architecture rtl of wf_cons_bytes_processor is
signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_rx_Length_byte : std_logic_vector (7 downto 0);
signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned(7 downto 0);
signal s_base_addr : unsigned(8 downto 0);
......@@ -207,14 +207,14 @@ begin
--! In memory mode, the incoming bytes (byte_i) after the Control byte and before the CRC bytes,
--! are written in the memory one by one as they arrive, on the moments when the signal
--! byte_ready_p_i is active.
--! The signals byte_index_i and Length (s_rx_Length_byte) are used to coordinate which bytes are
--! The signals byte_index_i and Length (s_cons_lgth_byte) are used to coordinate which bytes are
--! written and which are not:
--! the Control byte, that arrives when byte_index_i = 0, is not written
--! and the CRC bytes are not written by checking the amount of bytes indicated by the Length byte.
--! The byte_index_i signal is counting each byte after the FSS and before the FES (therefore,
--! apart from all the pure data-bytes,it also includes the Control, PDU, Length, MPS & CRC bytes).
--! The Length byte (s_rx_Length_byte) is received from the wf_rx_deserializer when byte_index_i is equal to 3
--! The Length byte (s_cons_lgth_byte) is received from the wf_rx_deserializer when byte_index_i is equal to 3
--! and indicates the amount of bytes in the frame after the Control, PDU_TYPE and itself and
--! before the CRC.
......@@ -225,7 +225,7 @@ begin
--! If the consumed variable is the reset one the process latches the first and second data bytes.
Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
byte_ready_p_i, s_base_addr, s_rx_Length_byte)
byte_ready_p_i, s_base_addr, s_cons_lgth_byte)
begin
......@@ -255,7 +255,7 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
if byte_index_i > c_LENGTH_BYTE_INDEX then -- after the reception
-- of the Length byte
if unsigned(byte_index_i) <= unsigned(s_rx_Length_byte) + two then -- less or eq
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two then -- less or eq
s_write_byte_to_mem_p <= byte_ready_p_i; -- "Length" amount of
-- bytes are written
else
......@@ -305,7 +305,7 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
if byte_index_i > c_LENGTH_BYTE_INDEX then
if unsigned(byte_index_i) <= unsigned(s_rx_Length_byte) + two then
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + two then
s_write_byte_to_mem_p <= byte_ready_p_i;
else
......@@ -409,7 +409,7 @@ Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
if nfip_urst_i = '1' then
cons_ctrl_byte_o <= (others => '0');
cons_pdu_byte_o <= (others => '0');
s_rx_Length_byte <= (others => '0');
s_cons_lgth_byte <= (others => '0');
else
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) then -- only for consumed vars
......@@ -421,20 +421,20 @@ Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
cons_pdu_byte_o <= byte_i;
elsif ((byte_index_i = c_LENGTH_BYTE_INDEX) and (byte_ready_p_i ='1')) then
s_rx_Length_byte <= byte_i;
s_cons_lgth_byte <= byte_i;
end if;
else
cons_ctrl_byte_o <= (others => '0');
cons_pdu_byte_o <= (others => '0');
s_rx_Length_byte <= (others => '0');
s_cons_lgth_byte <= (others => '0');
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
cons_lgth_byte_o <= s_rx_Length_byte;
cons_lgth_byte_o <= s_cons_lgth_byte;
end architecture rtl;
--=================================================================================================
......
wf_cons_frame_validator.vhd
View file @ 40153778
......@@ -86,9 +86,9 @@ entity WF_cons_frame_validator is
port (
-- INPUTS
-- Signals from the wf_cons_bytes_processor unit
rx_ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte
rx_pdu_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
rx_length_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
cons_ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
-- Signal from the wf_rx_deserializer unit
rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC
......@@ -116,7 +116,7 @@ end entity WF_cons_frame_validator;
--=================================================================================================
architecture rtl of WF_cons_frame_validator is
signal s_rx_ctrl_byte_ok, s_rx_pdu_byte_ok, s_rx_length_byte_ok : std_logic;
signal s_cons_ctrl_byte_ok, s_cons_pdu_byte_ok, s_cons_lgth_byte_ok : std_logic;
--=================================================================================================
-- architecture begin
......@@ -126,13 +126,13 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Consumed_Frame_Validator: validation of an RP_DAT
--! frame with respect to: Ctrl, PDU, Length bytes as well as CRC, FSS, FES and code violations.
--! The bytes rx_ctrl_byte_i, rx_pdu_byte_i, rx_length_byte_i that arrive at the beginning of a
--! The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that arrive at the beginning of a
--! frame, have been registered and keep their values until the end of a frame.
--! The signal rx_fss_crc_fes_viol_ok_p_i, is a pulse at the end of the FES that combines
--! the check of the FSS, CRC, FES and the code violations.
Consumed_Frame_Validator: process (var_i, rx_ctrl_byte_i, rx_byte_index_i, rx_pdu_byte_i,
rx_fss_crc_fes_viol_ok_p_i, rx_length_byte_i, rx_crc_wrong_p_i)
Consumed_Frame_Validator: process (var_i, cons_ctrl_byte_i, rx_byte_index_i, cons_pdu_byte_i,
rx_fss_crc_fes_viol_ok_p_i, cons_lgth_byte_i, rx_crc_wrong_p_i)
begin
case var_i is
......@@ -141,18 +141,18 @@ begin
when var_1 | var_2 | var_rst => -- only for consumed RP_DAT frames
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_rx_ctrl_byte_ok <= '1'; -- RP_DAT.CTRL byte
if cons_ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_cons_ctrl_byte_ok <= '1'; -- RP_DAT.CTRL byte
else
s_rx_ctrl_byte_ok <= '0';
s_cons_ctrl_byte_ok <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_pdu_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_rx_pdu_byte_ok <= '1'; -- PDU_TYPE byte
if cons_pdu_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_cons_pdu_byte_ok <= '1'; -- PDU_TYPE byte
else
s_rx_pdu_byte_ok <= '0' ;
s_cons_pdu_byte_ok <= '0' ;
end if;
......@@ -160,17 +160,17 @@ begin
if rx_fss_crc_fes_viol_ok_p_i = '1' then -- checking the RP_DAT.Data.Length
-- byte, when the end of frame
-- arrives correctly.
if rx_byte_index_i = (unsigned(rx_length_byte_i) + 5) then -- rx_byte_index starts counting
s_rx_length_byte_ok <= '1'; -- from 0 and apart from the
if rx_byte_index_i = (unsigned(cons_lgth_byte_i) + 5) then -- rx_byte_index starts counting
s_cons_lgth_byte_ok <= '1'; -- from 0 and apart from the
-- user-data bytes, also counts the
else -- Control, PDU_TYPE, Length,
-- the 2 CRC and the FES bytes
s_rx_length_byte_ok <= '0';
s_cons_lgth_byte_ok <= '0';
end if;
else
s_rx_length_byte_ok <= '0';
s_cons_lgth_byte_ok <= '0';
end if;
......@@ -181,17 +181,17 @@ begin
-----------------------------------------------------------------------------------------------
-- when var_presence | var_identif | var_3 | var_whatever =>
-- s_rx_ctrl_byte_ok <= '0';
-- s_rx_pdu_byte_ok <= '0';
-- s_rx_length_byte_ok <= '0';
-- s_cons_ctrl_byte_ok <= '0';
-- s_cons_pdu_byte_ok <= '0';
-- s_cons_lgth_byte_ok <= '0';
-------------------------------------------------------------------------------------------------
when others =>
s_rx_ctrl_byte_ok <= '0';
s_rx_pdu_byte_ok <= '0';
s_rx_length_byte_ok <= '0';
s_cons_ctrl_byte_ok <= '0';
s_cons_pdu_byte_ok <= '0';
s_cons_lgth_byte_ok <= '0';
nfip_status_r_fcser_p_o <= '0';
end case;
......@@ -201,13 +201,13 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignment for the output signals
cons_frame_ok_p_o <= rx_fss_crc_fes_viol_ok_p_i and
s_rx_length_byte_ok and
s_rx_ctrl_byte_ok and
s_rx_pdu_byte_ok;
s_cons_lgth_byte_ok and
s_cons_ctrl_byte_ok and
s_cons_pdu_byte_ok;
nfip_status_r_tler_o <= s_rx_length_byte_ok and
s_rx_ctrl_byte_ok and
s_rx_pdu_byte_ok;
nfip_status_r_tler_o <= s_cons_lgth_byte_ok and
s_cons_ctrl_byte_ok and
s_cons_pdu_byte_ok;
end architecture rtl;
--=================================================================================================
......
wf_engine_control.vhd
View file @ 40153778
This diff is collapsed.
wf_package.vhd
View file @ 40153778
This diff is collapsed.
wf_prod_data_lgth_calc.vhd
View file @ 40153778
......@@ -81,16 +81,16 @@ entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
-- Signal from the WF_engine_control
var_i : in t_var; --! variable type that is being treated
var_i : in t_var; --! variable type that is being treated
-- OUTPUT
-- Signal to the WF_engine_control
tx_data_length_o : out std_logic_vector(7 downto 0)
prod_data_length_o : out std_logic_vector(7 downto 0)
);
end entity WF_prod_data_lgth_calc;
......@@ -100,7 +100,7 @@ end entity WF_prod_data_lgth_calc;
--=================================================================================================
architecture rtl of WF_prod_data_lgth_calc is
signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
signal s_prod_data_length, s_p3_length_decoded : unsigned(7 downto 0);
--=================================================================================================
-- architecture begin
......@@ -124,13 +124,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_tx_data_length <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_length;
s_prod_data_length <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_tx_data_length <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_length;
s_prod_data_length <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
......@@ -154,35 +154,35 @@ begin
if slone_i = '1' then
if nostat_i = '1' then -- 6 bytes (counting starts from 0)
s_tx_data_length <= to_unsigned(5, s_tx_data_length'length);
s_prod_data_length <= to_unsigned(5, s_prod_data_length'length);
else -- 7 bytes (counting starts from 0)
s_tx_data_length <= to_unsigned(6, s_tx_data_length'length);
s_prod_data_length <= to_unsigned(6, s_prod_data_length'length);
end if;
else
if nostat_i = '0' then
s_tx_data_length <= s_p3_length_decoded + 4; -- (counting starts from 0)
s_prod_data_length <= s_p3_length_decoded + 4; -- (counting starts from 0)
else
s_tx_data_length <= s_p3_length_decoded + 3; -- (counting starts from 0)
s_prod_data_length <= s_p3_length_decoded + 3; -- (counting starts from 0)
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_1 | var_2 | var_rst => -- to avoid Warnings from Synthesiser
s_tx_data_length <= (others => '0');
s_prod_data_length <= (others => '0');
when others =>
s_tx_data_length <= (others => '0');
s_prod_data_length <= (others => '0');
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment for the output
tx_data_length_o <= std_logic_vector (s_tx_data_length);
prod_data_length_o <= std_logic_vector (s_prod_data_length);
end architecture rtl;
......
wf_status_bytes_gen.vhd
View file @ 40153778
......@@ -182,6 +182,7 @@ begin
-- var. when it was not ready
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_txer
if (fd_wdgn_i = '0') then -- FIELDRIVE transmission error
......@@ -195,36 +196,19 @@ begin
s_nFIP_status_byte(c_T_WDER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
s_nFIP_status_byte(c_R_TLER_INDEX) <= nfip_status_r_tler_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
s_nFIP_status_byte(c_R_FCSER_INDEX) <= nfip_status_r_fcser_p_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
-- if ((var_i = var_1 or var_i = var_2) and (nfip_status_r_tler_i = '1')) then
-- s_nFIP_status_byte(c_R_TLER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
-- a cons. var. arrived for this
-- station with wrong PDU_TYPE,
-- Control or Length bytes
-- end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
-- if ((var_i = var_1 or var_i = var_2) and (nfip_status_r_fcser_p_i = '1')) then
-- s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
-- a cons. var. with a wrong
-- CRC arrived for this station
-- end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end if;
end if;
end if;
......
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