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nanoFIP - Gateware
Commit 4303602e authored by egousiou's avatar egousiou
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- correction on bytes counters (there were errors when 124 data bytes had to be… 

- correction on bytes counters (there were errors when 124 data bytes had to be sent and the vectors of (6 downto 0) were changed to (7 downto 0))

 - correction on nFIP status byte generation

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@69 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 1a34c6d9
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nanofip.vhd
View file @ 4303602e
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status_gen.vhd
View file @ 4303602e
......@@ -90,9 +90,11 @@ port (
crc_wrong_p_i : in std_logic;
-- Signals from the central control unit wf_engine_control
var_i : in t_var; --! variable type
var1_rdy_i : in std_logic; --! Variable 1 ready
var2_rdy_i : in std_logic; --! Variable 2 ready
var3_rdy_i : in std_logic; --! Variable 3 ready
-- Signal from nanofip
reset_status_bytes_i : in std_logic;
......@@ -100,8 +102,8 @@ port (
-- OUTPUTS
-- Output to wf_produced_vars
status_byte_o : out std_logic_vector(7 downto 0); --! status byte
mps_byte_o : out std_logic_vector(7 downto 0) --! mps byte
status_byte_o : out std_logic_vector(7 downto 0); --! status byte
mps_byte_o : out std_logic_vector(7 downto 0) --! mps byte
);
end entity status_gen;
......@@ -127,9 +129,9 @@ begin
begin
if rising_edge (uclk_i) then
if nFIP_rst_i = '1' then
s_var1_access <= (others => '0');
s_var2_access <= (others => '0');
s_var3_access <= (others => '0');
s_var1_access <= (others => '0');
s_var2_access <= (others => '0');
s_var3_access <= (others => '0');
else
s_var1_access(0) <= var1_access_a_i;
s_var2_access(0) <= var2_access_a_i;
......@@ -150,36 +152,43 @@ begin
if rising_edge(uclk_i) then
if ((nFIP_rst_i = '1') or (reset_status_bytes_i = '1')) then
status_byte_o <= (others => '0');
if ((nFIP_rst_i = '1') or (reset_status_bytes_i = '1')) then -- the byte is reinitialized
status_byte_o <= (others => '0'); -- after having been delivered
else
if ((var1_rdy_i = '0' and s_var1_access(1) = '1') or -- the user logic accessed a cosumed
(var2_rdy_i = '0' and s_var2_access(1) = '1')) then -- variable when it was not ready
status_byte_o(c_U_CACER_INDEX) <= '1';
end if;
if ((var3_rdy_i = '0') and (s_var3_access(1) = '1')) then -- the user logic accessed a prod
status_byte_o(c_U_PACER_INDEX) <= '1'; -- variable when it was not ready
end if;
if (code_violation_p_i = '1') then -- a variable arrived for this
status_byte_o(c_R_BNER_INDEX) <= '1'; -- station with a manchester 2
end if; -- violation
if (crc_wrong_p_i = '1') then -- a variable arrived for this station with wrong checksum
status_byte_o(c_R_FCSER_INDEX) <= '1';
end if;
if (fd_wdgn_i = '1') then -- the FIELDRIVE signalled a transmission error
status_byte_o(c_T_TXER_INDEX) <= '1';
end if;
if (fd_txer_i = '1') then -- the FIELDRIVE signalled a watchdog timer problem
status_byte_o(c_T_WDER_INDEX) <= '1';
end if;
if ((var1_rdy_i = '0' and s_var1_access(1) = '1') or -- since the last time the status
(var2_rdy_i = '0' and s_var2_access(1) = '1')) then -- byte was delivered,
status_byte_o(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cosmd
end if; -- variable when it was not ready
if ((var3_rdy_i = '0') and (s_var3_access(1) = '1')) then -- since the last time the status
status_byte_o(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
end if; -- the user logic accessed a prod
-- variable when it was not ready
if ((var_i = var_1 or var_i = var_2) and (code_violation_p_i = '1')) then
status_byte_o(c_R_BNER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
end if; -- a consumed var arrived for
-- this station with a manch code
-- violation (on the rp_dat.Data)
if ((var_i = var_1 or var_i = var_2)and(crc_wrong_p_i = '1')) then
status_byte_o(c_R_FCSER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
end if; -- a consumed var with a wrong CRC
-- arrived for this station
if (fd_wdgn_i = '0') then -- since the last time the status
status_byte_o(c_T_TXER_INDEX) <= '1'; -- byte was delivered,
end if; -- there has been a signal for
-- a FIELDRIVE transmission error
if (fd_txer_i = '1') then -- since the last time the status
status_byte_o(c_T_WDER_INDEX) <= '1'; -- byte was delivered,
end if; -- there has been a signal for a
-- FIELDRIVE watchdog timer problem
end if;
end if;
end process;
......@@ -195,7 +204,7 @@ end process;
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' or reset_status_bytes_i = '1' then
s_refreshment <= '0';
s_refreshment <= '0';
else
if (var3_access_a_i = '1') then
......@@ -215,12 +224,12 @@ end process;
begin
if slone_i='1' then
mps_byte_o <= (others => '0');
mps_byte_o (c_REFRESHMENT_INDEX) <= '1';
mps_byte_o (c_REFRESHMENT_INDEX) <= '1';
mps_byte_o (c_SIGNIFICANCE_INDEX) <= '1';
else
mps_byte_o <= (others => '0');
mps_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_byte_o (c_SIGNIFICANCE_INDEX) <= s_refreshment;
end if;
end process;
......
wf_consumed_vars.vhd
View file @ 4303602e
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wf_engine_control.vhd
View file @ 4303602e
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wf_package.vhd
View file @ 4303602e
......@@ -53,7 +53,7 @@ package wf_package is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the MPS status bits
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
......@@ -91,16 +91,16 @@ package wf_package is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(6 downto 0);
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(0 to 7) :=
(0 => "0000010", -- 2 bytes
1 => "0001000", -- 8 bytes
2 => "0010000", -- 16 bytes
3 => "0100000", -- 32 bytes
4 => "1000000", -- 64 bytes
5 => "1111100", -- 124 bytes
others => "0000000" -- reserved
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000000" -- reserved
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -136,9 +136,9 @@ package wf_package is
constant c_VAR_2_INDEX : integer := 4;
constant c_RESET_VAR_INDEX : integer := 5;
constant c_2nd_byte_addr : std_logic_vector(6 downto 0) := "0000010";
constant c_1st_byte_addr : std_logic_vector(6 downto 0) := "0000001";
constant c_CTRL_BYTE_INDEX : std_logic_vector(6 downto 0) := "0000000";
constant c_2nd_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000010";
constant c_1st_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000001";
constant c_CTRL_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000000";
......@@ -316,13 +316,13 @@ package wf_package is
wb_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_p_i : in std_logic;
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
byte_ready_p_i : in std_logic;
index_offset_i : in std_logic_vector(6 downto 0);
index_offset_i : in std_logic_vector(7 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector(7 downto 0);
wb_data_o : out std_logic_vector (15 downto 0);
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
reset_nFIP_and_FD_o : out std_logic;
reset_RSTON_o : out std_logic
......@@ -334,7 +334,6 @@ package wf_package is
component wf_produced_vars is
port (
uclk_i : in std_logic;
nFIP_rst_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
m_id_dec_i : in std_logic_vector (7 downto 0);
......@@ -343,14 +342,14 @@ package wf_package is
wb_clk_i : in std_logic;
data_i : in std_logic_vector (15 downto 0);
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_p_i : in std_logic;
wb_stb_r_edge_p_i : in std_logic;
wb_we_p_i : in std_logic;
wb_cyc_i : in std_logic;
nFIP_status_byte_i : in std_logic_vector(7 downto 0);
mps_byte_i : in std_logic_vector(7 downto 0);
var_i : in t_var;
data_length_i : in std_logic_vector(6 downto 0);
index_offset_i : in std_logic_vector(6 downto 0);
data_length_i : in std_logic_vector(7 downto 0);
index_offset_i : in std_logic_vector(7 downto 0);
sending_mps_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
......@@ -385,8 +384,8 @@ package wf_package is
var3_rdy_o: out std_logic;
var_o : out t_var;
consume_byte_p_o : out std_logic;
add_offset_o : out std_logic_vector(6 downto 0);
data_length_o : out std_logic_vector(6 downto 0)
add_offset_o : out std_logic_vector(7 downto 0);
data_length_o : out std_logic_vector(7 downto 0)
);
end component wf_engine_control;
......@@ -472,7 +471,8 @@ package wf_package is
fd_txer_i : in std_logic;
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
var_i : in t_var;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
......
wf_produced_vars.vhd
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wf_rx.vhd
View file @ 4303602e
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wf_rx_osc.vhd
View file @ 4303602e
......@@ -168,11 +168,12 @@ architecture rtl of wf_rx_osc is
--=================================================================================================
begin
s_period <= C_UCLK_TICKS(to_integer(unsigned(rate_i))); -- s_period: # uclock ticks for a period
s_half_period <= (s_period srl 1); -- s_period shifted 1 bit
s_one_forth_period <= s_period srl 2; -- s_period shifted 2 bits
s_jitter <= s_period srl 3; -- jitter defined as 1/8 of the period
s_counter_full <= s_period-1;
s_period <= C_UCLK_TICKS(to_integer(unsigned(rate_i))); -- # uclock ticks for a period
s_half_period <= (s_period srl 1); -- s_period shifted 1 bit
s_one_forth_period <= s_period srl 2; -- s_period shifted 2 bits
s_jitter <= s_period srl 3; -- jitter defined as 1/8 of
-- the period
s_counter_full <= s_period-1;
---------------------------------------------------------------------------------------------------
......@@ -191,9 +192,9 @@ begin
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
s_counter_tx <= (others => '0');
s_counter_rx <= (others => '0');
s_tx_clk_d1 <= '0';
s_counter_tx <= (others => '0');
s_counter_rx <= (others => '0');
s_tx_clk_d1 <= '0';
s_tx_clk_p_buff <= (others => '0');
else
......@@ -201,13 +202,13 @@ begin
-- transmission counter:
-- free counter measuring transmission periods
if (s_counter_tx = s_counter_full) then
s_counter_tx <= (others => '0');
s_counter_tx <= (others => '0');
else
s_counter_tx <= s_counter_tx + 1 ;
s_counter_tx <= s_counter_tx + 1 ;
end if;
-- clk signals:
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left -1 downto 0) & s_tx_clk_p; -- buffer
......@@ -216,7 +217,7 @@ begin
-- counter initialized after the first falling edge of rx_data_i
if (wait_d_first_f_edge_i = '1') then
if rx_data_f_edge_i = '1' then -- 1st falling edge of an id_dat received
s_counter_rx <= (others => '0'); -- counter initialized
s_counter_rx <= (others => '0'); -- counter initialized
else
if (s_counter_rx=s_counter_full) then -- measurement of the first period
s_counter_rx <= (others => '0');
......@@ -228,14 +229,14 @@ begin
-- for the rest of the rxd
else
if (s_rx_signif_edge_window = '1') and (d_edge_i ='1') then
s_counter_rx <= (others => '0'); -- when an edge appears inside
s_counter_rx <= (others => '0'); -- when an edge appears inside
-- the expected window, the
-- counter is reinitialized
elsif (s_counter_rx=s_counter_full) then -- otherwise, it continues counting
s_counter_rx <= (others => '0'); -- complete nominal periods
s_counter_rx <= (others => '0'); -- complete nominal periods
else
s_counter_rx <= s_counter_rx + 1 ;
s_counter_rx <= s_counter_rx + 1 ;
end if;
end if;
......@@ -306,11 +307,11 @@ begin
if rising_edge(uclk_i) then
-- initializations:
if (nFIP_rst_i = '1') then
s_rx_manch_clk <='0';
s_rx_bit_clk <= '0';
s_rx_bit_clk_d1 <='0';
s_rx_manch_clk_d1 <='0';
s_signif_edge_found <='0';
s_rx_manch_clk <='0';
s_rx_bit_clk <='0';
s_rx_bit_clk_d1 <='0';
s_rx_manch_clk_d1 <='0';
s_signif_edge_found <='0';
s_adjac_bits_edge_found <='0';
......@@ -318,43 +319,46 @@ begin
-- regarding significant edges:
if (s_rx_signif_edge_window='1') then -- looking for a significant edge
if (d_edge_i='1') then -- inside the corresponding window
s_rx_manch_clk <= not s_rx_manch_clk;
s_signif_edge_found <= '1'; -- indication that the edge was found
s_rx_manch_clk <= not s_rx_manch_clk;
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
end if;
elsif (s_signif_edge_found='0')and(s_counter_rx=s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk; --if a significant edge is not found where
s_rx_manch_clk <= not s_rx_manch_clk;
--if a significant edge is not found where
-- expected (code violation), the
-- rx_manch_clk is inverted right after the
-- end of the signif_edge_window
s_adjac_bits_edge_found <= '0'; -- re-initialization before the next cycle
s_adjac_bits_edge_found <= '0'; -- re-initialization before the next cycle
-- regarding edges between adjacent bits:
elsif (s_rx_adjac_bits_window='1') then -- looking for an edge inside
if (d_edge_i='1') then -- the corresponding window
s_rx_manch_clk <= not s_rx_manch_clk;-- inversion of rx_manch_clk
s_rx_bit_clk <= not s_rx_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
elsif (s_rx_adjac_bits_window='1') then -- looking for an edge inside
if (d_edge_i='1') then -- the corresponding window
s_rx_manch_clk <= not s_rx_manch_clk;-- inversion of rx_manch_clk
s_rx_bit_clk <= not s_rx_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
s_signif_edge_found <= '0'; -- re-initialization before the next cycle
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
elsif (s_adjac_bits_edge_found='0')and(s_counter_rx=s_half_period+s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk; -- if no edge occurs inside the
s_rx_bit_clk <= not s_rx_bit_clk; -- adjac_bits_edge_window, both clks are
-- inverted right after the end of it.
s_rx_manch_clk <= not s_rx_manch_clk; -- if no edge occurs inside the
s_rx_bit_clk <= not s_rx_bit_clk; --adjac_bits_edge_window,both clks are
-- inverted right after the end of it
s_signif_edge_found <= '0'; -- re-initialization before the next cycle
s_signif_edge_found <= '0'; -- reinitialization before next cycle
end if;
s_rx_manch_clk_d1 <= s_rx_manch_clk; -- s_rx_manch_clk: ____|-----|_____|-----|____
s_rx_manch_clk_d1 <= s_rx_manch_clk;
-- s_rx_manch_clk: ____|-----|_____|-----|____
-- s_rx_manch_clk_d1: ______|-----|_____|-----|__
-- rx_manch_clk_p_o: ____|-|___|-|___|-|___|-|__
s_rx_bit_clk_d1 <= s_rx_bit_clk; -- s_rx_bit_clk: ____|-----------|___________
s_rx_bit_clk_d1 <= s_rx_bit_clk;
-- s_rx_bit_clk: ____|-----------|___________
-- s_rx_bit_clk_d1: ______|-----------|_________
-- rx_bit_clk_p_o: ____|-|_________|-|_________
......@@ -372,18 +376,18 @@ begin
-- 2) a new bit
-- ___|-|___|-|___|-|___
rx_bit_clk_p_o <= s_rx_bit_clk xor s_rx_bit_clk_d1; -- a pulse 1-uclk period long, after
rx_bit_clk_p_o <= s_rx_bit_clk xor s_rx_bit_clk_d1; -- a pulse 1-uclk period long, after
-- a new bit
-- _________|-|_________
-- clocks needed for the transmitter:
tx_clk_o <= s_tx_clk_d1;
tx_clk_p_buff_o <= s_tx_clk_p_buff;
tx_clk_o <= s_tx_clk_d1;
tx_clk_p_buff_o <= s_tx_clk_p_buff;
-- output signals that have also been used in this unit's processes:
rx_signif_edge_window_o <= s_rx_signif_edge_window;
rx_adjac_bits_window_o <= s_rx_adjac_bits_window;
rx_adjac_bits_window_o <= s_rx_adjac_bits_window;
end architecture rtl;
......
wf_tx.vhd
View file @ 4303602e
......@@ -451,10 +451,13 @@ Input_Byte_Sampling: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
s_byte <= (others => '0');
s_byte <= (others => '0');
else
if byte_ready_p_i = '1' then
s_byte <= byte_i;
end if;
end if;
end if;
......@@ -468,8 +471,8 @@ Input_Byte_Sampling: process(uclk_i)
Manchester_Encoder_byte: process(s_byte)
begin
for I in byte_i'range loop
s_byte_manch(I*2) <= not s_byte(I);
s_byte_manch(I*2+1) <= s_byte(I);
s_byte_manch(I*2) <= not s_byte(I);
s_byte_manch(I*2+1) <= s_byte(I);
end loop;
end process;
......@@ -481,8 +484,8 @@ Input_Byte_Sampling: process(uclk_i)
Manchester_Encoder_crc_byte: process(s_crc_byte_manch)
begin
for I in s_crc_byte_manch'range loop
s_manchester_crc(I*2) <= not s_crc_byte_manch(I);
s_manchester_crc(I*2+1) <= s_crc_byte_manch(I);
s_manchester_crc(I*2) <= not s_crc_byte_manch(I);
s_manchester_crc(I*2+1) <= s_crc_byte_manch(I);
end loop;
end process;
......@@ -497,7 +500,7 @@ Input_Byte_Sampling: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
tx_data_o <= '0';
tx_data_o <= '0';
tx_enable_o <= '0';
else
......@@ -505,7 +508,7 @@ Input_Byte_Sampling: process(uclk_i)
tx_data_o <= s_data_bit;
end if;
tx_enable_o <= s_tx_enable;
tx_enable_o <= s_tx_enable;
end if;
end if;
......@@ -519,7 +522,7 @@ Input_Byte_Sampling: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
s_bit_index <= (others => '0');
s_bit_index <= (others => '0');
else
if s_bit_index_load = '1' then
......
wf_tx_rx.vhd
View file @ 4303602e
......@@ -71,21 +71,16 @@ entity wf_tx_rx is
port (
uclk_i : in std_logic; --! User Clock
nFIP_rst_i : in std_logic;
start_produce_p_i : in std_logic;
request_byte_p_o : out std_logic;
byte_ready_p_i : in std_logic;
byte_i : in std_logic_vector(7 downto 0);
last_byte_p_i : in std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
d_clk_o : out std_logic;
d_a_i : in std_logic;
rate_i : in std_logic_vector(1 downto 0);
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic;
......@@ -93,7 +88,6 @@ entity wf_tx_rx is
code_violation_p_o : out std_logic;
crc_wrong_p_o : out std_logic;
crc_ok_p_o : out std_logic
);
end entity wf_tx_rx;
......@@ -109,16 +103,14 @@ architecture rtl of wf_tx_rx is
constant C_CLKFCDLENTGTH : natural := 4;
signal s_d_d : std_logic_vector(2 downto 0);
signal s_d_re, s_d_fe : std_logic;
signal s_clk_fixed_carrier_p : std_logic;
signal s_data_in_d3 : std_logic_vector(2 downto 0);
signal s_data_in_r_edge, s_data_in_f_edge : std_logic;
signal s_d_filtered : std_logic;
signal s_d_ready_p : std_logic;
signal s_first_fe : std_logic;
signal s_clk_carrier_p : std_logic;
signal s_clk_bit_180_p, s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_edge_window, edge_180_window : std_logic;
signal s_d_edge, s_code_violation : std_logic;
signal s_data_in_edge, s_code_violation : std_logic;
signal s_clk_fixed_carrier_p_d : std_logic_vector(C_CLKFCDLENTGTH - 1 downto 0);
begin
......@@ -128,13 +120,19 @@ begin
process(uclk_i)
begin
if rising_edge(uclk_i) then
s_d_d <= s_d_d(1 downto 0) & d_a_i;
s_d_re <= (not s_d_d(2)) and s_d_d(1) and s_d_d(0);
s_d_fe <= (s_d_d(2)) and (not s_d_d(1)) and (not s_d_d(0));
s_data_in_d3 <= s_data_in_d3(1 downto 0) & d_a_i;
end if;
end process;
s_d_edge <= s_d_fe or s_d_re;
s_data_in_r_edge <= (not s_data_in_d3(2)) and s_data_in_d3(1); -- 1st flip-flop not considered (metastability)
-- transition on input signal of less than 2 clock cycles are not considered
s_data_in_f_edge <= s_data_in_d3(2) and (not s_data_in_d3(1));
s_data_in_edge <= s_data_in_f_edge or s_data_in_r_edge;
uwf_tx: wf_tx
generic map(C_CLKFCDLENTGTH => C_CLKFCDLENTGTH)
......@@ -162,20 +160,16 @@ begin
last_byte_p_o => last_byte_p_o,
fss_decoded_p_o => fss_decoded_p_o,
crc_ok_p_o => crc_ok_p_o,
rx_data_f_edge_i => s_d_fe,
rx_data_r_edge_i => s_d_re,
rx_data_f_edge_i => s_data_in_f_edge,
rx_data_r_edge_i => s_data_in_r_edge,
rx_data_filtered_i => s_d_filtered,
sample_manch_bit_p_i => s_sample_manch_bit_p,
wait_d_first_f_edge_o=> s_first_fe,
code_violation_p_o => code_violation_p_o,
crc_wrong_p_o => crc_wrong_p_o,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => s_edge_window,
adjac_bits_window_i => edge_180_window
);
......@@ -187,27 +181,16 @@ begin
port map(
uclk_i => uclk_i, --! User Clock
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
d_edge_i => s_d_edge,
rx_data_f_edge_i => s_d_fe,
d_edge_i => s_data_in_edge,
rx_data_f_edge_i => s_data_in_f_edge,
wait_d_first_f_edge_i => s_first_fe,
--! Bit rate \n
--! 00: 31.25 kbit/s \n
--! 01: 1 Mbit/s \n
--! 10: 2.5 Mbit/s \n
--! 11: reserved, do not use
rate_i => rate_i, --! Bit rate
rate_i => rate_i,
tx_clk_p_buff_o => s_clk_fixed_carrier_p_d,
tx_clk_o => d_clk_o,
rx_manch_clk_p_o => s_clk_carrier_p,
rx_bit_clk_p_o => s_clk_bit_180_p,
rx_signif_edge_window_o => s_edge_window,
rx_adjac_bits_window_o => edge_180_window
);
......@@ -216,7 +199,7 @@ begin
generic map (C_ACULENGTH => 10)
Port map( uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
rx_data_i => s_d_d(2),
rx_data_i => s_data_in_d3(2),
rx_data_filtered_o => s_d_filtered,
sample_bit_p_i => s_clk_bit_180_p,
sample_manch_bit_p_i => s_clk_carrier_p,
......
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