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nanoFIP - Gateware
Commit 6ead92d5 authored by egousiou's avatar egousiou
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units rearranged; general timeout added in wf_engine_control; deglitcher changed 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@163 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 481c9121
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Showing with 2617 additions and 1963 deletions
DualClkRAM.vhd
View file @ 6ead92d5
......@@ -94,12 +94,12 @@ entity DualClkRAM is
-- OUTPUTS
-- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0);--! data out A
DOUTA : out std_logic_vector (7 downto 0); --! data out A
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) --! data out B
);
end DualClkRAM;
end DualClkRAM;
--=================================================================================================
......@@ -137,7 +137,7 @@ architecture RAM4K9 of DualClkRAM is
--! pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
generic (MEMORYFILE:string := "");
generic (MEMORYFILE : string := "");
port(
ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
......@@ -153,7 +153,7 @@ architecture RAM4K9 of DualClkRAM is
BLKA, BLKB,
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic:= 'U';
RESET : in std_logic := 'U';
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic
......@@ -176,7 +176,7 @@ architecture RAM4K9 of DualClkRAM is
---------------------------------------------------------------------------------------------------
signal POWER, GROUND : std_logic ;
signal POWER, GROUND : std_logic;
--=================================================================================================
......@@ -197,7 +197,7 @@ begin
--! o WMODEA, WMODEB : GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
port map (
-- INPUTS
-- INPUTS concerning port A
......@@ -276,7 +276,7 @@ begin
-- Oututs
-- output concerning port A
-- data out A (1 byte)
DOUTA8 => OPEN,
DOUTA8 => open,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
DOUTA5 => DOUTA(5),
......@@ -288,7 +288,7 @@ begin
-- output concerning port B
-- data out B (1 byte)
DOUTB8 => OPEN,
DOUTB8 => open,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
DOUTB5 => DOUTB(5),
......@@ -299,7 +299,7 @@ begin
DOUTB0 => DOUTB(0)
);
end RAM4K9;
end RAM4K9;
--=================================================================================================
-- architecture end
--=================================================================================================
......
nanofip.vhd
View file @ 6ead92d5
......@@ -187,12 +187,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W MT420 Found inferred clock nanofip|wclk_i"; "W MT420 Found inferred clock nanofip|uclk_i" --
-- The wclk and uclk are the nanoFIP's input clocks. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -210,7 +204,7 @@ entity nanofip is
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding (station address)
......@@ -244,10 +238,10 @@ entity nanofip is
-- User Interface, WISHBONE Slave
wclk_i : in std_logic; --! WISHBONE clock; may be independent of uclk
adr_i : in std_logic_vector(9 downto 0); --! WISHBONE address
adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address
cyc_i : in std_logic; --! WISHBONE cycle
dat_i : in std_logic_vector(15 downto 0);--! dat_i(7 downto 0) : WISHBONE data in, memory mode
dat_i : in std_logic_vector (15 downto 0);--! dat_i(7 downto 0) : WISHBONE data in, memory mode
--! dat_i(15 downto 0): data in, stand-alone mode
rst_i : in std_logic; --! WISHBONE reset
......@@ -261,7 +255,7 @@ entity nanofip is
-- WorldFIP settings
s_id_o : out std_logic_vector(1 downto 0); --! Identification selection
s_id_o : out std_logic_vector (1 downto 0);--! Identification selection
-- FIELDRIVE
......@@ -269,7 +263,7 @@ entity nanofip is
fd_rstn_o : out std_logic; --! Initialisation control, active low
fd_txck_o : out std_logic; --! Line driver half bit clock
fd_txd_o : out std_logic; --! Transmitter data
fd_txena_o: out std_logic; --! Transmitter enable
fd_txena_o : out std_logic; --! Transmitter enable
-- User Interface, General signals
......@@ -321,25 +315,20 @@ architecture struc of nanofip is
end component;
signal s_rst, s_rx_byte_ready, s_start_prod_p, s_rst_rx_osc, s_prod_request_byte_p : std_logic;
signal s_prod_last_byte_p : std_logic;
signal s_rstin_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch: std_logic;
signal s_fss_crc_fes_manch_ok_p, s_cons_fss_decoded_p, s_wb_rst, s_rx_bit_clk_p : std_logic;
signal s_crc_or_manch_wrong_p, s_reset_nFIP_and_FD_p, s_rx_manch_clk_p : std_logic;
signal s_var1_access_synch, s_var2_access_synch, s_var3_access_synch, s_wb_stb_synch : std_logic;
signal s_rst, s_rx_byte_ready, s_start_tx_p, s_prod_request_byte_p : std_logic;
signal s_prod_last_byte_p, s_rst_tx_p : std_logic;
signal s_fss_crc_fes_manch_ok_p, s_rx_fss_decoded_p, s_wb_rst : std_logic;
signal s_crc_or_manch_wrong_p, s_reset_nFIP_and_FD_p : std_logic;
signal s_var1_rdy, s_var2_rdy, s_var3_rdy, s_assert_RSTON_p, s_wb_ack_prod : std_logic;
signal s_rst_rx_unit_p, s_nfip_status_r_tler, s_signif_edge_window , s_wb_we_synch : std_logic;
signal s_fd_rxd_synch, s_fd_rxd_edge_p, s_fd_rxd_r_edge_p, s_fd_rxd_f_edge_p : std_logic;
signal s_wb_stb_r_edge, s_adjac_bits_window, s_wb_cyc_synch, s_prod_byte_ready_p : std_logic;
signal s_rx_rst_p, s_nfip_status_r_tler : std_logic;
signal s_prod_byte_ready_p : std_logic;
signal s_var_from_control : t_var;
signal s_data_length_from_control, s_subs_synch : std_logic_vector (7 downto 0);
signal s_rx_byte, s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_data_length_from_control : std_logic_vector (7 downto 0);
signal s_rx_byte, s_byte_to_tx, s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_cons_prod_byte_index_from_control : std_logic_vector (7 downto 0);
signal s_slone_dati_synch : std_logic_vector(15 downto 0);
signal s_m_id_synch, s_c_id_synch : std_logic_vector (3 downto 0);
signal s_p3_lgth_synch : std_logic_vector (2 downto 0);
signal s_rate_synch : std_logic_vector (1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
--=================================================================================================
......@@ -348,71 +337,16 @@ architecture struc of nanofip is
begin
---------------------------------------------------------------------------------------------------
-- WF_inputs_synchronizer --
---------------------------------------------------------------------------------------------------
synchronizer: WF_inputs_synchronizer
port map(
uclk_i => uclk_i,
wb_clk_i => wclk_i,
nfip_rst_i => s_rst,
rstin_a_i => rstin_i,
wb_rst_i => s_wb_rst,
slone_a_i => slone_i,
nostat_a_i => nostat_i,
fd_wdgn_a_i => fd_wdgn_i,
fd_txer_a_i => fd_txer_i,
fd_rxd_a_i => fd_rxd_i,
fd_rxcdn_a_i => fd_rxcdn_i,
wb_cyc_a_i => cyc_i,
wb_we_a_i => we_i,
wb_stb_a_i => stb_i,
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
dat_a_i => dat_i,
rate_a_i => rate_i,
subs_a_i => subs_i,
m_id_a_i => m_id_i,
c_id_a_i => c_id_i,
p3_lgth_a_i => p3_lgth_i,
---------------------------------------------------------
rstin_o => s_rstin_synch,
slone_o => s_slone_synch,
nostat_o => s_nostat_synch,
fd_wdgn_o => s_fd_wdgn_synch,
fd_txer_o => s_fd_txer_synch,
fd_rxd_o => s_fd_rxd_synch,
fd_rxd_edge_p_o => s_fd_rxd_edge_p,
fd_rxd_r_edge_p_o => s_fd_rxd_r_edge_p,
fd_rxd_f_edge_p_o => s_fd_rxd_f_edge_p,
wb_cyc_o => s_wb_cyc_synch,
wb_we_o => s_wb_we_synch,
wb_stb_o => s_wb_stb_synch,
wb_stb_r_edge_p_o => s_wb_stb_r_edge,
var1_access_o => s_var1_access_synch,
var2_access_o => s_var2_access_synch,
var3_access_o => s_var3_access_synch,
slone_dati_o => s_slone_dati_synch,
rate_o => s_rate_synch,
subs_o => s_subs_synch,
m_id_o => s_m_id_synch,
c_id_o => s_c_id_synch,
p3_lgth_o => s_p3_lgth_synch
---------------------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- WF_reset_unit --
---------------------------------------------------------------------------------------------------
reset_unit : WF_reset_unit
port map(
port map (
uclk_i => uclk_i,
rstin_i => s_rstin_synch,
wb_clk_i => wclk_i,
rstin_a_i => rstin_i,
rstpon_i => rstpon_i,
rate_i => s_rate_synch,
rate_i => rate_i,
rst_i => rst_i,
var_i => s_var_from_control,
rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p,
......@@ -421,33 +355,8 @@ begin
nFIP_rst_o => s_rst,
wb_rst_o => s_wb_rst,
rston_o => rston_o,
fd_rstn_o => fd_rstn_o
fd_rstn_o => fd_rstn_o);
---------------------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- WF_rx_tx_osc --
---------------------------------------------------------------------------------------------------
rx_tx_osc :WF_rx_tx_osc
generic map(C_PERIODS_COUNTER_LENGTH => 11,
c_TX_CLK_BUFF_LGTH => 4)
port map(
uclk_i => uclk_i,
nfip_rst_i => s_rst,
rxd_edge_p_i => s_fd_rxd_edge_p,
rst_rx_osc_i => s_rst_rx_osc,
rate_i => s_rate_synch,
---------------------------------------------------------
tx_clk_p_buff_o => s_tx_clk_p_buff,
tx_clk_o => fd_txck_o,
rx_manch_clk_p_o => s_rx_manch_clk_p,
rx_bit_clk_p_o => s_rx_bit_clk_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window
---------------------------------------------------------
);
......@@ -455,38 +364,47 @@ begin
-- WF_consumption --
---------------------------------------------------------------------------------------------------
Consumption: WF_consumption
port map(
port map (
uclk_i => uclk_i,
slone_i => slone_i,
nfip_rst_i => s_rst,
subs_i => s_subs_synch,
fd_rxd_i => s_fd_rxd_synch,
fd_rxd_r_edge_p_i => s_fd_rxd_r_edge_p,
fd_rxd_f_edge_p_i => s_fd_rxd_f_edge_p,
subs_i => subs_i,
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready,
rx_fss_crc_fes_manch_ok_p_i => s_fss_crc_fes_manch_ok_p,
rx_crc_or_manch_wrong_p_i => s_crc_or_manch_wrong_p,
wb_clk_i => wclk_i,
wb_adr_i => adr_i (8 downto 0),
var_i => s_var_from_control,
byte_index_i => s_cons_prod_byte_index_from_control,
rst_rx_unit_p_i => s_rst_rx_unit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
sample_bit_p_i => s_rx_bit_clk_p,
sample_manch_bit_p_i => s_rx_manch_clk_p,
---------------------------------------------------------
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
data_o => dat_o,
byte_o => s_rx_byte,
byte_ready_p_o => s_rx_byte_ready,
fss_received_p_o => s_cons_fss_decoded_p,
crc_or_manch_wrong_p_o => s_crc_or_manch_wrong_p,
fss_crc_fes_manch_ok_p_o=> s_fss_crc_fes_manch_ok_p,
nfip_status_r_tler_o => s_nfip_status_r_tler,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p,
rst_rx_osc_o => s_rst_rx_osc
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p);
---------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- WF_fd_receiver --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver: WF_fd_receiver
port map (
uclk_i => uclk_i,
rate_i => rate_i,
fd_rxd_a_i => fd_rxd_i,
nfip_rst_i => s_rst,
rx_rst_p_i => s_rx_rst_p,
---------------------------------------------------------
rx_byte_o => s_rx_byte,
rx_byte_ready_p_o => s_rx_byte_ready,
rx_fss_crc_fes_manch_ok_p_o => s_fss_crc_fes_manch_ok_p,
rx_fss_received_p_o => s_rx_fss_decoded_p,
rx_crc_or_manch_wrong_p_o => s_crc_or_manch_wrong_p);
---------------------------------------------------------
);
......@@ -494,7 +412,7 @@ begin
-- WF_production --
---------------------------------------------------------------------------------------------------
Production: WF_production
port map(
port map (
uclk_i => uclk_i,
slone_i => slone_i,
nostat_i => nostat_i,
......@@ -503,36 +421,52 @@ begin
wb_data_i => dat_i(7 downto 0),
wb_adr_i => adr_i(8 downto 0),
wb_ack_prod_p_i => s_wb_ack_prod,
slone_data_i => s_slone_dati_synch,
var1_acc_i => s_var1_access_synch,
var2_acc_i => s_var2_access_synch,
var3_acc_i => s_var3_access_synch,
fd_txer_i => s_fd_txer_synch,
fd_wdgn_i => s_fd_wdgn_synch,
slone_data_i => dat_i,
var1_acc_a_i => var1_acc_i,
var2_acc_a_i => var2_acc_i,
var3_acc_a_i => var3_acc_i,
fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i,
var_i => s_var_from_control,
data_length_i => s_data_length_from_control,
byte_index_i => s_cons_prod_byte_index_from_control,
start_prod_p_i => s_start_prod_p,
byte_request_accept_p_i => s_prod_byte_ready_p,
last_byte_p_i => s_prod_last_byte_p,
nfip_status_r_tler_i => s_nfip_status_r_tler,
nfip_status_r_fcser_p_i => s_crc_or_manch_wrong_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
tx_clk_p_buff_i => s_tx_clk_p_buff,
model_id_dec_i => s_model_id_dec,
constr_id_dec_i => s_constr_id_dec,
---------------------------------------------------------
byte_request_p_o => s_prod_request_byte_p,
tx_data_o => fd_txd_o,
tx_enable_o => fd_txena_o,
byte_o => s_byte_to_tx,
u_cacer_o => u_cacer_o,
u_pacer_o => u_pacer_o,
r_tler_o => r_tler_o,
r_fcser_o => r_fcser_o,
var3_rdy_o => s_var3_rdy
var3_rdy_o => s_var3_rdy);
---------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- WF_fd_Transmitter --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Transmitter: WF_fd_transmitter
port map (
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => s_rst,
tx_byte_i => s_byte_to_tx,
tx_byte_request_accept_p_i => s_prod_byte_ready_p,
tx_last_byte_p_i => s_prod_last_byte_p,
tx_start_p_i => s_start_tx_p,
tx_rst_p_i => s_rst_tx_p,
---------------------------------------------------------
tx_byte_request_p_o => s_prod_request_byte_p,
tx_data_o => fd_txd_o,
tx_enable_o => fd_txena_o,
tx_clk_o => fd_txck_o);
---------------------------------------------------------
);
......@@ -541,31 +475,30 @@ begin
---------------------------------------------------------------------------------------------------
engine_control : WF_engine_control
generic map( c_QUARTZ_PERIOD => c_QUARTZ_PERIOD)
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => s_rst,
tx_byte_request_p_i => s_prod_request_byte_p,
rx_fss_received_p_i => s_cons_fss_decoded_p,
rx_fss_received_p_i => s_rx_fss_decoded_p,
rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready,
rx_fss_crc_fes_manch_ok_p_i => s_fss_crc_fes_manch_ok_p,
rx_crc_or_manch_wrong_p_i => s_crc_or_manch_wrong_p,
rate_i => s_rate_synch,
subs_i => s_subs_synch,
p3_lgth_i => s_p3_lgth_synch,
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
rate_i => rate_i,
subs_i => subs_i,
p3_lgth_i => p3_lgth_i,
slone_i => slone_i,
nostat_i => nostat_i,
---------------------------------------------------------
var_o => s_var_from_control,
tx_start_prod_p_o => s_start_prod_p ,
tx_start_p_o => s_start_tx_p ,
tx_byte_request_accept_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control,
prod_data_length_o => s_data_length_from_control,
rst_rx_unit_p_o => s_rst_rx_unit_p
rx_rst_p_o => s_rx_rst_p,
rst_tx_p_o => s_rst_tx_p);
---------------------------------------------------------
);
var1_rdy_o <= s_var1_rdy;
var2_rdy_o <= s_var2_rdy;
......@@ -577,17 +510,17 @@ begin
-- WF_model_constr_decoder --
---------------------------------------------------------------------------------------------------
model_constr_decoder : WF_model_constr_decoder
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => s_rst,
model_id_i => s_m_id_synch,
constr_id_i => s_c_id_synch,
model_id_i => m_id_i,
constr_id_i => c_id_i,
---------------------------------------------------------
select_id_o => s_id_o,
model_id_dec_o => s_model_id_dec,
constr_id_dec_o => s_constr_id_dec
constr_id_dec_o => s_constr_id_dec);
---------------------------------------------------------
);
......@@ -598,15 +531,15 @@ begin
port map (
wb_clk_i => wclk_i,
wb_rst_i => rst_i,
wb_cyc_i => s_wb_cyc_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
wb_we_i => s_wb_we_synch,
wb_stb_i => stb_i,
wb_cyc_i => cyc_i,
wb_we_i => we_i,
wb_adr_id_i => adr_i (9 downto 7),
---------------------------------------------------------------
wb_ack_prod_p_o => s_wb_ack_prod,
wb_ack_p_o => ack_o
wb_ack_p_o => ack_o);
---------------------------------------------------------------
);
---------------------------------------------------------------------------------------------------
......
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ 6ead92d5
......@@ -66,11 +66,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -78,24 +73,24 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (C_RAM_DATA_LGTH : integer; -- length of data word
c_RAM_ADDR_LGTH : integer); -- memory depth
generic (g_ram_data_lgth : integer; -- length of data word
g_ram_addr_lgth : integer); -- memory depth
port (
-- INPUTS
-- Inputs concerning port A
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
addr_porta_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
-- Inputs concerning port B
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_portb_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
addr_portb_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
data_portb_i : in std_logic_vector (g_ram_data_lgth - 1 downto 0);
write_en_portb_i : in std_logic;
-- OUTPUT
-- Output concerning port A
data_porta_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
data_porta_o : out std_logic_vector (g_ram_data_lgth -1 downto 0)
);
end WF_DualClkRAM_clka_rd_clkb_wr;
......
wf_bits_to_txd.vhd
View file @ 6ead92d5
......@@ -70,11 +70,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -82,8 +77,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--=================================================================================================
entity WF_bits_to_txd is
generic (c_TX_CLK_BUFF_LGTH: natural := 4); --! length of the clk buffer used for
--! the transmission synchronization
port (
-- INPUTS
-- nanoFIP User Interface, General signals
......
wf_cons_bytes_processor.vhd
View file @ 6ead92d5
......@@ -98,11 +98,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -112,7 +107,7 @@ entity WF_cons_bytes_processor is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode (active high)
......@@ -164,8 +159,8 @@ signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned(7 downto 0);
signal s_base_addr : unsigned(8 downto 0);
signal two : unsigned (7 downto 0);
signal s_base_addr : unsigned (8 downto 0);
signal s_write_byte_to_mem_p : std_logic;
--=================================================================================================
......@@ -183,13 +178,13 @@ begin
--! (for both the consumed and consumed broadcast variables)
Consumed_Bytes_To_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map(
c_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
c_RAM_ADDR_LGTH => 9) -- 2^9: depth of consumed RAM
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of consumed RAM
-- first 2 bits: identification of the memory block
-- remaining 7 bits: address of a byte inside the block
-- port A: WISHBONE that reads from the Consumed RAM; port B: nanoFIP that writes
port map(
port map (
clk_porta_i => wb_clk_i, -- WISHBONE clock
addr_porta_i => wb_adr_i(8 downto 0), -- address of byte to be read
-----------------------------------------------------------------------------
......@@ -209,7 +204,7 @@ begin
--! to DAT_O;
Consumed_Bytes_To_DATO: WF_cons_bytes_to_dato
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
transfer_byte_p_i => s_slone_write_byte_p,
......@@ -258,17 +253,18 @@ begin
--! If the consumed variable is the reset one the process latches the first and second data bytes.
Bytes_Processing: process (var_i, byte_index_i, slone_i, byte_i, two,
byte_ready_p_i, s_base_addr, s_cons_lgth_byte)
begin
s_addr <= std_logic_vector (unsigned(byte_index_i)+s_base_addr - 1); -- memory address of
-- the byte to be written
-- (-1 bc the Ctrl
-- byte is not written)
Bytes_Processing: process (var_i, byte_index_i, slone_i, byte_i, two,
byte_ready_p_i, s_base_addr, s_cons_lgth_byte)
begin
case var_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......
wf_cons_bytes_to_dato.vhd
View file @ 6ead92d5
......@@ -87,7 +87,7 @@ entity WF_cons_bytes_to_dato is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit unit
......
wf_cons_frame_validator.vhd
View file @ 6ead92d5
......@@ -81,13 +81,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 2, 5, 6 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the consumed variables var_1, var_2 and var_rst. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -107,6 +100,8 @@ entity WF_cons_frame_validator is
rx_fss_crc_fes_manch_ok_p_i: in std_logic; --! indication of a frame with correct FSS, FES, CRC
--! and manch. encoding
rx_crc_or_manch_wrong_p_i : in std_logic; --! indication .................
-- Signals from the WF_engine_control unit
rx_byte_index_i : in std_logic_vector (7 downto 0); --! index of byte being received
var_i : in t_var; --! variable type that is being treated
......@@ -145,7 +140,7 @@ begin
--! the checks of the FSS, CRC, FES and of the manch. encoding.
Consumed_Frame_Validator: process (var_i, cons_ctrl_byte_i, rx_byte_index_i, cons_pdu_byte_i,
rx_fss_crc_fes_manch_ok_p_i, cons_lgth_byte_i)
rx_fss_crc_fes_manch_ok_p_i, cons_lgth_byte_i, rx_crc_or_manch_wrong_p_i)
begin
case var_i is
......@@ -170,8 +165,10 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_fss_crc_fes_manch_ok_p_i = '1' then -- checking the RP_DAT.Data.Length
-- byte, when the FES arrives.
if rx_fss_crc_fes_manch_ok_p_i = '1' or rx_crc_or_manch_wrong_p_i = '1' then -- checking the
-- RP_DAT.Data.Length byte,
-- when the FES arrives
if unsigned(rx_byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5) then
s_cons_lgth_byte_ok <= '1'; -- rx_byte_index starts counting
-- from 0 and apart from the
......
wf_cons_outcome.vhd
View file @ 6ead92d5
......@@ -89,12 +89,12 @@ entity WF_cons_outcome is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings (synchronized with uclk)
subs_i : in std_logic_vector(7 downto 0);--! subscriber number coding
-- nanoFIP WorldFIP Settings
subs_i : in std_logic_vector (7 downto 0);--! subscriber number coding
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......@@ -106,8 +106,8 @@ entity WF_cons_outcome is
var_i : in t_var; --! variable type that is being treated
-- Signals from the WF_cons_bytes_processor
cons_var_rst_byte_1_i : in std_logic_vector(7 downto 0);--! 1st data-byte of a received var_rst
cons_var_rst_byte_2_i : in std_logic_vector(7 downto 0);--! 2nd data-byte of a received var_rst
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);--! 1st data-byte of a received var_rst
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);--! 2nd data-byte of a received var_rst
-- OUTPUTS
......
wf_consumption.vhd
View file @ 6ead92d5
......@@ -120,11 +120,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -135,7 +130,7 @@ entity WF_consumption is
port (
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic;
-- used by: all the units
......@@ -146,7 +141,7 @@ entity WF_consumption is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP WorldFIP Settings (synchronized with uclk)
-- nanoFIP WorldFIP Settings
subs_i : in std_logic_vector (7 downto 0);
-- used by: WF_cons_outcome for checking if the 2 bytes of a var_rst match the station's addr
......@@ -160,14 +155,12 @@ entity WF_consumption is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the nanoFIP FIELDRIVE (WF_inputs_synchronizer)
fd_rxd_i : in std_logic;
-- used by: WF_deglitcher
-- Signals from the WF_fd_receiver
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
-- used by: WF_deserializer
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -188,21 +181,6 @@ entity WF_consumption is
-- used by: WF_cons_bytes_processor for the reception coordination
-- used by: WF_cons_frame_validator for the validation of the Length byte
rst_rx_unit_p_i : in std_logic;
-- used by: WF_rx_deserializer
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_rx_tx_osc
adjac_bits_window_i : in std_logic;
signif_edge_window_i : in std_logic;
-- used by: WF_rx_deserializer for the timing of the reception
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
-- used by: WF_rx_deglitcher and WF_rx_deserializer for the timing of the reception
-----------------------------------------------------------------------------------------------
-- OUTPUTS
......@@ -214,24 +192,12 @@ entity WF_consumption is
-- nanoFIP User Interface, WISHBONE Slave outputs
data_o : out std_logic_vector (15 downto 0);
-- Signals to the WF_engine_control
byte_o : out std_logic_vector (7 downto 0);
byte_ready_p_o : out std_logic;
fss_received_p_o : out std_logic;
fss_crc_fes_manch_ok_p_o : out std_logic;
-- Signals to the WF_engine_control and the WF_produce
crc_or_manch_wrong_p_o : out std_logic;
-- Signals to the WF_produce
nfip_status_r_tler_o : out std_logic;
-- Signals to the WF_reset_unit
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
-- Signal to the WF_tx_rx_osc
rst_rx_osc_o : out std_logic
rst_nfip_and_fd_p_o : out std_logic
);
end entity WF_consumption;
......@@ -243,12 +209,10 @@ end entity WF_consumption;
--=================================================================================================
architecture struc of WF_consumption is
signal s_rxd_filtered,s_rxd_filtered_f_edge_p,s_cons_frame_ok_p : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p, s_fss_crc_fes_manch_ok_p : std_logic;
signal s_crc_or_manch_wrong_p, s_byte_ready_p : std_logic;
signal s_cons_frame_ok_p : std_logic;
signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0);
signal s_byte_from_rx : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
......@@ -256,60 +220,6 @@ architecture struc of WF_consumption is
begin
---------------------------------------------------------------------------------------------------
-- Deglitcher --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_deglitcher unit that applies a glitch filter to the "nanoFIP
--! FIELDRIVE" input signal fd_rxd.
Consumption_Deglitcher : WF_rx_deglitcher
generic map (c_DEGLITCH_LGTH => 10)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
rxd_i => fd_rxd_i,
sample_bit_p_i => sample_bit_p_i,
sample_manch_bit_p_i => sample_manch_bit_p_i,
-------------------------------------------------
rxd_filtered_o => s_rxd_filtered,
rxd_filtered_f_edge_p_o => s_rxd_filtered_f_edge_p,
sample_manch_bit_p_o => s_sample_manch_bit_p,
sample_bit_p_o => s_sample_bit_p
-------------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Deserializer --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_deserializer unit that deserializes the deglitched fd_rxd
--! and constructs bytes of data.
Consumption_Deserializer: WF_rx_deserializer
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
rst_rx_unit_p_i => rst_rx_unit_p_i,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => signif_edge_window_i,
adjac_bits_window_i => adjac_bits_window_i,
rxd_f_edge_p_i => fd_rxd_f_edge_p_i,
rxd_r_edge_p_i => fd_rxd_r_edge_p_i,
rxd_filtered_i => s_rxd_filtered,
rxd_filtered_f_edge_p_i => s_rxd_filtered_f_edge_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
-------------------------------------------------
byte_ready_p_o => s_byte_ready_p,
byte_o => s_byte_from_rx,
fss_crc_fes_manch_ok_p_o => s_fss_crc_fes_manch_ok_p,
rst_rx_osc_o => rst_rx_osc_o,
fss_received_p_o => fss_received_p_o,
crc_or_manch_wrong_p_o => s_crc_or_manch_wrong_p
-------------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Bytes Processing --
......@@ -319,25 +229,24 @@ begin
--! transferring them to the "nanoFIP User Interface, NON_WISHBONE" output bus DAT_O.
Consumption_Bytes_Processor : WF_cons_bytes_processor
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
byte_ready_p_i => s_byte_ready_p,
byte_ready_p_i => rx_byte_ready_p_i,
var_i => var_i,
byte_index_i => byte_index_i,
byte_i => s_byte_from_rx,
byte_i => rx_byte_i,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
-------------------------------------------------
--------------------------------------------------------
data_o => data_o,
cons_ctrl_byte_o => s_cons_ctrl_byte,
cons_pdu_byte_o => s_cons_pdu_byte,
cons_lgth_byte_o => s_cons_lgth_byte,
cons_var_rst_byte_1_o => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_o => s_cons_var_rst_byte_2
-------------------------------------------------
);
cons_var_rst_byte_2_o => s_cons_var_rst_byte_2);
--------------------------------------------------------
......@@ -349,18 +258,18 @@ begin
--! bytes of the Manchester encoding.
Consumption_Frame_Validator: WF_cons_frame_validator
port map(
port map (
cons_ctrl_byte_i => s_cons_ctrl_byte,
cons_pdu_byte_i => s_cons_pdu_byte,
cons_lgth_byte_i => s_cons_lgth_byte,
rx_fss_crc_fes_manch_ok_p_i => s_fss_crc_fes_manch_ok_p,
rx_fss_crc_fes_manch_ok_p_i => rx_fss_crc_fes_manch_ok_p_i,
rx_crc_or_manch_wrong_p_i => rx_crc_or_manch_wrong_p_i,
var_i => var_i,
rx_byte_index_i => byte_index_i,
-------------------------------------------------------
--------------------------------------------------------
nfip_status_r_tler_o => nfip_status_r_tler_o,
cons_frame_ok_p_o => s_cons_frame_ok_p
-------------------------------------------------------
);
cons_frame_ok_p_o => s_cons_frame_ok_p);
--------------------------------------------------------
......@@ -381,23 +290,12 @@ begin
var_i => var_i,
cons_var_rst_byte_1_i => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_i => s_cons_var_rst_byte_2,
-------------------------------------------------------
--------------------------------------------------------
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
assert_rston_p_o => assert_rston_p_o,
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o
-------------------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Outputs --
---------------------------------------------------------------------------------------------------
byte_o <= s_byte_from_rx;
byte_ready_p_o <= s_byte_ready_p;
fss_crc_fes_manch_ok_p_o <= s_fss_crc_fes_manch_ok_p;
crc_or_manch_wrong_p_o <= s_crc_or_manch_wrong_p;
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o);
--------------------------------------------------------
end architecture struc;
......
wf_crc.vhd
View file @ 6ead92d5
......@@ -67,18 +67,12 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_crc
--=================================================================================================
entity WF_crc is
generic (c_GENERATOR_POLY_length : natural := 16); --! default value
port (
-- INPUTS
-- nanoFIP User Interface, General signals
......@@ -98,7 +92,7 @@ port (
crc_ok_p : out std_logic; --! signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH-1 downto 0)--!calculated CRC
);
end entity WF_crc;
......@@ -110,7 +104,7 @@ end entity WF_crc;
architecture rtl of WF_crc is
signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0);
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -124,14 +118,14 @@ begin
Gen_16_bit_Register_and_Interconnections:
for I in 0 to c_GENERATOR_POLY'left generate
for I in 0 to c_CRC_GENER_POLY'left generate
iteration_0: if I = 0 generate
s_q_nx(I) <= ((data_bit_i) xor s_q(s_q'left));
end generate;
next_iterations: if I > 0 generate
s_q_nx(I) <= s_q(I-1) xor (c_GENERATOR_POLY(I) and (data_bit_i xor s_q(s_q'left)));
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
end generate;
......@@ -171,15 +165,15 @@ crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
--! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_VERIFICATION_MASK. When the CRC calculated from the received data matches the
--! c_VERIFICATION_MASK, it is implied that a correct CRC word has been received for the preceded
--! predefined c_CRC_VERIFIC_MASK. When the CRC calculated from the received data matches the
--! c_CRC_VERIFIC_MASK, it is implied that a correct CRC word has been received for the preceded
--! data and the signal crc_ok_p gives a 1 uclk-wide pulse.
Syndrome_Verification: process (s_q, s_crc_bit_ready_p)
begin
s_q_check_mask <= s_q xor c_VERIFICATION_MASK;
s_q_check_mask <= s_q xor c_CRC_VERIFIC_MASK;------------
if (unsigned(not s_q_check_mask)) = 0 then
crc_ok_p <= s_crc_bit_ready_p;
......
wf_decr_counter.vhd
View file @ 6ead92d5
......@@ -55,11 +55,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -95,7 +90,7 @@ end entity WF_decr_counter;
--=================================================================================================
architecture rtl of WF_decr_counter is
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -126,7 +121,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
-- Concurrent assignments for the output signals
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
......
wf_engine_control.vhd
View file @ 6ead92d5
......@@ -103,29 +103,21 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_engine_control
--=================================================================================================
entity WF_engine_control is
generic (c_QUARTZ_PERIOD : real);
port (
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
nostat_i : in std_logic; --!if negated,nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings (synchronized with uclk)
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0);--! produced var user-data length
rate_i : in std_logic_vector (1 downto 0);--! WorldFIP bit rate
subs_i : in std_logic_vector (7 downto 0);--! subscriber number coding
......@@ -169,7 +161,7 @@ entity WF_engine_control is
-- Signal to the WF_tx_serializer unit
tx_byte_request_accept_p_o : out std_logic;--! answer to tx_byte_request_p_i
tx_last_byte_p_o : out std_logic;--! indication that it is the last data-byte
tx_start_prod_p_o : out std_logic;--! launches the transmitters's FSM
tx_start_p_o : out std_logic;--! launches the transmitters's FSM
-- Signal to the WF_prod_bytes_retriever
prod_data_length_o : out std_logic_vector (7 downto 0);--! # bytes of the Conrol & Data
......@@ -180,10 +172,12 @@ entity WF_engine_control is
-- Signals to the WF_consumption
-- Signal to the WF_rx_deserializer
rst_rx_unit_p_o : out std_logic;--!if a FES hasn't arrived after 8 bytes of an ID_DAT
rx_rst_p_o : out std_logic;--!if a FES hasn't arrived after 8 bytes of an ID_DAT
--!or after 134 bytes of a RP_DAT, the state machine
--!of the WF_rx_deserializer returns to idle state
rst_tx_p_o : out std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production & WF_consumption
......@@ -210,25 +204,26 @@ architecture rtl of WF_engine_control is
type control_st_t is (idle,
id_dat_control_byte, id_dat_var_byte, id_dat_subs_byte, id_dat_frame_ok,
consume, consume_wait_FSS,
consume_wait_FSS, consume,
produce_wait_turnar_time, produce);
signal control_st, nx_control_st :control_st_t;
signal s_var_aux, s_var, s_var_id : t_var;
signal s_time_c_is_zero, s_broadcast_var, s_tx_start_prod_p, s_inc_rx_bytes_counter : std_logic;
signal s_producing, s_consuming, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_cons_wait_FSS : std_logic;
signal s_prod_data_length_match, s_tx_byte_request_accept_p, s_prod_wait_turnar_time : std_logic;
signal s_tx_byte_request_accept_p_d1, s_load_time_counter : std_logic;
signal s_rst_rx_bytes_counter, s_tx_last_byte_p_d, s_tx_last_byte_p : std_logic;
signal s_id_dat_subs_byte, s_id_dat_frame_ok, s_tx_byte_request_accept_p_d2 : std_logic;
signal control_st, nx_control_st : control_st_t;
signal s_var_aux, s_var : t_var;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_subs_byte : std_logic;
signal s_id_dat_frame_ok, s_cons_wait_FSS, s_consuming, s_prod_wait_turnar_time : std_logic;
signal s_producing, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_rst_rx_bytes_counter, s_inc_rx_bytes_counter, s_var_identified : std_logic;
signal s_load_time_counter, s_time_c_is_zero, s_session_timedout : std_logic;
signal s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p_d2, s_tx_last_byte_p, s_tx_last_byte_p_d : std_logic;
signal s_prod_data_length_match, s_tx_start_prod_p, s_broadcast_var : std_logic;
signal s_time_counter_top, s_turnaround_time, s_silence_time : unsigned (14 downto 0);
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
signal s_time_counter_top, s_time_c, s_turnaround_time, s_silence_time : unsigned(14 downto 0);
signal s_prod_data_length, s_tx_byte_index, s_rx_byte_index : std_logic_vector (7 downto 0);
signal s_tx_byte_index, s_rx_byte_index, s_prod_data_length : std_logic_vector (7 downto 0);
signal s_produce_or_consume : std_logic_vector (1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -277,12 +272,12 @@ begin
--!@brief Combinatorial process Engine_Control_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
Engine_Control_FSM_Comb_State_Transitions: process (s_time_c_is_zero,s_produce_or_consume,subs_i,
Engine_Control_FSM_Comb_State_Transitions: process (s_time_c_is_zero, s_produce_or_consume,subs_i,
rx_crc_or_manch_wrong_p_i, s_session_timedout,
rx_fss_crc_fes_manch_ok_p_i, s_broadcast_var,
s_var_id, rx_byte_ready_p_i,rx_byte_i,
s_var_identified,rx_byte_ready_p_i,rx_byte_i,
control_st, rx_fss_received_p_i,
s_rx_bytes_c, s_tx_last_byte_p,
rx_crc_or_manch_wrong_p_i)
s_rx_bytes_c, s_tx_last_byte_p)
begin
......@@ -292,45 +287,55 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when idle =>
if rx_fss_received_p_i = '1' then -- correct FSS arrived
nx_control_st <= id_dat_control_byte;
if (rx_fss_received_p_i = '1') then -- correct FSS arrived
nx_control_st <= id_dat_control_byte;-- session timeout counter starts counting
else
nx_control_st <= idle;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_control_byte =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte; -- check of ID_DAT Control byte
elsif (rx_byte_ready_p_i = '1') then
nx_control_st <= idle; -- byte different than the expected ID_DAT Control
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
else
nx_control_st <= id_dat_control_byte;-- ID_DAT Control byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_var_byte =>
if (rx_byte_ready_p_i = '1') and (s_var_id /= var_whatever) then
if (rx_byte_ready_p_i = '1') and (s_var_identified = '1') then
nx_control_st <= id_dat_subs_byte; -- check of the ID_DAT variable
elsif (rx_byte_ready_p_i = '1') then
nx_control_st <= idle; -- byte not corresponding to an expected variable
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
else
nx_control_st <= id_dat_var_byte; -- ID_DAT variable byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_subs_byte =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i = subs_i) then
nx_control_st <= id_dat_frame_ok; -- check of the ID_DAT subscriber..
elsif (rx_byte_ready_p_i = '1') and (s_broadcast_var = '1') then--
elsif (rx_byte_ready_p_i = '1') and (s_broadcast_var = '1') then
nx_control_st <= id_dat_frame_ok; -- ..or if it is a broadcast variable
-- note: broadcast consumed vars are only treated in
-- memory mode, but at this moment we do not do this
......@@ -340,10 +345,14 @@ begin
elsif (rx_byte_ready_p_i = '1') then -- not the station's address, neither a broadcast
nx_control_st <= idle;
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
else
nx_control_st <= id_dat_subs_byte; -- ID_DAT subscriber byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when id_dat_frame_ok =>
......@@ -354,8 +363,10 @@ begin
nx_control_st <= consume_wait_FSS; -- CRC & FES check ok! station has to consume
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_rx_bytes_c > 2) then
-- 3 bytes after the arrival of the subscriber
nx_control_st <= idle; -- byte, a FES has not been detected
nx_control_st <= idle; -- 3 bytes after the arrival of the subscriber
-- byte, a FES has not been detected
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
else
nx_control_st <= id_dat_frame_ok; -- CRC & FES bytes being arriving
......@@ -365,24 +376,30 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce_wait_turnar_time =>
if s_time_c_is_zero = '1' then -- turnaround time passed
if (s_time_c_is_zero = '1') then -- turnaround time passed
nx_control_st <= produce;
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
else
nx_control_st <= produce_wait_turnar_time;-- waiting for turnaround time to pass
nx_control_st <= produce_wait_turnar_time; -- waiting for turnaround time to pass
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when consume_wait_FSS =>
if rx_fss_received_p_i = '1' then -- FSS of the consumed RP_DAT arrived
if (rx_fss_received_p_i = '1') then -- FSS of the consumed RP_DAT arrived
nx_control_st <= consume;
elsif s_time_c_is_zero = '1' then -- if the FSS of the consumed RP_DAT frame doesn't
elsif (s_time_c_is_zero = '1') then -- if the FSS of the consumed RP_DAT frame doesn't
nx_control_st <= idle; -- arrive before the expiration of the silence time,
-- the engine goes back to idle
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
else
nx_control_st <= consume_wait_FSS;-- counting silence time
end if;
......@@ -397,20 +414,28 @@ begin
nx_control_st <= idle; -- back to idle
elsif s_session_timedout = '1' then
nx_control_st <= idle;
else
nx_control_st <= consume; -- consuming bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when produce =>
if s_tx_last_byte_p = '1' then -- last byte to be produced
if (s_tx_last_byte_p = '1') then -- last byte to be produced
nx_control_st <= idle;
elsif (s_session_timedout = '1') then
nx_control_st <= idle;
else
nx_control_st <= produce; -- producing bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
nx_control_st <= idle;
......@@ -427,9 +452,10 @@ begin
case control_st is
when idle =>
--------------------------------
---------------------------------
s_idle_state <= '1';
--------------------------------
---------------------------------
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
......@@ -441,10 +467,11 @@ begin
when id_dat_control_byte =>
s_idle_state <= '0';
--------------------------------
---------------------------------
s_id_dat_ctrl_byte <= '1';
--------------------------------
---------------------------------
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
......@@ -453,12 +480,14 @@ begin
s_consuming <= '0';
s_producing <= '0';
when id_dat_var_byte =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
--------------------------------
---------------------------------
s_id_dat_var_byte <= '1';
--------------------------------
---------------------------------
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
......@@ -466,59 +495,69 @@ begin
s_consuming <= '0';
s_producing <= '0';
when id_dat_subs_byte =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
--------------------------------
---------------------------------
s_id_dat_subs_byte <= '1';
--------------------------------
---------------------------------
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when id_dat_frame_ok =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
--------------------------------
---------------------------------
s_id_dat_frame_ok <= '1';
--------------------------------
---------------------------------
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when produce_wait_turnar_time =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
--------------------------------
---------------------------------
s_prod_wait_turnar_time <= '1';
--------------------------------
---------------------------------
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_producing <= '0';
when consume_wait_FSS =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
--------------------------------
---------------------------------
s_cons_wait_FSS <= '1';
--------------------------------
---------------------------------
s_consuming <= '0';
s_producing <= '0';
when consume =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
......@@ -526,12 +565,14 @@ begin
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
--------------------------------
---------------------------------
s_consuming <= '1';
--------------------------------
---------------------------------
s_producing <= '0';
when produce =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
......@@ -540,15 +581,16 @@ begin
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
--------------------------------
---------------------------------
s_producing <= '1';
--------------------------------
---------------------------------
when others =>
--------------------------------
---------------------------------
s_idle_state <= '1';
--------------------------------
---------------------------------
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
......@@ -563,7 +605,6 @@ begin
---------------------------------------------------------------------------------------------------
-- Counters for the number of bytes being received or produced --
---------------------------------------------------------------------------------------------------
......@@ -574,7 +615,7 @@ begin
--! RP_DAT.Data.MPS_status and RP_DAT.Data.nanoFIP_status bytes).
Produced_Data_Length_Calculator: WF_prod_data_lgth_calc
port map(
port map (
slone_i => slone_i,
nostat_i => nostat_i,
p3_lgth_i => p3_lgth_i,
......@@ -590,10 +631,9 @@ begin
--! counts bytes following the "tx_byte_request_p_i" pulse in the "produce" state.
Produced_Bytes_Counter: WF_incr_counter
generic map(g_counter_lgth => 8)
port map(
generic map (g_counter_lgth => 8)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => s_rst_prod_bytes_counter,
incr_counter_i => s_inc_prod_bytes_counter,
-------------------------------------------------------
......@@ -620,10 +660,9 @@ begin
--! bytes following the "rx_byte_ready_p_i" pulse in the "consume" state.
Rx_Bytes_Counter: WF_incr_counter
generic map(g_counter_lgth => 8)
port map(
generic map (g_counter_lgth => 8)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => s_rst_rx_bytes_counter,
incr_counter_i => s_inc_rx_bytes_counter,
-------------------------------------------------------
......@@ -684,6 +723,34 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- General Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_decr_counter for the counting of turnaround and silence times.
--! The same counter is used in both cases. The signal s_time_counter_top initializes the counter
--! to either the turnaround or the silence time. If after the correct arrival of an ID_DAT frame
--! the identified variable is a produced one the counter loads to the turnaround time, whereas if
--! it had been a consumed variable it loads to the silence. The counting takes place during the
--! states "produce_wait_turnar_time" and "consume_wait_FSS" respectively.
General_Timeout_Counter: WF_decr_counter
generic map (g_counter_lgth => 21)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => (others => '1'),
counter_load_i => s_idle_state,
counter_decr_p_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Turnaround & Silence times --
---------------------------------------------------------------------------------------------------
......@@ -697,18 +764,18 @@ begin
--! states "produce_wait_turnar_time" and "consume_wait_FSS" respectively.
Turnaround_and_Silence_Time_Counter: WF_decr_counter
generic map(g_counter_lgth => 15)
port map(
generic map (g_counter_lgth => 15)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_time_counter_top,
counter_load_i => s_load_time_counter,
counter_decr_p_i => '1', -- on each uclk tick
counter_o => s_time_c,
counter_o => open,
-------------------------------------------------------
counter_is_zero_o => s_time_c_is_zero
counter_is_zero_o => s_time_c_is_zero);
-------------------------------------------------------
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of the turnaround and silence times (in equivalent number of uclk ticks) from the
......@@ -753,98 +820,120 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- Identification of the variable received by an ID_DAT frame --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! The following two processes: ID_DAT_var_identifier and ID_DAT_var manage the
--! signals s_var_id, s_var_aux and s_var. All of them are used to keep the value of the
--! ID_DAT.Identifier.Variable byte of the incoming ID_DAT frame, but change their value on
--! different moments:
--! s_var_id : is constantly following the incoming byte rx_byte_i
--! s_var_aux : locks to the value of s_var_id when the ID_DAT.Identifier.Variable byte
--! is received (in "id_dat_var_byte" state when "rx_byte_ready_p_i" is activated)
--! s_var : locks to the value of s_var_aux at the end of the ID_DAT frame if the frame has
--! been correct and the specified station address concerns the station.
--! The following process generates the signals:
--! o internal signal s_var_aux that locks to the value of the ID_DAT.Identifier.Variable byte
--! after its arrival
--! o output signal var_o (or s_var, used also internally by the WF_prod_data_lgth_calc) that
--! locks to the value of the ID_DAT.Identifier.Variable byte at the end of the reception of a
--! valid ID_DAT frame, if the specified station address concerns the station.
--! For a produced var this takes place at the "produce_wait_turnar_time" state, and
--! for a consumed at the "consume" state (not in the "consume_wait_silence_time", as
--! at this state it is not sure that a consumed RP_DAT frame will finally arrive).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ID_DAT_var_identifier: process (rx_byte_i)
begin
s_var_id <= var_whatever;
for I in c_VARS_ARRAY'range loop
if rx_byte_i = c_VARS_ARRAY(I).hexvalue then
s_var_id <= c_VARS_ARRAY(I).var;
exit;
end if;
end loop;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! for a consumed at the "consume" state (not in the "consume_wait_silence_time", as at this
--! state it is not sure that a consumed RP_DAT frame will finally arrive).
ID_DAT_var: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var <= var_whatever;
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_produce_or_consume <= "00";
s_broadcast_var <= '0';
else
if s_idle_state = '1' then
s_var_aux <= var_whatever;
elsif (s_id_dat_var_byte = '1') and (rx_byte_ready_p_i = '1') then
s_var_aux <= s_var_id;
end if;
if s_idle_state = '1' then
-------------------------------------------------------------------------------------------
if (s_idle_state = '1') or (s_id_dat_ctrl_byte = '1') then -- new frame initializations
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_produce_or_consume <= "00";
s_broadcast_var <= '0';
elsif (s_prod_wait_turnar_time = '1') or (s_consuming = '1') then
s_var <= s_var_aux;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief: Combinatorial process Var_Characteristics: management of the signals
--! s_produce_or_consume and s_broadcast_var, according to the value of s_var_aux.
Var_Characteristics: process (s_var_aux)
begin
-------------------------------------------------------------------------------------------
elsif (s_id_dat_var_byte = '1') and (rx_byte_ready_p_i = '1') then -- var byte arrived
case rx_byte_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue =>
s_var_aux <= var_presence;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue =>
s_var_aux <= var_identif;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue =>
s_var_aux <= var_1;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_1_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue =>
s_var_aux <= var_2;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_2_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue =>
s_var_aux <= var_3;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_3_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue =>
s_var_aux <= var_rst;
s_produce_or_consume <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_RST_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
s_var_aux <= var_whatever;
s_produce_or_consume <= "00";
s_broadcast_var <= '0';
end case;
for I in c_VARS_ARRAY'range loop
if s_var_aux = c_VARS_ARRAY(I).var then
-------------------------------------------------------------------------------------------
elsif (s_prod_wait_turnar_time = '1') or (s_consuming = '1') then -- ID_DAT OK!
s_var <= s_var_aux;
if c_VARS_ARRAY(I).response = produce then
s_produce_or_consume <= "10";
else
s_produce_or_consume <= "01";
end if;
exit;
end if;
end loop;
if ((s_var_aux = var_2) or (s_var_aux = var_rst)) then
s_broadcast_var <= '1';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment (needed by the FSM)
s_var_identified <= '1' when rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue
else '0';
---------------------------------------------------------------------------------------------------
-- Introducing delays --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief: Registering the signals tx_last_byte_p_o, tx_byte_request_accept_p_o,tx_start_prod_p_o
--!@brief: Registering the signals tx_last_byte_p_o, tx_byte_request_accept_p_o,tx_start_p_o
process (uclk_i)
begin
......@@ -871,6 +960,7 @@ begin
s_tx_last_byte_p <= s_producing and s_prod_data_length_match and tx_byte_request_p_i;
---------------------------------------------------------------------------------------------------
-- Concurrent Signal Assignments --
---------------------------------------------------------------------------------------------------
......@@ -889,14 +979,17 @@ begin
-- If the WF_rx_deserializer continues receiving bytes when the engine_control is idle, it has to
-- be reset. This happens when the number of bytes that have arrived exceed the expected (ID_DAT >8
-- bytes and consumed RP_DAT > 130 bytes)
rst_rx_unit_p_o <= s_idle_state and rx_byte_ready_p_i;
rx_rst_p_o <= (s_idle_state and rx_byte_ready_p_i) or s_session_timedout;
-- Production starts after the expiration of the turnaround time
tx_start_prod_p_o <= s_tx_start_prod_p;
tx_start_p_o <= s_tx_start_prod_p;
rst_tx_p_o <= s_session_timedout;
---------------------------------------------------------------------------------------------------
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
......
wf_fd_receiver.vhd 0 → 100644
View file @ 6ead92d5
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_fd_receiver.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_fd_receiver --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit groups the main actions that concern the FIELDRIVE receiver.
--! It instantiates the units:
--!
--! o WF_rx_deserializer : for the formation of bytes of data to be provided to the:
--! - WF_engine_control unit, for the contents of ID_DAT frames
--! - WF_cons_bytes_processor unit, for the contents of consumed
--! RP_DAT frames
--!
--! o WF_rx_osc : for the clock recovery
--!
--! o WF_rx_deglitcher : for the filtering of the input FD_RXD
--!
--!
--! _________________________ _________________________
--! | | | |
--! | WF_Consumption | | WF_engine_control |
--! |_________________________| |_________________________|
--! /\ /\
--! ___________________________________________________________
--! | WF_fd_revceiver |
--! | _________ |
--! | _______________________________________ | | |
--! | | | | | |
--! | | WF_rx_deserializer | | WF_rx | |
--! | | | < | _osc | |
--! | |_______________________________________| | | |
--! | /\ |_________| |
--! | _______________________________________ |
--! | | | |
--! | | WF_rx_deglitcher | |
--! | |_______________________________________| |
--! | |
--! |___________________________________________________________|
--! /\
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--!
--!
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 15/02/2011
--
--
--! @version v0.01
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! ->
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_fd_receiver
--=================================================================================================
entity WF_fd_receiver is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHZ clock
-- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- nanoFIP FIELDRIVE
fd_rxd_a_i : in std_logic; --! receiver data
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_engine_control unit
rx_rst_p_i : in std_logic; --! receiver timeout
--! in cases when reception is lasting more than
--! received (ID_DAT > 8 bytes, RP_DAT > 130 bytes)
-- OUTPUTS
-- Signals to the WF_engine_control and WF_consumption
rx_byte_o : out std_logic_vector (7 downto 0); --! retrieved data byte
rx_byte_ready_p_o : out std_logic;--! pulse indicating a new retrieved data byte
rx_fss_crc_fes_manch_ok_p_o : out std_logic;--! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
-- Signals to the WF_engine_control
rx_fss_received_p_o : out std_logic;--! pulse after the reception of a correct FSS(ID/RP)
-- Signal to the WF_engine_control and the WF_production units
rx_crc_or_manch_wrong_p_o : out std_logic --! indication of a wrong CRC or manch. encoding on
--!a ID_DAT or RP_DAT;pulse after the FES detection
);
end entity WF_fd_receiver;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture struc of WF_fd_receiver is
signal s_rx_osc_rst, s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p, s_rxd_filtered : std_logic;
signal s_rxd_filtered_edge_p, s_rxd_filtered_f_edge_p, s_rxd_filtered_r_edge_p : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Deglitcher --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_deglitcher unit.
FIELDRIVE_Receiver_Deglitcher: WF_rx_deglitcher
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
fd_rxd_a_i => fd_rxd_a_i,
-----------------------------------------------------------------
fd_rxd_filtered_o => s_rxd_filtered,
fd_rxd_filtered_edge_p_o => s_rxd_filtered_edge_p,
fd_rxd_filtered_f_edge_p_o => s_rxd_filtered_f_edge_p);
-----------------------------------------------------------------
s_rxd_filtered_r_edge_p <= s_rxd_filtered_edge_p and (not s_rxd_filtered_f_edge_p);
---------------------------------------------------------------------------------------------------
-- Oscillator --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_osc unit.
FIELDRIVE_Receiver_Oscillator: WF_rx_osc
port map (
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
fd_rxd_edge_p_i => s_rxd_filtered_edge_p,
rx_osc_rst_i => s_rx_osc_rst,
------------------------------------------------------
rx_manch_clk_p_o => s_sample_manch_bit_p,
rx_bit_clk_p_o => s_sample_bit_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window);
-----------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Deserializer --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_deserializer unit.
FIELDRIVE_Receiver_Deserializer: WF_rx_deserializer
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
rx_rst_p_i => rx_rst_p_i,
sample_bit_p_i => s_sample_bit_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
fd_rxd_f_edge_p_i => s_rxd_filtered_f_edge_p,
fd_rxd_r_edge_p_i => s_rxd_filtered_r_edge_p,
fd_rxd_i => s_rxd_filtered,
------------------------------------------------------
byte_ready_p_o => rx_byte_ready_p_o,
byte_o => rx_byte_o,
fss_crc_fes_manch_ok_p_o => rx_fss_crc_fes_manch_ok_p_o,
rx_osc_rst_o => s_rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
crc_or_manch_wrong_p_o => rx_crc_or_manch_wrong_p_o);
------------------------------------------------------
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
wf_manch_encoder.vhd → wf_fd_transmitter.vhd
View file @ 6ead92d5
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_manch_encoder.vhd |
--! @file WF_fd_transmitter.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -17,25 +17,60 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_manch_encoder --
-- WF_fd_transmitter --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Encoding of a word to its Manchester 2 (manch.) equivalent.
--! The manch. encoding ensures that there is one transition for each bit.
--! o bit : "0" "1"
--! o manch. encoded : "0 1" "1 0"
--! o scheme : _|- -|_
--! @brief The unit groups the main actions that regard data transmission.
--! It instantiates the units:
--!
--! o WF_tx_serializer : that receives bytes from the WF_Production, encodes them
--! (Manchester 2), adds the FSS, FCS & FES fields and puts one
--! by one bits to the FIELDRIVE output FD_TXD, following the
--! synchronization signals from the WF_tx_osc unit.
--! Also generates the nanoFIP output FD_TXENA.
--!
--! o WF_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK
--! and the array of pulses tx_clk_p_buff (used for the
--! synchronization of the WF_tx_serializer).
--! ___________________________________________________________
--! | |
--! | WF_Production |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________
--! | WF_fd_transmitter |
--! | |
--! | ________________________________________________ |
--! | | | |
--! | | WF_tx_osc | |
--! | |________________________________________________| |
--! | \/ |
--! | _________________________________________________ |
--! | | | |
--! | | WF_tx_serializer | |
--! | | | |
--! | |_________________________________________________| |
--! |___________________________________________________________|
--! \/
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--!
--!
--!
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 10/12/2010
--! @date 11/01/2011
--
--
--! @version v0.01
......@@ -43,17 +78,18 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_production \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b> \n
--! Evangelia Gousiou \n
--! \n<b>Modified by:</b>\n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 12/2010 v0.01 EG cleaned-up, commented (all 3 lines!) \n
--!
--! ->
--
---------------------------------------------------------------------------------------------------
--
......@@ -63,34 +99,58 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_manch_encoder
--! Entity declaration for WF_fd_transmitter
--=================================================================================================
entity WF_manch_encoder is
entity WF_fd_transmitter is
generic (word_length : natural := 8); --! default word length: 8
port (
-- INPUT
word_i : in std_logic_vector(word_length-1 downto 0); --! input word
-- INPUTS
-- nanoFIP User Interface, General signal
uclk_i : in std_logic; --! 40 MHz clock
-- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_production unit
tx_byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
-- Signals from the WF_engine_control
tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
tx_last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
tx_start_p_i : in std_logic; --! indication for the start of the production
tx_rst_p_i : in std_logic; --! transmitter timeout
-- OUTPUT
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0) --! output encoded word
-- OUTPUTS
-- Signal to the WF_engine_control
tx_byte_request_p_o : out std_logic;--! request for a new byte to be transmitted; pulse
--! at the end of the transmission of a previous byte
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic;--! transmitter data
tx_enable_o : out std_logic;--! transmitter enable
tx_clk_o : out std_logic --! line driver half bit clock
);
end entity WF_manch_encoder;
end entity WF_fd_transmitter;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_manch_encoder is
architecture struc of WF_fd_transmitter is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
--=================================================================================================
......@@ -98,25 +158,51 @@ architecture rtl of WF_manch_encoder is
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Oscillator --
---------------------------------------------------------------------------------------------------
--! @brief Combinatorial process Manchester_Encoder: The process takes a word (ex. 8 bits) and
--! creates its manchester encoded equivalent (ex. 16 bits).
--! Each bit '1' is replaced by '10' and each bit '0' by '01'.
Manchester_Encoder: process (word_i)
begin
--!@brief Instantiation of the WF_tx_osc unit
for I in word_i'range loop
tx_oscillator: WF_tx_osc
port map (
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
tx_rst_p_i => tx_rst_p_i,
-----------------------------------------------
tx_clk_o => tx_clk_o,
tx_clk_p_buff_o => s_tx_clk_p_buff);
-----------------------------------------------
---------------------------------------------------------------------------------------------------
-- Serializer --
---------------------------------------------------------------------------------------------------
word_manch_o(I*2) <= not word_i(I);
--!@brief Instantiation of the WF_tx_serializer unit
word_manch_o(I*2+1) <= word_i(I);
tx_serializer: WF_tx_serializer
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
tx_rst_p_i => tx_rst_p_i,
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => tx_byte_request_accept_p_i,
byte_i => tx_byte_i,
last_byte_p_i => tx_last_byte_p_i,
tx_clk_p_buff_i => s_tx_clk_p_buff,
-----------------------------------------------
tx_data_o => tx_data_o,
byte_request_p_o => tx_byte_request_p_o,
tx_enable_o => tx_enable_o );
-----------------------------------------------
end loop;
end process;
end architecture rtl;
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
......
wf_incr_counter.vhd
View file @ 6ead92d5
......@@ -68,9 +68,6 @@ entity WF_incr_counter is
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
incr_counter_i : in std_logic; --! increment enable
reinit_counter_i : in std_logic; --! reinitializes counter to 0
......@@ -90,8 +87,8 @@ end entity WF_incr_counter;
--=================================================================================================
architecture rtl of WF_incr_counter is
constant c_COUNTER_FULL : unsigned(g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -105,11 +102,7 @@ begin
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_counter <= (others => '0');
elsif reinit_counter_i = '1' then
if reinit_counter_i = '1' then
s_counter <= (others => '0');
elsif incr_counter_i = '1' then
......
wf_inputs_synchronizer.vhd
View file @ 6ead92d5
......@@ -69,11 +69,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -86,29 +81,10 @@ entity WF_inputs_synchronizer is
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
nostat_a_i : in std_logic;
rstin_a_i : in std_logic;
slone_a_i : in std_logic;
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP WorldFIP Settings
c_id_a_i : in std_logic_vector(3 downto 0);
m_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0);
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_rst_i : in std_logic; --! WISHBONE reset, includes also the PowerOnReset
--! Note: wb_rst is not registered, to comply
--! with WISHBONE rule 3.15
wb_cyc_a_i : in std_logic;
wb_stb_a_i : in std_logic;
wb_we_a_i : in std_logic;
-- nanoFIP User Interface, NON WISHBONE
dat_a_i : in std_logic_vector(15 downto 0);
var1_access_a_i : in std_logic;
......@@ -124,22 +100,7 @@ entity WF_inputs_synchronizer is
-- OUTPUTS
-- nanoFIP User Interface, General signals
nostat_o : out std_logic;
rstin_o : out std_logic;
slone_o : out std_logic;
-- nanoFIP WorldFIP Settings
c_id_o : out std_logic_vector(3 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0);
rate_o : out std_logic_vector(1 downto 0);
subs_o : out std_logic_vector(7 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
wb_cyc_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_p_o : out std_logic; --! 1 wb_clk-wide pulse on the rising edge of a STB_I
wb_we_o : out std_logic;
-- nanoFIP User Interface, NON WISHBONE
slone_dati_o : out std_logic_vector(15 downto 0);
......@@ -178,74 +139,13 @@ architecture rtl of WF_inputs_synchronizer is
signal s_slone_dati_d1, s_slone_dati_d3, s_slone_dati_d2 :std_logic_vector(15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
RSTIN_synchronization_with_uclk: process (uclk_i)
begin
if rising_edge (uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (1 downto 0) & rstin_a_i;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rstin_o <= s_u_rst_d3(2);
---------------------------------------------------------------------------------------------------
User_interf_general_signals_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_slone_d3 <= (others => '0');
s_nostat_d3 <= (others => '0');
else
s_slone_d3 <= s_slone_d3 (1 downto 0) & slone_a_i;
s_nostat_d3 <= s_nostat_d3(1 downto 0) & nostat_a_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
slone_o <= s_slone_d3(2);
nostat_o <= s_nostat_d3(2);
---------------------------------------------------------------------------------------------------
FIELDRIVE_inputs_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fd_rxd_d3 <= (others => '0');
s_fd_wdgn_d3 <= (others => '0');
s_fd_txer_d3 <= (others => '0');
else
s_fd_rxd_d3 <= s_fd_rxd_d3 (1 downto 0) & fd_rxd_a_i;
s_fd_wdgn_d3 <= s_fd_wdgn_d3(1 downto 0) & fd_wdgn_a_i;
s_fd_txer_d3 <= s_fd_txer_d3(1 downto 0) & fd_txer_a_i;
s_fd_rxcdn_d3 <= s_fd_rxcdn_d3(1 downto 0) & fd_rxcdn_a_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
fd_wdgn_o <= s_fd_wdgn_d3(2);
fd_txer_o <= s_fd_txer_d3(2);
fd_rxd_o <= s_fd_rxd_d3 (2) and (not s_fd_rxcdn_d3(2)); -- to clean rxd from txd
s_fd_rxd_r_edge <= (not s_fd_rxd_d3(2)) and (s_fd_rxd_d3(1)) and (not s_fd_rxcdn_d3(2));
s_fd_rxd_f_edge <= (s_fd_rxd_d3(2)) and (not s_fd_rxd_d3(1)) and (not s_fd_rxcdn_d3(2));
fd_rxd_r_edge_p_o <= s_fd_rxd_r_edge;
fd_rxd_f_edge_p_o <= s_fd_rxd_f_edge;
fd_rxd_edge_p_o <= s_fd_rxd_r_edge or s_fd_rxd_f_edge;
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronization: process (uclk_i)
begin
......@@ -283,117 +183,12 @@ begin
var3_access_o <= s_var3_access_d3;
---------------------------------------------------------------------------------------------------
WISHBONE_inputs_synchronization: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_stb_d1 <= '0';
s_wb_stb_d2 <= '0';
s_wb_stb_d3 <= '0';
s_wb_we_d1 <= '0';
s_wb_we_d2 <= '0';
s_wb_we_d3 <= '0';
s_wb_cyc_d1 <= '0';
s_wb_cyc_d2 <= '0';
s_wb_cyc_d3 <= '0';
else
s_wb_stb_d1 <= wb_stb_a_i;
s_wb_stb_d2 <= s_wb_stb_d1;
s_wb_stb_d3 <= s_wb_stb_d2;
s_wb_stb_d4 <= s_wb_stb_d3;
s_wb_we_d1 <= wb_we_a_i;
s_wb_we_d2 <= s_wb_we_d1;
s_wb_we_d3 <= s_wb_we_d2;
s_wb_cyc_d1 <= wb_cyc_a_i;
s_wb_cyc_d2 <= s_wb_cyc_d1;
s_wb_cyc_d3 <= s_wb_cyc_d2;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- --
wb_cyc_o <= s_wb_cyc_d3;
wb_we_o <= s_wb_we_d3;
wb_stb_o <= s_wb_stb_d3;
wb_stb_r_edge_p_o <= (not s_wb_stb_d4) and s_wb_stb_d3;
--------------------------------------------------------------------------------------------------
Slone_dat_i_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_slone_dati_d1 <= (others => '0');
s_slone_dati_d2 <= (others => '0');
s_slone_dati_d3 <= (others => '0');
else
s_slone_dati_d3 <= s_slone_dati_d2;
s_slone_dati_d2 <= s_slone_dati_d1;
s_slone_dati_d1 <= dat_a_i (15 downto 0);
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- --
slone_dati_o <= s_slone_dati_d3;
--------------------------------------------------------------------------------------------------
WorldFIP_Settings_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_rate_d1 <= (others => '0');
s_rate_d2 <= (others => '0');
s_rate_d3 <= (others => '0');
s_subs_d1 <= (others => '0');
s_subs_d2 <= (others => '0');
s_subs_d3 <= (others => '0');
s_mid_d1 <= (others => '0');
s_mid_d2 <= (others => '0');
s_mid_d3 <= (others => '0');
s_cid_d1 <= (others => '0');
s_cid_d2 <= (others => '0');
s_cid_d3 <= (others => '0');
s_p3_lgth_d1 <= (others => '0');
s_p3_lgth_d2 <= (others => '0');
s_p3_lgth_d3 <= (others => '0');
else
s_rate_d1 <= rate_a_i;
s_rate_d2 <= s_rate_d1;
s_rate_d3 <= s_rate_d2;
s_subs_d1 <= subs_a_i;
s_subs_d2 <= s_subs_d1;
s_subs_d3 <= s_subs_d2;
s_mid_d1 <= m_id_a_i;
s_mid_d2 <= s_mid_d1;
s_mid_d3 <= s_mid_d2;
s_cid_d1 <= c_id_a_i;
s_cid_d2 <= s_cid_d1;
s_cid_d3 <= s_cid_d2;
s_p3_lgth_d1 <= p3_lgth_a_i;
s_p3_lgth_d2 <= s_p3_lgth_d1;
s_p3_lgth_d3 <= s_p3_lgth_d2;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- --
rate_o <= s_rate_d3;
subs_o <= s_subs_d3;
m_id_o <= s_mid_d3;
c_id_o <= s_cid_d3;
p3_lgth_o <= s_p3_lgth_d3;
......
wf_model_constr_decoder.vhd
View file @ 6ead92d5
......@@ -75,11 +75,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -182,11 +177,10 @@ begin
--!@brief Instantiation of a counter WF_incr_counter
Free_Counter: WF_incr_counter
generic map(g_counter_lgth => 2)
port map(
generic map (g_counter_lgth => 2)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => '0',
reinit_counter_i => nfip_rst_i,
incr_counter_i => '1',
-----------------------------------------
counter_o => s_counter,
......
wf_package.vhd
View file @ 6ead92d5
......@@ -22,7 +22,7 @@ use ieee.numeric_std.all;
---------------------------------------------------------------------------------------------------
--
--
--! @brief Definitions of constants, types, entities
--! @brief Definitions of constants, types, entities, functions
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
......@@ -32,7 +32,7 @@ use ieee.numeric_std.all;
--! @date 11/01/2011
--
--
--! @version v0.03
--! @version v0.04
--
--
--! @details \n
......@@ -51,6 +51,7 @@ use ieee.numeric_std.all;
--! std_logic_vector(9 downto 0) to simplify calculations; cleaning-up
--! -> 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
--! added DualClkRam
--! -> 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics
--
---------------------------------------------------------------------------------------------------
--
......@@ -73,17 +74,15 @@ package WF_package is
constant c_QUARTZ_PERIOD : real := 25.0;
constant c_DEGLITCH_THRESHOLD : natural := 4;
---------------------------------------------------------------------------------------------------
-- Constants regarding the CRC calculator --
-- Constants regarding the CRC calculation --
---------------------------------------------------------------------------------------------------
constant c_GENERATOR_POLY_length : natural := 16;
-- Shift register xor mask
constant c_GENERATOR_POLY : std_logic_vector (c_GENERATOR_POLY_length- 1 downto 0) :=
constant c_CRC_GENER_POLY_LGTH : natural := 16;
constant c_CRC_GENER_POLY : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0) :=
"0001110111001111";
-- CRC check mask
constant c_VERIFICATION_MASK : std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
constant c_CRC_VERIFIC_MASK : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0) :=
"0001110001101011";
......@@ -92,14 +91,14 @@ package WF_package is
-- Constants regarding the the ID_DAT and RP_DAT frame structure --
---------------------------------------------------------------------------------------------------
constant VP : std_logic_vector (1 downto 0) := "11";
constant VN : std_logic_vector (1 downto 0) := "00";
constant ONE : std_logic_vector (1 downto 0) := "10";
constant ZERO : std_logic_vector (1 downto 0) := "01";
constant c_VP : std_logic_vector (1 downto 0) := "11";
constant c_VN : std_logic_vector (1 downto 0) := "00";
constant c_ONE : std_logic_vector (1 downto 0) := "10";
constant c_ZERO : std_logic_vector (1 downto 0) := "01";
constant c_PRE : std_logic_vector (15 downto 0) := ONE & ZERO & ONE & ZERO & ONE & ZERO & ONE & ZERO;
constant c_FSD : std_logic_vector (15 downto 0) := ONE & VP & VN & ONE & ZERO & VN & VP & ZERO;
constant c_FES : std_logic_vector (15 downto 0) := ONE & VP & VN & VP & VN & ONE & ZERO & ONE;
constant c_PRE : std_logic_vector (15 downto 0) := c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO;
constant c_FSD : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_ONE & c_ZERO & c_VN & c_VP & c_ZERO;
constant c_FES : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_VP & c_VN & c_ONE & c_ZERO & c_ONE;
constant c_FSS : std_logic_vector (31 downto 0) := c_PRE & c_FSD;
......@@ -113,6 +112,7 @@ package WF_package is
constant c_PROD_CONS_PDU_TYPE_BYTE : std_logic_vector (7 downto 0) := "01000000";
---------------------------------------------------------------------------------------------------
-- Constants regarding the nanoFIP status bits --
---------------------------------------------------------------------------------------------------
......@@ -125,6 +125,24 @@ package WF_package is
constant c_T_WDER_INDEX : integer := 7;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Model & Constructor decoding --
---------------------------------------------------------------------------------------------------
constant c_RELOAD_MID_CID : natural := 8;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Transmitter --
---------------------------------------------------------------------------------------------------
constant c_TX_CLK_BUFF_LGTH : natural := 4; -- length of the clk buffer used for
-- the transmission synchronization
---------------------------------------------------------------------------------------------------
-- Constants regarding the MPS status bits --
---------------------------------------------------------------------------------------------------
......@@ -133,6 +151,7 @@ package WF_package is
constant c_SIGNIFICANCE_INDEX : integer := 2;
---------------------------------------------------------------------------------------------------
-- Constants regarding the position of bytes in the frame structure --
---------------------------------------------------------------------------------------------------
......@@ -147,9 +166,11 @@ package WF_package is
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the P3_LGTH[2:0] settings --
---------------------------------------------------------------------------------------------------
-- Construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
......@@ -164,9 +185,11 @@ package WF_package is
);
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the bit rate --
---------------------------------------------------------------------------------------------------
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LENGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
......@@ -176,14 +199,14 @@ package WF_package is
-- transmission/ reception periods.
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LENGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LENGTH);
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned :=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LENGTH);
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
type t_uclk_ticks is array (Natural range <>) of unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks (3 downto 0):=
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
......@@ -195,9 +218,11 @@ package WF_package is
-- transmission period
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the turnaround and silence times --
---------------------------------------------------------------------------------------------------
-- Construction of a table with the turnaround and silence times for each bit rate.
-- The table contains the number of uclk ticks corresponding to the turnaround/ silence times.
......@@ -214,8 +239,7 @@ package WF_package is
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_TIMEOUTS_TABLE : t_timeouts_table(0 to 3) :=
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD),
silence => integer (5160000.0 / c_QUARTZ_PERIOD)),
......@@ -227,25 +251,25 @@ package WF_package is
silence => integer (100000.0 / c_QUARTZ_PERIOD)),
c_RESERVE_INDEX => (turnaround => integer (480000.0 /C_QUARTZ_PERIOD),
silence => integer (5160000.0 /C_QUARTZ_PERIOD))
);
silence => integer (5160000.0 /C_QUARTZ_PERIOD)));
---------------------------------------------------------------------------------------------------
-- Constants & Types regarding the consumed & produced variables --
---------------------------------------------------------------------------------------------------
-- Construction of a table that groups main information for all the variables
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector (7 downto 0);
type t_var_response is (produce, consume, reset);
type t_var_record is record
var : t_var;
hexvalue : std_logic_vector (7 downto 0);
response : t_var_response;
prod_or_cons : std_logic_vector (1 downto 0);
broadcast : std_logic;
base_addr : unsigned (8 downto 0);
array_length : unsigned (7 downto 0);
byte_array : t_byte_array (0 to 15);
......@@ -265,31 +289,34 @@ package WF_package is
(c_VAR_PRESENCE_INDEX => (var => var_presence,
hexvalue => x"14",
response => produce,
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_length => "00000111", -- 8 bytes in total including the Control byte
-- (counting starts from 0)
-- (counting starts from 0;-))
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
3 => x"80", 4 => x"03", 5 => x"00", 6 => x"f0",
3 => x"80", 4 => x"03" , 5 => x"00", 6 => x"f0",
7 => x"00", others => x"ff")),
c_VAR_IDENTIF_INDEX => (var => var_identif,
hexvalue => x"10",
response => produce,
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_length => "00001010", -- 11 bytes in total including the Control byte
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00", 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00", 9 => x"00", 10 => x"00",
3 => x"01", 4 => x"00" , 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00" , 9 => x"00", 10 => x"00",
others => x"ff")),
c_VAR_3_INDEX => (var => var_3,
hexvalue => x"06",
response => produce,
prod_or_cons => "10",
broadcast => '0',
base_addr => "100000000",
array_length => "00000001", -- only the Control and PDU type bytes are
array_length => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
......@@ -297,9 +324,10 @@ package WF_package is
c_VAR_1_INDEX => (var => var_1,
hexvalue => x"05",
response => consume,
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
array_length => "00000001", -- only the Control and PDU type bytes are
array_length => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
......@@ -307,107 +335,42 @@ package WF_package is
c_VAR_2_INDEX => (var => var_2,
hexvalue => x"91",
response => consume,
prod_or_cons => "01",
broadcast => '1',
base_addr => "010000000",
array_length => "00000001", -- only the Control and PDU type bytes are
array_length => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
c_VAR_RST_INDEX => (var => var_rst,
hexvalue => x"e0",
response => reset,
prod_or_cons => "01",
broadcast => '1',
base_addr => "---------",
array_length => "00000001", -- only the Control and PDU type bytes are
array_length => "00000001", -- only the Control and PDU_TYPE bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")));
---------------------------------------------------------------------------------------------------
-- Constant regarding the transmitters (WF_tx_serializer) clock --
---------------------------------------------------------------------------------------------------
constant c_TX_CLK_BUFF_LGTH : natural := 4;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Model & Constructor decoding --
---------------------------------------------------------------------------------------------------
constant c_RELOAD_MID_CID : natural := 8;
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
component WF_inputs_synchronizer is
port (
uclk_i : in std_logic;
wb_clk_i : in std_logic;
nfip_rst_i : in std_logic;
rstin_a_i : in std_logic;
wb_rst_i : in std_logic;
slone_a_i : in std_logic;
nostat_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_rxcdn_a_i : in std_logic;
wb_cyc_a_i : in std_logic;
wb_we_a_i : in std_logic;
wb_stb_a_i : in std_logic;
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
dat_a_i : in std_logic_vector(15 downto 0);
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
m_id_a_i : in std_logic_vector(3 downto 0);
c_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0);
-----------------------------------------------------------------
rstin_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
fd_wdgn_o : out std_logic;
fd_txer_o : out std_logic;
fd_rxd_o : out std_logic;
fd_rxd_edge_p_o : out std_logic;
fd_rxd_r_edge_p_o : out std_logic;
fd_rxd_f_edge_p_o : out std_logic;
wb_cyc_o : out std_logic;
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_p_o : out std_logic;
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
slone_dati_o : out std_logic_vector(15 downto 0);
rate_o : out std_logic_vector(1 downto 0);
subs_o : out std_logic_vector(7 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0)
-----------------------------------------------------------------
);
end component WF_inputs_synchronizer;
---------------------------------------------------------------------------------------------------
component WF_rx_deserializer
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
rst_rx_unit_p_i : in std_logic;
rx_rst_p_i : in std_logic;
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
rxd_r_edge_p_i : in std_logic;
rxd_f_edge_p_i : in std_logic;
rxd_filtered_i : in std_logic;
rxd_filtered_f_edge_p_i : in std_logic;
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
fd_rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
-----------------------------------------------------------------
......@@ -416,53 +379,32 @@ end component WF_inputs_synchronizer;
crc_or_manch_wrong_p_o : out std_logic;
fss_crc_fes_manch_ok_p_o : out std_logic;
fss_received_p_o : out std_logic;
rst_rx_osc_o : out std_logic
rx_osc_rst_o : out std_logic);
-----------------------------------------------------------------
);
end component WF_rx_deserializer;
---------------------------------------------------------------------------------------------------
component WF_tx_serializer
generic (c_TX_CLK_BUFF_LGTH : natural);
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
start_prod_p_i : in std_logic;
tx_start_p_i : in std_logic;
tx_rst_p_i : in std_logic;
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
-------------------------------------------------------------------------
-----------------------------------------------------------------
byte_request_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic
-------------------------------------------------------------------------
);
tx_enable_o : out std_logic);
-----------------------------------------------------------------
end component WF_tx_serializer;
---------------------------------------------------------------------------------------------------
component WF_rx_tx_osc
generic (C_PERIODS_COUNTER_LENGTH : natural;
c_TX_CLK_BUFF_LGTH : natural);
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
rxd_edge_p_i : in std_logic;
rst_rx_osc_i : in std_logic;
-------------------------------------------------------------------------
rx_manch_clk_p_o : out std_logic;
rx_bit_clk_p_o : out std_logic;
rx_signif_edge_window_o : out std_logic;
rx_adjac_bits_window_o : out std_logic;
tx_clk_o : out std_logic;
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0)
-------------------------------------------------------------------------
);
end component WF_rx_tx_osc;
---------------------------------------------------------------------------------------------------
component WF_cons_bytes_processor
......@@ -476,18 +418,18 @@ end component WF_inputs_synchronizer;
byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
-----------------------------------------------------------------
data_o : out std_logic_vector (15 downto 0);
cons_ctrl_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_lgth_byte_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_cons_bytes_processor;
---------------------------------------------------------------------------------------------------
component WF_cons_bytes_to_dato is
port (
......@@ -495,10 +437,9 @@ end component WF_inputs_synchronizer;
nfip_rst_i : in std_logic;
transfer_byte_p_i : in std_logic_vector (1 downto 0);
byte_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
slone_data_o : out std_logic_vector(15 downto 0)
---------------------------------------------------------------
);
-----------------------------------------------------------------
slone_data_o : out std_logic_vector (15 downto 0));
-----------------------------------------------------------------
end component WF_cons_bytes_to_dato;
......@@ -510,36 +451,63 @@ end component WF_inputs_synchronizer;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nfip_rst_i : in std_logic;
fd_rxd_i : in std_logic;
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector(8 downto 0);
wb_adr_i : in std_logic_vector (8 downto 0);
var_i : in t_var;
byte_index_i : in std_logic_vector (7 downto 0);
rst_rx_unit_p_i : in std_logic;
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
---------------------------------------------------------------
-----------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
data_o : out std_logic_vector (15 downto 0);
byte_o : out std_logic_vector (7 downto 0);
byte_ready_p_o : out std_logic;
fss_received_p_o : out std_logic;
nfip_status_r_tler_o : out std_logic;
crc_or_manch_wrong_p_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
fss_crc_fes_manch_ok_p_o : out std_logic;
rst_rx_osc_o : out std_logic
---------------------------------------------------------------
);
rst_nfip_and_fd_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_consumption;
---------------------------------------------------------------------------------------------------
component WF_fd_receiver is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
fd_rxd_a_i : in std_logic;
nfip_rst_i : in std_logic;
rx_rst_p_i : in std_logic;
-----------------------------------------------------------------
rx_byte_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_manch_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
rx_crc_or_manch_wrong_p_o : out std_logic );
-----------------------------------------------------------------
end component WF_fd_receiver;
---------------------------------------------------------------------------------------------------
component WF_rx_osc is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
fd_rxd_edge_p_i : in std_logic;
rx_osc_rst_i : in std_logic;
-----------------------------------------------------------------
rx_manch_clk_p_o : out std_logic;
rx_bit_clk_p_o : out std_logic;
rx_signif_edge_window_o : out std_logic;
rx_adjac_bits_window_o : out std_logic );
-----------------------------------------------------------------
end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_production is
port (
......@@ -548,40 +516,71 @@ end component WF_inputs_synchronizer;
nostat_i : in std_logic;
nfip_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(8 downto 0);
wb_adr_i : in std_logic_vector (8 downto 0);
wb_data_i : in std_logic_vector (7 downto 0);
wb_ack_prod_p_i : in std_logic;
slone_data_i : in std_logic_vector(15 downto 0);
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
var_i : in t_var;
data_length_i : in std_logic_vector (7 downto 0);
slone_data_i : in std_logic_vector (15 downto 0);
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
start_prod_p_i : in std_logic;
data_length_i : in std_logic_vector (7 downto 0);
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
var_i : in t_var;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
model_id_dec_i : in std_logic_vector (7 downto 0);
nfip_status_r_fcser_p_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
constr_id_dec_i : in std_logic_vector (7 downto 0);
--------------------------------------------------------------------------
byte_request_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
model_id_dec_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
byte_o : out std_logic_vector (7 downto 0);
u_cacer_o : out std_logic;
r_fcser_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
var3_rdy_o : out std_logic
--------------------------------------------------------------------------
);
end component WF_production;
var3_rdy_o : out std_logic);
-----------------------------------------------------------------
end component WF_production;
---------------------------------------------------------------------------------------------------
component WF_fd_transmitter is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
tx_byte_i : in std_logic_vector (7 downto 0);
tx_byte_request_accept_p_i : in std_logic;
tx_last_byte_p_i : in std_logic;
tx_start_p_i : in std_logic;
tx_rst_p_i : in std_logic;
-----------------------------------------------------------------
tx_byte_request_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
tx_clk_o : out std_logic);
-----------------------------------------------------------------
end component WF_fd_transmitter;
---------------------------------------------------------------------------------------------------
component WF_tx_osc is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
tx_rst_p_i : in std_logic;
-----------------------------------------------------------------
tx_clk_o : out std_logic;
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0));
-----------------------------------------------------------------
end component WF_tx_osc;
---------------------------------------------------------------------------------------------------
......@@ -605,14 +604,14 @@ end component WF_production;
byte_index_i : in std_logic_vector (7 downto 0);
byte_being_sent_p_i : in std_logic;
var3_rdy_i : in std_logic;
---------------------------------------------------------------
-----------------------------------------------------------------
rst_status_bytes_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_prod_bytes_retriever;
---------------------------------------------------------------------------------------------------
component WF_prod_bytes_from_dati is
port (
......@@ -621,16 +620,15 @@ end component WF_production;
slone_data_i : in std_logic_vector (15 downto 0);
var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
slone_byte_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
-----------------------------------------------------------------
slone_byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_prod_bytes_from_dati;
---------------------------------------------------------------------------------------------------
component WF_engine_control
generic ( c_QUARTZ_PERIOD : real);
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
......@@ -645,61 +643,63 @@ end component WF_production;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_byte_ready_p_i : in std_logic;
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
---------------------------------------------------------------
-----------------------------------------------------------------
tx_byte_request_accept_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;
tx_start_prod_p_o : out std_logic;
tx_start_p_o : out std_logic;
prod_cons_byte_index_o : out std_logic_vector (7 downto 0);
prod_data_length_o : out std_logic_vector (7 downto 0);
rst_rx_unit_p_o : out std_logic;
var_o : out t_var
---------------------------------------------------------------
);
rx_rst_p_o : out std_logic;
rst_tx_p_o : out std_logic;
var_o : out t_var);
-----------------------------------------------------------------
end component WF_engine_control;
---------------------------------------------------------------------------------------------------
component WF_reset_unit
port (
uclk_i : in std_logic;
rstin_i : in std_logic;
wb_clk_i : in std_logic;
rstin_a_i : in std_logic;
rstpon_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
var_i : in t_var;
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
---------------------------------------------------------------
-----------------------------------------------------------------
wb_rst_o : out std_logic;
nFIP_rst_o : out std_logic;
rston_o : out std_logic;
fd_rstn_o : out std_logic
---------------------------------------------------------------
);
fd_rstn_o : out std_logic);
-----------------------------------------------------------------
end component WF_reset_unit;
---------------------------------------------------------------------------------------------------
component WF_DualClkRAM_clka_rd_clkb_wr
generic (C_RAM_DATA_LGTH : integer;
c_RAM_ADDR_LGTH : integer);
generic (g_ram_data_lgth : integer;
g_ram_addr_lgth : integer);
port (
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
addr_porta_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_portb_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
addr_portb_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
data_portb_i : in std_logic_vector (g_ram_data_lgth - 1 downto 0);
write_en_portb_i : in std_logic;
--------------------------------------------------------------------------
data_porta_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
--------------------------------------------------------------------------
);
-----------------------------------------------------------------
data_porta_o : out std_logic_vector (g_ram_data_lgth -1 downto 0));
-----------------------------------------------------------------
end component WF_DualClkRAM_clka_rd_clkb_wr;
---------------------------------------------------------------------------------------------------
component DualClkRam is
port(
port (
CLKA : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
DINA : in std_logic_vector (7 downto 0);
......@@ -709,43 +709,42 @@ end component WF_production;
DINB : in std_logic_vector (7 downto 0);
RWB : in std_logic;
RESETn : in std_logic;
--------------------------------------------------------------------------
-----------------------------------------------------------------
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0)
--------------------------------------------------------------------------
);
DOUTB : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component DualClkRam;
---------------------------------------------------------------------------------------------------
component WF_crc
generic (c_GENERATOR_POLY_length : natural := 16);
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
start_crc_p_i : in std_logic;
data_bit_i : in std_logic;
data_bit_ready_p_i : in std_logic;
--------------------------------------------------------------------------
-----------------------------------------------------------------
crc_ok_p : out std_logic;
crc_o : out std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0)
--------------------------------------------------------------------------
);
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0));
-----------------------------------------------------------------
end component WF_crc;
---------------------------------------------------------------------------------------------------
component WF_manch_encoder is
generic (word_length : natural);
generic (g_word_length : natural);
port (
word_i : in std_logic_vector(word_length-1 downto 0);
---------------------------------------------------------------
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0)
---------------------------------------------------------------
);
word_i : in std_logic_vector (g_word_length-1 downto 0);
-----------------------------------------------------------------
word_manch_o : out std_logic_vector ((2*g_word_length)-1 downto 0));
-----------------------------------------------------------------
end component WF_manch_encoder;
---------------------------------------------------------------------------------------------------
component WF_rx_manch_code_check is
port (
......@@ -754,68 +753,63 @@ end component WF_production;
serial_input_signal_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
---------------------------------------------------------------
manch_code_viol_p_o : out std_logic
---------------------------------------------------------------
);
-----------------------------------------------------------------
manch_code_viol_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_rx_manch_code_check;
---------------------------------------------------------------------------------------------------
component WF_rx_deglitcher
generic (c_DEGLITCH_LGTH : integer := 10);
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
---------------------------------------------------------------
sample_manch_bit_p_o : out std_logic;
rxd_filtered_o : out std_logic;
rxd_filtered_f_edge_p_o : out std_logic;
sample_bit_p_o : out std_logic
---------------------------------------------------------------
);
fd_rxd_a_i : in std_logic;
-----------------------------------------------------------------
fd_rxd_filtered_o : out std_logic;
fd_rxd_filtered_edge_p_o : out std_logic;
fd_rxd_filtered_f_edge_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_rx_deglitcher;
---------------------------------------------------------------------------------------------------
component WF_status_bytes_gen
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_rst_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_txer_i : in std_logic;
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
rst_status_bytes_p_i : in std_logic;
---------------------------------------------------------------
-----------------------------------------------------------------
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
nFIP_status_byte_o : out std_logic_vector (7 downto 0);
mps_status_byte_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
mps_status_byte_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_status_bytes_gen;
---------------------------------------------------------------------------------------------------
component WF_bits_to_txd
generic (c_TX_CLK_BUFF_LGTH : natural := 4);
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
txd_bit_index_i : in unsigned(4 downto 0);
txd_bit_index_i : in unsigned (4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
sending_fss_i : in std_logic;
......@@ -824,14 +818,14 @@ end component WF_production;
sending_fes_i : in std_logic;
stop_transmission_i : in std_logic;
tx_clk_p_i : in std_logic;
---------------------------------------------------------------
-----------------------------------------------------------------
txd_o : out std_logic;
tx_enable_o : out std_logic
---------------------------------------------------------------
);
tx_enable_o : out std_logic);
-----------------------------------------------------------------
end component WF_bits_to_txd;
---------------------------------------------------------------------------------------------------
component nanofip
port (
......@@ -840,8 +834,8 @@ end component WF_production;
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
fd_wdgn_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
uclk_i : in std_logic;
......@@ -849,17 +843,17 @@ end component WF_production;
nostat_i : in std_logic;
rstin_i : in std_logic;
rstpon_i : in std_logic;
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
wb_clk_i : in std_logic;
dat_i : in std_logic_vector (15 downto 0);
adr_i : in std_logic_vector ( 9 downto 0);
adr_i : in std_logic_vector (9 downto 0);
rst_i : in std_logic;
stb_i : in std_logic;
cyc_i : in std_logic;
we_i : in std_logic;
---------------------------------------------------------------
-----------------------------------------------------------------
rston_o : out std_logic;
s_id_o : out std_logic_vector (1 downto 0);
fd_rstn_o : out std_logic;
......@@ -874,12 +868,12 @@ end component WF_production;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
ack_o : out std_logic;
dat_o : out std_logic_vector (15 downto 0)
---------------------------------------------------------------
);
dat_o : out std_logic_vector (15 downto 0));
-----------------------------------------------------------------
end component nanofip;
---------------------------------------------------------------------------------------------------
component WF_model_constr_decoder
port (
......@@ -887,15 +881,15 @@ end component WF_production;
nfip_rst_i : in std_logic;
model_id_i : in std_logic_vector (3 downto 0);
constr_id_i : in std_logic_vector (3 downto 0);
---------------------------------------------------------------
-----------------------------------------------------------------
select_id_o : out std_logic_vector (1 downto 0);
model_id_dec_o : out std_logic_vector (7 downto 0);
constr_id_dec_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
constr_id_dec_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_model_constr_decoder;
---------------------------------------------------------------------------------------------------
component WF_decr_counter is
generic (g_counter_lgth : natural := 5);
......@@ -905,30 +899,29 @@ end component WF_production;
counter_top : in unsigned (g_counter_lgth-1 downto 0);
counter_load_i : in std_logic;
counter_decr_p_i : in std_logic;
---------------------------------------------------------------
-----------------------------------------------------------------
counter_o : out unsigned (g_counter_lgth-1 downto 0);
counter_is_zero_o : out std_logic
---------------------------------------------------------------
);
counter_is_zero_o : out std_logic);
-----------------------------------------------------------------
end component WF_decr_counter;
---------------------------------------------------------------------------------------------------
component WF_incr_counter is
generic (g_counter_lgth : natural := 8);
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
reinit_counter_i : in std_logic;
incr_counter_i : in std_logic;
---------------------------------------------------------------
counter_o : out unsigned(g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic
---------------------------------------------------------------
);
-----------------------------------------------------------------
counter_o : out unsigned (g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
-----------------------------------------------------------------
end component WF_incr_counter;
---------------------------------------------------------------------------------------------------
component WF_prod_data_lgth_calc is
port (
......@@ -936,13 +929,13 @@ end component WF_production;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i : in t_var;
---------------------------------------------------------------
prod_data_length_o : out std_logic_vector(7 downto 0)
---------------------------------------------------------------
);
-----------------------------------------------------------------
prod_data_length_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_prod_data_lgth_calc;
---------------------------------------------------------------------------------------------------
component WF_cons_frame_validator is
port (
......@@ -950,16 +943,17 @@ end component WF_production;
cons_pdu_byte_i : in std_logic_vector (7 downto 0);
cons_lgth_byte_i : in std_logic_vector (7 downto 0);
rx_fss_crc_fes_manch_ok_p_i : in std_logic;
rx_crc_or_manch_wrong_p_i : in std_logic;
var_i : in t_var;
rx_byte_index_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
-----------------------------------------------------------------
cons_frame_ok_p_o : out std_logic;
nfip_status_r_tler_o : out std_logic
---------------------------------------------------------------
);
nfip_status_r_tler_o : out std_logic);
-----------------------------------------------------------------
end component WF_cons_frame_validator;
---------------------------------------------------------------------------------------------------
component WF_cons_outcome is
port (
......@@ -971,55 +965,85 @@ end component WF_production;
var_i : in t_var;
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
-----------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
---------------------------------------------------------------
);
rst_nfip_and_fd_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_cons_outcome;
---------------------------------------------------------------------------------------------------
component WF_prod_permit is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
var_i : in t_var;
---------------------------------------------------------------
var3_rdy_o : out std_logic
---------------------------------------------------------------
);
-----------------------------------------------------------------
var3_rdy_o : out std_logic);
-----------------------------------------------------------------
end component WF_prod_permit;
---------------------------------------------------------------------------------------------------
component WF_wb_controller is
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_r_edge_p_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_id_i : in std_logic_vector (2 downto 0);
---------------------------------------------------------------
-----------------------------------------------------------------
wb_ack_prod_p_o : out std_logic;
wb_ack_p_o : out std_logic
---------------------------------------------------------------
);
wb_ack_p_o : out std_logic);
-----------------------------------------------------------------
end component WF_wb_controller;
---------------------------------------------------------------------------------------------------
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
end WF_package;
--=================================================================================================
--! package body
--=================================================================================================
package body WF_package is
---------------------------------------------------------------------------------------------------
--!@brief Function for the encoding of a word to its Manchester 2 (manch.) equivalent.
--! Each bit "1" is replaced by "10" and each bit "0" by "01".
--! The manch. encoding ensures that there is one transition for each bit.
--! o bit : "0" "1"
--! o manch. encoded : "0 1" "1 0"
--! o scheme : _|- -|_
function f_manch_encoder (word_i : std_logic_vector) return std_logic_vector is
variable word_manch_o : std_logic_vector ((2*word_i'length) -1 downto 0);
begin
for I in word_i'range loop
word_manch_o (I*2) := not word_i(I);
word_manch_o (I*2+1) := word_i(I);
end loop;
-----------------------------------------------------------------
return word_manch_o;
-----------------------------------------------------------------
end function;
end WF_package;
--=================================================================================================
-- package end
......
wf_prod_bytes_retriever.vhd
View file @ 6ead92d5
......@@ -129,7 +129,7 @@ entity WF_prod_bytes_retriever is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
......@@ -139,23 +139,23 @@ entity WF_prod_bytes_retriever is
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_adr_i : in std_logic_vector(8 downto 0); --! WISHBONE address to memory
wb_data_i : in std_logic_vector(7 downto 0); --! WISHBONE data bus
wb_adr_i : in std_logic_vector (8 downto 0); --! WISHBONE address to memory
wb_data_i : in std_logic_vector (7 downto 0); --! WISHBONE data bus
-- Signal from the WF_wb_controller
wb_ack_prod_p_i : in std_logic; --! WISHBONE acknowledge
-- latching moment of wb_data_i
-- nanoFIP User Interface, NON WISHBONE (synchronized with uclk)
slone_data_i : in std_logic_vector(15 downto 0); --! input data bus for slone mode
-- nanoFIP User Interface, NON WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector(7 downto 0); --!index of the byte to be retrieved
byte_index_i : in std_logic_vector (7 downto 0); --!index of the byte to be retrieved
byte_being_sent_p_i : in std_logic; --! pulse on the beginning of the
--! delivery of a new byte
data_length_i : in std_logic_vector(7 downto 0); --! # bytes of the Conrol&Data fields
data_length_i : in std_logic_vector (7 downto 0); --! # bytes of the Conrol&Data fields
-- of the RP_DAT frame; includes:
-- 1 byte RP_DAT.Control,
-- 1 byte RP_DAT.Data.PDU_type,
......@@ -172,12 +172,12 @@ entity WF_prod_bytes_retriever is
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- Signals from the WF_status_bytes_gen
mps_status_byte_i : in std_logic_vector(7 downto 0); --! MPS status byte
nFIP_status_byte_i : in std_logic_vector(7 downto 0); --! nanoFIP status byte
mps_status_byte_i : in std_logic_vector (7 downto 0); --! MPS status byte
nFIP_status_byte_i : in std_logic_vector (7 downto 0); --! nanoFIP status byte
-- Signals from the WF_model_constr_dec unit
constr_id_dec_i : in std_logic_vector(7 downto 0); --! decoded constructor id settings
model_id_dec_i : in std_logic_vector(7 downto 0); --! decoded model id settings
constr_id_dec_i : in std_logic_vector (7 downto 0);--! decoded constructor id settings
model_id_dec_i : in std_logic_vector (7 downto 0);--! decoded model id settings
-- OUTPUTS
......@@ -187,7 +187,7 @@ entity WF_prod_bytes_retriever is
--! the delivery of the last one (MPS)
-- Signal to the WF_tx_serializer
byte_o : out std_logic_vector(7 downto 0) --! output byte to be serialized
byte_o : out std_logic_vector (7 downto 0) --! output byte to be serialized
);
end entity WF_prod_bytes_retriever;
......@@ -198,7 +198,7 @@ end entity WF_prod_bytes_retriever;
--=================================================================================================
architecture rtl of WF_prod_bytes_retriever is
signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0);
signal s_base_addr, s_mem_addr_offset : unsigned (8 downto 0);
signal s_byte_index_d_aux : integer range 0 to 15;
signal s_lgth_byte, s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0);
signal s_byte_index_d : std_logic_vector (7 downto 0);
......@@ -218,13 +218,13 @@ begin
--!@brief Instantiation of a Produced Dual Port RAM
Produced_Bytes_From_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map(
c_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
c_RAM_ADDR_LGTH => 9) -- 2^9: depth of produced ram
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of produced ram
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
-- port A corresponds to: nanoFIP that reads from the Produced ram & B to: WISHBONE that writes
port map(
port map (
clk_porta_i => uclk_i, -- 40 MHz clock
addr_porta_i => s_mem_addr_A, -- address of byte to be read from memory
------------------------------------------------------------------------------------
......@@ -245,7 +245,7 @@ begin
--! has been de-asserted.
Produced_Bytes_From_DATI: WF_prod_bytes_from_dati
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_data_i => slone_data_i,
......@@ -271,8 +271,7 @@ begin
Bytes_Generation: process (var_i, s_byte_index_d, data_length_i, constr_id_dec_i, model_id_dec_i,
nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_byte_index_d_aux,
s_mem_byte, s_byte_index_d_aux, nostat_i, byte_being_sent_p_i,
s_lgth_byte, slone_i)
s_mem_byte, nostat_i, byte_being_sent_p_i, s_lgth_byte, slone_i)
begin
......
wf_prod_bytes_to_dati.vhd
View file @ 6ead92d5
......@@ -90,7 +90,7 @@ entity WF_prod_bytes_from_dati is
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- (synchronized with uclk)
-- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector (7 downto 0); --! index of the byte to be produced
......
wf_prod_data_lgth_calc.vhd
View file @ 6ead92d5
......@@ -84,11 +84,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -99,10 +94,10 @@ entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- nanoFIP WorldFIP Settings (synchronized with uclk)
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length
-- User Interface, General signals (synchronized with uclk)
-- User Interface, General signals
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
......@@ -112,7 +107,7 @@ entity WF_prod_data_lgth_calc is
-- OUTPUT
-- Signal to the WF_engine_control and WF_production units
prod_data_length_o : out std_logic_vector(7 downto 0)
prod_data_length_o : out std_logic_vector (7 downto 0)
);
end entity WF_prod_data_lgth_calc;
......@@ -123,7 +118,7 @@ end entity WF_prod_data_lgth_calc;
--=================================================================================================
architecture rtl of WF_prod_data_lgth_calc is
signal s_prod_data_length, s_p3_length_decoded : unsigned(7 downto 0);
signal s_prod_data_length, s_p3_length_decoded : unsigned (7 downto 0);
--=================================================================================================
-- architecture begin
......
wf_prod_permit.vhd
View file @ 6ead92d5
......@@ -79,7 +79,7 @@ entity WF_prod_permit is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
......
wf_production.vhd
View file @ 6ead92d5
......@@ -30,11 +30,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @brief The unit groups the main actions that regard data production.
--! It instantiates the units:
--!
--! o WF_tx_serializer : that receives bytes from the WF_prod_bytes_retriever,
--! encodes them (Manchester 2), adds the FSS, FCS & FES
--! fields and puts one by one bits to the FIELDRIVE output
--! FD_TXD. Also handles the nanoFIP output FD_TXENA.
--!
--! o WF_prod_bytes_retriever: that retrieves
--! o user-data bytes: from the Produced RAM or the
--! "nanoFIP User Interface, NON-WISHBONE" bus DAT_I,
......@@ -42,35 +37,38 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o MPS,nFIP status: from the WF_status_bytes_gen
--! o LGTH byte : from the WF_prod_data_lgth_calc
--! and following the signals from the external unit
--! WF_engine_control forwards them to the WF_tx_serializer.
--! WF_engine_control forwards them to the WF_fd_transmitter
--!
--! o WF_status_bytes_gen : that receives information from the WF_consumption unit,
--! the "FIELDRIVE" and "User Interface,NON-WISHBONE"inputs
--! and outputs, for the generation of the nanoFIP & MPS
--! status bytes
--!
--! o WF_prod_permit : that signals the user that a variable can safely be
--! written (through the "nanoFIP User Interface,
--! NON-WISHBONE" signal VAR3_RDY)
--! o WF_prod_permit : that signals the user that user-data bytes can safely be
--! written
--!
--! _________________________________
--! ___________________________________________________________
--! | WF_production |
--! | |
--! | WF_prod_permit |
--! |_________________________________|
--! ^
--! _________________________________ ________________
--! | _________________________________ |
--! | | | |
--! | WF_prod_bytes_retriever | < | WF_status_bytes|
--! | | | _gen |
--! |_________________________________| |________________|
--! ^
--! _________________________________
--! | | WF_prod_permit | |
--! | |_________________________________| |
--! | |
--! | _________________________________ ________________ |
--! | | | | | |
--! | | WF_prod_bytes_retriever | < | WF_status_bytes| |
--! | | | | _gen | |
--! | |_________________________________| |________________| |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________
--! | |
--! | WF_tx_serializerr |
--! |_________________________________|
--! ^
--! _______________________________________________________________
--! 0__________________________FIELDBUS____________________________O
--! | WF_fd_transmitter |
--! |___________________________________________________________|
--! \/
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--!
--! Note: In the entity declaration of this unit, below each input signal, we mark
--! which of the instantiated units needs it.
......@@ -84,7 +82,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @date 11/01/2011
--
--
--! @version v0.01
--! @version v0.02
--
--
--! @details \n
......@@ -93,7 +91,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_reset_unit \n
--! WF_consumption \n
--! WF_engine_control \n
--! WF_tx_rx_osc \n
--! WF_fd_transmitter \n
--! WF_model_constr_decoder \n
--
--
......@@ -102,7 +100,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! ->
--! -> 2/2011 v0.02 EG WF_serializer removed from this unit
--
---------------------------------------------------------------------------------------------------
--
......@@ -127,9 +125,10 @@ entity WF_production is
port (
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic;
-- used by: all the units
slone_i : in std_logic;
-- used by: WF_prod_bytes_retriever for the selection of data bytes from the RAM or the DAT_I
......@@ -143,14 +142,15 @@ entity WF_production is
-- Signal from the WF_reset_unit unit
nfip_rst_i : in std_logic;
-- used by: all the units
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector(8 downto 0);
wb_data_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector (8 downto 0);
wb_data_i : in std_logic_vector (7 downto 0);
-- used by: WF_prod_bytes_retriever for the managment of the Production RAM
......@@ -162,22 +162,22 @@ entity WF_production is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, NON-WISHBONE (synchronized with uclk)
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector(15 downto 0);
slone_data_i : in std_logic_vector (15 downto 0);
-- used by: WF_prod_bytes_retriever for the bytes retreival in stand-alone mode
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
var1_acc_a_i : in std_logic;
var2_acc_a_i : in std_logic;
var3_acc_a_i : in std_logic;
-- used by: WF_status_bytes_gen for the nanoFIP status byte, bits 2, 3
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP FIELDRIVE (synchronized with uclk)
-- nanoFIP FIELDRIVE
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
-- used by: WF_status_bytes_gen for the nanoFIP status byte, bits 6, 7
......@@ -186,14 +186,10 @@ entity WF_production is
byte_index_i : in std_logic_vector (7 downto 0);
data_length_i : in std_logic_vector (7 downto 0);
byte_request_accept_p_i : in std_logic;
var_i : in t_var;-- also for the WF_prod_permit for the VAR3_RDY generation
-- used by: WF_prod_bytes_retriever for the definition of the bytes to be delivered
byte_request_accept_p_i : in std_logic;
last_byte_p_i : in std_logic;
start_prod_p_i : in std_logic;
-- used by: WF_tx_serializer for the delivery coordination
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_consumption
......@@ -205,13 +201,6 @@ entity WF_production is
-- used by: WF_status_bytes_gen for the generation of the nanoFIP status byte, bits 2, 4, 5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_rx_tx_osc
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
-- used by: WF_tx_serializer for the transmission synchronization
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_model_constr_decoder unit
......@@ -220,26 +209,19 @@ entity WF_production is
-- used by: WF_prod_bytes_retriever for the production of a var_identif
-------------------------------------------------------------------------------------------------
-- OUTPUTS
-- Signal to the WF_engine_control
byte_request_p_o : out std_logic;--! request for a new byte to be transmitted; pulse
--! at the end of the transmission of a previous byte
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; --! transmitter data
tx_enable_o : out std_logic; --! transmitter enable
-- Signal to the WF_FD_transmitter
byte_o : out std_logic_vector (7 downto 0);
-- nanoFIP User Interface, NON-WISHBONE outputs
u_cacer_o : out std_logic; --! nanoFIP status byte, bit 2
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
u_pacer_o : out std_logic; --! nanoFIP status byte, bit 3
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
var3_rdy_o : out std_logic --! signals the user that data can safely be written
u_cacer_o : out std_logic;
r_fcser_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
var3_rdy_o : out std_logic
);
end entity WF_production;
......@@ -250,9 +232,8 @@ end entity WF_production;
--=================================================================================================
architecture struc of WF_production is
signal s_byte_to_tx, s_stat, s_mps : std_logic_vector (7 downto 0);
signal s_var3_rdy, s_rst_status_bytes_p : std_logic;
signal s_stat, s_mps : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
......@@ -263,27 +244,28 @@ begin
---------------------------------------------------------------------------------------------------
-- Production Permit --
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_prod_permit unit
production_VAR3_RDY_generation: WF_prod_permit
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
var_i => var_i,
-----------------------------------------------
var3_rdy_o => s_var3_rdy
var3_rdy_o => s_var3_rdy);
-----------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Bytes Retreival --
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_prod_bytes_retriever unit
production_bytes_retriever : WF_prod_bytes_retriever
port map(
port map (
uclk_i => uclk_i,
model_id_dec_i => model_id_dec_i,
constr_id_dec_i => constr_id_dec_i,
......@@ -304,31 +286,31 @@ begin
var3_rdy_i => s_var3_rdy,
-----------------------------------------------
rst_status_bytes_p_o => s_rst_status_bytes_p,
byte_o => s_byte_to_tx
byte_o => byte_o);
-----------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Status Byte Generation --
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_status_bytes_gen unit
production_status_bytes_generator : WF_status_bytes_gen
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
fd_wdgn_i => fd_wdgn_i,
fd_txer_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_a_i,
fd_txer_a_i => fd_txer_a_i,
nfip_status_r_fcser_p_i => nfip_status_r_fcser_p_i,
var1_rdy_i => var1_rdy_i,
var2_rdy_i => var2_rdy_i,
var3_rdy_i => s_var3_rdy,
var1_acc_i => var1_acc_i,
var2_acc_i => var2_acc_i,
var3_acc_i => var3_acc_i,
var1_acc_a_i => var1_acc_a_i,
var2_acc_a_i => var2_acc_a_i,
var3_acc_a_i => var3_acc_a_i,
nfip_status_r_tler_i => nfip_status_r_tler_i,
rst_status_bytes_p_i => s_rst_status_bytes_p,
-----------------------------------------------
......@@ -337,33 +319,8 @@ begin
r_tler_o => r_tler_o,
r_fcser_o => r_fcser_o,
nFIP_status_byte_o => s_stat,
mps_status_byte_o => s_mps
-----------------------------------------------
);
---------------------------------------------------------------------------------------------------
-- Serializer --
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_tx_serializer unit
production_serializer: WF_tx_serializer
generic map(c_TX_CLK_BUFF_LGTH => c_TX_CLK_BUFF_LGTH)
PORT MAP(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_prod_p_i => start_prod_p_i,
byte_request_accept_p_i => byte_request_accept_p_i,
byte_i => s_byte_to_tx,
last_byte_p_i => last_byte_p_i,
tx_clk_p_buff_i => tx_clk_p_buff_i,
mps_status_byte_o => s_mps);
-----------------------------------------------
tx_data_o => tx_data_o,
byte_request_p_o => byte_request_p_o,
tx_enable_o => tx_enable_o
-----------------------------------------------
);
var3_rdy_o <= s_var3_rdy;
......
wf_reset_unit.vhd
View file @ 6ead92d5
......@@ -167,10 +167,13 @@ entity WF_reset_unit is
-- INPUTS
-- nanoFIP User Interface General signals
uclk_i : in std_logic; --! 40 MHz clock
rstin_i : in std_logic; --! initialisation control, active low (synch/ed with uclk)
rstin_a_i : in std_logic; --! initialisation control, active low (synch/ed with uclk)
rstpon_i : in std_logic; --! Power On Reset, active low
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate (synch/ed with uclk)
wb_clk_i : in std_logic;
-- nanoFIP User Interface WISHBONE Slave
rst_i : in std_logic; --! WISHBONE reset
......@@ -192,7 +195,7 @@ entity WF_reset_unit is
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
--! resets all nanoFIP logic, apart from the WISHBONE
-- Signal to the WF_inputs_synchronizer
-- Signal to the WF_wb_controller
wb_rst_o : out std_logic; --! reset of the WISHBONE logic
-- nanoFIP User Interface General signal output
......@@ -209,7 +212,8 @@ end entity WF_reset_unit;
--=================================================================================================
architecture rtl of WF_reset_unit is
signal s_counter_is_four, s_reinit_counter, s_rston, s_FD_rst_from_var_rst, s_por : std_logic;
signal s_counter_is_four, s_reinit_counter, s_rston, s_FD_rst_from_var_rst : std_logic;
signal s_u_por_ff1, s_u_por, s_wb_por_ff1, s_wb_por : std_logic;
signal s_intern_rst_from_RSTIN, s_intern_rst_from_var_rst, s_fd_rst_from_RSTIN : std_logic;
signal s_counter_is_ten, s_counter_is_full, s_counter_full : std_logic;
signal s_var_rst_counter_is_eight, s_var_rst_counter_is_two : std_logic;
......@@ -226,14 +230,13 @@ architecture rtl of WF_reset_unit is
signal after_a_var_rst_st, nx_after_a_var_rst_st : after_a_var_rst_t;
signal rstin_st, nx_rstin_st : rstin_st_t;
signal s_rsti_synch : std_logic_vector (2 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_por <= not rstpon_i;
s_transm_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks of a
-- transmission period
......@@ -245,16 +248,66 @@ begin
s_var_rst_counter_full <= '1' when s_var_rst_c = s_txck_four_periods else '0';
---------------------------------------------------------------------------------------------------
-- Power On Reset Synchronizers --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronization of the de-assertion of the Power On reset, with the wb_clk.
--! The second flip-flop is used to remove metastabilities.
PoR_wb_clk_Synchronizer: process (wb_clk_i, rstpon_i)
begin
if rstpon_i = '0' then
s_wb_por_ff1 <= '1';
s_wb_por <= '1';
elsif rising_edge (wb_clk_i) then
s_wb_por_ff1 <= '0';
s_wb_por <= s_wb_por_ff1;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronization of the de-assertion of the Power On reset, with the uclk.
--! The second flip-flop is used to remove metastabilities.
PoR_uclk_Synchronizer: process (uclk_i, rstpon_i)
begin
if rstpon_i = '0' then
s_u_por_ff1 <= '1';
s_u_por <= '1';
elsif rising_edge (uclk_i) then
s_u_por_ff1 <= '0';
s_u_por <= s_u_por_ff1;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- RSTIN --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief RSTIN synchronization with a set of 3 registers.
RSTIN_uclk_Synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
s_rsti_synch <= s_rsti_synch (1 downto 0) & not rstin_a_i;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief RSTIN FSM: the state machine is divided in three parts (a clocked process
--! to store the current state, a combinatorial process to manage state transitions and finally a
--! combinatorial process to manage the output signals), which are the three processes that follow.
--! The FSM is following the "User Interface, General signal" RSTIN (after synchronization) and
--! checks weather it stays active for more than 4 uclk cycles; if so, it enables the nanoFIP
--! checks whether it stays active for more than 4 uclk cycles; if so, it enables the nanoFIP
--! internal reset (s_intern_rst_from_RSTIN) and the FIELDRIVE reset (s_FD_rst_from_RSTIN). The
--! nanoFIP internal reset stays active for 2 uclk cycles and the FIELDRIVE for 4 FD_TXCK cycles.
--! The same counter is used for the evaluation of the RSTIN (if it is > 4 uclk) and for the
......@@ -266,7 +319,7 @@ begin
RSTIN_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_por = '1' or rst_nFIP_and_FD_p_i = '1' then
if s_u_por = '1' or rst_nFIP_and_FD_p_i = '1' then
rstin_st <= idle;
else
rstin_st <= nx_rstin_st;
......@@ -279,7 +332,7 @@ begin
--!@brief Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, rstin_i, s_counter_is_four,
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, s_rsti_synch(2), s_counter_is_four,
s_counter_is_ten, s_counter_is_full)
begin
......@@ -287,15 +340,16 @@ begin
case rstin_st is
when idle =>
if rstin_i = '0' then -- RSTIN active
if s_rsti_synch(2) = '1' then -- RSTIN active
nx_rstin_st <= rstin_eval;
else
nx_rstin_st <= idle;
end if;
when rstin_eval =>
if rstin_i = '1' then -- RSTIN deactivated
if s_rsti_synch(2) = '0' then -- RSTIN deactivated
nx_rstin_st <= idle;
else
......@@ -318,6 +372,7 @@ begin
nx_rstin_st <= intern_rst_ON_fd_rst_ON;
end if;
when intern_rst_OFF_fd_rst_ON =>
-- nanoFIP internal reset deactivated
if s_counter_is_full = '1' then -- FIELDRIVE reset continues being active
......@@ -328,7 +383,6 @@ begin
end if;
when others =>
nx_rstin_st <= idle;
end case;
......@@ -355,7 +409,7 @@ begin
when rstin_eval =>
s_reinit_counter <= '0'; -- counting until 4
-- if rstin_i is active
-- if RSTIN is active
s_intern_rst_from_RSTIN <= '0';
s_FD_rst_from_RSTIN <= '0';
......@@ -394,9 +448,8 @@ begin
RSTIN_free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LENGTH)
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => '0',
reinit_counter_i => s_reinit_counter,
incr_counter_i => '1',
counter_o => s_c,
......@@ -415,7 +468,6 @@ RSTIN_free_counter: WF_incr_counter
--!@brief Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
--! to store the current state, a combinatorial process to manage state transitions and finally a
--! combinatorial process to manage the output signals), which are the three processes that follow.
--! If after the reception or a var_rst the signal assert_RSTON_p_i is asserted, the FSM
--! asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
--! If after the reception or a var_rst the signal rst_nFIP_and_FD_p_i is asserted, the FSM
......@@ -432,7 +484,7 @@ RSTIN_free_counter: WF_incr_counter
Resets_after_a_var_rst_synch: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_por = '1' or s_intern_rst_from_RSTIN = '1' then
if s_u_por = '1' or s_intern_rst_from_RSTIN = '1' then
after_a_var_rst_st <= after_a_var_rst_idle;
else
after_a_var_rst_st <= nx_after_a_var_rst_st;
......@@ -456,8 +508,8 @@ RSTIN_free_counter: WF_incr_counter
when after_a_var_rst_idle =>
if (var_i = var_rst) and (assert_RSTON_p_i = '1') -- re-check of var_i
and (rst_nFIP_and_FD_p_i = '1') then -- just in case
if (var_i = var_rst) and (assert_RSTON_p_i = '1')
and (rst_nFIP_and_FD_p_i = '1') then
nx_after_a_var_rst_st <= after_a_var_rst_nFIP_ON_fd_ON_rston_ON;
elsif (var_i = var_rst) and (assert_RSTON_p_i = '1') then
......@@ -615,17 +667,16 @@ RSTIN_free_counter: WF_incr_counter
free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LENGTH)
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => '0',
reinit_counter_i => s_var_rst_reinit_counter,
incr_counter_i => '1',
counter_o => s_var_rst_c,
counter_is_full_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_counter_is_eight <= '1' when s_var_rst_c = to_unsigned(8, s_var_rst_c'length) else '0';
s_var_rst_counter_is_two <= '1' when s_var_rst_c = to_unsigned(10, s_var_rst_c'length) else '0';
s_var_rst_counter_is_eight <= '1' when s_var_rst_c= to_unsigned(8, s_var_rst_c'length) else '0';
s_var_rst_counter_is_two <= '1' when s_var_rst_c= to_unsigned(10, s_var_rst_c'length) else '0';
s_var_rst_counter_is_full <= s_var_rst_counter_full;
......@@ -634,17 +685,16 @@ free_counter: WF_incr_counter
-- Output Signals --
---------------------------------------------------------------------------------------------------
wb_rst_o <= rst_i or s_por; --f_edge of s_por has to be synched with wb_clk
wb_rst_o <= rst_i or s_wb_por;
nFIP_rst_o <= s_intern_rst_from_RSTIN or s_intern_rst_from_var_rst or s_u_por;
nFIP_rst_o <= s_intern_rst_from_RSTIN or s_intern_rst_from_var_rst or s_por; --f_edge of s_por
-- has to be synched with uclk
Outputs_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
rston_o <= not s_rston;
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_por);
fd_rstn_o <= not (s_FD_rst_from_RSTIN or s_FD_rst_from_var_rst or s_u_por);
end if;
end process;
......
wf_rx_deglitcher.vhd
View file @ 6ead92d5
......@@ -10,13 +10,15 @@
--! @file WF_rx_deglitcher.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
--! standard library
library IEEE;
--! Standard packages
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
......@@ -25,42 +27,23 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit applies a glitch filter; it follows each Manchester 2 encoded bit (manch.)
--! of the "nanoFIP FIELDRIVE" input signal FD_RXD (synchronized with uclk), counts the
--! number of zeros and ones throughout its duration and finally outputs the majority.
--! The output deglitched signal is one half-bit-clock period later than the input.
--!
--! Remark: We refer to
--! o a significant edge : for the edge of a manch. encoded bit
--! (bit 0: _|-, bit 1: -|_)
--!
--! o the sampling of a manch. bit : for the moments when a manch. encoded bit
--! should be sampled, before and after a significant edge
--!
--! o the sampling of a bit : for the sampling of only the 1st part,
--! before the transition.
--!
--! Example:
--! bits : 0 1
--! manch. encoded : _|- -|_
--! significant edge : ^ ^
--! sample_manch_bit_p : ^ ^ ^ ^
--! sample_bit_p : ^ ^ (this sampling will give the 0 and the 1)
--! @brief The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD.
--! It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
-- @date 23/08/2010
-- @date 14/02/2011
--
--
--! @version v0.02
--! @version v0.03
--
--
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_tx_rx_osc \n
--! WF_reset_unit \n
--
--
......@@ -73,6 +56,8 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! \n\n<b>Last changes:</b>\n
--! -> 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content
--! -> 23/08/2010 v0.02 EG code cleaned-up+commented
--! -> 14/02/2011 v0.03 EG changesd deglitcher philosophy, no dependency on osc;
--! fd_rxd deglitched right at reception
--
---------------------------------------------------------------------------------------------------
--
......@@ -87,7 +72,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
entity WF_rx_deglitcher is
generic (c_DEGLITCH_LGTH : integer := 10);
port(
-- INPUTS
......@@ -98,19 +82,14 @@ entity WF_rx_deglitcher is
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk)
rxd_i : in std_logic; --! ____|--------|________|--------|________
-- Signals from the WF_tx_rx_osc unit
sample_bit_p_i : in std_logic; --! ____|-|_______________|-|_______________
sample_manch_bit_p_i : in std_logic; --! ____|-|______|-|______|-|______|-|______
fd_rxd_a_i : in std_logic; --! receiver data
-- OUTPUTS
-- Signals to the WF_rx_deserializer unit
rxd_filtered_o : out std_logic; --! filtered output signal
rxd_filtered_f_edge_p_o : out std_logic; --! indicates a falling edge on the filtered signal
sample_bit_p_o : out std_logic; --! same as sample_bit_p_i
sample_manch_bit_p_o : out std_logic --! same as sample_manch_bit_p_i
fd_rxd_filtered_o : out std_logic; --! filtered output signal
fd_rxd_filtered_edge_p_o : out std_logic; --! indicates an edge on the filtered signal
fd_rxd_filtered_f_edge_p_o : out std_logic --! indicates a falling edge on the filtered signal
);
end WF_rx_deglitcher;
......@@ -121,10 +100,10 @@ end WF_rx_deglitcher;
--=================================================================================================
architecture Behavioral of WF_rx_deglitcher is
signal s_rxd_filtered : std_logic;
signal s_rxd_filtered_d : std_logic;
signal s_rxd_filtered_buff : std_logic_vector (1 downto 0);
signal s_zeros_and_ones_c : signed (c_DEGLITCH_LGTH - 1 downto 0);
signal s_rxd_filtered, s_rxd_filtered_d1 : std_logic;
signal s_rxd_filtered_r_edge_p, s_rxd_filtered_f_edge_p : std_logic;
signal s_deglitch_c : unsigned (3 downto 0);
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
--=================================================================================================
......@@ -132,85 +111,75 @@ signal s_zeros_and_ones_c : signed (c_DEGLITCH_LGTH - 1 downto 0);
--=================================================================================================
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
--!@brief Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input
--! FD_RXD to the uclk, using a set of 2 registers.
---------------------------------------------------------------------------------------------------
--! Synchronous process: Zeros_and_Ones_counter: For each manch. encoded bit (between two
--! sample_manch_bit_p_i pulses) at each uclk tick, the signed counter decreases by one if rxd_i
--! is "1" and increases by one if rxd_i is "0".
Zeros_and_Ones_counter: process (uclk_i)
FD_RXD_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_zeros_and_ones_c <= (others =>'0');
else
if sample_manch_bit_p_i = '1' then -- arrival of a new manchester bit
s_zeros_and_ones_c <= (others =>'0'); -- counter initialized
s_fd_rxd_synch <= (others => '0');
elsif rxd_i = '1' then
s_zeros_and_ones_c <= s_zeros_and_ones_c - 1;
else
s_zeros_and_ones_c <= s_zeros_and_ones_c + 1;
end if;
s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i;
end if;
end if;
end process;
end process;
---------------------------------------------------------------------------------------------------
--! Synchronous process Filtering: On the arrival of a new manch. bit, if the number of ones
--! that has been measured (for the bit that has already passed) is more than the number of zeros,
--! the filtered output is set to zero (until the new manch. bit), otherwise to one.
--! The filtered signal is one half-bit-clock cycle (+2 uclk cycles) late with respect to its input.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
--!@brief Synchronous process FD_RXD_deglitcher: the output signal rxd_filtered is updated only
--! after the accumulation of a sufficient (c_DEGLITCH_THRESHOLD+1) amount of identical bits.
--! The signal is therefore cleaned of any glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
Filtering: process (uclk_i)
FD_RXD_deglitcher: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_deglitch_c <= to_unsigned (c_DEGLITCH_THRESHOLD, s_deglitch_c'length) srl 1;-- middle value
s_rxd_filtered <= '0';
s_rxd_filtered_d <= '0';
else
if sample_manch_bit_p_i = '1' then
s_rxd_filtered <= s_zeros_and_ones_c (s_zeros_and_ones_c'left);-- if the ones are more than
-- the zeros, the output is
end if; -- 1 otherwise, 0
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if s_fd_rxd_synch(1) = '0' then -- arrival of a '0'
s_rxd_filtered_d <= s_rxd_filtered; -- 1 uclk period delay, so that the pulses sample_bit_p
-- and sample_manch_bit_p arrive 2 uclk periods before
end if; -- the rxd_filtered edges
end if;
end process;
if s_deglitch_c /= 0 then -- counter updated
s_deglitch_c <= s_deglitch_c - 1;
else
s_rxd_filtered <= '0'; -- output updated
end if; -- if counter = 0
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Detect_f_edge_rxd_filtered: detection of a falling edge on the
--! deglitched input signal (rxd_filtered).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif s_fd_rxd_synch(1) = '1' then -- arrival of a '1'
Detect_f_edge_rxd_filtered: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_rxd_filtered_buff <= (others => '0');
if s_deglitch_c /= c_DEGLITCH_THRESHOLD then
s_deglitch_c <= s_deglitch_c + 1; -- counter updated
else
-- buffer s_rxd_filtered_buff keeps the last 2 bits of s_rxd_filtered_d
s_rxd_filtered_buff <= s_rxd_filtered_buff(0) & s_rxd_filtered_d;
s_rxd_filtered <= '1'; -- output updated
end if; -- if counter = c_DEGLITCH_THRESHOLD
end if;
s_rxd_filtered_d1 <= s_rxd_filtered;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignments
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignments
s_rxd_filtered_r_edge_p <= (not s_rxd_filtered_d1) and s_rxd_filtered; -- pulse upon detection
-- of a falling edge
rxd_filtered_f_edge_p_o <= s_rxd_filtered_buff(1) and (not s_rxd_filtered_buff(0));
rxd_filtered_o <= s_rxd_filtered_d;
sample_bit_p_o <= sample_bit_p_i;
sample_manch_bit_p_o <= sample_manch_bit_p_i;
s_rxd_filtered_f_edge_p <= s_rxd_filtered_d1 and (not s_rxd_filtered); -- pulse upon detection
-- of a rising edge
fd_rxd_filtered_edge_p_o <= s_rxd_filtered_f_edge_p or s_rxd_filtered_r_edge_p;
fd_rxd_filtered_f_edge_p_o <= s_rxd_filtered_f_edge_p;
fd_rxd_filtered_o <= s_rxd_filtered;
end Behavioral;
......
wf_rx_deserializer.vhd
View file @ 6ead92d5
......@@ -36,7 +36,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! encoding.
--! At the end of a frame (FES detection) either the fss_crc_fes_manch_ok_p_o pulse
--! is assserted, indicating a frame with with correct FSS, CRC, FES and manch. encoding
--! or the pulse crc_or_manch_wrong_p_o is asserted indicating an error on the CRC or
--! or the pulse rx_crc_or_manch_wrong_p_o is asserted indicating an error on the CRC or
--! manch. encoding.
--! If a FES is not detected after the reception of more than 8 bytes for an ID_DAT or
--! more than 130 bytes for a RP_DAT the unit is reset by the WF_engine_control.
......@@ -76,20 +76,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 9/12/2010
--! @date 15/02/2011
--
--
--! @version v0.04
--! @version v0.05
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_tx_osc \n
--! WF_rx_osc \n
--! WF_rx_deglitcher \n
--! WF_engine_control \n
--! WF_inputs_synchronizer\n
--
--
--! \n<b>Modified by:</b> \n
......@@ -101,7 +100,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n\n<b>Last changes:</b>\n
--! -> 09/2009 v0.01 PAS First version \n
--! -> 10/2010 v0.02 EG state switch_to_deglitched added;
--! output signal rst_rx_osc_o added; signals renamed;
--! output signal rx_osc_rst_o added; signals renamed;
--! state machine rewritten (moore style);
--! units WF_rx_manch_code_check and Incoming_Bits_Index created;
--! each manch bit of FES checked (bf was just each bit, so any D5 was FES)
......@@ -115,6 +114,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if
--! bytes with size different than 8 have preceeded.
--! crc_or_manch_wrong_p_o replaced the crc_wrong_p_o.
--! -> 02/2011 v0.05 EG changed crc pulse transfer; removed switch to deglitch state
--
---------------------------------------------------------------------------------------------------
--
......@@ -123,11 +123,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -145,32 +140,27 @@ entity WF_rx_deserializer is
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_engine_control unit
rst_rx_unit_p_i : in std_logic; --! reset of the unit
rx_rst_p_i : in std_logic; --! receiver timeout
--! in cases when more bytes than expected are being
--! received (ID_DAT > 8 bytes, RP_DAT > 130 bytes)
-- Signals from the WF_rx_tx_osc unit
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
--! bits is expected
-- Signals from the WF_inputs_synchronizer unit
rxd_f_edge_p_i : in std_logic; --! indicates a falling edge on fd_rxd
rxd_r_edge_p_i : in std_logic; --! indicates a rising edge on fd_rxd
-- Signals from the WF_fd_deglitcher
fd_rxd_f_edge_p_i : in std_logic; --! indicates a falling edge on the deglitched fd_rxd
fd_rxd_r_edge_p_i : in std_logic; --! indicates a rising edge on the deglitched fd_rxd
fd_rxd_i : in std_logic; --! deglitched fd_rxd
-- Signals from the WF_rx_deglitcher unit
rxd_filtered_i : in std_logic; --! deglitched fd_rxd
rxd_filtered_f_edge_p_i : in std_logic; --! falling edge on the deglitched fd_rxd
-- Signals from the WF_rx_osc unit
sample_manch_bit_p_i : in std_logic; --! pulse indicating the sampling of a manch. bit
sample_bit_p_i : in std_logic; --! pulse indicating the sampling of a bit
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
--! bits is expected
-- OUTPUTS
-- Signals to the WF_cons_bytes_processor and the WF_engine_control units
-- Signals to the WF_consumption and the WF_engine_control units
byte_o : out std_logic_vector (7 downto 0) ; --! retrieved data byte
byte_ready_p_o : out std_logic; --! pulse indicating a new retrieved data byte
-- Signal to the WF_cons_frame_validator and the WF_engine_control units
fss_crc_fes_manch_ok_p_o: out std_logic; --! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding
......@@ -178,11 +168,11 @@ entity WF_rx_deserializer is
crc_or_manch_wrong_p_o : out std_logic; --! indication of a wrong CRC or manch. encoding on a
--! ID_DAT or RP_DAT; pulse after the FES detection
-- Signal to the WF_engine_control units
-- Signal to the WF_engine_control unit
fss_received_p_o : out std_logic; --! pulse after the reception of a correct FSS (ID/RP)
-- Signal to the WF_rx_tx_osc unit
rst_rx_osc_o : out std_logic --! resets the clk recovery procedure of rx_osc
-- Signal to the WF_rx_osc unit
rx_osc_rst_o : out std_logic --! resets the clk recovery procedure
);
end entity WF_rx_deserializer;
......@@ -195,23 +185,20 @@ architecture rtl of WF_rx_deserializer is
-- states of the receiver's state machine
type rx_st_t is (idle, pre_field_first_f_edge, pre_field_r_edge, pre_field_f_edge,
fsd_field, switch_to_deglitched, data_fcs_fes_fields);
fsd_field, ctrl_data_fcs_fes_fields);
signal rx_st, nx_rx_st : rx_st_t;
signal s_manch_code_viol_p, s_CRC_ok_p, s_crc_ok_p_d15 : std_logic;
signal s_fsd_last_bit, s_fes_wrong_bit, s_sample_manch_bit_p_d1 : std_logic;
signal s_fes_detected_p : std_logic;
signal s_manch_not_ok, s_switching_to_deglitched : std_logic;
signal s_receiving_fsd, s_receiving_bytes, s_receiving_pre : std_logic;
signal s_decr_manch_bit_index_p, s_manch_bit_index_load : std_logic;
signal s_manch_bit_index_is_zero, s_edge_outside_manch_window_p : std_logic;
signal s_byte_ready_p, s_write_bit_to_byte, s_idle : std_logic;
signal s_bit_r_edge_p,s_fsd_bit,s_fes_bit, s_fsd_wrong_bit : std_logic;
signal s_manch_r_edge_p, s_manch_f_edge_p : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned(3 downto 0);
signal s_idle, s_receiving_pre, s_receiving_fsd, s_receiving_bytes : std_logic;
signal s_fsd_bit, s_fes_bit, s_fsd_wrong_bit : std_logic;
signal s_fsd_last_bit, s_fes_wrong_bit, s_fes_detected_p : std_logic;
signal s_byte_ready_p, s_byte_ready_p_d1, s_write_bit_to_byte : std_logic;
signal s_manch_r_edge_p, s_manch_f_edge_p, s_bit_r_edge_p, s_edge_out_manch_window_p : std_logic;
signal s_manch_bit_index_load, s_decr_manch_bit_index_p, s_manch_bit_index_is_zero : std_logic;
signal s_manch_not_ok, s_manch_code_viol_p,s_CRC_ok_p,s_CRC_ok_p_d, s_CRC_ok_p_found : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned (3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_arriving_fes : std_logic_vector (15 downto 0);
signal s_CRC_ok_p_buff : std_logic_vector (14 downto 0);
--=================================================================================================
-- architecture begin
......@@ -221,16 +208,11 @@ architecture rtl of WF_rx_deserializer is
---------------------------------------------------------------------------------------------------
-- Deserializer's FSM --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Receiver's state machine: the state machine is divided in three parts (a clocked process
--! to store the current state, a combinatorial process to manage state transitions and finally a
--! combinatorial process to manage the output signals), which are the three processes that follow.
--! The unit starts by following directly the FIELDRIVE input fd_rxd for the identification of
--! the preamble field (PRE), and then switches to following the filtered signal rxd_filtered,
--! until the end of the frame. It is responsible for the detection of the the PRE, FSD and FES
--! of a received ID_DAT or consumed RP_DAT frame.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process Deserializer_FSM_Sync: storage of the current state of the FSM
......@@ -250,23 +232,24 @@ architecture rtl of WF_rx_deserializer is
--!@brief Combinatorial process Deserializer_FSM_Comb_State_Transitions: definition of the state
--! transitions of the FSM.
Deserializer_FSM_Comb_State_Transitions: process (s_bit_r_edge_p, s_edge_outside_manch_window_p,
Deserializer_FSM_Comb_State_Transitions: process (s_bit_r_edge_p, s_edge_out_manch_window_p,
rx_rst_p_i, fd_rxd_f_edge_p_i, s_manch_r_edge_p,
s_fsd_wrong_bit, s_manch_f_edge_p, rx_st,
s_fsd_last_bit, rxd_filtered_f_edge_p_i,
s_fes_detected_p, rst_rx_unit_p_i,
rxd_f_edge_p_i, s_manch_r_edge_p)
s_fsd_last_bit, s_fes_detected_p)
begin
nx_rx_st <= idle;
-- During the PRE, the WF_rx_osc is trying to synchronize to the transmitter's clock and every
-- edge detected in the deglitched FD_RXD is taken into account. At this phase, the unit uses
-- the WF_rx_osc signals adjac_bits_window_i and signif_edge_window_i and if edges are found
-- outside those windows the unit goes back to idle and the WF_rx_osc is reset.
-- For the rest of the frame, the unit is just sampling the deglitched FD_RXD on the moments
-- specified by the WF_rx_osc signals sample_manch_bit_p_i and sample_bit_p_i.
case rx_st is
-- During the PRE, the rx_osc (WF_tx_rx_osc unit) is trying to synchronize to the transmitter's
-- clock and every edge detected in the fd_rxd is taken into account. For the rest of the frame,
-- the unit uses the filtered version of the signal, cleaned of possible glitches.
when idle => -- in idle state until falling
if rxd_f_edge_p_i = '1' then -- edge detection
if fd_rxd_f_edge_p_i = '1' then -- edge detection
nx_rx_st <= pre_field_first_f_edge;
else
......@@ -278,7 +261,7 @@ architecture rtl of WF_rx_deserializer is
if s_manch_r_edge_p = '1' then -- arrival of a "manch."
nx_rx_st <= pre_field_r_edge; -- rising edge
elsif s_edge_outside_manch_window_p = '1' then -- arrival of any other edge
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
......@@ -292,50 +275,38 @@ architecture rtl of WF_rx_deserializer is
-- a rising and a falling edge are
-- expected for the PRE
elsif s_edge_outside_manch_window_p = '1' then -- arrival of any other edge
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
nx_rx_st <= pre_field_r_edge;
end if;
when pre_field_f_edge =>
if s_manch_r_edge_p = '1' then -- arrival of a manch. rising edge
nx_rx_st <= pre_field_r_edge;
elsif s_bit_r_edge_p = '1' then -- arrival of a rising edge between
nx_rx_st <= switch_to_deglitched; -- adjacent bits, signaling the
nx_rx_st <= fsd_field; -- adjacent bits, signaling the
-- beginning of the 1st V+ violation
-- of the FSD
elsif s_edge_outside_manch_window_p = '1' then -- arrival of any other edge
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
nx_rx_st <= pre_field_f_edge;
end if;
-- There is a half-bit-clock period of delay between the rxd and the rxd_filtered (output of the
-- WF_rx_deglitcher) which means that the last falling edge of the PRE of rxd arrives
-- earlier than the one of the rxd_filtered. The state switch_to_deglitched is used for
-- this purpose.
when switch_to_deglitched =>
if rxd_filtered_f_edge_p_i = '1' then
nx_rx_st <= fsd_field;
else
nx_rx_st <= switch_to_deglitched;
end if;
-- For the monitoring of the FSD, the unit is sampling each manch. bit of the incoming
-- filtered signal and it is comparing it to the nominal bit of the FSD (through the signal
-- s_fsd_wrong_bit). If a wrong bit is received, the state machine jumps back to idle,
-- whereas if the complete byte is correctly received, it jumps to the data_fcs_fes_fields state.
-- whereas if the complete byte is correctly received, it jumps to the ctrl_data_fcs_fes_fields
when fsd_field =>
if s_fsd_last_bit = '1' then -- reception of the last(15th)
nx_rx_st <= data_fcs_fes_fields; -- FSD bit
nx_rx_st <= ctrl_data_fcs_fes_fields;-- FSD bit
elsif s_fsd_wrong_bit = '1' then -- wrong bit
nx_rx_st <= idle;
......@@ -346,18 +317,18 @@ architecture rtl of WF_rx_deserializer is
-- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length
-- (not predefined) up to 132 bytes (FSD+Ctrl+PDU_TYPE+LGTH+124 application_data+MPS+FCS+FES).
-- (not predefined) up to 134 bytes (FSS+Ctrl+PDU_TYPE+LGTH+125 application_data+MPS+FCS+FES).
-- The WF_engine_control unit is following the amount of bytes being received and in case
-- their number exceeds the expected one, it activates the signal rst_rx_unit_p_i.
-- Therefore, the Receiver_FSM stays in the data_fcs_fes_fields state until the arrival of a
-- correct FES, or until the arrival of a reset signal from the WF_engine_control.
-- their number exceeds the expected one, it activates the signal rx_rst_p_i.
-- Therefore, the Receiver_FSM stays in the ctrl_data_fcs_fes_fields state until the arrival
-- of a correct FES, or until the arrival of a reset signal from the WF_engine_control.
when data_fcs_fes_fields =>
if (s_fes_detected_p = '1') or (rst_rx_unit_p_i = '1') then
when ctrl_data_fcs_fes_fields =>
if (s_fes_detected_p = '1') or (rx_rst_p_i = '1') then
nx_rx_st <= idle;
else
nx_rx_st <= data_fcs_fes_fields;
nx_rx_st <= ctrl_data_fcs_fes_fields;
end if;
......@@ -382,7 +353,6 @@ architecture rtl of WF_rx_deserializer is
s_idle <= '1';
------------------------------------
s_receiving_pre <= '0';
s_switching_to_deglitched <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
......@@ -392,39 +362,25 @@ architecture rtl of WF_rx_deserializer is
s_idle <= '0';
------------------------------------
s_receiving_pre <= '1';
------------------------------------
s_switching_to_deglitched <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when switch_to_deglitched =>
s_idle <= '0';
s_receiving_pre <= '0';
------------------------------------
s_switching_to_deglitched <= '1';
------------------------------------
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when fsd_field =>
s_idle <= '0';
s_receiving_pre <= '0';
s_switching_to_deglitched <= '0';
------------------------------------
s_receiving_fsd <= '1';
------------------------------------
s_receiving_bytes <= '0';
when data_fcs_fes_fields =>
when ctrl_data_fcs_fes_fields =>
s_idle <= '0';
s_receiving_pre <= '0';
s_switching_to_deglitched <= '0';
s_receiving_fsd <= '0';
------------------------------------
s_receiving_bytes <= '1';
......@@ -435,7 +391,6 @@ architecture rtl of WF_rx_deserializer is
s_idle <= '0';
s_receiving_pre <= '0';
s_switching_to_deglitched <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
......@@ -450,26 +405,27 @@ architecture rtl of WF_rx_deserializer is
--!@brief Synchronous process Append_Bit_To_Byte: creation of bytes of data.
--! A new bit of the (deglitched) input signal is appended to the output byte that is being formed
--! when the Deserializer's FSM is in the "data_fcs_fes_fields" state, on the "sampling of a bit"
--! moments.
--! when the Deserializer's FSM is in the "ctrl_data_fcs_fes_fields" state, on the
--! "sampling of a bit" moments.
Append_Bit_To_Byte: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
byte_ready_p_o <='0';
s_byte_ready_p_d1 <='0';
s_byte <= (others => '0');
else
byte_ready_p_o <= s_byte_ready_p;
s_byte_ready_p_d1 <= s_byte_ready_p;
if s_write_bit_to_byte = '1' then
s_byte <= s_byte(6 downto 0) & rxd_filtered_i;
s_byte <= s_byte(6 downto 0) & fd_rxd_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_write_bit_to_byte <= s_receiving_bytes and sample_bit_p_i;
s_byte_ready_p <= s_receiving_bytes and s_manch_bit_index_is_zero and sample_manch_bit_p_i
......@@ -485,8 +441,8 @@ architecture rtl of WF_rx_deserializer is
--! inside a manch. encoded byte (16 bits).
Incoming_Bits_Index: WF_decr_counter
generic map(g_counter_lgth => 4)
port map(
generic map (g_counter_lgth => 4)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_manch_bit_index_top,
......@@ -497,25 +453,26 @@ architecture rtl of WF_rx_deserializer is
counter_is_zero_o => s_manch_bit_index_is_zero);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FSD aux signals concurrent assignments:
s_fsd_bit <= s_receiving_fsd and c_FSD (to_integer(s_manch_bit_index));
s_fsd_last_bit <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor rxd_filtered_i) and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor fd_rxd_i) and sample_manch_bit_p_i;
-- FES aux signals concurrent assignments :
s_fes_bit <= s_receiving_bytes and c_FES (to_integer(s_manch_bit_index));
s_fes_wrong_bit <= (s_fes_bit xor rxd_filtered_i) and sample_manch_bit_p_i;
s_fes_wrong_bit <= (s_fes_bit xor fd_rxd_i) and sample_manch_bit_p_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Combinatorial process that according to the state of the FSM sets values to the
--! Incoming_Bits_Index inputs.
Bit_Index: process (s_idle,s_receiving_pre, s_switching_to_deglitched, s_receiving_fsd,
s_receiving_bytes, s_manch_bit_index_is_zero,sample_manch_bit_p_i)
Bit_Index: process (s_idle,s_receiving_pre, s_receiving_fsd, s_receiving_bytes,
s_manch_bit_index_is_zero,sample_manch_bit_p_i)
begin
if s_idle ='1' then -- counter re-initialization after a reception
......@@ -523,14 +480,9 @@ architecture rtl of WF_rx_deserializer is
s_manch_bit_index_load <= '1';
s_decr_manch_bit_index_p <= '0';
elsif s_receiving_pre = '1' then -- no action
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load <= '0';
s_decr_manch_bit_index_p <= '0';
elsif s_switching_to_deglitched = '1' then -- preparation for the FSD byte
s_manch_bit_index_top <= to_unsigned(c_FSD'left-1,s_manch_bit_index_top'length);
-- FSD'left-1: bc the 1st bit of the FSD has been covered at the state PRE_field_f_edge
elsif s_receiving_pre = '1' then -- preparation for the FSD byte
s_manch_bit_index_top <= to_unsigned(c_FSD'left-2,s_manch_bit_index_top'length);
-- FSD'left-2: bc the 1st bit of the FSD has been covered at the state PRE_field_f_edge
s_manch_bit_index_load <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_manch_bit_index_p <= '0';
......@@ -554,26 +506,26 @@ architecture rtl of WF_rx_deserializer is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process FES_Detector: The s_arriving_fes register is storing the last 16
--! manch. encoded bits received and the s_fes_detected_p indicates weather they match the FES.
--! manch. encoded bits received and the s_fes_detected_p indicates whether they match the FES.
FES_Detector: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_arriving_fes <= (others =>'0');
else
if s_receiving_bytes = '0' then
s_arriving_fes <= (others =>'0');
elsif s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
s_arriving_fes <= s_arriving_fes (14 downto 0) & rxd_filtered_i;
end if;
s_arriving_fes <= s_arriving_fes (14 downto 0) & fd_rxd_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_fes_detected_p <= '1' when s_arriving_fes = (c_FES) else '0'; -- 1 uclk-wide pulse
-- 1 uclk-wide pulse after the FES detection
s_fes_detected_p <= '1' when (s_arriving_fes = c_FES) and (s_byte_ready_p_d1 = '1') else '0';
---------------------------------------------------------------------------------------------------
......@@ -583,32 +535,33 @@ architecture rtl of WF_rx_deserializer is
--!@brief Instantiation of the CRC calculator unit that verifies the received FCS field.
CRC_Verification : WF_crc
generic map(c_GENERATOR_POLY_length => 16)
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_receiving_fsd,
data_bit_ready_p_i => s_write_bit_to_byte,
data_bit_i => rxd_filtered_i,
data_bit_i => fd_rxd_i,
crc_o => open,
---------------------------------------------------
crc_ok_p => s_CRC_ok_p);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of the WF_rx_manch_code_check unit that checks for manch. code violations.
Manch_Encoding_Verification: WF_rx_manch_code_check
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
serial_input_signal_i => rxd_filtered_i,
serial_input_signal_i => fd_rxd_i,
sample_bit_p_i => sample_bit_p_i,
sample_manch_bit_p_i => sample_manch_bit_p_i,
---------------------------------------------------
manch_code_viol_p_o => s_manch_code_viol_p);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that handles the s_manch_code_viol_p signal: If at any point after
--! the FSS and before the FES a code violation appears, the signal s_manch_not_ok stays
......@@ -617,11 +570,6 @@ architecture rtl of WF_rx_deserializer is
Code_viol: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_manch_not_ok <= '0';
else
if s_receiving_bytes = '0' then -- after the FSS
s_manch_not_ok <= '0';
......@@ -632,43 +580,38 @@ architecture rtl of WF_rx_deserializer is
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that handles the CRC signal: The crc_ok_p coming from the CRC
--! calculator unit is delayed for 15 manch. encoded bits. The matching of this delayed pulse
--! with the end of frame pulse (s_fes_detected_p), would confirm that the two last bytes
--! received before the FES were the correct CRC.
--!@brief Synchronous process that checks the position of the CRC bytes in the frame: the 1 uclk-
--! wide crc_ok_p coming from the CRC calculator is delayed for 1 complete byte. The matching of
--! this delayed pulse with the end of frame pulse (s_fes_detected_p), would confirm that the two
--! last bytes received before the FES were the correct CRC.
CRC_OK_pulse_delay: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_CRC_ok_p_buff <= (others => '0');
s_sample_manch_bit_p_d1 <= '0';
else
s_sample_manch_bit_p_d1 <= sample_manch_bit_p_i; -- delay for the synch of s_crc_ok_p
-- with s_sample_manch_bit_p_d1
if s_receiving_bytes = '0' then
s_CRC_ok_p_buff <= (others => '0');
s_CRC_ok_p_d <= '0';
s_CRC_ok_p_found <= '0';
else
-- a delay is added to s_CRC_ok_p with
if s_sample_manch_bit_p_d1 = '1' then -- each manch. bit arrival. In total 15
-- delays have to be added in order to
-- arrive to the FES.
s_CRC_ok_p_buff <= s_CRC_ok_p_buff(13 downto 0) & s_CRC_ok_p;
if s_CRC_ok_p = '1' then
s_CRC_ok_p_found <= '1';
end if;
if s_byte_ready_p = '1' and s_CRC_ok_p_found = '1' then -- arrival of the next byte
s_CRC_ok_p_d <= '1'; -- (FES normally)
s_CRC_ok_p_found <= '0';
else
s_CRC_ok_p_d <= '0';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_crc_ok_p_d15 <= s_CRC_ok_p_buff(14); -- pulse 1 half-bit-clock period long
......@@ -677,20 +620,21 @@ architecture rtl of WF_rx_deserializer is
---------------------------------------------------------------------------------------------------
-- aux signals concurrent assignments :
s_manch_r_edge_p <= signif_edge_window_i and rxd_r_edge_p_i;
s_manch_f_edge_p <= signif_edge_window_i and rxd_f_edge_p_i;
s_bit_r_edge_p <= adjac_bits_window_i and ( rxd_r_edge_p_i);
s_edge_outside_manch_window_p <= (not signif_edge_window_i)and(rxd_r_edge_p_i or rxd_f_edge_p_i);
s_manch_r_edge_p <= signif_edge_window_i and fd_rxd_r_edge_p_i;
s_manch_f_edge_p <= signif_edge_window_i and fd_rxd_f_edge_p_i;
s_bit_r_edge_p <= adjac_bits_window_i and fd_rxd_r_edge_p_i;
s_edge_out_manch_window_p <= (not signif_edge_window_i)and(fd_rxd_r_edge_p_i or fd_rxd_f_edge_p_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- output signals concurrent assignments :
byte_o <= s_byte;
rst_rx_osc_o <= s_idle;
byte_ready_p_o <= s_byte_ready_p_d1;
rx_osc_rst_o <= s_idle;
fss_received_p_o <= s_receiving_fsd and s_fsd_last_bit;
crc_or_manch_wrong_p_o <= s_fes_detected_p and ((not s_crc_ok_p_d15) or (not s_manch_not_ok));
fss_crc_fes_manch_ok_p_o <= s_fes_detected_p and s_crc_ok_p_d15 and (not s_manch_not_ok);
crc_or_manch_wrong_p_o <= s_fes_detected_p and ((not s_CRC_ok_p_d) or s_manch_not_ok);
fss_crc_fes_manch_ok_p_o <= s_fes_detected_p and s_CRC_ok_p_d and (not s_manch_not_ok);
end architecture rtl;
......
wf_rx_osc.vhd 0 → 100644
View file @ 6ead92d5
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_rx_osc.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_osc --
-- --
---------------------------------------------------------------------------------------------------
--
--! @brief Generation the clock signals needed for the reception (WF_rx_deserializer).
--!
--! Even if the bit rate of the communication is known, jitter is expected to affect the
--! arriving time of the incoming signal. The main idea of the unit is to recalculate
--! the expected arrival time of the next incoming bit, based on the arrival of the
--! previous one, so that drifts are not accumulated. The clock recovery is based on the
--! Manchester 2 coding which ensures that there is one edge (transition) for each bit.
--!
--! In this unit, we refer to
--! o a significant edge : for the edge of a manch. encoded bit (bit 0: _|-, bit 1: -|_)
--! o a transition : for the moment in between two adjacent bits, that may or
--! may not result in an edge (eg. a 0 followed by a 0 will give an edge _|-|_|-,
--! but a 0 followed by a 1 will not _|--|_ ).
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 14/02/2011
--
--
--! @version v0.04
--
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_deglitcher \n
--! WF_rx_deserializer\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 08/2009 v0.01 PS Entity Ports added, start of architecture content \n
--! -> 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned;
--! rx clk generation depends on edge detection;code cleanedup+commented
--! rst_rx_osc signal clearified
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments
--! -> 02/2011 v0.04 EG 2 units WF_rx_osc and WF_tx_osc; process replaced by WF_incr_counter
--
---------------------------------------------------------------------------------------------------
--
--! @todo -->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_rx_osc
--=================================================================================================
entity WF_rx_osc is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_deglitcher unit
fd_rxd_edge_p_i : in std_logic; --! indication of an edge on fd_rxd
-- Signal from WF_rx_deserializer unit
rx_osc_rst_i : in std_logic; --! resets the clock recovery procedure of the rx_osc
-- OUTPUTS
-- Signals to the WF_rx_deserializer
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! o on a significant edge
--! o between adjacent bits
--! ____|-|___|-|___|-|___
rx_bit_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! o between adjacent bits
--! __________|-|_________
rx_signif_edge_window_o : out std_logic; --! time window where a significant edge is expected
rx_adjac_bits_window_o : out std_logic --! time window where a transition between adjacent
--! bits is expected
);
end entity WF_rx_osc;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_rx_osc is
signal s_period_c, s_period, s_jitter : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_half_period, s_one_forth_period : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_counter_reinit, s_counter_is_full : std_logic;
signal s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
signal s_bit_clk, s_bit_clk_d1, s_manch_clk, s_manch_clk_d1 : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
-- # uclock ticks for a bit period, defined by the WorldFIP bit rate
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
s_counter_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
s_half_period <= s_period srl 1; -- 1/2 s_period
s_one_forth_period <= s_period srl 2; -- 1/4 s_period
s_jitter <= s_period srl 3; -- jitter defined as 1/8 s_period
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of a WF_incr_counter unit : the rx_counter starts counting after the
--! release of the reset signal rx_osc_rst_i. This takes place after a falling edge on the
--! deglitched FD_RXD; this edge should be representing the 1st Manchester (manch.) encoded bit '1'
--! of the PREamble. Starting from this edge, other falling or rising significant edges, are
--! expected around one period (s_period) later. A time window around the expected arrival time is
--! set and its length is defined as 1/4th of the period (1/8th before and 1/8th after the expected
--! time). When the actual edge arrives, the counter is reset.
--! If that first falling edge of FD_RXD is finally proven not to belong to a valid PRE (the
--! state machine of the WF_rx_deserializer unit is checking that and generating the rx_osc_rst_i),
--! the counter is reinitialialized.
rx_periods_count: WF_incr_counter
generic map (g_counter_lgth => c_PERIODS_COUNTER_LENGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_counter_reinit,
incr_counter_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if nfip_rst_i is active or
-- if the rx_osc_rst_i is active or
-- if an edge is detected in the expected window or
-- if it fills up
s_counter_reinit <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i) or s_counter_is_full;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process rx_clks: the process rx_clk is following the edges that appear on the
--! nanoFIP FIELDRIVE input fd_rxd and constructs two clock signals: rx_manch_clk & rx_bit_clk.
-- In detail, the process is looking for moments :
-- o of significant edges
-- o between boundary bits
-- the signal rx_manch_clk: is inverted on each significant edge,as well as between adjacent bits
-- the signal rx_bit_clk : is inverted only between adjacent bits
-- The significant edges are normally expected inside the signif_edge_window. In the cases of a
-- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
-- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
-- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
rx_clks: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') then
s_manch_clk <='0';
s_bit_clk <='0';
s_bit_clk_d1 <='0';
s_manch_clk_d1 <='0';
s_signif_edge_found <='0';
s_adjac_bits_edge_found <='0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding significant edges:
-- looking for a significant edge inside the corresponding window
if (s_signif_edge_window = '1') and (fd_rxd_edge_p_i = '1') and (s_signif_edge_found = '0') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
-- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_period_c = s_jitter) then
s_manch_clk <= not s_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
-- next cycle
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding edges between adjacent bits:
-- looking for an edge inside the corresponding window
elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_bit_clk <= not s_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
s_signif_edge_found <= '0'; -- re-initialization before next cycle
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_jitter) then
s_manch_clk <= not s_manch_clk;
s_bit_clk <= not s_bit_clk;
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_clk_d1 <= s_manch_clk;
-- s_manch_clk: ____|-----|_____|-----|____
-- s_manch_clk_d1: ______|-----|_____|-----|__
-- rx_manch_clk_p_o: ____|-|___|-|___|-|___|-|__
s_bit_clk_d1 <= s_bit_clk;
-- s_bit_clk: ____|-----------|___________
-- s_bit_clk_d1: ______|-----------|_________
-- rx_bit_clk_p_o: ____|-|_________|-|_________
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
--!@brief Concurrent signal assignments: creation of the windows where
--! "significant edges" and "adjacent bits transitions" are expected on the input signal.
--! o s_signif_edge_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! the completion of a period, where significant edges are expected.
--! o s_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! the middle of a period, where transitions between adjacent bits are expected.
s_signif_edge_window <= '1' when ((s_period_c < s_jitter) or
(s_period_c > s_period-1 - s_jitter-1))
else '0';
s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_jitter-1) and
(s_period_c < s_half_period+s_jitter))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output signals concurrent assignments
rx_manch_clk_p_o <= s_manch_clk_d1 xor s_manch_clk; -- a 1 uclk-wide pulse, after
-- o a significant edge
-- o a new bit
-- ___|-|___|-|___|-|___
rx_bit_clk_p_o <= s_bit_clk xor s_bit_clk_d1; -- a 1 uclk-wide pulse, after
-- o a new bit
-- _________|-|_________
rx_signif_edge_window_o <= s_signif_edge_window;
rx_adjac_bits_window_o <= s_adjac_bits_window;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_status_bytes_gen.vhd
View file @ 6ead92d5
......@@ -127,13 +127,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Synplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL189 Register bits s_nFIP_status_byte(0), s_nFIP_status_byte(1) are always 0, optimizing" --
-- "W CL260 Pruning Register bits 0 and 1 of s_nFIP_status_byte(7 downto 0)" --
-- Bits 0 and 1 of nanoFIP status byte are reserved for future ideas. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -143,21 +136,21 @@ entity WF_status_bytes_gen is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz Clock
slone_i : in std_logic; --! stand-alone mode
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanaoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk)
fd_txer_i : in std_logic; --! transmitter error
fd_wdgn_i : in std_logic; --! watchdog on transmitter
-- nanoFIP FIELDRIVE
fd_txer_a_i : in std_logic; --! transmitter error
fd_wdgn_a_i : in std_logic; --! watchdog on transmitter
-- nanoFIP User Interface, NON-WISHBONE (synchronized with uclk)
var1_acc_i : in std_logic; --! variable 1 access
var2_acc_i : in std_logic; --! variable 2 access
var3_acc_i : in std_logic; --! variable 3 access
-- nanoFIP User Interface, NON-WISHBONE
var1_acc_a_i : in std_logic; --! variable 1 access
var2_acc_a_i : in std_logic; --! variable 2 access
var3_acc_a_i : in std_logic; --! variable 3 access
-- Signals from the WF_consumption unit
nfip_status_r_fcser_p_i : in std_logic; --! wrong CRC bytes received
......@@ -196,6 +189,7 @@ signal s_refreshment
signal s_nFIP_status_byte : std_logic_vector (7 downto 0);
signal s_var1_rdy_incr_c, s_var1_rdy_extended : std_logic;
signal s_var2_rdy_incr_c, s_var2_rdy_extended, s_var3_rdy_incr_c, s_var3_rdy_extended : std_logic;
signal s_fd_txer_synch, s_fd_wdgn_synch, s_var1_acc_synch, s_var2_acc_synch, s_var3_acc_synch : std_logic_vector (2 downto 0);
signal s_var1_rdy_c, s_var2_rdy_c, s_var3_rdy_c : unsigned (3 downto 0);
......@@ -204,6 +198,44 @@ signal s_var1_rdy_c, s_var2_rdy_c, s_var3_rdy_c : unsi
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FD_TXER, FD_WDGN, VARx_ACC Synchronizers --
---------------------------------------------------------------------------------------------------
FIELDRIVE_inputs_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fd_wdgn_synch <= (others => '0');
s_fd_txer_synch <= (others => '0');
else
s_fd_wdgn_synch <= s_fd_wdgn_synch (1 downto 0) & fd_wdgn_a_i;
s_fd_txer_synch <= s_fd_txer_synch (1 downto 0) & fd_txer_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var1_acc_synch <= (others => '0');
s_var2_acc_synch <= (others => '0');
s_var3_acc_synch <= (others => '0');
else
s_var1_acc_synch <= s_var1_acc_synch(1 downto 0) & var1_acc_a_i;
s_var2_acc_synch <= s_var2_acc_synch(1 downto 0) & var2_acc_a_i;
s_var3_acc_synch <= s_var3_acc_synch(1 downto 0) & var3_acc_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- MPS status byte --
---------------------------------------------------------------------------------------------------
......@@ -222,7 +254,7 @@ begin
if rst_status_bytes_p_i = '1' then -- bit reinitialized after a var production
s_refreshment <= '0';
elsif (var3_acc_i = '1') then -- indication that the memory has been accessed
elsif (var3_acc_a_i = '1') then -- indication that the memory has been accessed
s_refreshment <= '1';
end if;
......@@ -279,8 +311,8 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_cacer
if ((s_var1_rdy_extended = '0' and var1_acc_i = '1') or
(s_var2_rdy_extended = '0' and var2_acc_i = '1')) then
if ((s_var1_rdy_extended = '0' and s_var1_acc_synch(2) = '1') or
(s_var2_rdy_extended = '0' and s_var2_acc_synch(2) = '1')) then
-- since the last time the status
-- byte was delivered,
s_nFIP_status_byte(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cons.
......@@ -290,7 +322,7 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_pacer
if (s_var3_rdy_extended = '0' and var3_acc_i = '1') then
if (s_var3_rdy_extended = '0' and s_var3_acc_synch(2) = '1') then
-- since the last time the status
s_nFIP_status_byte(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
-- the user logic accessed a prod.
......@@ -300,14 +332,14 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_wder
if (fd_wdgn_i = '0') then -- FIELDRIVE transmission error
if (s_fd_wdgn_synch(2) = '0') then -- FIELDRIVE transmission error
s_nFIP_status_byte(c_T_WDER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_rxer
if (fd_txer_i = '1') then -- FIELDRIVE watchdog timer problem
if (s_fd_txer_synch(2) = '1') then -- FIELDRIVE watchdog timer problem
s_nFIP_status_byte(c_T_TXER_INDEX) <= '1';
end if;
......@@ -337,9 +369,8 @@ end process;
Extend_VAR1_RDY: WF_incr_counter -- VAR1_RDY : __|---...---|___________________
generic map (g_counter_lgth => 4) -- s_var1_rdy_extended : __|---...------------------|____
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => var1_rdy_i,
incr_counter_i => s_var1_rdy_incr_c,
counter_is_full_o => open,
......@@ -353,9 +384,8 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR2_RDY: WF_incr_counter
generic map (g_counter_lgth => 4)
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => var2_rdy_i,
incr_counter_i => s_var2_rdy_incr_c,
counter_is_full_o => open,
......@@ -369,9 +399,8 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR3_RDY: WF_incr_counter
generic map (g_counter_lgth => 4)
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => VAR3_RDY_i,
incr_counter_i => s_var3_rdy_incr_c,
counter_is_full_o => open,
......
wf_tx_osc.vhd 0 → 100644
View file @ 6ead92d5
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_tx_osc.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx_osc --
-- --
---------------------------------------------------------------------------------------------------
--
--! @brief Generation the clock signals needed for the transmission (WF_tx_serializer)\n
--!
--! The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock)
--! and the nanoFIP internal signal tx_clk_p_buff:
--!
--! FD_TXCK : ___|--------...--------|________...________|--------...--------|_
--! tx_clk_p_buff(3) : |0|0|0|1 |0|0|0|1
--! tx_clk_p_buff(2) : |0|0|1|0 |0|0|1|0
--! tx_clk_p_buff(1) : |0|1|0|0 |0|1|0|0
--! tx_clk_p_buff(0) : |1|0|0|0 |1|0|0|0
--!
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 14/02/2011
--
--
--! @version v0.04
--
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 08/2009 v0.01 PS Entity Ports added, start of architecture content \n
--! -> 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned;
--! c_TX_CLK_BUFF_LGTH got 1 bit more\n
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_rst_p_i
--
---------------------------------------------------------------------------------------------------
--
--! @todo -->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_tx_osc
--=================================================================================================
entity WF_tx_osc is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control
tx_rst_p_i : in std_logic; --! transmitter timeout
-- OUTPUTS
-- nanoFIP FIELDRIVE output
tx_clk_o : out std_logic; --! line driver half bit clock
-- Signal to the WF_tx_serializer unit
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0)
--! buffer keeping the last values of tx_clk_o
);
end entity WF_tx_osc;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_tx_osc is
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LENGTH -1 downto 0);
signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LENGTH -1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p, s_counter_is_full, s_reinit_counter : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclock ticks for a
-- transmission period
s_one_forth_period <= s_period srl 2; -- 1/4 s_period
s_counter_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of a WF_incr_counter counting transmission periods.
tx_periods_count: WF_incr_counter
generic map (g_counter_lgth => c_PERIODS_COUNTER_LENGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_reinit_counter,
incr_counter_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- if the tx_rst_p_i is active or
-- if it fills up
s_reinit_counter <= nfip_rst_i or tx_rst_p_i or s_counter_is_full;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Clocks Constraction: Concurrent signals assignments and a synchronous process that use
--! the s_period_c to construct the tx_clk_o clock and the buffer of pulses tx_clk_p_buff_o.
-- Creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_period_c < s_one_forth_period) or
((s_period_c > (2*s_one_forth_period)-1) and
(s_period_c < 3*s_one_forth_period)))
else '0';
-- transm. period : _|----------|__________|--
-- tx_counter : 0 1/4 1/2 3/4 1
-- s_tx_clk : _|----|_____|----|_____|--
-- Creation of a pulse starting 1 uclk period before tx_clk_o
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk : __|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1 : ____|-----|_____|-----|___
-- not s_tx_clk_d1 : ----|_____|-----|_____|---
-- s_tx_clk_p : __|-|___|-|___|-|___|-|___
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_Signals_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_tx_clk_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left-1 downto 0) & s_tx_clk_p;
-- buffering of the s_tx_clk_p pulses
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Output signals assignments
tx_clk_o <= s_tx_clk_d1;
tx_clk_p_buff_o <= s_tx_clk_p_buff;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_tx_serializer.vhd
View file @ 6ead92d5
......@@ -31,7 +31,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @brief The unit is generating the nanoFIP FIELDRIVE outputs FD_TXD and FD_TXENA. It is
--! retreiving bytes of data from:
--! o the WF_prod_bytes_retriever (from the Ctrl until the MPS)
--! o the WF_production (from the Ctrl until the MPS)
--! o WF_package (FSS, FES)
--! o and the WF_CRC (CRC bytes).
--! It encodes the bytes to the Manchester 2 scheme and outputs one by one the encoded
......@@ -51,7 +51,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
--!
--! |--------- Bytes from the WF_prod_bytes_retriever -------|
--! |------------- Bytes from the WF_production -------------|
--!
--
--
......@@ -68,8 +68,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Dependencies:</b> \n
--! WF_engine_control \n
--! WF_prod_bytes_retriever \n
--! WF_rx_tx_osc \n
--! WF_production \n
--! WF_tx_osc \n
--! WF_reset_unit \n
--
--
......@@ -86,8 +86,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! renamed from tx to tx_serializer;
--! stop_transmission state added for the synch of txena
--! -> v0.04 01/2011 EG sync_to_txck state added to start always with the bits 1,2,3 of the
--! clock buffer available(start_prod_p_i may arrive at any time)
--! clock buffer available(tx_start_p_i may arrive at any time)
--
---------------------------------------------------------------------------------------------------
--
......@@ -100,24 +99,24 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Entity declaration for WF_tx_serializer
--=================================================================================================
entity WF_tx_serializer is
generic (c_TX_CLK_BUFF_LGTH: natural);
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_prod_bytes_retriever
byte_i : in std_logic_vector (7 downto 0); --! data byte to be delivered
-- Signals from the WF_production
byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
-- Signals from the WF_engine_control
start_prod_p_i : in std_logic; --! indication for the start of the production
tx_rst_p_i : in std_logic;
tx_start_p_i : in std_logic; --! indication for the start of the production
byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
-- Signal from the WF_rx_tx_osc
-- Signal from the WF_tx_osc
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
--! clk for the transmission synchronization
......@@ -146,12 +145,12 @@ architecture rtl of WF_tx_serializer is
signal tx_state, nx_tx_state : tx_state_t;
signal s_prepare_to_produce, s_sending_fss, s_sending_data, s_sending_crc : std_logic;
signal s_sending_fes, s_start_crc_p, s_data_bit_to_crc_p, s_stop_transmission : std_logic;
signal s_sending_fes, s_stop_transmission, s_start_crc_p, s_data_bit_to_crc_p : std_logic;
signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero, s_tx_enable : std_logic;
signal s_bit_index, s_bit_index_top : unsigned(4 downto 0);
signal s_bit_index, s_bit_index_top : unsigned (4 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_crc_bytes_manch : std_logic_vector(31 downto 0);
signal s_crc_bytes,s_data_byte_manch : std_logic_vector(15 downto 0);
signal s_crc_bytes_manch : std_logic_vector (31 downto 0);
signal s_crc_bytes, s_data_byte_manch : std_logic_vector (15 downto 0);
--=================================================================================================
......@@ -215,14 +214,14 @@ begin
--! transitions of the FSM
Serializer_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
start_prod_p_i, tx_clk_p_buff_i)
tx_rst_p_i, tx_start_p_i, tx_clk_p_buff_i)
begin
nx_tx_state <= idle;
case tx_state is
when idle =>
if start_prod_p_i = '1' then
if tx_start_p_i = '1' then
nx_tx_state <= sync_to_txck;
else
nx_tx_state <= idle;
......@@ -232,6 +231,10 @@ begin
when sync_to_txck =>
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4) = '1' then
nx_tx_state <= send_fss;
elsif tx_rst_p_i = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= sync_to_txck;
end if;
......@@ -240,6 +243,10 @@ begin
when send_fss =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1' then
nx_tx_state <= send_data_byte;
elsif tx_rst_p_i = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= send_fss;
end if;
......@@ -248,6 +255,10 @@ begin
when send_data_byte =>
if last_byte_p_i = '1' then
nx_tx_state <= send_crc_bytes;
elsif tx_rst_p_i = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= send_data_byte;
end if;
......@@ -256,22 +267,37 @@ begin
when send_crc_bytes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= send_fes; -- state change early enough (tx_clk_p_buff_i(2))
else -- for the Outgoing_Bits_Index, that is loaded on
nx_tx_state <= send_crc_bytes;-- tx_clk_p_buff_i(3), to get the 31 as top value
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_clk_p_buff_i(3), to get the 31 as top value
elsif tx_rst_p_i = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= send_crc_bytes;
end if;
when send_fes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= stop_transmission; -- state change early enough (tx_clk_p_buff_i(2))
else -- for the Outgoing_Bits_Index that is loaded on
nx_tx_state <= send_fes; -- tx_clk_p_buff_i(3) to get the 15 as top value
-- for the Outgoing_Bits_Index that is loaded on
-- tx_clk_p_buff_i(3) to get the 15 as top value
elsif tx_rst_p_i = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= send_fes;
end if;
when stop_transmission =>
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= idle;
elsif tx_rst_p_i = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= stop_transmission;
end if;
......@@ -404,24 +430,8 @@ Input_Byte_Retrieval: process (uclk_i)
-- Manchester Encoding --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--@brief Instantiation of a manchester encoder for a data byte (8 bits long)
data_byte_manc_encoder: WF_manch_encoder
generic map(word_length => 8)
port map(
word_i => s_byte,
word_manch_o => s_data_byte_manch
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--@brief Instantiation of a manchester encoder for the CRC bytes (16 bits long)
crc_bytes_manc_encoder: WF_manch_encoder
generic map(word_length => 16)
port map(
word_i => s_crc_bytes,
word_manch_o => s_crc_bytes_manch
);
s_data_byte_manch <= f_manch_encoder (s_byte);
s_crc_bytes_manch <= f_manch_encoder (s_crc_bytes);
......@@ -431,18 +441,18 @@ crc_bytes_manc_encoder: WF_manch_encoder
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Instantiation of the CRC unit
crc_generation: WF_crc
generic map(
c_GENERATOR_POLY_length => 16)
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
crc_o => s_crc_bytes,
crc_ok_p => open);
crc_ok_p => open,
-------------------------------------------------
crc_o => s_crc_bytes);
-------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- concurrent signals assignement for the crc_generator inputs
......@@ -465,8 +475,8 @@ crc_bytes_manc_encoder: WF_manch_encoder
--! CRC or a FES byte.
Outgoing_Bits_Index: WF_decr_counter
generic map(g_counter_lgth => 5)
port map(
generic map (g_counter_lgth => 5)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_bit_index_top,
......@@ -531,7 +541,7 @@ crc_bytes_manc_encoder: WF_manch_encoder
--! The unit also generates the tx_enable_o signal.
bits_to_txd: WF_bits_to_txd
port map(
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
txd_bit_index_i => s_bit_index,
......
wf_wb_controller.vhd
View file @ 6ead92d5
......@@ -81,13 +81,10 @@ entity WF_wb_controller is
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
wb_rst_i : in std_logic; --! WISHBONE reset
wb_stb_i : in std_logic; --! WISHBONE strobe
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_stb_r_edge_p_i : in std_logic; --! rising edge on WISHBONE strobe
--! 1 wb-clk wide pulse
wb_we_i : in std_logic; --! WISHBONE write enable
wb_adr_id_i : in std_logic_vector (2 downto 0);--! 3 first bits of WISHBONE address
wb_adr_id_i : in std_logic_vector (2 downto 0); --! 3 first bits of WISHBONE address
-- OUTPUTS
......@@ -108,36 +105,64 @@ end entity WF_wb_controller;
--=================================================================================================
architecture rtl of WF_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p : std_logic;
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_stb_r_edge_p : std_logic;
signal s_wb_we_d3, s_wb_cyc_d3 : std_logic_vector (2 downto 0);
signal s_wb_stb_d4 : std_logic_vector (3 downto 0);
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
--!@brief Triple buffering of the WISHBONE control signals: stb, cyc, we.
WISHBONE_inputs_synchronization: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_stb_d4 <= (others => '0');
s_wb_cyc_d3 <= (others => '0');
s_wb_we_d3 <= (others => '0');
else
s_wb_stb_d4 <= s_wb_stb_d4 (2 downto 0) & wb_stb_i;
s_wb_cyc_d3 <= s_wb_cyc_d3 (1 downto 0) & wb_cyc_i;
s_wb_we_d3 <= s_wb_we_d3 (1 downto 0) & wb_we_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_wb_stb_r_edge_p <= (not s_wb_stb_d4(3)) and s_wb_stb_d4(2);
---------------------------------------------------------------------------------------------------
--!@brief Generate_wb_ack_write_p_o: Generation of the wb_ack_write_p signal
--! (acknowledgement from WISHBONE Slave of the write cycle, as a response to the master's storbe).
--! The 1 wb_clk-wide pulse is generated if the wb_cyc and wb_we are asserted and the WISHBONE input
--! address corresponds to an address in the Produced memory block.
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_id_i = "010") and
(wb_we_i = '1') and
(wb_cyc_i = '1'))
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_d3 (2) = '1') and
(s_wb_cyc_d3(2) = '1') and
(wb_adr_id_i = "010"))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
--!@brief Generate_wb_ack_read_p: Generation of the wb_ack_read_p signal
--! (acknowledgement from WISHBONE Slave of the read cycle, as a response to the master's strobe).
--! The 1 wb_clk-wide pulse is generated if the wb_cyc is asserted and the WISHBONE input address
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_id_i(2 downto 1) = "00") and
(wb_cyc_i = '1'))
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_cyc_d3(2) = '1') and
(s_wb_we_d3(2) = '0') and
(wb_adr_id_i(2 downto 1) = "00"))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
--!@brief Output_Register
WB_ACK: process (wb_clk_i)
......
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