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nanoFIP - Gateware
Commit 7676925e authored by egousiou's avatar egousiou
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comments mainly; wf_reset_unit: added s_rstin_c_is_full, s_var_rst_c_is_full as… 

comments mainly; wf_reset_unit: added s_rstin_c_is_full, s_var_rst_c_is_full as additional way to reset FSMs

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@241 7f0067c9-7624-46c7-bd39-3fb5400c0213
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dualram_512x8.vhd
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......@@ -100,23 +100,23 @@ architecture RAM4K9 of dualram_512x8 is
-- read with both ports simultaneously. Moreover, reading from one port while writing to the other
-- is possible.
-- WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1 :
-- WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1:
-- Aspect ratio configuration.
-- WENA, WENB :
-- WENA, WENB:
-- Switching between Read and Write modes for the respective ports.
-- A Low indicates Write operation and a High indicates a Read.
-- BLKA, BLKB :
-- BLKA, BLKB:
-- Active low enable for the respective ports.
-- PIPEA, PIPEB :
-- PIPEA, PIPEB:
-- Control of the optional pipeline stages.
-- A Low on the PIPEA or PIPEB indicates a non-pipelined Read and the data appears on the output
-- in the same clock cycle.
-- A High indicates a pipelined Read and data appears on the output in the next clock cycle.
-- WMODEA, WMODEB :
-- WMODEA, WMODEB:
-- Configuration of the behavior of the output when the RAM is in the Write mode.
-- A Low on this signal makes the output retain data from the previous Read. A High indicates a
-- pass-through behavior where the data being written will appear on the output immediately.
......@@ -175,12 +175,12 @@ begin
---------------------------------------------------------------------------------------------------
-- Instantiation of the component RAM4K9.
-- The following configuration has been applied:
-- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
-- o word width : 8 bits (DINA8, DINB8: GND, DOUTA8, DOUTB8 : open)
-- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9 : GND)
-- o BLKA, BLKB : GND (ports enabled)
-- o PIPEA, PIPEB : GND (not pipelined read)
-- o WMODEA, WMODEB : GND (in write mode the output retains the data from the previous read)
-- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
-- o word width : 8 bits (DINA8, DINB8: GND; DOUTA8, DOUTB8 : open)
-- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GND)
-- o BLKA, BLKB : GND (ports enabled)
-- o PIPEA, PIPEB : GND (not pipelined read)
-- o WMODEA, WMODEB: GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
......
nanofip.vhd
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wf_cons_bytes_processor.vhd
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wf_cons_outcome.vhd
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wf_consumption.vhd
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wf_crc.vhd
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......@@ -7,21 +7,24 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_crc |
-- wf_crc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_crc.vhd |
-- File wf_crc.vhd |
-- |
-- Description The unit creates the modules for: |
-- o the generation of the CRC of serial data, |
-- o the verification of an incoming CRC syndrome. |
-- The unit is instantiated in both the wf_fd_transmitter, for the generation of the |
-- FCS field of produced RP_DAT frames, and the wf_fd_receiver for the validation of |
-- of an incoming ID_DAT or consumed RP_DAT frame. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Date 23/02/2011 |
-- Version v0.04 |
-- Depends on WF_reset_unit |
-- WF_rx_deserializer |
-- WF_tx_serializer |
-- Depends on wf_reset_unit |
-- wf_rx_deserializer |
-- wf_tx_serializer |
---------------- |
-- Last changes |
-- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content |
......@@ -58,40 +61,40 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_crc
-- Entity declaration for wf_crc
--=================================================================================================
entity WF_crc is port(
entity wf_crc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the WF_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the WF_rx_deserializer/ WF_tx_serializer units
-- Signals from the wf_rx_deserializer/ wf_tx_serializer units
data_bit_i : in std_logic; -- incoming data bit stream
data_bit_ready_p_i : in std_logic; -- indicates the sampling moment of data_bit_i
start_crc_p_i : in std_logic; -- beginning of the CRC calculation
-- OUTPUTS
-- Signal to the WF_rx_deserializer unit
-- Signal to the wf_rx_deserializer unit
crc_ok_p_o : out std_logic; -- signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit
-- Signal to the wf_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)); -- calculated CRC
end entity WF_crc;
end entity wf_crc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_crc is
architecture rtl of wf_crc is
signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);
......@@ -154,9 +157,9 @@ begin
---------------------------------------------------------------------------------------------------
-- During reception, the CRC is being calculated as data is arriving (same as in the transmission)
-- and it is being compared to the predefined c_CRC_VERIF_POLY. When the CRC calculated from the
-- received data matches the c_CRC_VERIF_POLY, it is implied that a correct CRC word has been
-- and at the same time it is being compared to the predefined c_CRC_VERIF_POLY. When the CRC
-- calculated from the received data matches the c_CRC_VERIF_POLY, it is implied that a correct CRC
-- word has been received for the preceded data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
crc_ok_p_o <= data_bit_ready_p_i when s_q = not c_CRC_VERIF_POLY else '0';
......
wf_decr_counter.vhd
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......@@ -7,20 +7,22 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_decr_counter |
-- wf_decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_decr_counter.vhd |
-- File wf_decr_counter.vhd |
-- Description Decreasing counter with synchronous reset, load enable and decrease enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/2010 |
-- Version v0.01 |
-- Depends on WF_reset_unit |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 10/2010 EG v0.01b initial value after reset is all '1' not all '0' |
-- 10/2011 EG v0.01b nfip_rst_i renamed to counter_rst_i; counter_top renamed to |
-- counter_top_i; initial value after reset is all '1'; |
-- counter_decr_p_i renamed to counter_decr_i |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -48,27 +50,27 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_decr_counter
-- Entity declaration for wf_decr_counter
--=================================================================================================
entity WF_decr_counter is
entity wf_decr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_reset_unit
counter_rst_i : in std_logic; -- resets counter to all '1'
-- Signals from any unit
counter_decr_p_i : in std_logic; -- decrement enable
counter_load_i : in std_logic; -- load enable
counter_top : in unsigned (g_counter_lgth-1 downto 0); -- load value
counter_decr_i : in std_logic; -- decrement enable
counter_load_i : in std_logic; -- load enable; loads counter to counter_top_i
counter_top_i : in unsigned (g_counter_lgth-1 downto 0); -- load value
-- OUTPUTS
......@@ -76,13 +78,13 @@ entity WF_decr_counter is
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_zero_o : out std_logic); -- empty counter indication
end entity WF_decr_counter;
end entity wf_decr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_decr_counter is
architecture rtl of wf_decr_counter is
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
......@@ -100,14 +102,14 @@ begin
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if counter_rst_i = '1' then
s_counter <= (others => '1');
else
if counter_load_i = '1' then
s_counter <= counter_top;
s_counter <= counter_top_i;
elsif counter_decr_p_i = '1' then
elsif counter_decr_i = '1' then
s_counter <= s_counter - 1;
end if;
......
wf_dualram_512x8_clka_rd_clkb_wr.vhd
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......@@ -8,19 +8,19 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_dualram_512x8_clka_rd_clkb_wr |
-- wf_dualram_512x8_clka_rd_clkb_wr |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_dualram_512x8_clka_rd_clkb_wr.vhd |
-- File wf_dualram_512x8_clka_rd_clkb_wr.vhd |
-- |
-- Description The unit takes the complete dual port 512x8 memory and disables writing from one |
-- side and reading from the other. Finally from port A only reading is possible |
-- Description The unit adds a layer over the dual port 512x8 memory, by disabling writing from |
-- one side and reading from the other. Finally from port A only reading is possible |
-- and from port B only writing. |
-- Commented in the unit is the memory triplication. Precision RadTol makes the |
-- triplication automatically; in Synplify the comments have to be removed. With the |
-- triplication each incoming byte is written at the same position in the three |
-- memories, whereas each outgoing one is the outcome of a majority voter. |
-- |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
......@@ -59,14 +59,14 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_dualram_512x8_clka_rd_clkb_wr
-- Entity declaration for wf_dualram_512x8_clka_rd_clkb_wr
--=================================================================================================
entity WF_dualram_512x8_clka_rd_clkb_wr is port(
entity wf_dualram_512x8_clka_rd_clkb_wr is port(
-- INPUTS
-- Inputs concerning port A
clk_porta_i : in std_logic;
......@@ -83,13 +83,13 @@ entity WF_dualram_512x8_clka_rd_clkb_wr is port(
-- Output concerning port A
data_porta_o : out std_logic_vector (7 downto 0));
end WF_dualram_512x8_clka_rd_clkb_wr;
end wf_dualram_512x8_clka_rd_clkb_wr;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture syn of WF_dualram_512x8_clka_rd_clkb_wr is
architecture syn of wf_dualram_512x8_clka_rd_clkb_wr is
signal s_one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
......
wf_engine_control.vhd
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wf_fd_receiver.vhd
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wf_fd_transmitter.vhd
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wf_incr_counter.vhd
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......@@ -7,15 +7,16 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_incr_counter |
-- wf_incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_incr_counter.vhd |
-- Description Increasing counter with synchronous reset, reinitialise and increase enable |
-- File wf_incr_counter.vhd |
-- Description Increasing counter with synchronous reinitialise and increase enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2011 |
-- Version v0.011 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
......@@ -47,23 +48,23 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_incr_counter
-- Entity declaration for wf_incr_counter
--=================================================================================================
entity WF_incr_counter is
generic(g_counter_lgth : natural := 4); -- default length
entity wf_incr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signals from any unit
incr_counter_i : in std_logic; -- increment enable
reinit_counter_i : in std_logic; -- reinitializes counter to 0
counter_incr_i : in std_logic; -- increment enable
counter_reinit_i : in std_logic; -- reinitializes counter to 0
-- OUTPUT
......@@ -71,13 +72,13 @@ entity WF_incr_counter is
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic); -- counter full indication
-- (all bits to '1')
end entity WF_incr_counter;
end entity wf_incr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_incr_counter is
architecture rtl of wf_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
......@@ -95,10 +96,10 @@ begin
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if reinit_counter_i = '1' then
if counter_reinit_i = '1' then
s_counter <= (others => '0');
elsif incr_counter_i = '1' then
elsif counter_incr_i = '1' then
s_counter <= s_counter + 1;
end if;
......
wf_jtag_controller.vhd
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wf_model_constr_decoder.vhd
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......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_model_constr_decoder |
-- wf_model_constr_decoder |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_model_constr_decoder.vhd |
-- File wf_model_constr_decoder.vhd |
-- |
-- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. |
-- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1 |
......@@ -26,7 +26,7 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 21/01/2011 |
-- Version v0.03 |
-- Depends on WF_reset_unit |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 11/09/2009 v0.01 PAS First version |
......@@ -63,18 +63,18 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_model_constr_decoder
-- Entity declaration for wf_model_constr_decoder
--=================================================================================================
entity WF_model_constr_decoder is port(
entity wf_model_constr_decoder is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 Mhz clock
-- Signal from the WF_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP WorldFIP Settings (synchronised with uclk_i)
......@@ -86,17 +86,17 @@ entity WF_model_constr_decoder is port(
-- nanoFIP WorldFIP Settings output
s_id_o : out std_logic_vector (1 downto 0); -- Identification selection
-- Signal to the WF_prod_bytes_retriever unit
-- Signal to the wf_prod_bytes_retriever unit
constr_id_dec_o : out std_logic_vector (7 downto 0); -- Constructor identification decoded
model_id_dec_o : out std_logic_vector (7 downto 0));-- Model identification decoded
end entity WF_model_constr_decoder;
end entity wf_model_constr_decoder;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_model_constr_decoder is
architecture rtl of wf_model_constr_decoder is
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
......@@ -157,14 +157,14 @@ begin
---------------------------------------------------------------------------------------------------
-- Instantiation of a counter WF_incr_counter
-- Instantiation of a counter wf_incr_counter
Free_Counter: WF_incr_counter
Free_Counter: wf_incr_counter
generic map(g_counter_lgth => 2)
port map(
uclk_i => uclk_i,
reinit_counter_i => nfip_rst_i,
incr_counter_i => '1',
counter_reinit_i => nfip_rst_i,
counter_incr_i => '1',
counter_is_full_o => open,
-----------------------------------------
counter_o => s_counter);
......
wf_package.vhd
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wf_prod_bytes_retriever.vhd
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wf_prod_data_lgth_calc.vhd
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......@@ -7,27 +7,27 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_prod_data_lgth_calc |
-- wf_prod_data_lgth_calc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_prod_data_lgth_calc.vhd |
-- File wf_prod_data_lgth_calc.vhd |
-- |
-- Description Calculation of the number of bytes, after the FSS and before the FCS, that have to|
-- be transferred when a variable is produced (var_pres, var_identif, var_3, var_jc3)|
-- In detail, the unit adds-up: |
-- be transferred when a variable is produced (var_pres, var_identif, var_3, var_5) |
-- As the following figure indicates, in detail, the unit adds-up: |
-- o 1 byte RP_DAT.CTRL, |
-- o 1 byte RP_DAT.Data.PDU_TYPE, |
-- o 1 byte RP_DAT.Data.LGTH, |
-- o 1-124 RP_DAT.Data.User_Data bytes according to the variable type: |
-- - var_pres: 5 bytes |
-- - var_pres: 8 bytes |
-- - var_jc3 : 1 byte |
-- - var_5 : 1 byte |
-- - var_3 : 2-124 bytes defined by the "nanoFIP User Interface,General signal"|
-- SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH |
-- o 1 byte RP_DAT.Data.nanoFIP_status, always for a var_jc3 |
-- SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH, |
-- o 1 byte RP_DAT.Data.nanoFIP_status, always for a var_5 |
-- and for a var_3, if the "nanoFIP User |
-- Interface General signal" NOSTAT is negated|
-- o 1 byte RP_DAT.Data.MPS_status, for a var_jc3 and a var_3 |
-- Interface General signal"NOSTAT is negated,|
-- o 1 byte RP_DAT.Data.MPS_status, for a var_3 and a var_5 |
-- |
-- |
-- Reminder: |
......@@ -44,7 +44,7 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 09/12/2010 |
-- Version v0.02 |
-- Depends on WF_engine_control |
-- Depends on wf_engine_control |
---------------- |
-- Last changes |
-- 12/2010 v0.02 EG code cleaned-up+commented |
......@@ -75,19 +75,19 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_prod_data_lgth_calc
-- Entity declaration for wf_prod_data_lgth_calc
--=================================================================================================
entity WF_prod_data_lgth_calc is port(
entity wf_prod_data_lgth_calc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the WF_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP WorldFIP Settings
......@@ -97,21 +97,21 @@ entity WF_prod_data_lgth_calc is port(
nostat_i : in std_logic; -- if negated, nFIP status is sent
slone_i : in std_logic; -- stand-alone mode
-- Signal from the WF_engine_control unit
-- Signal from the wf_engine_control unit
var_i : in t_var; -- variable type that is being treated
-- OUTPUT
-- Signal to the WF_engine_control and WF_production units
-- Signal to the wf_engine_control and wf_production units
prod_data_lgth_o : out std_logic_vector (7 downto 0));
end entity WF_prod_data_lgth_calc;
end entity wf_prod_data_lgth_calc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture behavior of WF_prod_data_lgth_calc is
architecture behavior of wf_prod_data_lgth_calc is
signal s_prod_data_lgth, s_p3_lgth_decoded : unsigned (7 downto 0);
......@@ -124,8 +124,9 @@ begin
---------------------------------------------------------------------------------------------------
-- Combinatorial process data_length_calcul: calculation of the amount of bytes, after the
-- FSS and before the FCS, that have to be transferred when a variable is produced. In the case
-- of the presence and the identification variables, the data length is predefined in the WF_package.
-- In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the calculation.
-- of the presence, the identification and the var5 variables, the data length is predefined in the
-- wf_package. In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the
-- calculation.
data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i)
begin
......@@ -137,13 +138,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth;
......@@ -184,23 +185,14 @@ begin
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_jc3 =>
-- data length calculation regardless of the operational mode, the P3_LGTH and the NOSTAT
-- 1 byte of data from the JTAG_controller
-- to these there should be added: 1 byte CTRL
-- 1 byte PDU_TYPE
-- 1 byte LGTH
-- 1 byte nFIP status (regardless of the NOSTAT input)
-- 1 byte MPS status
-- 6 bytes (counting starts from 0!)
s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_5 =>
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_5_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when others =>
s_prod_data_lgth <= (others => '0');
......
wf_prod_permit.vhd
View file @ 7676925e
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_prod_permit |
-- wf_prod_permit |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_prod_permit.vhd |
-- File wf_prod_permit.vhd |
-- |
-- Description Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY, |
-- according to the variable (var_i) that is being treated. |
......@@ -19,8 +19,8 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/1/2011 |
-- Version v0.01 |
-- Depends on WF_engine_control |
-- WF_reset_unit |
-- Depends on wf_engine_control |
-- wf_reset_unit |
---------------- |
-- Last changes |
-- 1/2011 v0.01 EG First version |
......@@ -51,22 +51,22 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_prod_permit
-- Entity declaration for wf_prod_permit
--=================================================================================================
entity WF_prod_permit is port(
entity wf_prod_permit is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the WF_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the WF_engine_control
-- Signals from the wf_engine_control
var_i : in t_var; -- variable type that is being treated
......@@ -74,13 +74,13 @@ entity WF_prod_permit is port(
-- nanoFIP User Interface, NON-WISHBONE outputs
var3_rdy_o : out std_logic); -- signals the user that data can safely be written
end entity WF_prod_permit;
end entity wf_prod_permit;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_prod_permit is
architecture rtl of wf_prod_permit is
--=================================================================================================
-- architecture begin
......@@ -91,16 +91,14 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process VAR3_RDY_Generation:
-- VAR3_RDY (for produced vars): signals that the user can safely write to the produced variable
-- memory or to the DAT_I bus. It is deasserted right after the end of the reception of a
-- correct var_3 ID_DAT frame and stays de-asserted until the end of the transmission of the
-- corresponding RP_DAT from nanoFIP.
-- VAR3_RDY: signals that the user can safely write to the produced variable memory or to the
-- DAT_I bus. It is deasserted right after the end of the reception of a correct var_3 ID_DAT frame
-- and stays de-asserted until the end of the transmission of the corresponding RP_DAT from nanoFIP.
-- Note: A correct ID_DAT frame along with the variable it contained is signaled by the var_i.
-- For produced variables, the signal var_i gets its value after the reception of a correct ID_DAT
-- frame (with correct FSS, CTRL, PDU_TYPE, LGTH, CRC and FES bytes) and retains it until the end
-- of the transmission of the corresponding RP_DAT. An example follows:
--
-- frame and retains it until the end of the transmission of the corresponding RP_DAT.
-- An example follows:
-- frames : ___[ID_DAT,var_3]__[......RP_DAT......]______________[ID_DAT,var_3]___[.....RP_DAT..
-- var_i : var_whatever > < var_3 > < var_whatever > < var_3
-- VAR3_RDY: -------------------|__________________|--------------------------------|___________
......
wf_production.vhd
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wf_reset_unit.vhd
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This diff is collapsed.
wf_rx_deglitcher.vhd
View file @ 7676925e
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_rx_deglitcher |
-- wf_rx_deglitcher |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_rx_deglitcher.vhd |
-- File wf_rx_deglitcher.vhd |
-- |
-- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD. |
-- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. |
......@@ -19,7 +19,7 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.03 |
-- Depends on WF_reset_unit |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content |
......@@ -53,19 +53,19 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_rx_deglitcher
-- Entity declaration for wf_rx_deglitcher
--=================================================================================================
entity WF_rx_deglitcher is port(
entity wf_rx_deglitcher is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the WF_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk)
......@@ -73,19 +73,19 @@ entity WF_rx_deglitcher is port(
-- OUTPUTS
-- Signals to the WF_rx_deserializer unit
-- Signals to the wf_rx_deserializer unit
fd_rxd_filt_o : out std_logic; -- filtered output signal
fd_rxd_filt_edge_p_o : out std_logic; -- indicates an edge on the filtered signal
fd_rxd_filt_f_edge_p_o : out std_logic);-- indicates a falling edge on the filtered signal
end WF_rx_deglitcher;
end wf_rx_deglitcher;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_rx_deglitcher is
architecture rtl of wf_rx_deglitcher is
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
signal s_fd_rxd_filt, s_fd_rxd_filt_d1 : std_logic;
......
wf_rx_deserializer.vhd
View file @ 7676925e
This diff is collapsed.
wf_rx_osc.vhd
View file @ 7676925e
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_rx_osc |
-- wf_rx_osc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_rx_osc.vhd |
-- File wf_rx_osc.vhd |
-- |
-- Description Generation of the clock signals needed for the FIELDRIVE reception |
-- |
......@@ -31,9 +31,9 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.04 |
-- Depends on WF_reset_unit |
-- WF_deglitcher |
-- WF_rx_deserializer |
-- Depends on wf_reset_unit |
-- wf_deglitcher |
-- wf_rx_deserializer |
------------------ |
-- Last changes |
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content |
......@@ -42,7 +42,7 @@
-- rst_rx_osc signal clearified |
-- 12/2010 v0.03 EG code cleaned-up |
-- 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments |
-- 02/2011 v0.04 EG 2 units WF_rx_osc and WF_tx_osc; process replaced by WF_incr_counter |
-- 02/2011 v0.04 EG 2 units wf_rx_osc and wf_tx_osc; process replaced by wf_incr_counter |
-- check for code violations removed completely |
---------------------------------------------------------------------------------------------------
......@@ -71,31 +71,31 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_rx_osc
-- Entity declaration for wf_rx_osc
--=================================================================================================
entity WF_rx_osc is port(
entity wf_rx_osc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the WF_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the WF_deglitcher unit
-- Signal from the wf_deglitcher unit
fd_rxd_edge_p_i : in std_logic; -- indication of an edge on fd_rxd
-- Signal from WF_rx_deserializer unit
-- Signal from wf_rx_deserializer unit
rx_osc_rst_i : in std_logic; -- resets the clock recovery procedure
-- OUTPUTS
-- Signals to the WF_rx_deserializer
-- Signals to the wf_rx_deserializer
rx_manch_clk_p_o : out std_logic; -- signal with uclk-wide pulses
-- o on a significant edge
-- o between adjacent bits
......@@ -109,14 +109,14 @@ entity WF_rx_osc is port(
rx_adjac_bits_window_o : out std_logic); -- time window where a transition between adjacent
-- bits is expected
end entity WF_rx_osc;
end entity wf_rx_osc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_rx_osc is
architecture rtl of wf_rx_osc is
-- reception period counter
signal s_period_c, s_period, s_margin : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
......@@ -141,29 +141,29 @@ begin
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- # uclock ticks for a bit period, defined by the WorldFIP bit rate
-- # uclk ticks for a bit period, defined by the WorldFIP bit rate
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
s_half_period <= s_period srl 1; -- 1/2 s_period
s_margin <= s_period srl 3; -- margin for jitter defined as 1/8 of the period
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a WF_incr_counter unit : the rx_counter starts counting after the
-- Instantiation of a wf_incr_counter unit : the rx_counter starts counting after the
-- release of the reset signal rx_osc_rst_i. This takes place after a falling edge on the
-- filtered FD_RXD; this edge should be representing the 1st Manchester (manch.) encoded bit '1'
-- filtered FD_RXD; this edge should be representing the 1st Manchester 2 (manch.) encoded bit '1'
-- of the PREamble. Starting from this edge, other falling or rising significant edges, are
-- expected around one period (s_period) later. A time window around the expected arrival time is
-- set and its length is defined as 1/4th of the period (1/8th before and 1/8th after the expected
-- time). When the actual edge arrives, the counter is reset.
-- If that first falling edge of FD_RXD is finally proven not to belong to a valid PRE the counter
-- is reinitialialized through the rx_osc_rst_i signal from the WF_rx_deserializer.
-- is reinitialialized through the rx_osc_rst_i signal from the wf_rx_deserializer.
rx_periods_count: WF_incr_counter
rx_periods_count: wf_incr_counter
generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_period_c_reinit,
incr_counter_i => '1',
counter_reinit_i => s_period_c_reinit,
counter_incr_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
......@@ -201,12 +201,8 @@ begin
-- Clocks Generation --
---------------------------------------------------------------------------------------------------
-- Synchronous process rx_clks: the process rx_clk is following the edges that appear on the
-- nanoFIP FIELDRIVE input fd_rxd and constructs two clock signals: rx_manch_clk & rx_bit_clk.
-- In detail, the process is looking for moments:
-- o of significant edges
-- o between boundary bits
-- Synchronous process rx_clks: the process rx_clk is following the edges that appear on the fd_rxd
-- and constructs two clock signals: rx_manch_clk & rx_bit_clk.
-- The signal rx_manch_clk: is inverted on each significant edge, as well as between adjacent bits
-- The signal rx_bit_clk : is inverted only between adjacent bits
......@@ -295,7 +291,7 @@ begin
---------------------------------------------------------------------------------------------------
rx_manch_clk_p_o <= s_manch_clk_d1 xor s_manch_clk; -- a 1 uclk-wide pulse, after
-- o a significant edge
-- o a significant edge and
-- o a new bit
-- ___|-|___|-|___|-|___
......
wf_status_bytes_gen.vhd
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wf_tx_osc.vhd
View file @ 7676925e
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_tx_osc |
-- wf_tx_osc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_tx_osc.vhd |
-- File wf_tx_osc.vhd |
-- |
-- Description Generation of the clock signals needed for the FIELDRIVE transmission. |
-- |
......@@ -28,14 +28,14 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.04 |
-- Depends on WF_reset_unit |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content |
-- 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned; |
-- c_TX_SCHED_BUFF_LGTH got 1 bit more |
-- 12/2010 v0.03 EG code cleaned-up |
-- 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_osc_rst_p_i
-- 01/2011 v0.04 EG wf_tx_osc as different unit; use of wf_incr_counter;added tx_osc_rst_p_i
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -63,24 +63,24 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_tx_osc
-- Entity declaration for wf_tx_osc
--=================================================================================================
entity WF_tx_osc is
entity wf_tx_osc is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the WF_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the WF_engine_control
-- Signals from the wf_engine_control
tx_osc_rst_p_i : in std_logic; -- transmitter timeout
......@@ -88,17 +88,17 @@ entity WF_tx_osc is
-- nanoFIP FIELDRIVE output
tx_clk_o : out std_logic; -- line driver half bit clock
-- Signal to the WF_tx_serializer unit
-- Signal to the wf_tx_serializer unit
tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0));
-- buffer of pulses used for the scheduling
-- of the actions of the WF_tx_serializer
end entity WF_tx_osc;
-- of the actions of the wf_tx_serializer
end entity wf_tx_osc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_tx_osc is
architecture rtl of wf_tx_osc is
-- transmission periods counter
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
......@@ -128,14 +128,14 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a WF_incr_counter counting transmission periods.
-- Instantiation of a wf_incr_counter counting transmission periods.
tx_periods_count: WF_incr_counter
tx_periods_count: wf_incr_counter
generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_period_c_reinit,
incr_counter_i => '1',
counter_reinit_i => s_period_c_reinit,
counter_incr_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
......
wf_tx_serializer.vhd
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wf_wb_controller.vhd
View file @ 7676925e
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- WF_wb_controller |
-- wf_wb_controller |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_wb_controller.vhd |
-- File wf_wb_controller.vhd |
-- |
-- Description The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to |
-- the user's STBs. |
......@@ -19,7 +19,7 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 21/01/2011 |
-- Version v0.01 |
-- Depends on WF_production |
-- Depends on wf_production |
---------------- |
-- Last changes |
-- 21/01/2011 v0.011 EG changed registering |
......@@ -50,14 +50,14 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_wb_controller
-- Entity declaration for wf_wb_controller
--=================================================================================================
entity WF_wb_controller is port(
entity wf_wb_controller is port(
-- INPUTS
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; -- WISHBONE clock
......@@ -69,19 +69,19 @@ entity WF_wb_controller is port(
-- OUTPUTS
-- Signal from the WF_production_unit
-- Signal from the wf_production_unit
wb_ack_prod_p_o : out std_logic; -- response to a write cycle
-- latching moment of wb_dat_i
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_p_o : out std_logic); -- WISHBONE acknowledge
end entity WF_wb_controller;
end entity wf_wb_controller;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_wb_controller is
architecture rtl of wf_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_stb_r_edge_p : std_logic;
signal s_wb_we_synch, s_wb_cyc_synch : std_logic_vector (2 downto 0);
......
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