comments added to wf_model_constr_decoder; signal C_RECALC_MID_CID renamed to C_RELOAD_MID_CID.

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@95 7f0067c9-7624-46c7-bd39-3fb5400c0213

comments added to wf_model_constr_decoder; signal C_RECALC_MID_CID renamed to C_RELOAD_MID_CID.
git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@95 7f0067c9-7624-46c7-bd39-3fb5400c0213
7a2e56fc · egousiou · 9e8eb517 · 7a2e56fc · 7a2e56fc · 7a2e56fc
Commit 7a2e56fc authored Oct 25, 2010 by egousiou
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Showing with 10 additions and 10 deletions

nanofip.vhd nanofip.vhd +1 -1

wf_model_constr_decoder.vhd wf_model_constr_decoder.vhd +7 -7

wf_package.vhd wf_package.vhd +2 -2

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--- a/nanofip.vhd
+++ b/nanofip.vhd
@@ -386,7 +386,7 @@ begin
 ---------------------------------------------------------------------------------------------------

 model_constr_decoder : wf_model_constr_decoder 
-  generic map (C_RECALC_MID_CID => C_RECALC_MID_CID)
+  generic map (C_RELOAD_MID_CID => C_RELOAD_MID_CID)
  port map(
    uclk_i        => uclk_i,
    nFIP_u_rst_i    => s_rst,

--- a/wf_model_constr_decoder.vhd
+++ b/wf_model_constr_decoder.vhd
@@ -57,7 +57,7 @@ use IEEE.NUMERIC_STD.all;     --! conversion functions
 --!     -> 11/09/2009  v0.01  EB  First version \n
 --!     -> 20/08/2010  v0.02  EG  S_ID corrected so that S_ID0 is always the opposite of S_ID1
 --!                               "for" loop replaced with signals concatenation; 
--!                               Counter is of C_RECALC_MID_CID bits; Code cleaned-up \n
+--!                               Counter is of C_RELOAD_MID_CID bits; Code cleaned-up \n
 --
 ---------------------------------------------------------------------------------------------------
 --
@@ -77,8 +77,8 @@ use IEEE.NUMERIC_STD.all;     --! conversion functions
 --!                             Entity declaration for wf_model_constr_decoder
 --=================================================================================================
 entity wf_model_constr_decoder is
-  generic (C_RECALC_MID_CID : natural);             --! recalculation of M_ID & C_ID 
-                                                    --! every 2^(C_RECALC_MID_CID-1) uclk ticks
+  generic (C_RELOAD_MID_CID : natural);             --! reloading of model & constructor 
+                                                    --! every 2^(C_RELOAD_MID_CID) uclk ticks
  port (
  -- INPUTS 
    -- User Interface general signal
@@ -113,7 +113,7 @@ architecture rtl of wf_model_constr_decoder is


  signal s_load_model_constr_p :       std_logic;
-  signal s_counter, s_counter_full :   unsigned (C_RECALC_MID_CID-1 downto 0);
+  signal s_counter, s_counter_full :   unsigned (C_RELOAD_MID_CID-1 downto 0);
  signal s_model_even, s_model_odd :   std_logic_vector (3 downto 0);
  signal s_constr_even, s_constr_odd : std_logic_vector (3 downto 0);

@@ -131,9 +131,9 @@ begin
 --! of all the odd bits of M_ID and C_ID are loaded on the registers s_model_odd/ s_constr_odd
 --! and on the second uclk tick, the values of all the even bits are loaded on the registers
 --! s_model_even/ s_constr_even.
--! The signal s_load_model_constr_p signals that the odd and even parts of the model and
--! constructor have been received and can be concatenated to form the m_id_dec_o and c_id_dec_o 
--! decoded outputs (s_load_model_constr_p is activated every 4 uclk periods).
+--! The signal s_load_model_constr_p signals the recalculation of the model and constructor.
+--! It is activated every 2^(C_RELOAD_MID_CID) uclk periods. At those moments, the odd and even
+--! parts are concatenated to form the m_id_dec_o and c_id_dec_o decoded outputs.

  Model_Constructor_Decoder: process(uclk_i)
  begin

--- a/wf_package.vhd
+++ b/wf_package.vhd
@@ -24,7 +24,7 @@ package wf_package is

  constant C_TXCLKBUFFLENTGTH :  natural := 4;

-  constant C_RECALC_MID_CID : natural := 2;
+  constant C_RELOAD_MID_CID : natural := 8;


  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --
@@ -716,7 +716,7 @@ end component wf_bits_to_txd;

 ---------------------------------------------------------------------------------------------------
 component wf_model_constr_decoder 
-  generic (C_RECALC_MID_CID : natural); 
+  generic (C_RELOAD_MID_CID : natural); 
  port (
    uclk_i :     in std_logic; 
    nFIP_u_rst_i : in std_logic;