Commit 7da7370b authored by egousiou's avatar egousiou

wf_engine_control small issue with FES detection solved

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@124 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 2e4bdf05
......@@ -432,7 +432,7 @@ begin
port map(
uclk_i => uclk_i,
nfip_rst_i => s_rst,
rxd_edge_i => s_fd_rxd_edge_p,
rxd_edge_p_i => s_fd_rxd_edge_p,
rst_rx_osc_i => s_rst_rx_osc,
rate_i => s_rate_synch,
---------------------------------------------------------
......
......@@ -126,7 +126,7 @@ architecture rtl of WF_bits_to_txd is
begin
---------------------------------------------------------------------------------------------------
--! @brief Synchronous process Bits_Delivery: managment of nanoFIP output signal FD_TXD by
--! @brief Synchronous process Bits_Delivery: handling of nanoFIP output signal FD_TXD by
--! placing bits of data according to the state of WF_tx_serializer's state machine (sending_fss,
--! sending_data, sending_crc, sending_fes, stop_transmission) and to the counter txd_bit_index.
--! The delivery is synchronised by the tx_clk_p_buff(1) signal.
......@@ -151,7 +151,7 @@ begin
txd_o <= crc_byte_manch_i (to_integer (txd_bit_index_i)); -- CRC: 2 bytes long
elsif sending_fes_i = '1' then
txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
else
txd_o <= '0';
......@@ -180,12 +180,12 @@ begin
(sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then
if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enabble with the
tx_enable_o <= '1'; -- activation of tx_enable with the
end if; -- the delivery of the 1st FSS bit
-- txd (FSS) :________|-----|___________|--------
-- FD_TXD (FSS) :________|-----|___________|--------
-- tx_clk_p_buff(1):______|-|___|-|___|-|___|-|___|-|__
-- sending_FSS :___|-------------------------------
-- tx_enable :________|--------------------------
-- FD_TXENA :________|--------------------------
else
tx_enable_o <= '0';
end if;
......
......@@ -33,21 +33,22 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--!
--! o If the consumed variable had been a var_1 or a var_2:
--!
--! o If the operation is in memory mode : the unit is registering the pure-data
--! bytes along with the PDU_TYPE, Length and MPS bytes in the Consumed memories
--! o If the operation is in memory mode : the unit is registering the
--! application-data bytes along with the PDU_TYPE, Length and MPS bytes in the
--! Consumed memories
--!
--! o If the operation is in standalone mode: the unit is transferring the 2
--! pure-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O.
--! o If the operation is in standalone mode: the unit is transferring the 2 appli-
--! cation-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O
--!
--! o If the consumed variable had been a var_rst, the 2 pure-data bytes are just
--! o If the consumed variable had been a var_rst, the 2 application-data bytes are just
--! identified and sent to the WF_reset_unit.
--!
--! ------------------------------------------------------------------------------------
--! Reminder:
--!
--! Consumed RP_DAT frame structure :
--! ___________ ______ _______ ________ ________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|__LGTH__|__..PureData..__|__MPS__||____FCS____|__FES__|
--! ___________ ______ _______ ________ __________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|__LGTH__|__..ApplicData..__|__MPS__||____FCS____|__FES__|
--!
--! |-------LGTH bytes-------|
--! |--------write to Consumed memory---------|
......@@ -114,7 +115,7 @@ entity WF_cons_bytes_processor is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode (active high)
-- Signal from the WF_reset_unit
......
......@@ -28,8 +28,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--
--! @brief In stand-alone mode, after the reception of a consumed or consumed broadcast
--! variable, the unit is responsible for transering the two pure-data bytes to the
--! 2-bytes long bus DAT_O.
--! variable, the unit is responsible for transering the two application-data bytes to
--! the 2-bytes long bus DAT_O.
--! The bytes are put in the bus one by one as they arrive, as the signal
--! transfer_byte_p_i indicates.
--!
......@@ -88,7 +88,7 @@ entity WF_cons_bytes_to_dato is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......@@ -134,14 +134,14 @@ Data_Transfer_To_Dat_o: process (uclk_i)
if transfer_byte_p_i(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
slone_data_o(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
if transfer_byte_p_i(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
slone_data_o(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
......
......@@ -90,7 +90,7 @@ entity WF_cons_outcome is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings (synchronized with uclk)
......
......@@ -72,7 +72,7 @@ entity WF_decr_counter is
port (
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
This diff is collapsed.
......@@ -66,7 +66,7 @@ entity WF_incr_counter is
port (
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
......@@ -84,7 +84,7 @@ entity WF_inputs_synchronizer is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
nostat_a_i : in std_logic;
rstin_a_i : in std_logic;
slone_a_i : in std_logic;
......
......@@ -90,7 +90,7 @@ entity WF_rx_manch_code_check is
port (
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
......@@ -184,7 +184,7 @@ package WF_package is
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks(3 downto 0):=
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks (3 downto 0):=
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
......@@ -278,7 +278,6 @@ package WF_package is
response => produce,
base_addr => "---------",
array_length => "00001010", -- 11 bytes in total including the Control byte
-- (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00", 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00", 9 => x"00", 10 => x"00",
......@@ -290,7 +289,7 @@ package WF_package is
response => produce,
base_addr => "100000000",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
......@@ -300,17 +299,17 @@ package WF_package is
response => consume,
base_addr => "000000000",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
c_VAR_2_INDEX => (var => var_2,
hexvalue => x"91", --------------
hexvalue => x"91",
response => consume,
base_addr => "010000000",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
......@@ -318,8 +317,8 @@ package WF_package is
hexvalue => x"e0",
response => reset,
base_addr => "---------",
array_length => "00000001", -- only the Control byte is predefined
-- (counting starts from 0)
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")));
......@@ -450,7 +449,7 @@ end component WF_inputs_synchronizer;
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic;
rxd_edge_i : in std_logic;
rxd_edge_p_i : in std_logic;
rst_rx_osc_i : in std_logic;
-------------------------------------------------------------------------
rx_manch_clk_p_o : out std_logic;
......
......@@ -130,7 +130,7 @@ entity WF_prod_bytes_retriever is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
......
......@@ -82,7 +82,7 @@ entity WF_prod_bytes_from_dati is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
......@@ -80,7 +80,7 @@ entity WF_prod_permit is
port (
-- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
......@@ -58,8 +58,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Reminder:
--!
--! Consumed RP_DAT frame structure :
--! _______ _______ ______ _______ ______ ______________ _______ ___________ _______
--! |__PRE__|__FSD__|_Ctrl_||__PDU__|_LGTH_|_..PureData.._|__MPS__||____FCS____|__FES__|
--! _______ _______ ______ _______ ______ ________________ _______ ___________ _______
--! |__PRE__|__FSD__|_Ctrl_||__PDU__|_LGTH_|_..ApplicData.._|__MPS__||____FCS____|__FES__|
--!
--! ------------------------------------------------------------------------------------
--
......@@ -130,7 +130,7 @@ entity WF_rx_deserializer is
port (
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
......@@ -201,7 +201,7 @@ architecture rtl of WF_rx_deserializer is
signal s_manch_bit_index, s_manch_bit_index_top : unsigned(3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_CRC_ok_p_buff, s_arriving_fes : std_logic_vector (15 downto 0);
signal s_arriving_fes : std_logic_vector (14 downto 0);
--=================================================================================================
-- architecture begin
......@@ -336,7 +336,7 @@ architecture rtl of WF_rx_deserializer is
-- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length
-- (not predefined) up to 132 bytes (FSD+Ctrl+PDU_TYPE+LGTH+124 pure_data+MPS+FCS+FES).
-- (not predefined) up to 132 bytes (FSD+Ctrl+PDU_TYPE+LGTH+124 application_data+MPS+FCS+FES).
-- The WF_engine_control unit is following the amount of bytes being received and in case
-- their number overpasses the expected one, it activates the signal rst_rx_unit_p_i.
-- Therefore, the Receiver_FSM stays in the data_fcs_fes_fields state until the arrival of a
......@@ -551,17 +551,19 @@ architecture rtl of WF_rx_deserializer is
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_arriving_fes <= (others =>'0');
else
if s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
if s_receiving_bytes = '0' then
s_arriving_fes <= (others =>'0');
elsif s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
s_arriving_fes <= s_arriving_fes (14 downto 0) & rxd_filtered_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_fes_detected_p <= '1' when s_arriving_fes = (c_FES) and sample_manch_bit_p_i = '1' else '0';
s_fes_detected_p <= '1' when s_arriving_fes = (c_FES);
---------------------------------------------------------------------------------------------------
......@@ -626,7 +628,7 @@ architecture rtl of WF_rx_deserializer is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that handles the CRC signal: The crc_ok_p coming from the CRC
--! calculator unit is delayed for 16 manch. encoded bits. The matching of this delayed pulse
--! calculator unit is delayed for 15 manch. encoded bits. The matching of this delayed pulse
--! with the end of frame pulse (s_fes_detected_p), would confirm that the two last bytes
--! received before the FES were the correct CRC.
......@@ -656,7 +658,7 @@ architecture rtl of WF_rx_deserializer is
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(15); -- pulse 1 half-bit-clock period long
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(14); -- pulse 1 half-bit-clock period long
......
This diff is collapsed.
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