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nanoFIP - Gateware
Commit ad26318d authored by egousiou's avatar egousiou
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small units eliminated; 

corrections on nFIP status byte

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@170 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 4abbe8b9
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DualClkRAM.vhd
View file @ ad26318d
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! ProASIC3 library
library PROASIC3;
library PROASIC3; --! component specific library
--! ProASIC3 packages
use PROASIC3.all;
......@@ -31,7 +31,7 @@ use PROASIC3.all;
---------------------------------------------------------------------------------------------------
--
--
--! @brief Instantiation of a template RAM4K9 memory component with
--! @brief Instantiation of a template ProAsic3 RAM4K9 memory component with
--! o word width : 8 bits and
--! o depth : 512 bytes.
--
......@@ -183,6 +183,7 @@ architecture RAM4K9 of DualClkRAM is
-- architecture begin
--=================================================================================================
begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
......@@ -197,107 +198,106 @@ begin
--! o WMODEA, WMODEB : GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map (
-- INPUTS
-- INPUTS concerning port A
-- data in A (1 byte, (7 downto 0))
DINA8 => GROUND,
DINA7 => DINA(7),
DINA6 => DINA(6),
DINA5 => DINA(5),
DINA4 => DINA(4),
DINA3 => DINA(3),
DINA2 => DINA(2),
DINA1 => DINA(1),
DINA0 => DINA(0),
-- address A (512 bytes depth, (8 downto 0))
ADDRA11 => GROUND,
ADDRA10 => GROUND,
ADDRA9 => GROUND,
ADDRA8 => ADDRA(8),
ADDRA7 => ADDRA(7),
ADDRA6 => ADDRA(6),
ADDRA5 => ADDRA(5),
ADDRA4 => ADDRA(4),
ADDRA3 => ADDRA(3),
ADDRA2 => ADDRA(2),
ADDRA1 => ADDRA(1),
ADDRA0 => ADDRA(0),
-- read/ write mode for A
WENA => RWA,
-- clock for A
CLKA => CLKA,
-- aspect ratio, block, pipeline, write mode configurations for port A
WIDTHA0 => POWER,
WIDTHA1 => POWER,
BLKA => GROUND,
PIPEA => GROUND,
WMODEA => GROUND,
-- INPUTS concerning port B
-- data in B (1 byte, (7 downto 0))
DINB8 => GROUND,
DINB7 => DINB(7),
DINB6 => DINB(6),
DINB5 => DINB(5),
DINB4 => DINB(4),
DINB3 => DINB(3),
DINB2 => DINB(2),
DINB1 => DINB(1),
DINB0 => DINB(0),
-- address B (512 bytes depth, (8 downto 0))
ADDRB11 => GROUND,
ADDRB10 => GROUND,
ADDRB9 => GROUND,
ADDRB8 => ADDRB(8),
ADDRB7 => ADDRB(7),
ADDRB6 => ADDRB(6),
ADDRB5 => ADDRB(5),
ADDRB4 => ADDRB(4),
ADDRB3 => ADDRB(3),
ADDRB2 => ADDRB(2),
ADDRB1 => ADDRB(1),
ADDRB0 => ADDRB(0),
-- read/ write mode for B
WENB => RWB,
-- clock for B
CLKB => CLKB,
-- aspect ratio, block, pipeline, write mode configurations for port B
WIDTHB0 => POWER,
WIDTHB1 => POWER,
BLKB => GROUND,
PIPEB => GROUND,
WMODEB => GROUND,
-- reset
RESET => RESETn,
-- Oututs
-- output concerning port A
-- data out A (1 byte)
DOUTA8 => open,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
DOUTA5 => DOUTA(5),
DOUTA4 => DOUTA(4),
DOUTA3 => DOUTA(3),
DOUTA2 => DOUTA(2),
DOUTA1 => DOUTA(1),
DOUTA0 => DOUTA(0),
-- output concerning port B
-- data out B (1 byte)
DOUTB8 => open,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
DOUTB5 => DOUTB(5),
DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3),
DOUTB2 => DOUTB(2),
DOUTB1 => DOUTB(1),
DOUTB0 => DOUTB(0)
);
port map (
-- INPUTS
-- inputs concerning port A
-- data in A (1 byte, (7 downto 0))
DINA8 => GROUND,
DINA7 => DINA(7),
DINA6 => DINA(6),
DINA5 => DINA(5),
DINA4 => DINA(4),
DINA3 => DINA(3),
DINA2 => DINA(2),
DINA1 => DINA(1),
DINA0 => DINA(0),
-- address A (512 bytes depth, (8 downto 0))
ADDRA11 => GROUND,
ADDRA10 => GROUND,
ADDRA9 => GROUND,
ADDRA8 => ADDRA(8),
ADDRA7 => ADDRA(7),
ADDRA6 => ADDRA(6),
ADDRA5 => ADDRA(5),
ADDRA4 => ADDRA(4),
ADDRA3 => ADDRA(3),
ADDRA2 => ADDRA(2),
ADDRA1 => ADDRA(1),
ADDRA0 => ADDRA(0),
-- read/ write mode for A
WENA => RWA,
-- clock for A
CLKA => CLKA,
-- aspect ratio, block, pipeline, write mode configurations for port A
WIDTHA0 => POWER,
WIDTHA1 => POWER,
BLKA => GROUND,
PIPEA => GROUND,
WMODEA => GROUND,
-- inputs concerning port B
-- data in B (1 byte, (7 downto 0))
DINB8 => GROUND,
DINB7 => DINB(7),
DINB6 => DINB(6),
DINB5 => DINB(5),
DINB4 => DINB(4),
DINB3 => DINB(3),
DINB2 => DINB(2),
DINB1 => DINB(1),
DINB0 => DINB(0),
-- address B (512 bytes depth, (8 downto 0))
ADDRB11 => GROUND,
ADDRB10 => GROUND,
ADDRB9 => GROUND,
ADDRB8 => ADDRB(8),
ADDRB7 => ADDRB(7),
ADDRB6 => ADDRB(6),
ADDRB5 => ADDRB(5),
ADDRB4 => ADDRB(4),
ADDRB3 => ADDRB(3),
ADDRB2 => ADDRB(2),
ADDRB1 => ADDRB(1),
ADDRB0 => ADDRB(0),
-- read/ write mode for B
WENB => RWB,
-- clock for B
CLKB => CLKB,
-- aspect ratio, block, pipeline, write mode configurations for port B
WIDTHB0 => POWER,
WIDTHB1 => POWER,
BLKB => GROUND,
PIPEB => GROUND,
WMODEB => GROUND,
-- input reset
RESET => RESETn,
-------------------------------
-- OUTPUTS
-- output concerning port A
-- data out A (1 byte)
DOUTA8 => open,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
DOUTA5 => DOUTA(5),
DOUTA4 => DOUTA(4),
DOUTA3 => DOUTA(3),
DOUTA2 => DOUTA(2),
DOUTA1 => DOUTA(1),
DOUTA0 => DOUTA(0),
-- output concerning port B
-- data out B (1 byte)
DOUTB8 => open,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
DOUTB5 => DOUTB(5),
DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3),
DOUTB2 => DOUTB(2),
DOUTB1 => DOUTB(1),
DOUTB0 => DOUTB(0));
-------------------------------
end RAM4K9;
--=================================================================================================
......
nanofip.vhd
View file @ ad26318d
......@@ -156,7 +156,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details\n
--
--! \n<b>Dependencies:</b> \n
--! WF_inputs_synchronizer \n
--! WF_reset_unit \n
--! WF_model_constr_dec \n
--! WF_tx_rx_osc \n
......@@ -323,7 +322,7 @@ architecture struc of nanofip is
signal s_rx_rst_p, s_nfip_status_r_tler : std_logic;
signal s_prod_byte_ready_p : std_logic;
signal s_var_from_control : t_var;
signal s_data_length_from_control : std_logic_vector (7 downto 0);
signal s_data_lgth_from_control : std_logic_vector (7 downto 0);
signal s_rx_byte, s_byte_to_tx, s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_cons_prod_byte_index_from_control : std_logic_vector (7 downto 0);
......@@ -381,7 +380,7 @@ begin
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
data_o => dat_o,
nfip_status_r_tler_o => s_nfip_status_r_tler,
nfip_status_r_tler_p_o => s_nfip_status_r_tler,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p);
---------------------------------------------------------
......@@ -428,10 +427,10 @@ begin
fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i,
var_i => s_var_from_control,
data_length_i => s_data_length_from_control,
data_lgth_i => s_data_lgth_from_control,
byte_index_i => s_cons_prod_byte_index_from_control,
byte_request_accept_p_i => s_prod_byte_ready_p,
nfip_status_r_tler_i => s_nfip_status_r_tler,
nfip_status_r_tler_p_i => s_nfip_status_r_tler,
nfip_status_r_fcser_p_i => s_crc_or_manch_wrong_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
......@@ -460,7 +459,6 @@ begin
tx_byte_request_accept_p_i => s_prod_byte_ready_p,
tx_last_byte_p_i => s_prod_last_byte_p,
tx_start_p_i => s_start_tx_p,
tx_rst_p_i => s_rst_tx_p,
---------------------------------------------------------
tx_byte_request_p_o => s_prod_request_byte_p,
tx_data_o => fd_txd_o,
......@@ -495,9 +493,8 @@ begin
tx_byte_request_accept_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control,
prod_data_length_o => s_data_length_from_control,
rx_rst_p_o => s_rx_rst_p,
rst_tx_p_o => s_rst_tx_p);
prod_data_lgth_o => s_data_lgth_from_control,
rx_rst_p_o => s_rx_rst_p);
---------------------------------------------------------
var1_rdy_o <= s_var1_rdy;
......
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ ad26318d
......@@ -100,13 +100,10 @@ end WF_DualClkRAM_clka_rd_clkb_wr;
--=================================================================================================
architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
---------------------------------------------------------------------------------------------------
type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
signal zero, one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
signal s_one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
......@@ -114,44 +111,45 @@ signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
begin
zero <= '0';
one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
s_one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
--!@brief: memory triplication
--! The component DualClkRam is generated three times.
--! Port A is used for reading only, port B for writing only.
--! The input DINB is written in the same position in the 3 memories.
--! The output DOUTA from each memory is kept in the array data_o_A_array.
--! The output DOUTA from each memory is kept in the array s_data_o_A_array.
G_memory_triplication: for I in 0 to 2 generate
G_memory_triplication: for I in 0 to 2 generate
UDualClkRam : DualClkRam
port map (
DINA => s_zeros,
ADDRA => addr_porta_i,
RWA => s_one,
CLKA => clk_porta_i,
UDualClkRam : DualClkRam
port map ( DINA => s_zeros,
ADDRA => addr_porta_i,
RWA => one,
CLKA => clk_porta_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_portb_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_portb_i,
RESETn => s_one,
RESETn => one,
DOUTA => s_data_o_A_array(I),
DOUTB => open);
DOUTA => data_o_A_array(I),
DOUTB => open) ;
end generate;
end generate;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial Majority_Voter
Majority_Voter: data_porta_o <= (data_o_A_array(0) and data_o_A_array(1)) or
(data_o_A_array(1) and data_o_A_array(2)) or
(data_o_A_array(2) and data_o_A_array(0));
Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
(s_data_o_A_array(1) and s_data_o_A_array(2)) or
(s_data_o_A_array(2) and s_data_o_A_array(0));
end syn;
--=================================================================================================
......
wf_bits_to_txd.vhd
View file @ ad26318d
......@@ -46,9 +46,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_tx_rx_osc \n
--! WF_tx_serializer \n
--! WF_reset_unit \n
--! WF_tx_osc \n
--! WF_tx_serializer \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -96,7 +96,7 @@ entity WF_bits_to_txd is
txd_bit_index_i : in unsigned(4 downto 0); --! index of a bit inside a byte
-- Signals from the WF_tx_rx_osc unit
-- Signals from the WF_tx_osc unit
tx_clk_p_i : in std_logic; --!clk for transmission synchronization
......@@ -112,7 +112,8 @@ end entity WF_bits_to_txd;
--! architecture declaration
--=================================================================================================
architecture rtl of WF_bits_to_txd is
signal s_fss : std_logic_vector (31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -155,7 +156,7 @@ begin
end if;
end process;
s_fss<=c_FSS;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
......
wf_cons_bytes_processor.vhd
View file @ ad26318d
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wf_cons_bytes_to_dato.vhd deleted 100644 → 0
View file @ 4abbe8b9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_cons_bytes_to_dato.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_bytes_to_dato --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief In stand-alone mode, after the reception of a consumed (var_1) or a consumed
--! broadcast variable (var_2), the unit is responsible for transering the two
--! application-data bytes to the 2-bytes long bus DAT_O.
--! The bytes are put in the bus one by one as they arrive, as the signal
--! transfer_byte_p_i indicates.
--!
--! Note: The validity of these transfered bytes is indicated by the "nanoFIP
--! User Interface, NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY which arrive later, after
--! the end of the reception of the consumed frame.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 10/01/2011
--
--
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 10/1/2011 v0.02 EG unit renamed from WF_slone_cons_bytes_to_dato to
--! WF_cons_bytes_to_dato; cleaning-up + commenting
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_cons_bytes_to_dato
--=================================================================================================
entity WF_cons_bytes_to_dato is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_cons_bytes_processor
byte_i : in std_logic_vector (7 downto 0); --! de-serialised byte
transfer_byte_p_i : in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_O(7:0)
--! 10: byte_i transfered to DAT_O(15:8)
-- OUTPUTS
-- nanoFIP, User Interface NON WISHBONE output
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
);
end entity WF_cons_bytes_to_dato;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_cons_bytes_to_dato is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, according to the signal
--! transfer_byte_p_i, the first or second byte of the "User Interface, NON WISHBONE" bus DAT_O
--! takes the byte byte_i.
Data_Transfer_To_Dat_o: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
slone_data_o <= (others => '0'); -- bus initialization
else
if transfer_byte_p_i(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
slone_data_o(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
if transfer_byte_p_i(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
slone_data_o(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_cons_frame_validator.vhd deleted 100644 → 0
View file @ 4abbe8b9
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wf_cons_outcome.vhd
View file @ ad26318d
This diff is collapsed.
wf_consumption.vhd
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wf_crc.vhd
View file @ ad26318d
......@@ -35,10 +35,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--
--
--! @date 08/2010
--! @date 23/02/2011
--
--
--! @version v0.03
--! @version v0.04
--
--
--! @details \n
......@@ -58,8 +58,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n\n<b>Last changes:</b>\n
--! -> 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content \n
--! -> 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
--! variable v_q_check_mask replaced with a signal,
--! code cleaned-up+commented \n
--! variable v_q_check_mask replaced with a signal,
--! code cleaned-up+commented \n
--! -> 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list!
--! xor replaced with if(Syndrome_Verification); processes rewritten;
--! delay on data_bit_ready_p_i removed.
--
---------------------------------------------------------------------------------------------------
--
......@@ -73,7 +76,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Entity declaration for WF_crc
--=================================================================================================
entity WF_crc is
port (
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
......@@ -89,7 +92,7 @@ port (
-- OUTPUTS
-- Signal to the WF_rx_deserializer unit
crc_ok_p : out std_logic; --! signals a correct received CRC syndrome
crc_ok_p_o : out std_logic; --! signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH-1 downto 0)--!calculated CRC
......@@ -103,8 +106,8 @@ end entity WF_crc;
--=================================================================================================
architecture rtl of WF_crc is
signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0);
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -116,50 +119,43 @@ begin
--! of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
--! are interconnected as a linear feedback shift register.
Gen_16_bit_Register_and_Interconnections:
Generate_16_bit_Register_and_Interconnections:
for I in 0 to c_CRC_GENER_POLY'left generate
s_q_nx(0) <= data_bit_i xor s_q(s_q'left);
iteration_0: if I = 0 generate
s_q_nx(I) <= ((data_bit_i) xor s_q(s_q'left));
end generate;
next_iterations: if I > 0 generate
G: for I in 1 to c_CRC_GENER_POLY'left generate
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
end generate;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process CRC_calculation: the process "moves" the shift register described
--! above, for the calculation of the CRC.
CRC_calculation: process (uclk_i)
begin
if rising_edge (uclk_i) then
CRC_calculation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_q <= (others => '0');
if nfip_rst_i = '1' then
s_q <= (others => '0');
else
if start_crc_p_i = '1' then
s_q <= (others => '1'); -- register initialization
-- (initially preset, according to the Annex)
else
elsif data_bit_ready_p_i = '1' then -- new data bit to be considered for the CRC calculation
s_q <= s_q_nx; -- data propagation
end if;
if start_crc_p_i = '1' then
s_q <= (others => '1');-- register initialization
-- (initially preset, according to the Annex)
s_crc_bit_ready_p <= data_bit_ready_p_i;
elsif data_bit_ready_p_i = '1' then -- new bit to be considered for the CRC calculation
s_q <= s_q_nx; -- data propagation
end if;
end if;
end if;
end if;
end process;
end process;
-- -- -- -- --
crc_o <= not s_q;
-- -- -- -- --
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
......@@ -167,26 +163,23 @@ crc_o <= not s_q;
--! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_CRC_VERIFIC_MASK. When the CRC calculated from the received data matches the
--! c_CRC_VERIFIC_MASK, it is implied that a correct CRC word has been received for the preceded
--! data and the signal crc_ok_p gives a 1 uclk-wide pulse.
--! data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
Syndrome_Verification: process (s_q, s_crc_bit_ready_p)
Syndrome_Verification: process (s_q, data_bit_ready_p_i)
begin
begin
s_q_check_mask <= s_q xor c_CRC_VERIFIC_MASK;------------
if (unsigned(not s_q_check_mask)) = 0 then
crc_ok_p <= s_crc_bit_ready_p;
if s_q = not c_CRC_VERIFIC_MASK then
crc_ok_p_o <= data_bit_ready_p_i;
else
crc_ok_p <= '0';
else
crc_ok_p_o <= '0';
end if;
end process;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
......
wf_decr_counter.vhd
View file @ ad26318d
......@@ -90,7 +90,8 @@ end entity WF_decr_counter;
--=================================================================================================
architecture rtl of WF_decr_counter is
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
......
wf_engine_control.vhd
View file @ ad26318d
This diff is collapsed.
wf_fd_receiver.vhd
View file @ ad26318d
......@@ -39,31 +39,29 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o WF_rx_deglitcher : for the filtering of the input FD_RXD
--!
--!
--! _________________________ _________________________
--! | | | |
--! | WF_Consumption | | WF_engine_control |
--! |_________________________| |_________________________|
--! /\ /\
--! ___________________________________________________________
--! | WF_fd_revceiver |
--! | _________ |
--! | _______________________________________ | | |
--! | | | | | |
--! | | WF_rx_deserializer | | WF_rx | |
--! | | | < | _osc | |
--! | |_______________________________________| | | |
--! | /\ |_________| |
--! | _______________________________________ |
--! | | | |
--! | | WF_rx_deglitcher | |
--! | |_______________________________________| |
--! | |
--! |___________________________________________________________|
--! /\
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--!
--!
--! _________________________ _________________________
--! | | | |
--! | WF_Consumption | | WF_engine_control |
--! |_________________________| |_________________________|
--! /\ /\
--! ___________________________________________________________
--! | WF_fd_revceiver |
--! | _________ |
--! | _______________________________________ | | |
--! | | | | | |
--! | | WF_rx_deserializer | | WF_rx | |
--! | | | < | _osc | |
--! | |_______________________________________| | | |
--! | /\ |_________| |
--! | _______________________________________ |
--! | | | |
--! | | WF_rx_deglitcher | |
--! | |_______________________________________| |
--! | |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
......
wf_fd_transmitter.vhd
View file @ ad26318d
......@@ -39,28 +39,28 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o WF_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK
--! and the array of pulses tx_clk_p_buff (used for the
--! synchronization of the WF_tx_serializer).
--! ___________________________________________________________
--! | |
--! | WF_Production |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________
--! | WF_fd_transmitter |
--! | |
--! | ________________________________________________ |
--! | | | |
--! | | WF_tx_osc | |
--! | |________________________________________________| |
--! | \/ |
--! | _________________________________________________ |
--! | | | |
--! | | WF_tx_serializer | |
--! | | | |
--! | |_________________________________________________| |
--! |___________________________________________________________|
--! \/
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--! ___________________________________________________________
--! | |
--! | WF_Production |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________
--! | WF_fd_transmitter |
--! | |
--! | ________________________________________________ |
--! | | | |
--! | | WF_tx_osc | |
--! | |________________________________________________| |
--! | \/ |
--! | _________________________________________________ |
--! | | | |
--! | | WF_tx_serializer | |
--! | | | |
--! | |_________________________________________________| |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--!
--!
--!
......@@ -98,11 +98,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -129,7 +124,6 @@ entity WF_fd_transmitter is
tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
tx_last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
tx_start_p_i : in std_logic; --! indication for the start of the production
tx_rst_p_i : in std_logic; --! transmitter timeout
-- OUTPUTS
......@@ -151,6 +145,7 @@ end entity WF_fd_transmitter;
architecture struc of WF_fd_transmitter is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic;
--=================================================================================================
......@@ -170,7 +165,7 @@ begin
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
tx_rst_p_i => tx_rst_p_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
-----------------------------------------------
tx_clk_o => tx_clk_o,
tx_clk_p_buff_o => s_tx_clk_p_buff);
......@@ -188,15 +183,15 @@ begin
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
tx_rst_p_i => tx_rst_p_i,
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => tx_byte_request_accept_p_i,
byte_i => tx_byte_i,
last_byte_p_i => tx_last_byte_p_i,
tx_clk_p_buff_i => s_tx_clk_p_buff,
-----------------------------------------------
tx_data_o => tx_data_o,
byte_request_p_o => tx_byte_request_p_o,
tx_data_o => tx_data_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o );
-----------------------------------------------
......
wf_incr_counter.vhd
View file @ ad26318d
......@@ -90,6 +90,7 @@ architecture rtl of WF_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......
wf_inputs_synchronizer.vhd deleted 100644 → 0
View file @ 4abbe8b9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_inputs_synchronizer.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_inputs_synchronizer --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit synchronizes the nanoFIP's input signals to the uclk or the wb_clk;
--! a set of 3 registers is used for each signal.
--! Notes : Regarding the WISHBONE interface, only the control signals STB, CYC, WE are
--! synchronized.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 09/12/2010
--
--
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 10/2010 v0.01 EG First version
--! 12/2010 v0.02 EG fd_rxcdn added;
--! in nanoFIP input fd_rxd we also see the nanoFIP output fd_txd; in order to
--! get only the receiver's data, we filter fd_rxd with the reception activity
--! detection fd_rxcdn.
--! 1/2011 v0.021 EG wb_rst_a_i renamed to wb_rst_i
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_inputs_synchronizer
--=================================================================================================
entity WF_inputs_synchronizer is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, NON WISHBONE
dat_a_i : in std_logic_vector(15 downto 0);
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
-- nanoFIP FIELDRIVE
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
-- OUTPUTS
-- nanoFIP User Interface, General signals
rstin_o : out std_logic;
-- nanoFIP User Interface, NON WISHBONE
slone_dati_o : out std_logic_vector(15 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
-- nanoFIP FIELDRIVE
fd_rxd_o : out std_logic;
fd_rxd_edge_p_o : out std_logic;
fd_rxd_f_edge_p_o : out std_logic;
fd_rxd_r_edge_p_o : out std_logic;
fd_txer_o : out std_logic;
fd_wdgn_o : out std_logic
);
end entity WF_inputs_synchronizer;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_inputs_synchronizer is
signal s_wb_we_d3, s_wb_cyc_d1, s_wb_cyc_d2, s_wb_cyc_d3, s_fd_rxd_f_edge : std_logic;
signal s_var1_access_d1, s_var2_access_d1, s_var3_access_d1, s_fd_rxd_r_edge : std_logic;
signal s_var1_access_d2, s_var2_access_d2, s_var3_access_d2 : std_logic;
signal s_var1_access_d3, s_var2_access_d3, s_var3_access_d3 : std_logic;
signal s_wb_stb_d1, s_wb_stb_d2, s_wb_stb_d3, s_wb_stb_d4, s_wb_we_d1, s_wb_we_d2 : std_logic;
signal s_mid_d1, s_mid_d2, s_mid_d3, s_cid_d1, s_cid_d2, s_cid_d3 : std_logic_vector(3 downto 0);
signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3, s_fd_rxcdn_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3 : std_logic_vector(2 downto 0);
signal s_u_rst_d3 : std_logic_vector(2 downto 0);
signal s_nostat_d3, s_slone_d3 : std_logic_vector(2 downto 0);
signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0);
signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0);
signal s_slone_dati_d1, s_slone_dati_d3, s_slone_dati_d2 :std_logic_vector(15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronization: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var1_access_d1 <= '0';
s_var1_access_d2 <= '0';
s_var1_access_d3 <= '0';
s_var2_access_d1 <= '0';
s_var2_access_d2 <= '0';
s_var1_access_d3 <= '0';
s_var3_access_d1 <= '0';
s_var3_access_d2 <= '0';
s_var1_access_d3 <= '0';
else
s_var1_access_d1 <= var1_access_a_i;
s_var1_access_d2 <= s_var1_access_d1;
s_var1_access_d3 <= s_var1_access_d2;
s_var2_access_d1 <= var2_access_a_i;
s_var2_access_d2 <= s_var2_access_d1;
s_var2_access_d3 <= s_var2_access_d2;
s_var3_access_d1 <= var3_access_a_i;
s_var3_access_d2 <= s_var3_access_d1;
s_var3_access_d3 <= s_var3_access_d2;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
var1_access_o <= s_var1_access_d3;
var2_access_o <= s_var2_access_d3;
var3_access_o <= s_var3_access_d3;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_manch_code_viol_check.vhd
View file @ ad26318d
......@@ -63,9 +63,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx_deglitcher \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_deglitcher \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -117,6 +117,7 @@ architecture rtl of WF_rx_manch_code_check is
signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_signal_d : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -134,25 +135,25 @@ begin
-- check_code_viol : ^ ^ ^
Check_code_violations: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_check_code_viol_p <= '0';
s_sample_bit_p_d1 <= '0';
s_sample_bit_p_d2 <= '0';
s_serial_input_signal_d <= '0';
else
if sample_manch_bit_p_i = '1' then
s_serial_input_signal_d <= serial_input_signal_i;
end if;
s_check_code_viol_p <= s_sample_bit_p_d2; -- 2 uclk ticks delay
s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i;
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_check_code_viol_p <= '0';
s_sample_bit_p_d1 <= '0';
s_sample_bit_p_d2 <= '0';
s_serial_input_signal_d <= '0';
else
if sample_manch_bit_p_i = '1' then
s_serial_input_signal_d <= serial_input_signal_i;
end if;
end if;
s_check_code_viol_p <= s_sample_bit_p_d2; -- 2 uclk ticks delay
s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i;
end if;
end if;
end process;
......
wf_model_constr_decoder.vhd
View file @ ad26318d
......@@ -49,8 +49,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -107,14 +107,11 @@ entity WF_model_constr_decoder is
end entity WF_model_constr_decoder;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_model_constr_decoder is
signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
......
wf_package.vhd
View file @ ad26318d
This diff is collapsed.
wf_prod_bytes_retriever.vhd
View file @ ad26318d
This diff is collapsed.
wf_prod_bytes_to_dati.vhd deleted 100644 → 0
View file @ 4abbe8b9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_prod_bytes_from_dati.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_bytes_from_dati --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Unit responsible for the sampling of the DAT_I bus in stand-alone operation.
--! Following to the functional specs page 15, in stand-alone mode, the nanoFIP
--! samples the data on the first clock cycle after the de-assertion of VAR3_RDY.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 04/01/2011
--
--
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_prod_permit \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 4/1/2011 v0.02 EG unit renamed from WF_slone_prod_dati_bytes_sampler to
--! WF_prod_bytes_from_dati; cleaning-up + commenting
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_prod_bytes_from_dati
--=================================================================================================
entity WF_prod_bytes_from_dati is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- Signals from the WF_engine_control unit
byte_index_i : in std_logic_vector (7 downto 0); --! index of the byte to be produced
-- Signals from the WF_prod_permit unit
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- OUTPUTS
-- Signal to the WF_prod_bytes_retriever
slone_byte_o : out std_logic_vector (7 downto 0) --! sampled byte to be sent
);
end entity WF_prod_bytes_from_dati;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_bytes_from_dati is
signal s_var3_rdy_d4 : std_logic_vector (3 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Sample_DAT_I_bus: the sampling of the DAT_I bus in stand-alone mode
--! has to take place on the first clock cycle after the de-assertion of VAR3_RDY.
--! Note: Since slone_data_i is the triply registered version of the bus DAT_I (for synchronization),
--! the signal VAR3_RDY has to be (internally) delayed for 3 uclk cycles too, before the sampling;
--! the 4th delay is added in order to have the sampling 1 uclk AFTER the de-assertion.
Sample_DAT_I_bus: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var3_rdy_d4 <= (others=>'0');
s_sampled_data <= (others=>'0');
else
s_var3_rdy_d4 <= s_var3_rdy_d4(2 downto 0) & var3_rdy_i;
if s_var3_rdy_d4(3) = '1' then -- data latching
s_sampled_data <= slone_data_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
slone_byte_o <= s_sampled_data(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX
else s_sampled_data(15 downto 8);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_prod_data_lgth_calc.vhd
View file @ ad26318d
......@@ -63,8 +63,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
--! \n<b>Dependencies:</b> \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -95,19 +95,19 @@ entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length
-- User Interface, General signals
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode
-- Signal from the WF_engine_control unit
var_i : in t_var; --! variable type that is being treated
var_i : in t_var; --! variable type that is being treated
-- OUTPUT
-- Signal to the WF_engine_control and WF_production units
prod_data_length_o : out std_logic_vector (7 downto 0)
prod_data_lgth_o : out std_logic_vector (7 downto 0)
);
end entity WF_prod_data_lgth_calc;
......@@ -116,9 +116,10 @@ end entity WF_prod_data_lgth_calc;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_data_lgth_calc is
architecture behavior of WF_prod_data_lgth_calc is
signal s_prod_data_lgth, s_p3_lgth_decoded : unsigned (7 downto 0);
signal s_prod_data_length, s_p3_length_decoded : unsigned (7 downto 0);
--=================================================================================================
-- architecture begin
......@@ -131,10 +132,10 @@ begin
--! of the presence and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the calculation.
data_length_calcul: process (var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i)
data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i)
begin
s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
s_p3_lgth_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
case var_i is
......@@ -142,13 +143,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_prod_data_length <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_length;
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_prod_data_length <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_length;
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
......@@ -162,7 +163,7 @@ begin
-- 1 byte MPS status
-- optionally 1 byte nFIP status
-- in memory mode the signal "s_p3_length_decoded" indicates the amount of user-data
-- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data
-- to these, there should be added 1 byte Control
-- 1 byte PDU_TYPE
-- 1 byte Length
......@@ -172,39 +173,40 @@ begin
if slone_i = '1' then
if nostat_i = '1' then -- 6 bytes (counting starts from 0)
s_prod_data_length <= to_unsigned(5, s_prod_data_length'length);
s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length);
else -- 7 bytes
s_prod_data_length <= to_unsigned(6, s_prod_data_length'length);
s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length);
end if;
else
if nostat_i = '0' then
s_prod_data_length <= s_p3_length_decoded + 4;
s_prod_data_lgth <= s_p3_lgth_decoded + 4;
else
s_prod_data_length <= s_p3_length_decoded + 3;
end if;
end if;
else
s_prod_data_lgth <= s_p3_lgth_decoded + 3;
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_1 | var_2 | var_rst =>
s_prod_data_length <= (others => '0');
s_prod_data_lgth <= (others => '0');
when others =>
s_prod_data_length <= (others => '0');
s_prod_data_lgth <= (others => '0');
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment for the output
prod_data_length_o <= std_logic_vector (s_prod_data_length);
prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth);
end architecture rtl;
end architecture behavior;
--=================================================================================================
-- architecture end
--=================================================================================================
......
wf_prod_permit.vhd
View file @ ad26318d
......@@ -44,8 +44,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
--! WF_reset_unit \n
--! WF_engine_control \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -62,13 +62,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 5, 6 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the variables var_1, var_2, var_3 and var_rst. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......
wf_production.vhd
View file @ ad26318d
......@@ -47,28 +47,28 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o WF_prod_permit : that signals the user that user-data bytes can safely be
--! written
--!
--! ___________________________________________________________
--! | WF_production |
--! | |
--! | _________________________________ |
--! | | | |
--! | | WF_prod_permit | |
--! | |_________________________________| |
--! | |
--! | _________________________________ ________________ |
--! | | | | | |
--! | | WF_prod_bytes_retriever | < | WF_status_bytes| |
--! | | | | _gen | |
--! | |_________________________________| |________________| |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________
--! | |
--! | WF_fd_transmitter |
--! |___________________________________________________________|
--! \/
--! ______________________________________________________
--! 0______________________FIELDBUS________________________O
--! ___________________________________________________________
--! | WF_production |
--! | |
--! | _________________________________ |
--! | | | |
--! | | WF_prod_permit | |
--! | |_________________________________| |
--! | |
--! | _________________________________ ________________ |
--! | | | | | |
--! | | WF_prod_bytes_retriever | < | WF_status_bytes| |
--! | | | | _gen | |
--! | |_________________________________| |________________| |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________
--! | |
--! | WF_fd_transmitter |
--! |___________________________________________________________|
--! \/
--! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O
--!
--! Note: In the entity declaration of this unit, below each input signal, we mark
--! which of the instantiated units needs it.
......@@ -91,6 +91,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! WF_reset_unit \n
--! WF_consumption \n
--! WF_engine_control \n
--! WF_wb_controller \n
--! WF_fd_transmitter \n
--! WF_model_constr_decoder \n
--
......@@ -109,11 +110,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -185,7 +181,7 @@ entity WF_production is
-- Signals from the WF_engine_control
byte_index_i : in std_logic_vector (7 downto 0);
data_length_i : in std_logic_vector (7 downto 0);
data_lgth_i : in std_logic_vector (7 downto 0);
byte_request_accept_p_i : in std_logic;
var_i : in t_var;-- also for the WF_prod_permit for the VAR3_RDY generation
-- used by: WF_prod_bytes_retriever for the definition of the bytes to be delivered
......@@ -197,7 +193,7 @@ entity WF_production is
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_tler_p_i : in std_logic;
-- used by: WF_status_bytes_gen for the generation of the nanoFIP status byte, bits 2, 4, 5
......@@ -280,7 +276,7 @@ begin
var_i => var_i,
byte_index_i => byte_index_i,
byte_being_sent_p_i => byte_request_accept_p_i,
data_length_i => data_length_i,
data_lgth_i => data_lgth_i,
wb_data_i => wb_data_i,
slone_data_i => slone_data_i,
var3_rdy_i => s_var3_rdy,
......@@ -311,7 +307,7 @@ begin
var1_acc_a_i => var1_acc_a_i,
var2_acc_a_i => var2_acc_a_i,
var3_acc_a_i => var3_acc_a_i,
nfip_status_r_tler_i => nfip_status_r_tler_i,
nfip_status_r_tler_p_i => nfip_status_r_tler_p_i,
rst_status_bytes_p_i => s_rst_status_bytes_p,
-----------------------------------------------
u_cacer_o => u_cacer_o,
......
wf_reset_unit.vhd
View file @ ad26318d
......@@ -213,13 +213,13 @@ end entity WF_reset_unit;
architecture rtl of WF_reset_unit is
signal s_counter_is_four, s_reinit_counter, s_rston, s_FD_rst_from_var_rst : std_logic;
signal s_u_por_ff1, s_u_por, s_wb_por_ff1, s_wb_por : std_logic;
signal s_u_por_ff1, s_u_por, s_wb_por_ff1, s_wb_por : std_logic;
signal s_intern_rst_from_RSTIN, s_intern_rst_from_var_rst, s_fd_rst_from_RSTIN : std_logic;
signal s_counter_is_ten, s_counter_is_full, s_counter_full : std_logic;
signal s_var_rst_counter_is_eight, s_var_rst_counter_is_two : std_logic;
signal s_var_rst_reinit_counter, s_var_rst_counter_is_full, s_var_rst_counter_full : std_logic;
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_c, s_var_rst_c, s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_c, s_var_rst_c, s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
type rstin_st_t is (idle, rstin_eval, intern_rst_ON_FD_rst_ON,intern_rst_OFF_FD_rst_ON);
type after_a_var_rst_t is (after_a_var_rst_idle, after_a_var_rst_rston_ON,
......@@ -447,13 +447,15 @@ begin
--!@brief Instantiation of a WF_incr_counter: the counter counts from 0 to 4 FD_TXCK.
RSTIN_free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LENGTH)
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_reinit_counter,
incr_counter_i => '1',
counter_o => s_c,
counter_is_full_o => open);
counter_is_full_o => open,
----------------------------------------
counter_o => s_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_counter_is_four <= '1' when s_c = to_unsigned(4, s_c'length) else '0';
......@@ -468,12 +470,12 @@ RSTIN_free_counter: WF_incr_counter
--!@brief Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
--! to store the current state, a combinatorial process to manage state transitions and finally a
--! combinatorial process to manage the output signals), which are the three processes that follow.
--! If after the reception or a var_rst the signal assert_RSTON_p_i is asserted, the FSM
--! If after the reception of a var_rst the signal assert_RSTON_p_i is asserted, the FSM
--! asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
--! If after the reception or a var_rst the signal rst_nFIP_and_FD_p_i is asserted, the FSM
--! If after the reception of a var_rst the signal rst_nFIP_and_FD_p_i is asserted, the FSM
--! asserts the nanoFIP internal reset (s_intern_rst_from_var_rst) for 2 uclk cycles and the
--! "nanoFIP FIELDRIVE" output (s_FD_rst_from_var_rst) for 4 FD_TXCK cycles.
--! If after the reception or a var_rst both assert_RSTON_p_i and rst_nFIP_and_FD_p_i
--! If after the reception of a var_rst both assert_RSTON_p_i and rst_nFIP_and_FD_p_i
--! are asserted, the FSM asserts the s_intern_rst_from_var_rst for 2 uclk cycles, the RSTON for 8
--! uclk cycles and the s_FD_rst_from_var_rst for 4 FD_TXCK cycles.
--! The same counter is used for all the countings!
......@@ -666,13 +668,15 @@ RSTIN_free_counter: WF_incr_counter
--! from 0 to 4 * FD_TXCK, if rst_nFIP_and_FD_p has been activated.
free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LENGTH)
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_var_rst_reinit_counter,
incr_counter_i => '1',
counter_o => s_var_rst_c,
counter_is_full_o => open);
counter_is_full_o => open,
----------------------------------------
counter_o => s_var_rst_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_counter_is_eight <= '1' when s_var_rst_c= to_unsigned(8, s_var_rst_c'length) else '0';
......
wf_rx_deglitcher.vhd
View file @ ad26318d
......@@ -43,8 +43,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -100,10 +100,12 @@ end WF_rx_deglitcher;
--=================================================================================================
architecture Behavioral of WF_rx_deglitcher is
signal s_rxd_filtered, s_rxd_filtered_d1 : std_logic;
signal s_rxd_filtered_r_edge_p, s_rxd_filtered_f_edge_p : std_logic;
signal s_deglitch_c : unsigned (3 downto 0);
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
signal s_rxd_filtered, s_rxd_filtered_d1 : std_logic;
signal s_rxd_filtered_r_edge_p : std_logic;
signal s_rxd_filtered_f_edge_p : std_logic;
signal s_fd_rxd_no_activity : std_logic;
signal s_deglitch_c : unsigned (3 downto 0);
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
--=================================================================================================
......@@ -168,6 +170,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignments
......
wf_rx_deserializer.vhd
View file @ ad26318d
This diff is collapsed.
wf_rx_osc.vhd
View file @ ad26318d
......@@ -25,7 +25,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
---------------------------------------------------------------------------------------------------
--
--! @brief Generation the clock signals needed for the reception (WF_rx_deserializer).
--! @brief Generation of the clock signals needed for the reception (WF_rx_deserializer).
--!
--! Even if the bit rate of the communication is known, jitter is expected to affect the
--! arriving time of the incoming signal. The main idea of the unit is to recalculate
......@@ -50,10 +50,10 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.04
--
--
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_deglitcher \n
--! WF_rx_deserializer\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_deglitcher \n
--! WF_rx_deserializer \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -126,8 +126,8 @@ end entity WF_rx_osc;
--=================================================================================================
architecture rtl of WF_rx_osc is
signal s_period_c, s_period, s_jitter : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_half_period, s_one_forth_period : unsigned (c_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_period_c, s_period, s_jitter : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_half_period, s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_reinit_counter, s_counter_is_full : std_logic;
signal s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
......@@ -161,7 +161,7 @@ begin
--! the counter is reinitialialized.
rx_periods_count: WF_incr_counter
generic map (g_counter_lgth => c_PERIODS_COUNTER_LENGTH)
generic map (g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_reinit_counter,
......@@ -198,76 +198,76 @@ begin
-- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
-- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
rx_clks: process (uclk_i)
rx_clks: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') then
s_manch_clk <='0';
s_bit_clk <='0';
s_bit_clk_d1 <='0';
s_manch_clk_d1 <='0';
s_signif_edge_found <='0';
s_adjac_bits_edge_found <='0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding significant edges:
-- looking for a significant edge inside the corresponding window
if (s_signif_edge_window = '1') and (fd_rxd_edge_p_i = '1') and (s_signif_edge_found = '0') then
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') then
s_manch_clk <='0';
s_bit_clk <='0';
s_bit_clk_d1 <='0';
s_manch_clk_d1 <='0';
s_signif_edge_found <='0';
s_adjac_bits_edge_found <='0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding significant edges:
-- looking for a significant edge inside the corresponding window
if (s_signif_edge_window = '1') and (fd_rxd_edge_p_i = '1') and (s_signif_edge_found = '0') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
-- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_period_c = s_jitter) then
-- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_period_c = s_jitter) then
s_manch_clk <= not s_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
-- next cycle
s_manch_clk <= not s_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
-- next cycle
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding edges between adjacent bits:
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding edges between adjacent bits:
-- looking for an edge inside the corresponding window
elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then
-- looking for an edge inside the corresponding window
elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_bit_clk <= not s_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_bit_clk <= not s_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
s_signif_edge_found <= '0'; -- re-initialization before next cycle
s_signif_edge_found <= '0'; -- re-initialization before next cycle
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_jitter) then
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_jitter) then
s_manch_clk <= not s_manch_clk;
s_bit_clk <= not s_bit_clk;
s_manch_clk <= not s_manch_clk;
s_bit_clk <= not s_bit_clk;
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_clk_d1 <= s_manch_clk;
-- s_manch_clk: ____|-----|_____|-----|____
-- s_manch_clk_d1: ______|-----|_____|-----|__
-- rx_manch_clk_p_o: ____|-|___|-|___|-|___|-|__
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_clk_d1 <= s_manch_clk;
-- s_manch_clk: ____|-----|_____|-----|____
-- s_manch_clk_d1: ______|-----|_____|-----|__
-- rx_manch_clk_p_o: ____|-|___|-|___|-|___|-|__
s_bit_clk_d1 <= s_bit_clk;
-- s_bit_clk: ____|-----------|___________
-- s_bit_clk_d1: ______|-----------|_________
-- rx_bit_clk_p_o: ____|-|_________|-|_________
s_bit_clk_d1 <= s_bit_clk;
-- s_bit_clk: ____|-----------|___________
-- s_bit_clk_d1: ______|-----------|_________
-- rx_bit_clk_p_o: ____|-|_________|-|_________
end if;
end if;
end process;
end if;
end process;
......
wf_rx_tx_osc.vhd deleted 100644 → 0
View file @ 4abbe8b9
This diff is collapsed.
wf_status_bytes_gen.vhd
View file @ ad26318d
......@@ -100,16 +100,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_consumption \n
--! WF_bytes_retriever \n
--! WF_prod_permit \n
--! WF_reset_unit \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_consumption \n
--! WF_prod_bytes_retriever \n
--! WF_prod_permit \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -117,9 +118,9 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 07/07/2009 v0.01 PA First version \n
--! -> 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status
--! errors few cycles after var_rdy deactivation
--! -> 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_i
--! -> 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_p_i
--! for nanoFIP status bit 4; var_i input not needed as the signals
--! nfip_status_r_fcser_p_i and nfip_status_r_tler_i check the var
--! nfip_status_r_fcser_p_i and nfip_status_r_tler_p_i check the var
--
---------------------------------------------------------------------------------------------------
--
......@@ -154,7 +155,7 @@ port (
-- Signals from the WF_consumption unit
nfip_status_r_fcser_p_i : in std_logic; --! wrong CRC bytes received
nfip_status_r_tler_i : in std_logic; --! wrong PDU_TYPE, Control or Length bytes received
nfip_status_r_tler_p_i : in std_logic; --! wrong PDU_TYPE, Control or Length bytes received
var1_rdy_i : in std_logic; --! variable 1 ready
var2_rdy_i : in std_logic; --! variable 2 ready
......@@ -334,7 +335,7 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_wder
if (s_fd_wdg_synch(2) = '1') then -- FIELDRIVE transmission error
if (s_fd_wdg_synch(2) = '1') then -- FIELDRIVE transmission error
s_nFIP_status_byte(c_T_WDER_INDEX) <= '1';
end if;
......@@ -348,13 +349,15 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
s_nFIP_status_byte(c_R_TLER_INDEX) <= nfip_status_r_tler_i;
if (nfip_status_r_tler_p_i = '1') then
s_nFIP_status_byte(c_R_TLER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
s_nFIP_status_byte(c_R_FCSER_INDEX) <= nfip_status_r_fcser_p_i;
if (nfip_status_r_fcser_p_i = '1') then
s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......
wf_tx_osc.vhd
View file @ ad26318d
......@@ -25,16 +25,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
---------------------------------------------------------------------------------------------------
--
--! @brief Generation the clock signals needed for the transmission (WF_tx_serializer)\n
--! @brief Generation of the clock signals needed for the transmission (WF_tx_serializer)\n
--!
--! The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock)
--! and the nanoFIP internal signal tx_clk_p_buff:
--!
--! FD_TXCK : ___|--------...--------|________...________|--------...--------|_
--! tx_clk_p_buff(3) : |0|0|0|1 |0|0|0|1
--! tx_clk_p_buff(2) : |0|0|1|0 |0|0|1|0
--! tx_clk_p_buff(1) : |0|1|0|0 |0|1|0|0
--! tx_clk_p_buff(0) : |1|0|0|0 |1|0|0|0
--!
--! uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|
--! FD_TXCK : _____|--------...--------|________...________|--------...--------|__
--! tx_clk_p_buff(3) : 0 0 0 1 0 0 0 1
--! tx_clk_p_buff(2) : 0 0 1 0 0 0 1 0
--! tx_clk_p_buff(1) : 0 1 0 0 0 1 0 0
--! tx_clk_p_buff(0) : 1 0 0 0 1 0 0 0
--!
--
--
......@@ -64,7 +65,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned;
--! c_TX_CLK_BUFF_LGTH got 1 bit more\n
--! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_rst_p_i
--! -> 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_osc_rst_p_i
--
---------------------------------------------------------------------------------------------------
--
......@@ -89,7 +90,7 @@ entity WF_tx_osc is
nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control
tx_rst_p_i : in std_logic; --! transmitter timeout
tx_osc_rst_p_i : in std_logic; --! transmitter timeout
-- OUTPUTS
......@@ -110,8 +111,8 @@ end entity WF_tx_osc;
--=================================================================================================
architecture rtl of WF_tx_osc is
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LENGTH -1 downto 0);
signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LENGTH -1 downto 0);
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p, s_counter_is_full, s_reinit_counter : std_logic;
......@@ -132,7 +133,7 @@ begin
--!@brief Instantiation of a WF_incr_counter counting transmission periods.
tx_periods_count: WF_incr_counter
generic map (g_counter_lgth => c_PERIODS_COUNTER_LENGTH)
generic map (g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_reinit_counter,
......@@ -144,9 +145,9 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- if the tx_rst_p_i is active or
-- if the tx_osc_rst_p_i is active or
-- if it fills up
s_reinit_counter <= nfip_rst_i or tx_rst_p_i or s_counter_is_full;
s_reinit_counter <= nfip_rst_i or tx_osc_rst_p_i or s_counter_is_full;
......@@ -176,7 +177,7 @@ begin
clk_Signals_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then
s_tx_clk_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
......
wf_tx_serializer.vhd
View file @ ad26318d
......@@ -110,8 +110,7 @@ entity WF_tx_serializer is
-- Signals from the WF_production
byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
-- Signals from the WF_engine_control
tx_rst_p_i : in std_logic;
-- Signals from the WF_engine_control unit
tx_start_p_i : in std_logic; --! indication for the start of the production
byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
......@@ -126,6 +125,9 @@ entity WF_tx_serializer is
-- Signal to the WF_engine_control unit
byte_request_p_o : out std_logic;
-- Signal to the WF_tx_osc unit
tx_osc_rst_p_o : out std_logic;
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; --! transmitter serial data
tx_enable_o : out std_logic --! transmitter enable
......@@ -144,6 +146,7 @@ architecture rtl of WF_tx_serializer is
send_fes, stop_transmission);
signal tx_state, nx_tx_state : tx_state_t;
signal s_session_timedout : std_logic;
signal s_prepare_to_produce, s_sending_fss, s_sending_data, s_sending_crc : std_logic;
signal s_sending_fes, s_stop_transmission, s_start_crc_p, s_data_bit_to_crc_p : std_logic;
signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero, s_tx_enable : std_logic;
......@@ -214,7 +217,7 @@ begin
--! transitions of the FSM
Serializer_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
tx_rst_p_i, tx_start_p_i, tx_clk_p_buff_i)
s_session_timedout,tx_start_p_i, tx_clk_p_buff_i)
begin
nx_tx_state <= idle;
......@@ -232,7 +235,7 @@ begin
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4) = '1' then
nx_tx_state <= send_fss;
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -241,10 +244,10 @@ begin
when send_fss =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1' then
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1') then
nx_tx_state <= send_data_byte;
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -256,7 +259,7 @@ begin
if last_byte_p_i = '1' then
nx_tx_state <= send_crc_bytes;
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -265,11 +268,11 @@ begin
when send_crc_bytes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= send_fes; -- state change early enough (tx_clk_p_buff_i(2))
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_clk_p_buff_i(3), to get the 31 as top value
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -279,11 +282,11 @@ begin
when send_fes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
if (s_bit_index_is_zero = '1') and (tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1') then
nx_tx_state <= stop_transmission; -- state change early enough (tx_clk_p_buff_i(2))
-- for the Outgoing_Bits_Index that is loaded on
-- tx_clk_p_buff_i(3) to get the 15 as top value
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -295,7 +298,7 @@ begin
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= idle;
elsif tx_rst_p_i = '1' then
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
else
......@@ -449,7 +452,7 @@ Input_Byte_Retrieval: process (uclk_i)
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
crc_ok_p => open,
crc_ok_p_o => open,
-------------------------------------------------
crc_o => s_crc_bytes);
-------------------------------------------------
......@@ -541,23 +544,45 @@ Input_Byte_Retrieval: process (uclk_i)
--! The unit also generates the tx_enable_o signal.
bits_to_txd: WF_bits_to_txd
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch,
sending_fss_i => s_sending_fss,
sending_data_i => s_sending_data,
sending_crc_i => s_sending_crc,
sending_fes_i => s_sending_fes,
stop_transmission_i => s_stop_transmission,
tx_clk_p_i => tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-3),
---------------------------------------------
txd_o => s_txd,
tx_enable_o => s_tx_enable);
---------------------------------------------
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch,
sending_fss_i => s_sending_fss,
sending_data_i => s_sending_data,
sending_crc_i => s_sending_crc,
sending_fes_i => s_sending_fes,
stop_transmission_i => s_stop_transmission,
tx_clk_p_i => tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-3),
---------------------------------------------
txd_o => s_txd,
tx_enable_o => s_tx_enable);
---------------------------------------------
---------------------------------------------------------------------------------------------------
-- Independant Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_decr_counter relying only on the system clock as an additional
--! way to go back to Idle state, in case any other logic is being stuck.
Session_Timeout_Counter: WF_decr_counter
generic map (g_counter_lgth => 21)
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => (others => '1'),
counter_load_i => s_prepare_to_produce,
counter_decr_p_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
......@@ -569,6 +594,8 @@ Input_Byte_Retrieval: process (uclk_i)
tx_enable_o <= s_tx_enable;
tx_osc_rst_p_o <= s_session_timedout;
byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
-- request for a new byte from the WF_prod_bytes_retriever unit (passing from WF_engine_control)
......
wf_wb_controller.vhd
View file @ ad26318d
......@@ -45,7 +45,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
--! \n<b>Dependencies:</b> \n
--! WF_production \n
--! WF_consumption \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -63,11 +62,6 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
......@@ -107,10 +101,13 @@ architecture rtl of WF_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_stb_r_edge_p : std_logic;
signal s_wb_we_d3, s_wb_cyc_d3 : std_logic_vector (2 downto 0);
signal s_wb_stb_d4 : std_logic_vector (3 downto 0);
signal s_wb_we_synch, s_wb_cyc_synch : std_logic_vector (2 downto 0);
signal s_wb_stb_synch : std_logic_vector (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
......@@ -120,20 +117,20 @@ begin
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_stb_d4 <= (others => '0');
s_wb_cyc_d3 <= (others => '0');
s_wb_we_d3 <= (others => '0');
s_wb_stb_synch <= (others => '0');
s_wb_cyc_synch <= (others => '0');
s_wb_we_synch <= (others => '0');
else
s_wb_stb_d4 <= s_wb_stb_d4 (2 downto 0) & wb_stb_i;
s_wb_cyc_d3 <= s_wb_cyc_d3 (1 downto 0) & wb_cyc_i;
s_wb_we_d3 <= s_wb_we_d3 (1 downto 0) & wb_we_i;
s_wb_stb_synch <= s_wb_stb_synch (2 downto 0) & wb_stb_i;
s_wb_cyc_synch <= s_wb_cyc_synch (1 downto 0) & wb_cyc_i;
s_wb_we_synch <= s_wb_we_synch (1 downto 0) & wb_we_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_wb_stb_r_edge_p <= (not s_wb_stb_d4(3)) and s_wb_stb_d4(2);
s_wb_stb_r_edge_p <= (not s_wb_stb_synch(3)) and s_wb_stb_synch(2);
---------------------------------------------------------------------------------------------------
......@@ -143,8 +140,8 @@ begin
--! address corresponds to an address in the Produced memory block.
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_d3 (2) = '1') and
(s_wb_cyc_d3(2) = '1') and
(s_wb_we_synch (2) = '1') and
(s_wb_cyc_synch(2) = '1') and
(wb_adr_id_i = "010"))
else '0';
......@@ -156,8 +153,8 @@ begin
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_cyc_d3(2) = '1') and
(s_wb_we_d3(2) = '0') and
(s_wb_cyc_synch(2) = '1') and
(s_wb_we_synch(2) = '0') and
(wb_adr_id_i(2 downto 1) = "00"))
else '0';
......
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