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nanoFIP - Gateware
Commit c0ef0386 authored by egousiou's avatar egousiou
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wf_rx: renamed to wf_rx_deserializer.vhd 

wf_tx: renamed to wf_tx_serializer
wf_deglitcher: renamed to wf_rx_deglitcher
wf_cons_bytes_from_rx: renamed to wf_cons_bytes_processor
wf_slone_bytes_to_DATO renamed to: wf_bytes_to_dato
wf_prod_bytes_to_tx renamed to: wf_prod_bytes_retriever
wf_slone_prod_DATI_bytes_sampler renamed to wf_prod_bytes_to_dati
new nanoFIP outputs added: u_cacer, u_pacer, r_tler, r_fcser; fx_rxd, fx_rxa, fx_txd renamed to fd_rxd, fd_rxcdn, fd_txd; pdc file updated as well.
no broadcast vars in slone mode finally!
broadcast var 91h instead of 04h.
wf_crc: timing for checking the crc bytes changed (before there was no check with respect to the FES)
wf_engine_control: removed the check of # bytes in slone mode; if > 2 data bytes arrive, nanoFIP puts to DATO the first 2.
new units wf_production and wf_consumption created to clearify the structure!


git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@103 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 24c51736
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Showing with 4842 additions and 2374 deletions
DualClkRAM.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -26,30 +26,30 @@ use PROASIC3.all;
---------------------------------------------------------------------------------------------------
-- --
-- DualClkRAM --
-- DualClkRAM --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Instantiation of a template RAM4K9 component with
--! word width: 8 bits (1 byte) and
--! memory depth: 512 bytes.
--! @brief Instantiation of a template RAM4K9 memory component with
--! word width : 8 bits and
--! depth : 512 bytes.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 16/08/2010
--! @date 15/12/2010
--
--
--! @version v0.1
--! @version v0.02
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! no dependancies \n
--! ProASIC3 lib \n
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
......@@ -57,14 +57,14 @@ use PROASIC3.all;
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes: </b>\n
--! -> pepeline not used! data appears in output 1 clock cycle after the address is given
--! (otherwise it was 2 clock cycles later) slack checked and is ok!
--! -> code cleaned-up and commented \n
--! -> 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
--! address is given (otherwise it was 2 clock cycles later) slack
--! checked and is ok! code cleaned-up and commented \n
--! ->15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! -> explanation on blka, blkb \n
--
---------------------------------------------------------------------------------------------------
......@@ -77,26 +77,27 @@ entity DualClkRAM is
port(
-- INPUTS
-- Inpouts concerning port A
DINA : in std_logic_vector (7 downto 0); --! data in A
ADDRA : in std_logic_vector (8 downto 0); --! address A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKA : in std_logic; --! clock A for synchronous read/ write operations
-- may be indipendant of clock B
DINA : in std_logic_vector (7 downto 0); --! data in A
ADDRA : in std_logic_vector (8 downto 0); --! address A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKA : in std_logic; --! clock A for synchronous read/ write operations
-- may be indipendant of clock B
-- Inpouts concerning port B
DINB : in std_logic_vector (7 downto 0); --! data in B
ADDRB : in std_logic_vector (8 downto 0); --! address B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKB : in std_logic; --! clock B for synchronous read/ write operations
-- may be indipendant of clock A
DINB : in std_logic_vector (7 downto 0); --! data in B
ADDRB : in std_logic_vector (8 downto 0); --! address B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKB : in std_logic; --! clock B for synchronous read/ write operations
-- may be indipendant of clock A
-- Reset
RESETn : in std_logic; --! sets all outputs low; does not reset the memory
RESETn : in std_logic; --! sets all outputs low; does not reset the memory
-- OUTPUTS
-- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0);--! data out A
DOUTA : out std_logic_vector (7 downto 0);--! data out A
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) --! data out B
DOUTB : out std_logic_vector (7 downto 0) --! data out B
);
end DualClkRAM;
......@@ -107,33 +108,33 @@ entity DualClkRAM is
architecture RAM4K9 of DualClkRAM is
---------------------------------------------------------------------------------------------------
-- !@brief component RAM4K9:
-- !@brief component RAM4K9 :
--! General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional
--! pipeline stage. It provides variable aspect ratios of 4096 x 1, 2048 x 2, 1024 x 4 and 512 x 9.
--! Both ports are capable of reading and writing, making it possible to write with both ports or
--! read with both ports simultaneously. Moreover, reading from one port while writing to the other
--! is possible.
--! WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1:
--! WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1 :
--! Apect ratio configuration.
--! WENA, WENB
--! WENA, WENB :
--! Switching between Read and Write modes for the respective ports.
--! A Low indicates Write operation and a High indicates a Read.
--! BLKA, BLKB: *******************************************************************
--! These signals are active low and will enable the respective ports when asserted.
--! When BLK signals are de-asserted the output holds the previous value.
--! BLKA, BLKB :
--! Activw low enable for the respective ports.
--! PIPEA, PIPEB
--! PIPEA, PIPEB :
--! Control of the optional pipeline stages.
--! A Low on the PIPEA or PIPEB indicates a non-pipelined Read and the data appears on the output
--! in the same clock cycle.
--! A High indicates a pipelined Read and data appears on the output in the next clock cycle.
--! WMODEA, WMODEB
--! WMODEA, WMODEB :
--! Configuration of the behavior of the output when the RAM is in the Write mode.
--! A Low on this signal makes the output retain data from the previous Read.
--! A Low on this signal makes the output retain data from the previous Read. A High indicates a
--! pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
......@@ -153,7 +154,7 @@ architecture RAM4K9 of DualClkRAM is
BLKA, BLKB,
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic := 'U';
RESET : in std_logic:= 'U';
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic
......@@ -164,14 +165,14 @@ architecture RAM4K9 of DualClkRAM is
--!@brief Instantiation of the component VCC
component VCC
port( Y : out std_logic);
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the component GND
component GND
port( Y : out std_logic);
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
......@@ -182,19 +183,19 @@ architecture RAM4K9 of DualClkRAM is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
power_supply_signal : VCC port map(Y => POWER);
ground_signal : GND port map(Y => GROUND);
begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
---------------------------------------------------------------------------------------------------
--!@brief: Instantiation of the component RAM4K9.
--! The following configuration has been applied:
--! aspect ratio: 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 to VCC)
--! word width: 8 bits (1 byte); DINA8, DINB8: GND, DOUTA8, DOUTB8: open
--! memory depth: 512 bytes; ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GND
--! BLKA, BLKB: GND
--! PIPEA, PIPEB: VCC (pipelined read; data appears on the output in the next clock cycle)
--! WMODEA, WMODEB: GND (in the write mode the output retains the data from the previous read)
--! aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
--! word width : 8 bits (DINA8, DINB8: GND, DOUTA8, DOUTB8 : open)
--! memory depth : 512 bytes (ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9 : GND)
--! BLKA, BLKB : GND
--! PIPEA, PIPEB : GND (not pipelined read)
--! WMODEA, WMODEB : GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
......@@ -232,7 +233,7 @@ architecture RAM4K9 of DualClkRAM is
WIDTHA0 => POWER,
WIDTHA1 => POWER,
BLKA => GROUND,
PIPEA => GROUND,--POWER,
PIPEA => GROUND,
WMODEA => GROUND,
-- INPUTS concerning port B
......@@ -267,7 +268,7 @@ architecture RAM4K9 of DualClkRAM is
WIDTHB0 => POWER,
WIDTHB1 => POWER,
BLKB => GROUND,
PIPEB => GROUND,--POWER,
PIPEB => GROUND,
WMODEB => GROUND,
-- reset
......
NanoFip.pdc
View file @ c0ef0386
......@@ -333,19 +333,19 @@ set_io fd_wdgn_i \
-DIRECTION Input
set_io fx_rxa_i \
set_io fd_rxcdn_i \
-pinname 121 \
-fixed yes \
-DIRECTION Input
set_io fx_rxd_i \
set_io fd_rxd_i \
-pinname 127 \
-fixed yes \
-DIRECTION Input
set_io fx_txd_o \
set_io fd_txd_o \
-pinname 131 \
-fixed yes \
-DIRECTION Output
......@@ -554,8 +554,25 @@ set_io we_i \
-fixed yes \
-DIRECTION Input
set_io u_cacer_o \
-pinname 78 \
-fixed yes \
-DIRECTION Output
set_io u_pacer_o \
-pinname 79 \
-fixed yes \
-DIRECTION Output
set_io r_tler_o \
-pinname 80 \
-fixed yes \
-DIRECTION Output
set_io r_fcser_o \
-pinname 85 \
-fixed yes \
-DIRECTION Output
#
# Non IO constraints
#
......
nanofip.vhd
View file @ c0ef0386
......@@ -10,7 +10,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- library synplify;
-- use synplify.attributes.all;
......@@ -58,7 +58,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! <HR>
--! @image html nanofip_image_1s.gif "Block diagram of the NanoFIP design"
--!
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--
--! @date 07/07/2009
--
......@@ -96,68 +96,69 @@ entity nanofip is
port (
-- WorldFIP settings
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- FIELDRIVE connections
fx_rxa_i : in std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
fd_rxcdn_i : in std_logic; --! Reception activity detection
fd_rxd_i : in std_logic; --! Receiver data
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fx_txd_o : out std_logic; --! Transmitter data
fd_rstn_o : out std_logic; --! Initialisation control, active low
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fd_txd_o : out std_logic; --! Transmitter data
fd_rstn_o : out std_logic; --! Initialisation control, active low
-- USER INTERFACE, General signals
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! No NanoFIP status transmission
rstin_i : in std_logic; --! Initialisation control, active low
uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! No NanoFIP status transmission
rstin_i : in std_logic; --! Initialisation control, active low
rston_o : out std_logic; --! Reset output, active low
rston_o : out std_logic; --! Reset output, active low
-- USER INTERFACE, non WISHBONE
-- USER INTERFACE, NON WISHBONE
var1_acc_i: in std_logic; --! Variable 1 access
var2_acc_i: in std_logic; --! Variable 2 access
var3_acc_i: in std_logic; --! Variable 3 access
var1_acc_i : in std_logic; --! Variable 1 access
var2_acc_i : in std_logic; --! Variable 2 access
var3_acc_i : in std_logic; --! Variable 3 access
var1_rdy_o: out std_logic; --! Variable 1 ready
var2_rdy_o: out std_logic; --! Variable 2 ready
var3_rdy_o: out std_logic; --! Variable 3 ready
var1_rdy_o : out std_logic; --! Variable 1 ready
var2_rdy_o : out std_logic; --! Variable 2 ready
var3_rdy_o : out std_logic; --! Variable 3 ready
u_cacer_o : out std_logic; --! nanoFIP status byte, bit 2
u_pacer_o : out std_logic; --! nanoFIP status byte, bit 3
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
-- USER INTERFACE, WISHBONE SLAVE
-- USER INTERFACE, WISHBONE Slave
wclk_i : in std_logic; --! WISHBONE clock. May be independent of UCLK.
rst_i : in std_logic; --! WISHBONE reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
cyc_i : in std_logic;
we_i : in std_logic; --! Write enable
adr_i : in std_logic_vector ( 9 downto 0); --! Address
DAT_I : in std_logic_vector (15 downto 0); --! Data in
DAT_O : out std_logic_vector (15 downto 0); --! Data out
ack_o : out std_logic --! Acknowledge
wclk_i : in std_logic; --! WISHBONE clock. May be independent of UCLK.
rst_i : in std_logic; --! WISHBONE reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
cyc_i : in std_logic;
we_i : in std_logic; --! Write enable
adr_i : in std_logic_vector ( 9 downto 0); --! Address
dat_i : in std_logic_vector (15 downto 0); --! Data in
dat_o : out std_logic_vector (15 downto 0); --! Data out
ack_o : out std_logic --! Acknowledge
);
-- attribute syn_keep of fx_rxa_i : signal is true;
-- attribute syn_preserve of fx_rxa_i : signal is true;
-- attribute syn_insert_buffer : string;
-- attribute syn_insert_buffer of wbclk_i : signal is "GL25";
-- attribute syn_insert_buffer of clk_wb_i : signal is "GL25";
end entity nanofip;
--=================================================================================================
......@@ -173,69 +174,66 @@ end entity nanofip;
architecture struc of nanofip is
--=================================================================================================
-- TMR
attribute syn_radhardlevel : string;
-- Triple Module Redundancy
attribute syn_radhardlevel of struc: architecture is "tmr";
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of struc : architecture is "tmr";
--=================================================================================================
component CLKBUF
port (PAD : in std_logic;
Y : out std_logic);
port (PAD : in std_logic;
Y : out std_logic);
end component;
signal s_data_length_from_control : std_logic_vector (7 downto 0);
signal s_byte_to_tx : std_logic_vector (7 downto 0);
signal s_rst : std_logic;
signal s_start_send_p : std_logic;
signal s_request_byte_from_tx_p : std_logic;
signal s_byte_to_tx_ready_p : std_logic;
signal s_last_byte_to_tx_p : std_logic;
signal s_byte_from_rx_ready_p : std_logic;
signal s_byte_from_rx : std_logic_vector (7 downto 0);
signal s_cons_byte_we_from_control : std_logic;
signal s_rst, s_nfip_status_r_fcser_p : std_logic;
signal s_start_prod_p, s_rst_rx_osc : std_logic;
signal s_prod_request_byte_p, s_prod_sending_mps : std_logic;
signal s_prod_byte_ready_p : std_logic;
signal s_prod_last_byte_p : std_logic;
signal s_cons_byte_ready_p : std_logic;
signal s_cons_byte : std_logic_vector (7 downto 0);
signal s_cons_byte_ready_from_control : std_logic;
signal s_var_from_control : t_var;
signal s_add_offset_from_control : std_logic_vector (7 downto 0);
signal s_CRC_ok_from_rx, s_urst_r_edge : std_logic;
signal fss_decoded_p_from_rx, s_assert_RSTON_p : std_logic;
signal s_stat : std_logic_vector (7 downto 0);
signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_rst_status_bytes, s_sending_mps: std_logic;
signal s_crc_bad_p, s_reset_nFIP_and_FD_p : std_logic;
signal s_cons_prod_byte_index_from_control : std_logic_vector (7 downto 0);
signal s_fss_crc_fes_viol_ok_p, s_urst_r_edge : std_logic;
signal s_cons_fss_decoded_p, s_assert_RSTON_p : std_logic;
signal s_prod_ack, s_wb_ack_cons, s_ack_o: std_logic;
signal s_rst_status_bytes: std_logic;
signal s_cons_crc_wrong_p, s_reset_nFIP_and_FD_p : std_logic;
signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic;
signal s_mps : std_logic_vector (7 downto 0);
signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector (7 downto 0);
signal s_rst_rx_unit_p : std_logic;
signal s_ctrl_byte_received, s_pdu_byte_received, s_length_byte_received : std_logic_vector (7 downto 0);
signal s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_rst_rx_unit_p, s_nfip_status_r_tler, s_signif_edge_window, s_adjac_bits_window, s_rx_bit_clk_p, s_rx_manch_clk_p : std_logic;
signal s_cons_ctrl_byte, s_cons_PDU_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_urst_synch, s_slone_synch, s_nostat_synch, s_fd_wdgn_synch, s_fd_txer_synch: std_logic;
signal s_fd_rxd_synch, s_fd_rxd_edge, s_rxd_r_edge, s_rxd_f_edge, s_wb_cyc_synch: std_logic;
signal s_fd_rxd_synch, s_fd_rxd_edge_p, s_fd_rxd_r_edge_p, s_fd_rxd_f_edge_p, s_wb_cyc_synch: std_logic;
signal s_wb_we_synch, s_wb_stb_synch, s_wb_stb_r_edge: std_logic;
signal s_wb_dati_synch: std_logic_vector(7 downto 0);
signal s_wb_adri_synch: std_logic_vector(9 downto 0);
signal s_var1_access_synch, s_var2_access_synch, s_var3_access_synch: std_logic;
signal s_slone_dati_synch: std_logic_vector(15 downto 0);
signal s_rate_synch: std_logic_vector(1 downto 0);
signal s_subs_synch, s_rx_var_rst_byte_1, s_rx_var_rst_byte_2 : std_logic_vector(7 downto 0);
signal s_subs_synch, s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector(7 downto 0);
signal s_m_id_synch, s_c_id_synch : std_logic_vector(3 downto 0);
signal s_p3_lgth_synch : std_logic_vector(2 downto 0);
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
begin
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
reset_unit : WF_reset_unit
port map(
uclk_i => uclk_i,
urst_i => s_urst_synch,
rate_i => s_rate_synch,
rate_i => s_rate_synch,--------------------
urst_r_edge_i => s_urst_r_edge,
var_i => s_var_from_control,
subs_i => s_subs_synch,
subs_i => s_subs_synch,--------------------
rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p,
assert_RSTON_p_i => s_assert_RSTON_p,
rston_o => rston_o,
......@@ -245,41 +243,44 @@ begin
---------------------------------------------------------------------------------------------------
engine_control : WF_engine_control
generic map( C_QUARTZ_PERIOD => C_QUARTZ_PERIOD)
generic map( c_QUARTZ_PERIOD => c_QUARTZ_PERIOD)
port map(
uclk_i => uclk_i,
nFIP_urst_i => s_rst,
tx_request_byte_p_i => s_request_byte_from_tx_p,
rx_FSS_received_p_i => fss_decoded_p_from_rx,
rx_byte_ready_p_i => s_byte_from_rx_ready_p,
rx_byte_i => s_byte_from_rx,
rx_CRC_FES_ok_p_i => s_CRC_ok_from_rx,
tx_sending_mps_i => s_sending_mps,
rx_Ctrl_byte_i => s_ctrl_byte_received,
rx_PDU_byte_i => s_pdu_byte_received,
rx_Length_byte_i => s_length_byte_received,
rx_var_rst_byte_1_i => s_rx_var_rst_byte_1,
rx_var_rst_byte_2_i => s_rx_var_rst_byte_2,
rate_i => s_rate_synch,
subs_i => s_subs_synch,
p3_lgth_i => s_p3_lgth_synch,
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
tx_start_produce_p_o => s_start_send_p ,
tx_byte_ready_p_o => s_byte_to_tx_ready_p,
tx_last_byte_p_o => s_last_byte_to_tx_p,
tx_rx_byte_index_o => s_add_offset_from_control,
tx_data_length_o => s_data_length_from_control,
rx_byte_ready_p_o => s_cons_byte_we_from_control,
rst_rx_unit_p_o => s_rst_rx_unit_p,
assert_RSTON_p_o => s_assert_RSTON_p,
rst_nFIP_and_FD_p_o => s_reset_nFIP_and_FD_p,
rst_status_bytes_o => s_rst_status_bytes
uclk_i => uclk_i,
nfip_urst_i => s_rst,
tx_request_byte_p_i => s_prod_request_byte_p,
rx_FSS_received_p_i => s_cons_fss_decoded_p,
rx_byte_ready_p_i => s_cons_byte_ready_p,
rx_byte_i => s_cons_byte,
rx_CRC_FES_ok_p_i => s_fss_crc_fes_viol_ok_p,
rx_crc_wrong_p_i => s_cons_crc_wrong_p,
tx_sending_mps_i => s_prod_sending_mps,
rx_ctrl_byte_i => s_cons_ctrl_byte,
rx_pdu_byte_i => s_cons_PDU_byte,
rx_length_byte_i => s_cons_lgth_byte,
rx_var_rst_byte_1_i => s_cons_var_rst_byte_1,
rx_var_rst_byte_2_i => s_cons_var_rst_byte_2,
rate_i => s_rate_synch,----------------
subs_i => s_subs_synch,----------------
p3_lgth_i => s_p3_lgth_synch, ----------------------
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
tx_start_produce_p_o => s_start_prod_p ,
tx_byte_ready_p_o => s_prod_byte_ready_p,
tx_last_byte_p_o => s_prod_last_byte_p,
tx_rx_byte_index_o => s_cons_prod_byte_index_from_control,
tx_data_length_o => s_data_length_from_control,
rx_byte_ready_p_o => s_cons_byte_ready_from_control,
rst_rx_unit_p_o => s_rst_rx_unit_p,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p,
nfip_status_r_fcser_p_o => s_nfip_status_r_fcser_p,
rst_status_bytes_o => s_rst_status_bytes,
nfip_status_r_tler_o => s_nfip_status_r_tler
);
var1_rdy_o <= s_var1_rdy;
......@@ -287,119 +288,125 @@ begin
var3_rdy_o <= s_var3_rdy;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
Consumption: wf_consumption
port map(
uclk_i => uclk_i,
slone_i => slone_i,
nfip_urst_i => s_rst,
fd_rxd_i => s_fd_rxd_synch,
fd_rxd_r_edge_p_i => s_fd_rxd_r_edge_p,
fd_rxd_f_edge_p_i => s_fd_rxd_f_edge_p,
clk_wb_i => wclk_i,
wb_adr_i => s_wb_adri_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
wb_cyc_i => s_wb_cyc_synch,
var_i => s_var_from_control,
byte_ready_p_i => s_cons_byte_ready_from_control,
byte_index_i => s_cons_prod_byte_index_from_control,
rst_rx_unit_p_i => s_rst_rx_unit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
sample_bit_p_i => s_rx_bit_clk_p,
sample_manch_bit_p_i => s_rx_manch_clk_p,
---------------------------------------------------------------
data_o => dat_o,
wb_ack_cons_p_o => s_wb_ack_cons,
byte_o => s_cons_byte,
byte_ready_p_o => s_cons_byte_ready_p,
fss_received_p_o => s_cons_fss_decoded_p,
crc_wrong_p_o => s_cons_crc_wrong_p,
fss_crc_fes_viol_ok_p_o => s_fss_crc_fes_viol_ok_p,
cons_var_rst_byte_1_o => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_o => s_cons_var_rst_byte_2,
cons_ctrl_byte_o => s_cons_ctrl_byte,
cons_pdu_byte_o => s_cons_PDU_byte,
cons_lgth_byte_o => s_cons_lgth_byte,
rst_rx_osc_o => s_rst_rx_osc
---------------------------------------------------------------
);
tx_rx : WF_tx_rx
---------------------------------------------------------------------------------------------------
rx_tx_osc :WF_rx_tx_osc
generic map(C_PERIODS_COUNTER_LENGTH => 11,
c_TX_CLK_BUFF_LGTH => 4)
port map(
uclk_i => uclk_i,
nFIP_urst_i => s_rst,
rst_rx_unit_p_i => s_rst_rx_unit_p,
start_produce_p_i => s_start_send_p,
request_byte_p_o => s_request_byte_from_tx_p,
byte_ready_p_i => s_byte_to_tx_ready_p,
byte_i => s_byte_to_tx,
last_byte_p_i => s_last_byte_to_tx_p,
tx_data_o => fx_txd_o,
tx_enable_o => fd_txena_o,
d_clk_o => fd_txck_o,
fd_rxd => s_fd_rxd_synch,
fd_rxd_edge_i => s_fd_rxd_edge,
fd_rxd_r_edge_i => s_rxd_r_edge,
fd_rxd_f_edge_i => s_rxd_f_edge,
rate_i => s_rate_synch,
byte_ready_p_o => s_byte_from_rx_ready_p,
byte_o => s_byte_from_rx,
CRC_wrong_p_o => s_crc_bad_p,
FSS_received_p_o => fss_decoded_p_from_rx,
FSS_CRC_FES_viol_ok_p_o => s_CRC_ok_from_rx
nfip_urst_i => s_rst,
rxd_edge_i => s_fd_rxd_edge_p,
rst_rx_osc_i => s_rst_rx_osc,
rate_i => s_rate_synch,
tx_clk_p_buff_o => s_tx_clk_p_buff,
tx_clk_o => fd_txck_o,
rx_manch_clk_p_o => s_rx_manch_clk_p,
rx_bit_clk_p_o => s_rx_bit_clk_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window
);
---------------------------------------------------------------------------------------------------
consumed_vars : WF_cons_bytes_from_rx
port map(
uclk_i => uclk_i,
nFIP_urst_i => s_rst,
slone_i => s_slone_synch,
byte_ready_p_i => s_cons_byte_we_from_control,
var_i => s_var_from_control,
byte_index_i => s_add_offset_from_control,
byte_i => s_byte_from_rx,
wb_clk_i => wclk_i,
wb_adr_i => s_wb_adri_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
wb_cyc_i => s_wb_cyc_synch,
wb_ack_cons_p_o => s_ack_consumed,
data_o => DAT_O,
rx_Ctrl_byte_o => s_ctrl_byte_received,
rx_PDU_byte_o => s_PDU_byte_received,
rx_Length_byte_o => s_length_byte_received,
rx_var_rst_byte_1_o => s_rx_var_rst_byte_1,
rx_var_rst_byte_2_o => s_rx_var_rst_byte_2
);
---------------------------------------------------------------------------------------------------
produced_vars : WF_prod_bytes_to_tx
---------------------------------------------------------------------------------------------------
Production: wf_production
port map(
uclk_i => uclk_i,
slone_i => slone_i,
nostat_i => nostat_i,
nfip_urst_i => s_rst,
clk_wb_i => wclk_i,
wb_data_i => s_wb_dati_synch,
wb_adr_i => s_wb_adri_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
wb_we_i => s_wb_we_synch,
wb_cyc_i => s_wb_cyc_synch,
slone_data_i => s_slone_dati_synch,
var1_acc_i => s_var1_access_synch,
var2_acc_i => s_var2_access_synch,
var3_acc_i => s_var3_access_synch,
fd_txer_i => s_fd_txer_synch,
fd_wdgn_i => s_fd_wdgn_synch,
var_i => s_var_from_control,
data_length_i => s_data_length_from_control,
byte_index_i => s_cons_prod_byte_index_from_control,
start_prod_p_i => s_start_prod_p,
byte_ready_p_i => s_prod_byte_ready_p,
last_byte_p_i => s_prod_last_byte_p,
rst_status_bytes_i => s_rst_status_bytes,
nfip_status_r_tler_i => s_nfip_status_r_tler,
nfip_status_r_fcser_p_i => s_cons_crc_wrong_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
var3_rdy_i => s_var3_rdy,
tx_clk_p_buff_i => s_tx_clk_p_buff,
model_id_dec_i => s_model_id_dec,
constr_id_dec_i => s_constr_id_dec,
--------------------------------------------------------------------------
request_byte_p_o => s_prod_request_byte_p,
sending_mps_o => s_prod_sending_mps,
tx_data_o => fd_txd_o,
tx_enable_o => fd_txena_o,
u_cacer_o => u_cacer_o,
u_pacer_o => u_pacer_o,
r_tler_o => r_tler_o,
r_fcser_o => r_fcser_o,
wb_ack_prod_p_o => s_prod_ack
--------------------------------------------------------------------------
);
port map(
uclk_i => uclk_i,
m_id_dec_i => s_m_id_dec_o,
c_id_dec_i => s_c_id_dec_o,
slone_i => s_slone_synch,
nostat_i => s_nostat_synch,
nFIP_urst_i => s_rst,
wb_clk_i => wclk_i,
wb_adr_i => s_wb_adri_synch,
wb_stb_r_edge_p_i => s_wb_stb_r_edge,
wb_cyc_i => s_wb_cyc_synch,
wb_we_p_i => s_wb_we_synch,
nFIP_status_byte_i => s_stat,
mps_status_byte_i => s_mps,
var_i => s_var_from_control,
byte_index_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control,
wb_data_i => s_wb_dati_synch,
slone_data_i => s_slone_dati_synch,
var3_rdy_i => s_var3_rdy,
sending_mps_o => s_sending_mps,
byte_o => s_byte_to_tx,
wb_ack_prod_p_o => s_ack_produced
);
---------------------------------------------------------------------------------------------------
status_bytes_gen : WF_status_bytes_gen
port map(
uclk_i => uclk_i,
nFIP_urst_i => s_rst,
slone_i => s_slone_synch,
fd_wdgn_i => s_fd_wdgn_synch,
fd_txer_i => s_fd_txer_synch,
crc_wrong_p_i => s_crc_bad_p,
var_i => s_var_from_control,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
var3_rdy_i => s_var3_rdy,
var1_acc_i => s_var1_access_synch,
var2_acc_i => s_var2_access_synch,
var3_acc_i => s_var3_access_synch,
rst_status_bytes_i => s_rst_status_bytes,
nFIP_status_byte_o => s_stat,
mps_status_byte_o => s_mps
);
---------------------------------------------------------------------------------------------------
model_constr_decoder : WF_model_constr_decoder
generic map (C_RELOAD_MID_CID => C_RELOAD_MID_CID)
port map(
uclk_i => uclk_i,
nFIP_urst_i => s_rst,
s_id_o => s_id_o,
m_id_dec_o => s_m_id_dec_o,
c_id_dec_o => s_c_id_dec_o,
m_id_i => s_m_id_synch,
c_id_i => s_c_id_synch
uclk_i => uclk_i,
nfip_urst_i => s_rst,
model_id_i => s_m_id_synch,--------------
constr_id_i => s_c_id_synch,
select_id_o => s_id_o,
model_id_dec_o => s_model_id_dec,
constr_id_dec_o => s_constr_id_dec
);
......@@ -407,72 +414,70 @@ begin
synchronizer: WF_inputs_synchronizer
port map(
uclk_i => uclk_i,
wbclk_i => wclk_i,
nFIP_urst_i => s_rst,
rstin_a_i => rstin_i,
wb_rst_a_i => rst_i,
slone_a_i => slone_i,
nostat_a_i => nostat_i,
fd_wdgn_a_i => fd_wdgn_i,
fd_txer_a_i => fd_txer_i,
fd_rxd_a_i => fx_rxd_i,
wb_cyc_a_i => cyc_i,
wb_we_a_i => we_i,
wb_stb_a_i => stb_i,
wb_adr_a_i => adr_i,
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
dat_a_i => DAT_I,
rate_a_i => rate_i,
subs_a_i => subs_i,
m_id_a_i => m_id_i,
c_id_a_i => c_id_i,
p3_lgth_a_i => p3_lgth_i,
rsti_o => s_urst_synch,
urst_r_edge_o => s_urst_r_edge,
slone_o => s_slone_synch,
nostat_o => s_nostat_synch,
fd_wdgn_o => s_fd_wdgn_synch,
fd_txer_o => s_fd_txer_synch,
fd_rxd_o => s_fd_rxd_synch,
fd_rxd_edge_o => s_fd_rxd_edge,
fd_rxd_r_edge_o => s_rxd_r_edge,
fd_rxd_f_edge_o => s_rxd_f_edge,
wb_cyc_o => s_wb_cyc_synch,
wb_we_o => s_wb_we_synch,
wb_stb_o => s_wb_stb_synch,
wb_stb_r_edge_o => s_wb_stb_r_edge,
wb_dati_o => s_wb_dati_synch,
wb_adri_o => s_wb_adri_synch,
var1_access_o => s_var1_access_synch,
var2_access_o => s_var2_access_synch,
var3_access_o => s_var3_access_synch,
slone_dati_o => s_slone_dati_synch,
rate_o => s_rate_synch,
subs_o => s_subs_synch,
m_id_o => s_m_id_synch,
c_id_o => s_c_id_synch,
p3_lgth_o => s_p3_lgth_synch
uclk_i => uclk_i,
clk_wb_i => wclk_i,
nfip_urst_i => s_rst,
rstin_a_i => rstin_i,
wb_rst_a_i => rst_i,
slone_a_i => slone_i,
nostat_a_i => nostat_i,
fd_wdgn_a_i => fd_wdgn_i,
fd_txer_a_i => fd_txer_i,
fd_rxd_a_i => fd_rxd_i,
fd_rxcdn_a_i => fd_rxcdn_i,
wb_cyc_a_i => cyc_i,
wb_we_a_i => we_i,
wb_stb_a_i => stb_i,
wb_adr_a_i => adr_i,
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
dat_a_i => dat_i,
rate_a_i => rate_i,
subs_a_i => subs_i,
m_id_a_i => m_id_i,
c_id_a_i => c_id_i,
p3_lgth_a_i => p3_lgth_i,
rsti_o => s_urst_synch,
urst_r_edge_o => s_urst_r_edge,
slone_o => s_slone_synch,
nostat_o => s_nostat_synch,
fd_wdgn_o => s_fd_wdgn_synch,
fd_txer_o => s_fd_txer_synch,
fd_rxd_o => s_fd_rxd_synch,
fd_rxd_edge_p_o => s_fd_rxd_edge_p,
fd_rxd_r_edge_p_o => s_fd_rxd_r_edge_p,
fd_rxd_f_edge_p_o => s_fd_rxd_f_edge_p,
wb_cyc_o => s_wb_cyc_synch,
wb_we_o => s_wb_we_synch,
wb_stb_o => s_wb_stb_synch,
wb_stb_r_edge_o => s_wb_stb_r_edge,
wb_dati_o => s_wb_dati_synch,
wb_adri_o => s_wb_adri_synch,
var1_access_o => s_var1_access_synch,
var2_access_o => s_var2_access_synch,
var3_access_o => s_var3_access_synch,
slone_dati_o => s_slone_dati_synch,
rate_o => s_rate_synch,
subs_o => s_subs_synch,
m_id_o => s_m_id_synch,
c_id_o => s_c_id_synch,
p3_lgth_o => s_p3_lgth_synch
);
---------------------------------------------------------------------------------------------------
ack_o <= (s_ack_produced or s_ack_consumed); --and stb_i;
s_ack_o <= s_ack_produced or s_ack_consumed;
ack_o <= (s_prod_ack or s_wb_ack_cons); --and stb_i;
s_ack_o <= s_prod_ack or s_wb_ack_cons;
---------------------------------------------------------------------------------------------------
end architecture struc;
--============================================================================
--============================================================================
-- architecture end
--============================================================================
--============================================================================
-------------------------------------------------------------------------------
-- E N D O F F I L E
-------------------------------------------------------------------------------
\ No newline at end of file
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -19,7 +19,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- WF_DualClkRAM_clka_rd_clkb_wr --
-- WF_DualClkRAM_clka_rd_clkb_wr --
-- --
---------------------------------------------------------------------------------------------------
--
......@@ -30,16 +30,17 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! The component DualClkRam (512 bytes) is triplicated; each incoming byte is written
--! at the same position in the three memories, whereas each outgoing byte is the
--! outcome of a majority voter.
--! The memory is dual port; port A is used for reading only, port B for writing only.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 08/2010
--! @date 10/12/2010
--
--
--! @version v0.1
--! @version v0.02
--
--
--! @details\n
......@@ -54,7 +55,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes: </b>\n
--! -> code cleaned-up and commented
--! -> 12/2010 v0.02 EG code cleaned-up+commented \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -62,6 +63,12 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_DualClkRAM_clka_rd_clkb_wr
......@@ -69,19 +76,19 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (C_RAM_DATA_LGTH : integer; -- length of data word
C_RAM_ADDR_LGTH : integer); -- memory depth
c_RAM_ADDR_LGTH : integer); -- memory depth
port (
clk_A_i : in std_logic;
addr_A_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
clk_B_i : in std_logic;
addr_B_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_B_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
write_en_B_i : in std_logic;
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_portb_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
write_en_portb_i : in std_logic;
data_A_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
data_porta_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
);
end WF_DualClkRAM_clka_rd_clkb_wr;
......@@ -95,28 +102,28 @@ architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
--!@brief: component DualClkRam declaration
component DualClkRam is
port(
DINA : in std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
RWA : in std_logic;
CLKA : in std_logic;
DINB : in std_logic_vector (7 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
RWB : in std_logic;
CLKB : in std_logic;
DINA : in std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
RWA : in std_logic;
CLKA : in std_logic;
DINB : in std_logic_vector (7 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
RWB : in std_logic;
CLKB : in std_logic;
RESETn : in std_logic;
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0)
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0)
);
end component DualClkRam;
---------------------------------------------------------------------------------------------------
type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
signal data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
signal zero, one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
......@@ -127,7 +134,7 @@ begin
zero <= '0';
one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_B_i;
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
--!@brief: memory triplication
......@@ -140,14 +147,14 @@ G_memory_triplication: for I in 0 to 2 generate
UDualClkRam : DualClkRam
port map ( DINA => s_zeros,
ADDRA => addr_A_i,
ADDRA => addr_porta_i,
RWA => one,
CLKA => clk_A_i,
CLKA => clk_porta_i,
DINB => data_B_i,
ADDRB => addr_B_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_B_i,
CLKB => clk_portb_i,
RESETn => one,
......@@ -161,7 +168,7 @@ end generate;
--! output of the majority voter. The majority voter considers the outputs of the three memories
--! and "calculates" their majority with combinatorial logic.
majority_voter: data_A_o <= (data_o_A_array(0) and data_o_A_array(1)) or
majority_voter: data_porta_o <= (data_o_A_array(0) and data_o_A_array(1)) or
(data_o_A_array(1) and data_o_A_array(2)) or
(data_o_A_array(2) and data_o_A_array(0));
......
wf_VAR_RDY_generator.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_VAR_RDY_generator.vhd
--! @file WF_var_rdy_generator.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -10,33 +18,31 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_VAR_RDY_generator --
-- --
-- CERN, BE/CO/HT --
-- WF_var_rdy_generator --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Generation of the nanoFIP output signals VAR1_RDY, VAR2_RDY, VAR3_RDY according to
--! the variable that is being treated (var_i) and to the correct frame indicator,
--! the variable that is being treated (var_i) and to the "correct frame" indicator,
--! cons_frame_ok_p_i.
--! If the received variable is the var_rst, the unit generates the signals
--! rst_nFIP_and_FD_p and assert_RSTON_p, according to the data bytes received and to
--! the correct frame indicator, cons_frame_ok_p_i.
--! the "correct frame" indicator, cons_frame_ok_p_i.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 10/12/2010
--
--
--! @version v0.02
--! @version v0.03
--
--
--! @details \n
......@@ -50,9 +56,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 10/2010 v0.01 EG First version \n
--! 11/2011 v0.02 EG Treatment of reset vars added to the unit
--! Correction on var1_rdy, var2_rdy for slone
--! -> 10/2010 v0.01 EG First version \n
--! -> 11/2010 v0.02 EG Treatment of reset vars added to the unit
--! Correction on var1_rdy, var2_rdy for slone
--! -> 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting
--
---------------------------------------------------------------------------------------------------
--
......@@ -61,71 +68,69 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 5, 6 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the variables var_1, var_2, var_3 and var_rst. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_VAR_RDY_generator
--! Entity declaration for WF_var_rdy_generator
--=================================================================================================
entity WF_VAR_RDY_generator is
entity WF_var_rdy_generator is
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
subs_i : in std_logic_vector (7 downto 0); --! Station address
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
subs_i : in std_logic_vector (7 downto 0); --! Station address
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from WF_cons_frame_validator
cons_frame_ok_p_i : in std_logic; --! pulse after a correct consumed frame
var_i : in t_var; --! variable that is being treated
-- Signals from the WF_cons_frame_validator
cons_frame_ok_p_i : in std_logic; --! pulse after a correct consumed frame
var_i : in t_var; --! variable type that is being treated
-- Signals from WF_cons_bytes_from_rx
rx_var_rst_byte_1_i : in std_logic_vector(7 downto 0); --! First & second data bytes of a
rx_var_rst_byte_2_i : in std_logic_vector(7 downto 0); --! reset variable
-- Signals from the wf_cons_bytes_processor
rx_var_rst_byte_1_i : in std_logic_vector(7 downto 0); --! first & second data bytes of a
rx_var_rst_byte_2_i : in std_logic_vector(7 downto 0); --! reset variable
-- OUTPUT
-- nanoFIP output signals
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
-- nanoFIP User Interface, NON-WISHBONE outputs
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
-- Signals for the WF_reset_unit
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
);
end entity WF_VAR_RDY_generator;
end entity WF_var_rdy_generator;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_VAR_RDY_generator is
architecture rtl of WF_var_rdy_generator is
signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
signal s_rst_nFIP_and_FD, s_assert_RSTON : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process VAR_RDY_Generation:
--! For produced variables, the signal var_i gets its value (var3, var_presence, var_identif) after
--! the reception of a correct ID_DAT frame (with correct FSS, Control, PDU_TYPE, Length, CRC and
--! FES bytes and without unexpected code violations) and retains it until the end of the
--! transmission of the corresponding RP_DAT (in detail, until the end of the transmission of the
--! RP_DAT.data field; var_i becomes var_whatever during the RP_DAT.FCS and RP_DAT.FES transmission)
--! For consumed variables, var_i gets its value (var1, var2, var_rst) after the reception of a
--! correct ID_DAT frame and of a correct FSS of the corresponding RP_DAT frame and it retains it
--! unitl the end of the reception.
--! Memory Mode:
--! In memory mode, since the three memories (consumed, consumed broadcast, produced) are
--! independant, when a produced var is being sent, the user can read form the consumed memories;
......@@ -146,32 +151,39 @@ signal s_rst_nFIP_and_FD, s_assert_RSTON : std_logic;
--! nanoFIP.
--! Stand-alone Mode:
--! In stand-alone mode, since the DAT_O bus is the same for consumed and consumed broadcast
--! variables, only one of the VAR1_RDY and VAR2_RDY can be enabled at a time.
--! VAR3_RDY remains independant.
--! In stand-alone mode, the DAT_I and DAT_O buses for the produced and the consumed bytes
--! are independant. Stand-alone mode does not treat the consumed broadcast variable.
--! VAR1_RDY (for consumed vars): signals that the user can safely retreive data from the DAT_O
--! bus. The signal is asserted only after the reception of a correct RP_DAT frame.
--! It is de-asserted after the reception of a correct var1 or var2 ID_DAT frame.
--! It is de-asserted after the reception of a correct var1 ID_DAT frame(same as in memory mode).
--! VAR2_RDY (for broadcast consumed vars): signals that the user can safely retreive data from
--! the DAT_O bus. The signal is asserted only after the reception of a correct consumed
--! broadcast RP_DAT frame. It is deasserted after the reception of a correct var2 or var_1
--! ID_DAT frame.
--! VAR2_RDY (for broadcast consumed vars): stays always deasserted.
--! VAR3_RDY (for produced vars): signals that the user can safely access the DAT_I bus
--! (same treatment as in memory mode).
--! (same as in memory mode).
--! Note: A correct consumed RP_DAT frame is signaled by the cons_frame_ok_p_i, whereas a correct
--! ID_DAT frame along with the variable it contained is signaled by the var_i.
--! For produced variables, the signal var_i gets its value (var3, var_presence, var_identif)
--! after the reception of a correct ID_DAT frame (with correct FSS, Control, PDU_TYPE, Length, CRC
--! and FES bytes and without unexpected code violations) and retains it until the end of the
--! transmission of the corresponding RP_DAT (in detail, until the end of the transmission of the
--! RP_DAT.data field;var_i becomes var_whatever during the RP_DAT.FCS and RP_DAT.FES transmission).
--! For consumed variables, var_i gets its value (var1, var2, var_rst) after the reception of a
--! correct ID_DAT frame and of a correct FSS of the corresponding RP_DAT frame and it retains it
--! unitl the end of the reception.
VAR_RDY_Generation: process(uclk_i)
VAR_RDY_Generation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
var1_rdy_o <= '0';
var2_rdy_o <= '0';
var3_rdy_o <= '0';
s_var1_received <= '0';
s_var2_received <= '0';
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
var1_rdy_o <= '0';
var2_rdy_o <= '0';
var3_rdy_o <= '0';
s_var1_received <= '0';
s_var2_received <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -181,14 +193,7 @@ signal s_rst_nFIP_and_FD, s_assert_RSTON : std_logic;
--------------------
var1_rdy_o <= '0'; -- while consuming a var1, VAR1_RDY is 0
var3_rdy_o <= '1'; -- VAR3_RDY is independant of var1
if slone_i = '0' then
var2_rdy_o <= s_var2_received; -- in memory mode VAR2_RDY retains its value
else
var2_rdy_o <= '0'; -- in slone VAR2_RDY is de-asserted (bc of the
s_var2_received <= '0'; -- reception of a valid ID_DAT frame for a var1)
end if;
var2_rdy_o <= s_var2_received; -- VAR2_RDY retains its value
-- -- -- -- -- -- -- -- -- -- --
......@@ -204,39 +209,30 @@ signal s_rst_nFIP_and_FD, s_assert_RSTON : std_logic;
------------------------------
var2_rdy_o <= '0'; -- while consuming a var2, VAR2_RDY is 0
var3_rdy_o <= '1'; -- VAR3_RDY independant of var2
var1_rdy_o <= s_var1_received; -- VAR1_RDY retains its value
if slone_i = '0' then
var1_rdy_o <= s_var1_received; -- in memory mode VAR1_RDY retains its value
else
var1_rdy_o <= '0'; -- in slone VAR1_RDY is de-asserted (bc of the
s_var1_received <= '0'; -- reception of a valid ID_DAT frame for a var2)
end if;
if cons_frame_ok_p_d1 = '1' then -- only if the received RP_DAT frame is correct,
-- the nanoFIP signals the user to retreive data
s_var2_received <= '1'; -- note:the signal s_var2_received remains asser-
-- ted after the end of the cons_frame_ok_p pulse
end if;
if slone_i = '0' and cons_frame_ok_p_d1 = '1' then
-- only in memory mode and if the received RP_DAT
s_var2_received <= '1'; -- frame is correct, the nanoFIP signals the user
-- to retreive data.
-- note:the signal s_var2_received remains asser-
end if; -- ted after the end of the cons_frame_ok_p pulse
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_3 => -- nanoFIP producing
--------------------
var3_rdy_o <= '0'; -- while producing VAR3_RDY is 0
var1_rdy_o <= s_var1_received;
var2_rdy_o <= s_var2_received;
var3_rdy_o <= '0'; -- while producing VAR3_RDY is 0
var1_rdy_o <= s_var1_received;
var2_rdy_o <= s_var2_received;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
var1_rdy_o <= s_var1_received;
var2_rdy_o <= s_var2_received;
var3_rdy_o <= '1';
var1_rdy_o <= s_var1_received;
var2_rdy_o <= s_var2_received;
var3_rdy_o <= '1';
end case;
end if;
......@@ -245,14 +241,14 @@ signal s_rst_nFIP_and_FD, s_assert_RSTON : std_logic;
---------------------------------------------------------------------------------------------------
-- a 1-uclk delay is needed for the signal cons_frame_ok_p_i, so that it gets synchronized with
-- the var_i (the end of the pulse takes place at the same moment that var_i changes from one
--!@brief Synchronous process Cons_frame_ok_p_delay : a 1-uclk delay is needed for the signal
--! cons_frame_ok_p_i, so that it gets synchronized with the var_i (the end of the pulse takes
--! place at the same moment that var_i changes from one variable to another).
Cons_frame_ok_p_delay: process (uclk_i)
begin
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
cons_frame_ok_p_d1 <= '0';
else
cons_frame_ok_p_d1 <= cons_frame_ok_p_i;
......@@ -262,18 +258,18 @@ Cons_frame_ok_p_delay: process(uclk_i)
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@ brief: Generation of the signals s_rst_nFIP_and_FD: signals that the 1st byte of a consumed
--!@ brief: Generation of the signals s_rst_nfip_and_fd : signals that the 1st byte of a consumed
--! reset var contains the station address
--! and s_assert_RSTON: signals that the 2nd byte of a consumed
--! and s_assert_rston : signals that the 2nd byte of a consumed
--! reset var contains the station address
Reset_Signals: process (uclk_i)
Reset_Signals: process (uclk_i)
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
if nFIP_urst_i = '1' then
s_rst_nFIP_and_FD <= '0';
s_assert_RSTON <= '0';
if nfip_urst_i = '1' then
s_rst_nfip_and_fd <= '0';
s_assert_rston <= '0';
else
......@@ -281,28 +277,28 @@ Reset_Signals: process (uclk_i)
if rx_var_rst_byte_1_i = subs_i then
s_rst_nFIP_and_FD <= '1'; -- rst_nFIP_and_FD_o stays asserted until
s_rst_nfip_and_fd <= '1'; -- rst_nFIP_and_FD_o stays asserted until
end if; -- the end of the current RP_DAT frame
if rx_var_rst_byte_2_i = subs_i then
s_assert_RSTON <= '1'; -- assert_RSTON_o stays asserted until
s_assert_rston <= '1'; -- assert_RSTON_o stays asserted until
end if; -- the end of the current RP_DAT frame
else
s_rst_nFIP_and_FD <= '0';
s_assert_RSTON <= '0';
s_rst_nfip_and_fd <= '0';
s_assert_rston <= '0';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_nFIP_and_FD_p_o <= '1' when s_rst_nFIP_and_FD = '1' and cons_frame_ok_p_d1= '1'
else '0';
rst_nfip_and_fd_p_o <= '1' when s_rst_nfip_and_fd = '1' and cons_frame_ok_p_d1= '1'
else '0';
assert_RSTON_p_o <= '1' when s_assert_RSTON = '1' and cons_frame_ok_p_d1= '1'
else '0';
assert_rston_p_o <= '1' when s_assert_rston = '1' and cons_frame_ok_p_d1= '1'
else '0';
end architecture rtl;
......
wf_bits_to_txd.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_bits_to_txd.vhd
---------------------------------------------------------------------------------------------------
......@@ -10,37 +18,37 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_bits_to_txd --
-- --
-- CERN, BE/CO/HT --
-- WF_bits_to_txd --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief In stand-alone mode, the unit is responsible for transering the two desirialized
--! bytes from the filedbus to the 2bytes long bus DAT_O. The bytes are put in the bus
--! one by one as they arrive.
--! Note: After the reception of a correct FCS and the FES the signal VAR1_RDY/ VAR2_RDY
--! is asserted and that signals the user that the data in DAT_O are valid and stable.
--! @brief According to the state of the FSM of the wf_tx_serializer, the unit is responsible
--! for putting in nanoFIP's output FD_TXD one by one all the bits required for the
--! formation of the RP_DAT frame (that is: manch. encoded FSS, data, CRC and FES bits).
--! The unit also manages the output FD_TXENA.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 07/01/2011
--
--
--! @version v0.02
--! @version v0.03
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_tx_rx_osc \n
--! wf_tx_serializer \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -49,6 +57,11 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 8/2010 v0.02 EG tx_enable has to be synched with txd! sending_fss not enough;
--! need for tx_clk_p_buff signal
--! -> 7/1/2011 v0.03 EG tx_enable now starts 1 uclk tick earlier, at the same moment as txd
--! becomes 1 for the 1st bit of preamble
--! signals s_tx_enable & s_start_tx_enable removed for simplification
--
---------------------------------------------------------------------------------------------------
--
......@@ -57,41 +70,46 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_bits_to_txd
--=================================================================================================
entity WF_bits_to_txd is
generic(C_TXCLKBUFFLENTGTH: natural);
generic (c_TX_CLK_BUFF_LGTH: natural := 4); -- default
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from WF_tx
txd_bit_index_i : in unsigned(4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
sending_FSS_i : in std_logic;
sending_data_i : in std_logic;
sending_crc_i : in std_logic;
sending_QUEUE_i : in std_logic;
stop_transmission_i : in std_logic;
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the wf_tx_serializer
txd_bit_index_i : in unsigned(4 downto 0); --! index of bit inside a byte
data_byte_manch_i : in std_logic_vector (15 downto 0);--! manch. encoded data byte to be sent
crc_byte_manch_i : in std_logic_vector (31 downto 0);--! manch. encoded CRC bytes to be sent
sending_fss_i : in std_logic; --! wf_tx_serializer FSM states
sending_data_i : in std_logic; --! -----"----"-----
sending_crc_i : in std_logic; --! -----"----"-----
sending_fes_i : in std_logic; --! -----"----"-----
stop_transmission_i : in std_logic; --! -----"----"-----
-- Signals for the receiver WF_tx_rx_osc
tx_clk_p_buff_i : in std_logic_vector (C_TXCLKBUFFLENTGTH-1 downto 0);
--! clk for transmission synchronization
tx_clk_p_i : in std_logic;
--!clk for transmission synchronization
-- OUTPUTS
-- Signal to WF_prod_bytes_to_tx
txd_o : out std_logic;
tx_enable_o : out std_logic
-- nanoFIP FIELDRIVE outputs
txd_o : out std_logic; --! FD_TXD
tx_enable_o : out std_logic --! FD_TXENA
);
end entity WF_bits_to_txd;
......@@ -101,43 +119,41 @@ end entity WF_bits_to_txd;
--=================================================================================================
architecture rtl of WF_bits_to_txd is
signal s_start_tx_enable, s_tx_enable : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--! @brief synchronous process tx_Outputs:managment of nanoFIP output signals tx_data and tx_enable
--! tx_data: placement of bits of data to the output of the unit
--! tx_enable: flip-floped s_tx_enable (s_tx_enable is activated during bits delivery: from the
--! beginning of tx_state send_fss until the end of send_queue state)
--! @brief Synchronous process Bits_Delivery: managment of nanoFIP output signal FD_TXD by
--! placing bits of data according to the state of wf_tx_serializer's state machine (sending_fss,
--! sending_data, sending_crc, sending_fes, stop_transmission) and to the counter txd_bit_index.
--! The delivery is synchronised by the tx_clk_p_buff(1) signal.
Bits_Delivery: process(uclk_i)
Bits_Delivery: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
txd_o <= '0';
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
txd_o <= '0';
else
if tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-3) = '1' then
if tx_clk_p_i = '1' then
if sending_FSS_i = '1' then
txd_o <= FSS (to_integer (txd_bit_index_i));
if sending_fss_i = '1' then
txd_o <= FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize)
elsif sending_data_i = '1' then
txd_o <= data_byte_manch_i (to_integer (resize (txd_bit_index_i, 4)));
txd_o <= data_byte_manch_i (to_integer (resize(txd_bit_index_i, 4))); -- 1 data-byte
elsif sending_crc_i = '1' then
txd_o <= crc_byte_manch_i (to_integer(txd_bit_index_i));
txd_o <= crc_byte_manch_i (to_integer (txd_bit_index_i)); -- CRC: 2 bytes long
elsif sending_QUEUE_i = '1' then
txd_o <= FRAME_END(to_integer(resize(txd_bit_index_i,4)));
elsif sending_fes_i = '1' then
txd_o <= FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
else
txd_o <= '0';
txd_o <= '0';
end if;
end if;
......@@ -146,35 +162,34 @@ signal s_start_tx_enable, s_tx_enable : std_logic;
end process;
------------------------------------------------------------------------------------------------
s_tx_enable <= sending_FSS_i or sending_data_i or sending_crc_i or sending_QUEUE_i or stop_transmission_i;
-- beginning of considering data bits
-- for the CRC calculation when the
-- 1st bit of data is to be sent
-- (note: the CRC calculator uses the
-- signal s_bit, not tx_data_o)
tx_enable_manager: process(uclk_i)
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
--! same moment as the first bit of the PRE starts being delivered and stays asserted until the
--! end of the delivery of the last FES bit.
FD_TXENA_Generator: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
tx_enable_o <= '0';
s_start_tx_enable <= '0';
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
tx_enable_o <= '0';
else
if s_tx_enable = '1' then
if tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-3) = '1' then
s_start_tx_enable <= '1';
end if;
if ((sending_fss_i = '1') or (sending_data_i = '1') or -- tx sending bits
(sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then
if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enabble with the
end if; -- the delivery of the 1st FSS bit
-- txd :________|-----|___________|--------
-- tx_clk_p_buff(1):______|-|___|-|___|-|___|-|___|-|__
-- sending_FSS :___|-------------------------------
-- tx_enable :________|--------------------------
else
s_start_tx_enable <= '0';
tx_enable_o <= '0';
end if;
tx_enable_o <= s_tx_enable and s_start_tx_enable;
end if;
end if;
end if;
end process;
......
wf_cons_bytes_from_rx.vhd → wf_cons_bytes_processor.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_cons_bytes_from_rx.vhd
--! @file wf_cons_bytes_processor.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -10,47 +18,45 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_bytes_from_rx --
-- --
-- CERN, BE/CO/HT --
-- wf_cons_bytes_processor --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: WF_cons_bytes_from_rx
-- unit name: wf_cons_bytes_processor
--
--! @brief Consumption of data bytes, arriving from the WF_rx unit, by registering them in
--! the Consumend memory, if the operation is in memory mode, or by transferring them
--! to the user interface data bus, if the operation is stand-alone.
--! In the case of a consumed reset variable, the 1st and 2nd data byte are registered
--! @brief Consumption of data bytes, arriving from the wf_rx_deserializer unit, by registering
--! them in the Consumend memory, if the operation is in memory mode, or by transferring
--! them to the user interface data bus DAT_O, if the operation is in stand-alone.
--! In the case of a consumed reset variable, the two data bytes are registered
--! and sent to the reset unit.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 07/2010
--! @date 15/12/2010
--
--
--! @version v0.02
--! @version v0.03
--
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx \n
--! WF_engine_control\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! wf_rx_deserializer \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
---------------------------------------------------------------------------------------------------
--
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/09/2009 v0.01 EB First version \n
......@@ -58,16 +64,18 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! creation for simplification; Signals renamed;
--! Ctrl, PDU_TYPE, Length bytes registered;
--! Code cleaned-up & commented.\n
--! -> 15/12/2010 v0.03 EG Unit renamed from wf_cons_bytes_from_rx to wf_cons_bytes_processor
--! Code cleaned-up & commented (more!) \n
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! --> separate unit for the wb_ack treatment
--! --> two constant!
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\--------------------------/!\--
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
......@@ -75,70 +83,73 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for WF_cons_bytes_from_rx
--! Entity declaration for wf_cons_bytes_processor
--=================================================================================================
entity WF_cons_bytes_from_rx is
entity wf_cons_bytes_processor is
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode (active high)
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode (active high)
-- Signal from the WF_reset_unit
nFIP_urst_i : in std_logic; --! internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- User Interface WISHBONE Slave
wb_clk_i : in std_logic; --! WISHBONE clock
-- note: may be independent of uclk
-- nanoFIP User Interface, WISHBONE Slave
clk_wb_i : in std_logic; --! WISHBONE clock
-- note: may be independent of uclk
wb_adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address to memory
wb_stb_r_edge_p_i : in std_logic; --! pulse on the rising edge of stb_i
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address to memory
wb_stb_r_edge_p_i : in std_logic; --! pulse on the rising edge of stb_i
wb_cyc_i : in std_logic; --! WISHBONE cycle
-- Signals from the receiver WF_rx
byte_i : in std_logic_vector (7 downto 0); --! de-serialized byte
byte_ready_p_i : in std_logic; --! indication of a valid byte
-- Signals from the wf_rx_deserializer
byte_i : in std_logic_vector (7 downto 0); --! input byte
byte_ready_p_i : in std_logic; --! indication of a valid input byte
-- Signals from the WF_engine_control
byte_index_i : in std_logic_vector (7 downto 0); --! index of a byte inside the frame
var_i : in t_var; --! variable type
byte_index_i : in std_logic_vector (7 downto 0); --! index of a byte inside the frame
-- starting from 0, it counts all the
-- bytes after the FSS&before the FES
var_i : in t_var; --! variable type that is being treated
-- OUTPUTS
-- OUTPUTS to the User Interface WISHBONE slave
data_o : out std_logic_vector (15 downto 0);--! DAT_O bus
wb_ack_cons_p_o : out std_logic; --! WISHBONE acknowledge
-- OUTPUTS to the WF_VAR_RDY_generator
rx_Ctrl_byte_o : out std_logic_vector (7 downto 0); --! received Control byte
rx_PDU_byte_o : out std_logic_vector (7 downto 0); --! received PDY_TYPE byte
rx_Length_byte_o : out std_logic_vector (7 downto 0); --! received Length byte
rx_var_rst_byte_1_o : out std_logic_vector (7 downto 0); --! content of the 1st data byte of
--! a reset variable
rx_var_rst_byte_2_o : out std_logic_vector (7 downto 0) --! content of the 2nd data byte of
--! a reset variable
-- nanoFIP User Interface, WISHBONE Slave outputs
data_o : out std_logic_vector (15 downto 0);--! data out bus
wb_ack_cons_p_o : out std_logic; --! WISHBONE acknowledge
-- Signals to the WF_cons_frame_validator
cons_ctrl_byte_o : out std_logic_vector (7 downto 0); --! received Control byte
cons_pdu_byte_o : out std_logic_vector (7 downto 0); --! received PDY_TYPE byte
cons_lgth_byte_o : out std_logic_vector (7 downto 0); --! received Length byte
-- Signals to the WF_var_rdy_generator
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); --! content of the 1st data byte of
--! a reset variable
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0) --! content of the 2nd data byte of
--! a reset variable
);
end entity WF_cons_bytes_from_rx;
end entity wf_cons_bytes_processor;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_cons_bytes_from_rx is
architecture rtl of wf_cons_bytes_processor is
signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_rx_Length_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned(7 downto 0);
signal s_base_addr : unsigned(8 downto 0);
signal s_write_byte_to_mem_p : std_logic;
signal s_slone_data : std_logic_vector (15 downto 0);
signal s_addr : std_logic_vector (8 downto 0);
signal s_mem_data_out, s_rx_Length_byte : std_logic_vector (7 downto 0);
signal s_slone_write_byte_p : std_logic_vector (1 downto 0);
signal two : unsigned(7 downto 0);
signal s_base_addr : unsigned(8 downto 0);
signal s_write_byte_to_mem_p : std_logic;
--=================================================================================================
-- architecture begin
......@@ -148,35 +159,33 @@ begin
two <= to_unsigned (2, two'length);
---------------------------------------------------------------------------------------------------
-- !@brief Instantiation of a dual port Consumed RAM
-- !@brief Instantiation of a Dual Port Consumed RAM
--! (for both the consumed and consumed broadcast variables)
Consumption_DPRAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map(C_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
C_RAM_ADDR_LGTH => 9) -- 2^9: depth of consumed RAM
-- first 2 bits: identification of the memory block
-- remaining 7 bits: address of a byte inside the block
-- port A: WISHBONE that reads from the Consumed RAM
-- port B: nanoFIP that writes
port map (clk_A_i => wb_clk_i, -- WISHBONE clck
addr_A_i => wb_adr_i(8 downto 0), -- address of byte to be read
data_A_o => s_mem_data_out, -- output byte read
clk_B_i => uclk_i, -- 40 MHz clck
addr_B_i => s_addr(8 downto 0), -- address of byte to be written
data_B_i => byte_i, -- byte to be written
write_en_B_i => s_write_byte_to_mem_p -- write enable
);
Consumed_Bytes_To_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map(
c_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
c_RAM_ADDR_LGTH => 9) -- 2^9: depth of consumed RAM
-- first 2 bits: identification of the memory block
-- remaining 7 bits: address of a byte inside the block
-- port A: WISHBONE that reads from the Consumed RAM; port B: nanoFIP that writes
port map(
clk_porta_i => clk_wb_i, -- WISHBONE clock
addr_porta_i => wb_adr_i(8 downto 0), -- address of byte to be read
-----------------------------------------------------------------------------
data_porta_o => s_mem_data_out, -- output byte read
-----------------------------------------------------------------------------
clk_portb_i => uclk_i, -- 40 MHz clock
addr_portb_i => s_addr(8 downto 0), -- address of byte to be written
data_portb_i => byte_i, -- byte to be written
write_en_portb_i => s_write_byte_to_mem_p ); -- write enable
---------------------------------------------------------------------------------------------------
--!@brief Generate_wb_ack_cons_p_o: Generation of the wb_ack_cons_p_o signal
--! (acknowledgement from WISHBONE slave of the read cycle, as a response to the master's strobe).
--! wb_ack_cons_p_o is 1 wclk-wide pulse asserted 3 wclk cycles after the assertion of the
--! asynchronous strobe signal, if the wb_cyc is asserted and the WISHBONE input address
--! corresponds to an address in the Consumed memory block.
--!@brief Generate_wb_ack_cons_p_o: Generation of the wb_ack_cons_p_o signal
--! (acknowledgement from WISHBONE Slave of the read cycle, as a response to the master's strobe).
--! wb_ack_cons_p_o is 1 wclk-wide pulse asserted 3 wclk cycles after the assertion of the
--! asynchronous strobe signal, if the wb_cyc is asserted and the WISHBONE input address
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_cons_p_o: wb_ack_cons_p_o <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 8) = "00") and
......@@ -188,28 +197,32 @@ begin
--!@brief Combinatorial process Bytes_Consumption: Data bytes are consumed according to the
--! variable type they belong.
--! The treatment of a var1 is identical to the one of a var2 for both modes (only the memory block
--! differs in memory mode).
--! In memory mode the treatment of a var1 is identical to the one of a var2; only the base address
--! of the memory differs.
--! Bytes are consumed even if the Ctrl, PDU_TYPE, Length, CRC, FES bytes are incorrect or if
--! code violations are detected;
--! Bytes are consumed even if the Control, PDU_TYPE, Length, CRC, FES bytes are incorrect or if
--! code violations have been detected;
--! It is the VAR_RDY signal that signals the user for the validity of the consumed data.
--! In memory mode, the incoming bytes after the Ctrl byte and before the CRC bytes, are written
--! in the memory one by one as they arrive, on the moments when the signal byte_ready_p_i is
--! active. The signals byte_index_i and Length (s_rx_Length_byte) are used to coordinate which
--! bytes are written and which are not (example Ctrl byte, CRC bytes).
--! In memory mode, the incoming bytes (byte_i) after the Control byte and before the CRC bytes,
--! are written in the memory one by one as they arrive, on the moments when the signal
--! byte_ready_p_i is active.
--! The signals byte_index_i and Length (s_rx_Length_byte) are used to coordinate which bytes are
--! written and which are not:
--! the Control byte, that arrives when byte_index_i = 0, is not written
--! and the CRC bytes are not written by checking the amount of bytes indicated by the Length byte.
--! The byte_index_i signal is counting each byte after the FSS and before the FES (therefore,
--! apart from all the pure data-bytes, it also includes the Ctrl, PDU, Length, MPS and CRC bytes).
--! The Length byte (s_rx_Length_byte) is received from the WF_rx when byte_index_i is equal to 3
--! and if it is correct, it indicates the amount of bytes after in the frame the Ctrl, PDU_TYPE
--! and Length and before the CRC.
--! apart from all the pure data-bytes,it also includes the Control, PDU, Length, MPS & CRC bytes).
--! The Length byte (s_rx_Length_byte) is received from the wf_rx_deserializer when byte_index_i is equal to 3
--! and indicates the amount of bytes in the frame after the Control, PDU_TYPE and itself and
--! before the CRC.
--! In stand-alone mode, in total two bytes of data have to be transferred to the DAT_O bus. The
--! In stand-alone mode, in total two bytes of data have to be transferred to the data out bus. The
--! process manages the signal slone_write_byte_p which indicates which of the bytes of the bus
--! (msb: 15 downto 8 or lsb: 7 downto 0) have to be written.
--! If the consumed variable is the reset one (E0h) the process latches the first and second bytes.
--! If the consumed variable is the reset one the process latches the first and second data bytes.
Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
byte_ready_p_i, s_base_addr, s_rx_Length_byte)
......@@ -225,33 +238,34 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
case var_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_1 =>
rx_var_rst_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_addr; -- base address info
-- from WF_package
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_addr;-- base address
-- from WF_package
-- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode
if slone_i = '0' then
s_slone_write_byte_p <= (others => '0');
s_slone_write_byte_p <= (others => '0');
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits
if byte_index_i > c_LENGTH_BYTE_INDEX then -- after the reception
-- of the Length byte
if unsigned(byte_index_i) <= unsigned(s_rx_Length_byte) + two then
s_write_byte_to_mem_p <= byte_ready_p_i; -- the # bytes indicated
-- by Length are written
if unsigned(byte_index_i) <= unsigned(s_rx_Length_byte) + two then -- less or eq
s_write_byte_to_mem_p <= byte_ready_p_i; -- "Length" amount of
-- bytes are written
else
s_write_byte_to_mem_p <= '0';
end if;
else -- before the reception
s_write_byte_to_mem_p <= byte_ready_p_i; -- of the Length byte
end if; -- all the bytes
-- are written
end if; -- all the bytes (after
-- Control) are written
else
s_write_byte_to_mem_p <= '0';
end if;
......@@ -260,32 +274,32 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
-- in stand-alone mode
elsif slone_i = '1' then
s_write_byte_to_mem_p <= '0';
s_write_byte_to_mem_p <= '0';
if byte_index_i = c_1st_DATA_BYTE_INDEX then -- 1st byte to be transferred
s_slone_write_byte_p <= '0'& byte_ready_p_i;
s_slone_write_byte_p <= '0'& byte_ready_p_i;
elsif byte_index_i = c_2nd_DATA_BYTE_INDEX then -- 2nd byte to be transferred
s_slone_write_byte_p <= byte_ready_p_i & '0';
s_slone_write_byte_p <= byte_ready_p_i & '0';
else
s_slone_write_byte_p <= (others=>'0');
s_slone_write_byte_p <= (others=>'0');
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_2 =>
rx_var_rst_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_addr;
-- same treatment as var 1 on a different memory location (base_addr)
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_addr;
-- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode
if slone_i = '0' then
s_slone_write_byte_p <= (others => '0');
s_slone_write_byte_p <= (others => '0');
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then
......@@ -307,54 +321,55 @@ Bytes_Consumption: process (var_i, byte_index_i, slone_i, byte_i, two,
end if;
-- -- -- -- -- -- -- -- -- -- -- --
-- in stand-alone mode
-- stand-alone mode does not treat consumed broadcast vars
else
s_write_byte_to_mem_p <= '0';
if byte_index_i = c_1st_DATA_BYTE_INDEX then
s_slone_write_byte_p <= '0'& byte_ready_p_i;
elsif byte_index_i = c_2nd_DATA_BYTE_INDEX then
s_slone_write_byte_p <= byte_ready_p_i & '0';
else
s_slone_write_byte_p <= (others=>'0');
end if;
s_write_byte_to_mem_p <= '0';
s_slone_write_byte_p <= (others => '0');
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_rst =>
s_write_byte_to_mem_p <= '0';
s_slone_write_byte_p <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_VAR_RST_INDEX).base_addr;
s_write_byte_to_mem_p <= '0'; -- no writing in memory for the reset var
s_slone_write_byte_p <= (others => '0');
s_base_addr <= (others => '0');
if ((byte_ready_p_i = '1')and(byte_index_i = c_1st_DATA_BYTE_INDEX)) then -- 1st byte
rx_var_rst_byte_1_o <= byte_i;
rx_var_rst_byte_2_o <= (others => '0');
cons_var_rst_byte_1_o <= byte_i;
cons_var_rst_byte_2_o <= (others => '0');
elsif ((byte_ready_p_i='1')and(byte_index_i=c_2nd_DATA_BYTE_INDEX)) then -- 2nd byte
rx_var_rst_byte_2_o <= byte_i;
rx_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= byte_i;
cons_var_rst_byte_1_o <= (others => '0');
else
rx_var_rst_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= (others => '0');
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_3 | var_presence | var_identif | var_whatever =>
s_write_byte_to_mem_p <= '0';
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
s_write_byte_to_mem_p <= '0';
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
rx_var_rst_byte_1_o <= (others => '0');
rx_var_rst_byte_2_o <= (others => '0');
s_write_byte_to_mem_p <= '0';
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
cons_var_rst_byte_1_o <= (others => '0');
cons_var_rst_byte_2_o <= (others => '0');
end case;
......@@ -362,53 +377,64 @@ end process;
---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the unit responsible for the transfer of 2 de-serialized data bytes
--! @brief Instantiation of the unit responsible for the transfering of 2 de-serialized data bytes
--! to DAT_O;
Bytes_Transfer_To_DATO: WF_slone_bytes_to_DATO
Consumed_Bytes_To_DATO: wf_cons_bytes_to_dato
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
nfip_urst_i => nfip_urst_i,
transfer_byte_p_i => s_slone_write_byte_p,
byte_i => byte_i,
------------------------------------------
slone_data_o => s_slone_data);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- in stand-alone mode the 16 bits DAT_O fills up with the output of the WF_slone_bytes_to_DATO
-- unit.
-- In memory mode, the lsb of DAT_O contains the output of the reading of the consumed memory.
data_o <= s_slone_data when slone_i = '1'
else "00000000" & s_mem_data_out;
-- In stand-alone mode the 16 bits DAT_O fills up with the output of the wf_cons_bytes_to_dato
-- unit.In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory
data_o <= s_slone_data when slone_i = '1'
else "00000000" & s_mem_data_out;
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Buffer_Ctrl_PDU_Length_bytes: Storage of the RP_DAT.Control, PDU_TYPE
--! and Length bytes of an incoming RP_DAT frame. The bytes are sent to the WF_VAR_RDY_generator
--! unit that accordingly enables or not the signals VAR1_RDY, VAR2_RDY.
--!@brief Synchronous process Buffer_Ctrl_PDU_Length_bytes: Storage of the Control, PDU_TYPE
--! and Length bytes of an incoming RP_DAT frame. The bytes are sent to the WF_var_rdy_generator
--! unit that accordingly enables or not the signals VAR1_RDY (for a var1), VAR2_RDY (for a var2),
--! assert_rston_p and rst_nfip_and_fd_p (for a var_rst).
Buffer_Ctrl_PDU_Length_bytes: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
rx_Ctrl_byte_o <= (others=>'0');
rx_PDU_byte_o <= (others=>'0');
s_rx_Length_byte <= (others=>'0');
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
cons_ctrl_byte_o <= (others => '0');
cons_pdu_byte_o <= (others => '0');
s_rx_Length_byte <= (others => '0');
else
if ((byte_ready_p_i='1') and (byte_index_i = c_CTRL_BYTE_INDEX)) then
rx_Ctrl_byte_o <= byte_i;
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) then -- only for consumed vars
if ((byte_index_i = c_CTRL_BYTE_INDEX) and (byte_ready_p_i='1')) then
cons_ctrl_byte_o <= byte_i;
elsif ((byte_index_i = c_PDU_BYTE_INDEX) and (byte_ready_p_i ='1')) then
cons_pdu_byte_o <= byte_i;
elsif byte_index_i = c_PDU_BYTE_INDEX and byte_ready_p_i ='1'then
rx_PDU_byte_o <= byte_i;
elsif ((byte_index_i = c_LENGTH_BYTE_INDEX) and (byte_ready_p_i ='1')) then
s_rx_Length_byte <= byte_i;
end if;
elsif byte_index_i = c_LENGTH_BYTE_INDEX and byte_ready_p_i ='1' then
s_rx_Length_byte <= byte_i;
else
cons_ctrl_byte_o <= (others => '0');
cons_pdu_byte_o <= (others => '0');
s_rx_Length_byte <= (others => '0');
end if;
end if;
end if;
end process;
rx_Length_byte_o <= s_rx_Length_byte;
-- -- -- -- -- -- -- -- -- -- -- --
cons_lgth_byte_o <= s_rx_Length_byte;
end architecture rtl;
--=================================================================================================
......
wf_slone_bytes_to_DATO.vhd → wf_cons_bytes_to_dato.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_slone_bytes_to_DATO.vhd |
--! @file wf_cons_bytes_to_dato.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -18,27 +18,28 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_slone_bytes_to_DATO --
-- wf_cons_bytes_to_dato --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief In stand-alone mode, the unit is responsible for transering the two desirialized
--! bytes from the filedbus to the 2bytes long bus DAT_O. The bytes are put in the bus
--! one by one as they arrive.
--! @brief In stand-alone mode, if a consumed or consumed broadcast variable has been received,
--! the unit is responsible for transering the two desirialized data-bytes from the
--! filedbus to the 2-bytes long bus DAT_O. The bytes are put in the bus one by one as
--! they arrive, as signal transfer_byte_p_i indicates.
--! Note: After the reception of a correct FCS and the FES the signal VAR1_RDY/ VAR2_RDY
--! is asserted and that signals the user that the data in DAT_O are valid and stable.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 10/01/2011
--
--
--! @version v0.02
......@@ -46,7 +47,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! wf_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -55,6 +58,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 10/1/2011 v0.02 EG unit renamed from wf_slone_cons_bytes_to_dato to
--! wf_cons_bytes_to_dato; cleaning-up + commenting
--
---------------------------------------------------------------------------------------------------
--
......@@ -63,78 +69,81 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_slone_bytes_to_DATO
--! Entity declaration for wf_cons_bytes_to_dato
--=================================================================================================
entity WF_slone_bytes_to_DATO is
entity wf_cons_bytes_to_dato is
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from WF_cons_bytes_from_rx
transfer_byte_p_i: in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_o(7:0)
--! 10: byte_i transfered to DAT_o(15:8)
-- Signals from the wf_cons_bytes_processor
transfer_byte_p_i : in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_O(7:0)
--! 10: byte_i transfered to DAT_O(15:8)
-- Signals for the receiver WF_rx
byte_i : in std_logic_vector (7 downto 0); --! byte received from the rx unit
byte_i : in std_logic_vector (7 downto 0); --! de-serialised byte
-- OUTPUTS
-- Signal to WF_prod_bytes_to_tx
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
-- Signal to the wf_prod_bytes_retriever
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
);
end entity WF_slone_bytes_to_DATO;
end entity wf_cons_bytes_to_dato;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_slone_bytes_to_DATO is
architecture rtl of wf_cons_bytes_to_dato is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, accrording to the signal
--! transfer_byte_p_i, the first or second byte of the user interface bus DAT_o takes the
--! transfer_byte_p_i, the first or second byte of the user interface bus DAT_O takes the
--! incoming byte byte_i.
Data_Transfer_To_Dat_o: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
slone_data_o <= (others => '0'); -- bus initialization
begin
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
slone_data_o <= (others => '0'); -- bus initialization
else
else
if transfer_byte_p_i(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
if transfer_byte_p_i(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
slone_data_o(7 downto 0) <= byte_i; -- the data stays there until a new byte arrives
slone_data_o(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives
end if;
end if;
if transfer_byte_p_i(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
if transfer_byte_p_i(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
slone_data_o(15 downto 8) <= byte_i; -- the data stays there until a new byte arrives
slone_data_o(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives
end if;
end if;
end if;
end if;
end if;
end process;
end process;
end architecture rtl;
......
wf_cons_frame_validator.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_cons_frame_validator.vhd
---------------------------------------------------------------------------------------------------
......@@ -10,26 +18,28 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_frame_validator --
-- --
-- CERN, BE/CO/HT --
-- WF_cons_frame_validator --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Validation of a received RP_DAT frame with respect to: Ctrl, PDU, Length bytes as
--! well as CRC and FSS, FES and code violations.
--! @brief Validation of a received RP_DAT frame with respect to the correctness of the
--! Control, PDU_TYPE and Length bytes, coming from the wf_cons_bytes_processor unit,
--! as well of the CRC, FSS, FES bytes and of the manchester encoding (no occurence of
--! unwanted code violations), all coming directly from the wf_rx_deserializer unit.
--! After these verifications, the unit wf_VAR_RDY_generator treats accordingly the
--! signals VAR1_RDY/ VAR2_RDY, or nFIP_and_FD_p/ assert_RSTON_p.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 10/12/2010
--
--
--! @version v0.02
......@@ -37,7 +47,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! \n<b>Dependencies:</b> \n
--! wf_cons_bytes_processor \n
--! WF_engine_control \n
--! wf_rx_deserializer \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -46,6 +59,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 12/2010 v0.02 EG code cleaned-up+commented \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -54,6 +68,14 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 2, 5, 6 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the consumed variables var_1, var_2 and var_rst. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_cons_frame_validator
......@@ -63,22 +85,28 @@ entity WF_cons_frame_validator is
port (
-- INPUTS
-- Signals from the WF_cons_bytes_from_rx unit
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte
rx_PDU_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
rx_Length_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
-- Signals from the wf_cons_bytes_processor unit
rx_ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte
rx_pdu_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
rx_length_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
-- Signal from the WF_rx unit
rx_FSS_CRC_FES_viol_ok_p_i : in std_logic; --! indication that CRC and FES have
-- Signals from WF_engine_control
var_i: in t_var;
rx_byte_index_i : in unsigned(7 downto 0);
-- Signal from the wf_rx_deserializer unit
rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC
rx_fss_crc_fes_viol_ok_p_i : in std_logic; --! indication of a frame with a correct FSS,FES,CRC
--! and with no unexpected manch code violations
-- Signals from the WF_engine_control
var_i : in t_var; --! variable type that is being treated
rx_byte_index_i : in unsigned (7 downto 0); --! index of the byte being received
-- OUTPUT
-- Signal to WF_engine_control
cons_frame_ok_p_o : out std_logic
-- Signal to the WF_engine_control
cons_frame_ok_p_o : out std_logic; --! pulse at the end of the FES
--! indicating a valid frame
-- Signal to the WF_status_bytes_gen
nfip_status_r_fcser_p_o : out std_logic; --! indication of a consumed frame with wrong CRC
nfip_status_r_tler_o : out std_logic --! indication of the correctness of the PDU_TYPE,
--! Control or Length bytes of the consumed frame
);
end entity WF_cons_frame_validator;
......@@ -88,70 +116,98 @@ end entity WF_cons_frame_validator;
--=================================================================================================
architecture rtl of WF_cons_frame_validator is
signal s_rx_ctrl_byte_ok, s_rx_PDU_byte_ok, s_rx_length_byte_ok : std_logic;
signal s_rx_ctrl_byte_ok, s_rx_pdu_byte_ok, s_rx_length_byte_ok : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Consumed_Frame_Validator: validation of an RP_DAT
--! frame with respect to: Ctrl, PDU, Length bytes as well as CRC and FSS, FES and code violations.
Consumed_Frame_Validator: process ( var_i, rx_FSS_CRC_FES_viol_ok_p_i, rx_byte_index_i, rx_PDU_byte_i,
rx_Ctrl_byte_i, rx_Length_byte_i )
--! frame with respect to: Ctrl, PDU, Length bytes as well as CRC, FSS, FES and code violations.
--! The bytes rx_ctrl_byte_i, rx_pdu_byte_i, rx_length_byte_i that arrive at the beginning of a
--! frame, have been registered and keep their values until the end of a frame.
--! The signal rx_fss_crc_fes_viol_ok_p_i, is a pulse at the end of the FES that combines
--! the check of the FSS, CRC, FES and the code violations.
Consumed_Frame_Validator: process (var_i, rx_ctrl_byte_i, rx_byte_index_i, rx_pdu_byte_i,
rx_fss_crc_fes_viol_ok_p_i, rx_length_byte_i, rx_crc_wrong_p_i)
begin
if var_i = var_1 or var_i = var_2 then
case var_i is
-------------------------------------------------------------------------------------------------
when var_1 | var_2 | var_rst => -- only for consumed RP_DAT frames
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_Ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_rx_ctrl_byte_ok <= '1'; -- RP_DAt_CTRL byte
if rx_ctrl_byte_i = c_RP_DAT_CTRL_BYTE then -- comparison with the expected
s_rx_ctrl_byte_ok <= '1'; -- RP_DAT.CTRL byte
else
s_rx_ctrl_byte_ok <= '0';
s_rx_ctrl_byte_ok <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_PDU_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_rx_PDU_byte_ok <= '1'; -- PDU_TYPE byte
if rx_pdu_byte_i = c_PROD_CONS_PDU_TYPE_BYTE then -- comparison with the expected
s_rx_pdu_byte_ok <= '1'; -- PDU_TYPE byte
else
s_rx_PDU_byte_ok <= '0' ;
s_rx_pdu_byte_ok <= '0' ;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_FSS_CRC_FES_viol_ok_p_i = '1' then -- checking the RP_DAT.Data.Length
if rx_fss_crc_fes_viol_ok_p_i = '1' then -- checking the RP_DAT.Data.Length
-- byte, when the end of frame
-- arrives correctly
if rx_byte_index_i = (unsigned(rx_Length_byte_i) + 5) then -- rx_byte_index starts counting
s_rx_length_byte_ok <= '1'; -- from 0 and apart from the user-data
-- bytes, also counts ctrl, PDU,
else -- Length, 2 CRC and FES bytes
-- arrives correctly.
if rx_byte_index_i = (unsigned(rx_length_byte_i) + 5) then -- rx_byte_index starts counting
s_rx_length_byte_ok <= '1'; -- from 0 and apart from the
-- user-data bytes, also counts the
else -- Control, PDU_TYPE, Length,
-- the 2 CRC and the FES bytes
s_rx_length_byte_ok <= '0';
end if;
else
s_rx_length_byte_ok <= '0';
s_rx_length_byte_ok <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
nfip_status_r_fcser_p_o <= rx_crc_wrong_p_i;
-----------------------------------------------------------------------------------------------
-- when var_presence | var_identif | var_3 | var_whatever =>
-- s_rx_ctrl_byte_ok <= '0';
-- s_rx_pdu_byte_ok <= '0';
-- s_rx_length_byte_ok <= '0';
-------------------------------------------------------------------------------------------------
when others =>
s_rx_ctrl_byte_ok <= '0';
s_rx_pdu_byte_ok <= '0';
s_rx_length_byte_ok <= '0';
nfip_status_r_fcser_p_o <= '0';
else
s_rx_ctrl_byte_ok <= '0';
s_rx_PDU_byte_ok <= '0';
s_rx_length_byte_ok <= '0';
end if;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
cons_frame_ok_p_o <= rx_FSS_CRC_FES_viol_ok_p_i and
s_rx_length_byte_ok and
s_rx_ctrl_byte_ok and
s_rx_PDU_byte_ok;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignment for the output signals
cons_frame_ok_p_o <= rx_fss_crc_fes_viol_ok_p_i and
s_rx_length_byte_ok and
s_rx_ctrl_byte_ok and
s_rx_pdu_byte_ok;
nfip_status_r_tler_o <= s_rx_length_byte_ok and
s_rx_ctrl_byte_ok and
s_rx_pdu_byte_ok;
end architecture rtl;
--=================================================================================================
......
wf_consumption.vhd 0 → 100644
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file wf_consumption.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- wf_consumption --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 11/01/2011
--
--
--! @version v0.01
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! wf_prod_bytes_retriever \n
--! WF_status_bytes_gen \n
--! wf_tx_serializer \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! \n\n<b>Last changes:</b>\n
--! ->
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for wf_consumption
--=================================================================================================
entity wf_consumption is
port (
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic;
--! wf_cons_bytes_processor : for the storage of data bytes to the RAM or the DATO bus
slone_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit unit
nfip_urst_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP FIELDRIVE (actually from the WF_inputs_synchronizer)
fd_rxd_i : in std_logic;
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
--! wf_cons_bytes_processor : for the managment of the Consumption RAM
clk_wb_i : in std_logic;
wb_adr_i : in std_logic_vector(9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_engine_control
--! wf_cons_bytes_processor : for the reception coordination
var_i : in t_var;
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
--! wf_rx_deserializer : for the reseting of the wf_rx_deserializer unit
rst_rx_unit_p_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_rx_tx_osc
--! WF_rx_deglitcher & wf_rx_deserializer : for the timing of the reception
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
-----------------------------------------------------------------------------------------------
-- OUTPUTS
-- nanoFIP User Interface, WISHBONE Slave outputs
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
-- Signals to the WF_engine_control
byte_o : out std_logic_vector (7 downto 0);
byte_ready_p_o : out std_logic;
fss_received_p_o : out std_logic;
crc_wrong_p_o : out std_logic;
fss_crc_fes_viol_ok_p_o : out std_logic;
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0);
cons_ctrl_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_lgth_byte_o : out std_logic_vector (7 downto 0);
-- Signals to the WF_tx_rx_osc
rst_rx_osc_o : out std_logic
);
end entity wf_consumption;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture struc of wf_consumption is
signal s_rxd_filtered, s_rxd_filtered_f_edge_p : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_byte_from_rx : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
Consumption_Level_1 : wf_cons_bytes_processor
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
slone_i => slone_i,
byte_ready_p_i => byte_ready_p_i,
var_i => var_i,
byte_index_i => byte_index_i,
byte_i => s_byte_from_rx,
clk_wb_i => clk_wb_i,
wb_adr_i => wb_adr_i,
wb_stb_r_edge_p_i => wb_stb_r_edge_p_i,
wb_cyc_i => wb_cyc_i,
-------------------------------------------------
wb_ack_cons_p_o => wb_ack_cons_p_o,
data_o => data_o,
cons_ctrl_byte_o => cons_ctrl_byte_o,
cons_pdu_byte_o => cons_pdu_byte_o,
cons_lgth_byte_o => cons_lgth_byte_o,
cons_var_rst_byte_1_o => cons_var_rst_byte_1_o,
cons_var_rst_byte_2_o => cons_var_rst_byte_2_o
-------------------------------------------------
);
---------------------------------------------------------------------------------------------------
Consumption_Level_0_Deserializer: wf_rx_deserializer
port map (
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
rst_rx_unit_p_i => rst_rx_unit_p_i,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => signif_edge_window_i,
adjac_bits_window_i => adjac_bits_window_i,
rxd_f_edge_p_i => fd_rxd_f_edge_p_i,
rxd_r_edge_p_i => fd_rxd_r_edge_p_i,
rxd_filtered_i => s_rxd_filtered,
rxd_filtered_f_edge_p_i => s_rxd_filtered_f_edge_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
-------------------------------------------------
byte_ready_p_o => byte_ready_p_o,
byte_o => s_byte_from_rx,
fss_crc_fes_viol_ok_p_o => fss_crc_fes_viol_ok_p_o,
rst_rx_osc_o => rst_rx_osc_o,
fss_received_p_o => fss_received_p_o,
crc_wrong_p_o => crc_wrong_p_o
-------------------------------------------------
);
---------------------------------------------------------------------------------------------------
Consumption_Level_0_Deglitcher : WF_rx_deglitcher
generic map (c_DEGLITCH_LGTH => 10)
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
rxd_i => fd_rxd_i,
sample_bit_p_i => sample_bit_p_i,
sample_manch_bit_p_i => sample_manch_bit_p_i,
-------------------------------------------------
rxd_filtered_o => s_rxd_filtered,
rxd_filtered_f_edge_p_o => s_rxd_filtered_f_edge_p,
sample_manch_bit_p_o => s_sample_manch_bit_p,
sample_bit_p_o => s_sample_bit_p
-------------------------------------------------
);
---------------------------------------------------------------------------------------------------
byte_o <= s_byte_from_rx;
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
wf_crc.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
......@@ -26,15 +26,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name WF_crc
--
--
--! @brief The unit includes the modules for the generation of the CRC of serialized data,
--! as well as for the verification of an incoming CRC syndrome
--! @brief The unit includes the modules for the generation of the CRC of serial data,
--! as well as for the verification of an incoming CRC syndrome.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 08/2010
......@@ -48,17 +46,17 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--! \n<b>Dependencies:</b>\n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! \n<b>Modified by:</b> \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content
--! 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
--! variable v_q_check_mask replaced with a signal,
--! code cleaned-up+commented
--! -> 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content \n
--! -> 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
--! variable v_q_check_mask replaced with a signal,
--! code cleaned-up+commented \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -66,23 +64,33 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--!
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_crc
--=================================================================================================
entity WF_crc is
generic(c_GENERATOR_POLY_length : natural);
generic (c_GENERATOR_POLY_length : natural := 16); --! default value
port (
-- INPUTS
uclk_i : in std_logic; --! 40 MHz clock
nFIP_urst_i : in std_logic; --! internal reset
start_CRC_p_i : in std_logic; --! signaling the beginning of the CRC calculation
data_bit_i : in std_logic; --! incoming data bit stream
data_bit_ready_p_i : in std_logic; --! signaling that data_bit_i can be sampled
-- Inputs from the wf_rx_deserializer/ wf_tx_serializer
uclk_i : in std_logic; --! 40 MHz clock
nfip_urst_i : in std_logic; --! nanoFIP internal reset
start_crc_p_i : in std_logic; --! beginning of the CRC calculation
data_bit_i : in std_logic; --! incoming data bit stream
data_bit_ready_p_i : in std_logic; --! indicator of sampling time for data_bit_i
-- OUTPUTS
CRC_ok_p : out std_logic; --! signaling of a correct received CRC syndrome
CRC_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
-- Signal to the wf_rx_deserializer
crc_ok_p : out std_logic; --! signaling of a correct received CRC syndrome
-- Signal to the wf_tx_serializer
crc_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
);
end entity WF_crc;
......@@ -93,7 +101,7 @@ end entity WF_crc;
--=================================================================================================
architecture rtl of WF_crc is
signal s_crc_bit_ready_p : std_logic;
signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0);
--=================================================================================================
......@@ -102,38 +110,41 @@ signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length
begin
---------------------------------------------------------------------------------------------------
--!@brief The gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
--!@brief The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
--! of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
--! are interconnected as a linear feedback shift register.
gen_16_bit_Register_and_Interconnections: for I in 0 to c_GENERATOR_POLY'left generate
Gen_16_bit_Register_and_Interconnections:
iteration_0: if I = 0 generate
s_q_nx(I) <= ((data_bit_i) xor s_q(s_q'left));
end generate;
for I in 0 to c_GENERATOR_POLY'left generate
iteration_0: if I = 0 generate
s_q_nx(I) <= ((data_bit_i) xor s_q(s_q'left));
end generate;
iterations: if I > 0 generate
s_q_nx(I) <= s_q(I-1) xor (c_GENERATOR_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
next_iterations: if I > 0 generate
s_q_nx(I) <= s_q(I-1) xor (c_GENERATOR_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
end generate;
end generate;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process CRC_calculation: the process "moves" the shift register described
--! above, for the calculation of the CRC
CRC_calculation: process(uclk_i)
CRC_calculation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_q <= (others => '1'); -- register initialization
-- (initially preset, according to annex A)
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_q <= (others => '0');
else
if start_CRC_p_i = '1' then
if start_crc_p_i = '1' then
s_q <= (others => '1'); -- register initialization
-- (initially preset, according to the Annex)
elsif data_bit_ready_p_i = '1' then -- new data bit to be considered for the CRC calculation
s_q <= s_q_nx; -- data propagation
......@@ -146,27 +157,27 @@ begin
end process;
-- -- -- -- --
CRC_o <= not s_q;
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
--! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_VERIFICATION_MASK. When the CRC calculated from the received data maches the
--! c_VERIFICATION_MASK, it means a correct CRC word has been received and the signal CRC_ok_p
--! gives a pulse.
--! predefined c_VERIFICATION_MASK. When the CRC calculated from the received data matches the
--! c_VERIFICATION_MASK, it is implied that a correct CRC word has been received and the signal
--! crc_ok_p gives a pulse.
Syndrome_Verification: process(s_q, s_crc_bit_ready_p)
Syndrome_Verification: process (s_q, s_crc_bit_ready_p)
begin
s_q_check_mask <= s_q xor c_VERIFICATION_MASK;
if (unsigned(not s_q_check_mask)) = 0 then
CRC_ok_p <= s_crc_bit_ready_p;
crc_ok_p <= s_crc_bit_ready_p;
else
CRC_ok_p <= '0';
crc_ok_p <= '0';
end if;
end process;
......
wf_decr_counter.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd
---------------------------------------------------------------------------------------------------
......@@ -13,22 +21,21 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- --
-- WF_decr_counter --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Synchronous decreasing counter with a load enable and decrease enable signals;
--! @brief Synchronous decreasing counter with a reset, a load enable & a decrease
--! enable signal.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 06/2010
--! @date 10/2010
--
--
--! @version v0.02
--! @version v0.01
--
--
--! @details \n
......@@ -37,7 +44,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -50,31 +56,37 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_decr_counter
--=================================================================================================
entity WF_decr_counter is
generic(counter_length : natural);
generic (g_counter_lgth : natural := 4); --! default length
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
counter_top : in unsigned (counter_length-1 downto 0); --! load value
counter_load_i : in std_logic; --! load enable
counter_decr_p_i : in std_logic; --! decrement enable
-- Signals from any unit
counter_top : in unsigned (g_counter_lgth-1 downto 0); --! load value
counter_load_i : in std_logic; --! load enable
counter_decr_p_i : in std_logic; --! decrement enable
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (counter_length-1 downto 0);--! counter
counter_is_zero_o : out std_logic --! empty counter indication
counter_o : out unsigned (g_counter_lgth-1 downto 0); --! counter
counter_is_zero_o : out std_logic --! empty counter indication
);
end entity WF_decr_counter;
......@@ -84,18 +96,20 @@ end entity WF_decr_counter;
--=================================================================================================
architecture rtl of WF_decr_counter is
signal s_counter : unsigned(counter_length-1 downto 0);
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
Decr_Counter: process(uclk_i)
-- Synchronous process Decr_Counter
Decr_Counter: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_counter <= (others => '0');
else
......@@ -110,8 +124,8 @@ signal s_counter : unsigned(counter_length-1 downto 0);
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
......
wf_engine_control.vhd
View file @ c0ef0386
......@@ -27,7 +27,7 @@ use work.WF_PACKAGE.all;
--!
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
......@@ -60,7 +60,9 @@ use work.WF_PACKAGE.all;
--! if ID_DAT>8 bytes or RP_DAT>134 (bf reception of a FES) go to idle
--! state consume_wait_FSS, for the correct use of the silence time(time
--! stops counting when an RP_DAT frame has started)
--! removed check on slone mode for #bytes>4
--!
--! 12/2010 v0.02 EG removed check on slone mode for #bytes>4
--! in slone no broadcast
--
---------------------------------------------------------------------------------------------------
--
......@@ -74,74 +76,81 @@ use work.WF_PACKAGE.all;
--=================================================================================================
entity WF_engine_control is
generic( C_QUARTZ_PERIOD : real);
generic ( c_QUARTZ_PERIOD : real);
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! no NanoFIP status transmission
rate_i : in std_logic_vector (1 downto 0); --! Worldfip bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_tx unit
tx_request_byte_p_i : in std_logic; --!
-- Signals from the WF_rx unit
rx_FSS_received_p_i : in std_logic; --! correct FSS detected by WF_rx
rx_byte_ready_p_i : in std_logic; --! new byte from the receiver on rx_byte_i
rx_byte_i : in std_logic_vector (7 downto 0); -- Decoded byte
rx_CRC_FES_ok_p_i : in std_logic;
-- Signal from the WF_prod_bytes_to_tx
tx_sending_mps_i : in std_logic;
-- Signal from the WF_prod_bytes_to_tx
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_PDU_byte_i : in std_logic_vector (7 downto 0);
rx_Length_byte_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode
nostat_i : in std_logic; --! no NanoFIP status transmission
rate_i : in std_logic_vector (1 downto 0); --! Worldfip bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
p3_lgth_i : in std_logic_vector (2 downto 0); --! Produced variable data length
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the wf_tx_serializer unit
tx_request_byte_p_i : in std_logic; --!
-- Signals from the wf_rx_deserializer unit
rx_FSS_received_p_i : in std_logic; --! correct FSS detected by wf_rx_deserializer
rx_byte_ready_p_i : in std_logic; --! new byte from the receiver on rx_byte_i
rx_byte_i : in std_logic_vector (7 downto 0); -- Decoded byte
rx_CRC_FES_ok_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic; --! indication of a wrong CRC reception
-- Signal from the wf_prod_bytes_retriever
tx_sending_mps_i : in std_logic;
-- Signal from the wf_prod_bytes_retriever
rx_ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_pdu_byte_i : in std_logic_vector (7 downto 0);
rx_length_byte_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
-- OUTPUTS
-- User interface, non-WISHBONE nanoFIP outputs
var1_rdy_o : out std_logic; --! signals new data received and can safely be read
var2_rdy_o : out std_logic; --! signals new data received and can safely be read
var3_rdy_o : out std_logic; --! signals that data can safely be written in the memory
-- nanoFIP User Interface, NON-WISHBONE nanoFIP outputs
var1_rdy_o : out std_logic; --! signals new data received and can safely be read
var2_rdy_o : out std_logic; --! signals new data received and can safely be read
var3_rdy_o : out std_logic; --! signals that data can safely be written in the memory
-- Outputs to the WF_tx unit
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
-- Signal to the wf_tx_serializer unit
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
-- Output to WF_rx
rst_rx_unit_p_o : out std_logic;--! if an FES has not arrived after 8 bytes of an ID_DAT,
-- Signal to the wf_rx_deserializer
rst_rx_unit_p_o : out std_logic;--! if an FES has not arrived after 8 bytes of an ID_DAT,
--! or after 134 bytes of an RP_DAT, the state machine
--! of the WF_rx unit returns to idle state
--! of the wf_rx_deserializer unit returns to idle state
-- Signal to the wf_cons_bytes_processor, wf_prod_bytes_retriever, WF_reset_unit, WF_status_bytes_gen,
-- wf_var_rdy_generator, wf_prod_data_lgth_calc, wf_cons_frame_validator
var_o : out t_var;
-- Output to WF_concumed_vars and WF_prod_bytes_to_tx
var_o : out t_var;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
-- Signal to the wf_cons_bytes_processor, wf_prod_bytes_retriever
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
-- Output to WF_prod_bytes_to_tx
tx_data_length_o : out std_logic_vector (7 downto 0);
-- Signal to the wf_prod_bytes_retriever
tx_data_length_o : out std_logic_vector (7 downto 0);
-- Output to WF_tx
tx_byte_ready_p_o : out std_logic;
-- Signal to the wf_tx_serializer
tx_byte_ready_p_o : out std_logic;
-- output to WF_cons_bytes_from_rx
rx_byte_ready_p_o : out std_logic;
-- Signal to the wf_cons_bytes_processor
rx_byte_ready_p_o : out std_logic;
-- Output to WF_reset_unit
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic;
-- Signal to the WF_reset_unit
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
-- output to the WF_status_bytes_gen
rst_status_bytes_o : out std_logic
-- Signal to the WF_status_bytes_gen
nfip_status_r_fcser_p_o : out std_logic; --! indication of a wrong CRC reception
rst_status_bytes_o : out std_logic;
nfip_status_r_tler_o : out std_logic
);
end entity WF_engine_control;
......@@ -170,7 +179,7 @@ architecture rtl of WF_engine_control is
signal s_rx_bytes_c, s_tx_bytes_c : unsigned(7 downto 0);
signal s_tx_data_length : std_logic_vector(7 downto 0);
signal s_time_counter_top, s_time_c: unsigned(14 downto 0);
signal s_response_time, s_silence_time : unsigned(14 downto 0);
signal s_turnaround_time, s_silence_time : unsigned(14 downto 0);
signal s_produce_or_consume : std_logic_vector (1 downto 0);
signal s_id_dat_subs_byte, s_id_dat_frame_ok : std_logic;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_cons_wait_FSS: std_logic;
......@@ -196,10 +205,10 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Receiver_FSM_Sync: storage of the current state of the FSM
Central_Control_FSM_Sync: process(uclk_i)
Central_Control_FSM_Sync: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
control_st <= idle;
else
control_st <= nx_control_st;
......@@ -213,9 +222,9 @@ begin
Central_Control_FSM_Comb_State_Transitions:process (control_st, rx_FSS_received_p_i, s_tx_last_byte_p,
s_var_id, rx_byte_ready_p_i,rx_byte_i, subs_i,
s_time_c_is_zero,s_produce_or_consume, slone_i,
rx_CRC_FES_ok_p_i, s_broadcast_var, s_rx_bytes_c)
s_var_id, rx_byte_ready_p_i,rx_byte_i, s_rx_bytes_c,
s_time_c_is_zero,s_produce_or_consume,subs_i,
rx_CRC_FES_ok_p_i, s_broadcast_var)
begin
......@@ -262,9 +271,10 @@ begin
if (rx_byte_ready_p_i = '1') and (rx_byte_i = subs_i) then
nx_control_st <= id_dat_frame_ok;
elsif (rx_byte_ready_p_i = '1') and (s_broadcast_var = '1') then
nx_control_st <= id_dat_frame_ok;
elsif (rx_byte_ready_p_i = '1') and (s_broadcast_var = '1') then-- at this moment we do not
nx_control_st <= id_dat_frame_ok; -- check if slone=1, as the
-- rst var which is broad-
-- cast is treaded in slone
elsif (rx_byte_ready_p_i = '1') then
nx_control_st <= idle;
......@@ -453,7 +463,7 @@ begin
when others =>
s_idle_state <= '0';
s_idle_state <= '1';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
......@@ -483,24 +493,26 @@ begin
---------------------------------------------------------------------------------------------------
Cons_Frame_Validator: WF_cons_frame_validator
port map(
rx_Ctrl_byte_i => rx_Ctrl_byte_i,
rx_PDU_byte_i => rx_PDU_byte_i,
rx_Length_byte_i => rx_Length_byte_i,
rx_FSS_CRC_FES_viol_ok_p_i => rx_CRC_FES_ok_p_i,
rx_ctrl_byte_i => rx_ctrl_byte_i,
rx_pdu_byte_i => rx_pdu_byte_i,
rx_length_byte_i => rx_length_byte_i,
rx_fss_crc_fes_viol_ok_p_i => rx_CRC_FES_ok_p_i,
rx_crc_wrong_p_i => rx_crc_wrong_p_i,
var_i => s_var,
rx_byte_index_i => s_rx_bytes_c,
------------------------------------------------
cons_frame_ok_p_o => s_cons_frame_ok_p
------------------------------------------------
);
----------------------------------------------------
nfip_status_r_fcser_p_o => nfip_status_r_fcser_p_o,
nfip_status_r_tler_o => nfip_status_r_tler_o,
cons_frame_ok_p_o => s_cons_frame_ok_p);
----------------------------------------------------
---------------------------------------------------------------------------------------------------
VAR_RDY_Signals_Generation: WF_VAR_RDY_generator
VAR_RDY_Signals_Generation: WF_var_rdy_generator
port map (
uclk_i => uclk_i,
slone_i => slone_i,
subs_i => subs_i,
nFIP_urst_i => nFIP_urst_i,
nfip_urst_i => nfip_urst_i,
cons_frame_ok_p_i => s_cons_frame_ok_p,
var_i => s_var,
rx_var_rst_byte_1_i => rx_var_rst_byte_1_i,
......@@ -509,18 +521,18 @@ begin
var1_rdy_o => var1_rdy_o,
var2_rdy_o => var2_rdy_o,
var3_rdy_o => var3_rdy_o,
assert_RSTON_p_o => assert_RSTON_p_o,
rst_nFIP_and_FD_p_o => rst_nFIP_and_FD_p_o
assert_rston_p_o => assert_rston_p_o,
rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o
---------------------------------------
);
---------------------------------------------------------------------------------------------------
--!@brief Counter that counts the number of produced or consumed bytes of data.
Rx_Bytes_Counter: WF_incr_counter
generic map(counter_length => 8)
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
nfip_urst_i => nfip_urst_i,
reinit_counter_i => s_rst_rx_bytes_counter,
incr_counter_i => s_inc_rx_bytes_counter,
---------------------------------------------
......@@ -532,14 +544,15 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Counter that counts the number of produced or consumed bytes of data.
Tx_Bytes_Counter: WF_incr_counter
generic map(counter_length => 8)
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
nfip_urst_i => nfip_urst_i,
reinit_counter_i => s_rst_tx_bytes_counter,
incr_counter_i => s_inc_tx_bytes_counter,
---------------------------------------------
counter_o => s_tx_bytes_c
counter_o => s_tx_bytes_c,
counter_is_full_o => open
---------------------------------------------
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -593,14 +606,14 @@ begin
else s_rx_byte_index;
---------------------------------------------------------------------------------------------------
-- Managing the counter that counts either response or silence times in uclk ticks.
-- Managing the counter that counts either turnaround or silence times in uclk ticks.
-- The same counter is used in both cases. The signal s_time_counter_top initializes the counter
-- to either the response or the silence time.
-- to either the turnaround or the silence time.
Response_and_Silence_Time_Counter: WF_decr_counter
generic map(counter_length => 15)
generic map(g_counter_lgth => 15)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
nfip_urst_i => nfip_urst_i,
counter_top => s_time_counter_top,
counter_load_i => s_load_time_c,
counter_decr_p_i => '1',
......@@ -611,22 +624,22 @@ Response_and_Silence_Time_Counter: WF_decr_counter
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of response and silence times information (in equivalent number of uclk ticks) from
-- retrieval of turnaround and silence times information (in equivalent number of uclk ticks) from
-- the c_TIMEOUTS_TABLE declared in the WF_package unit.
s_response_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).response),
s_response_time'length);
s_turnaround_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).turnaround),
s_turnaround_time'length);
s_silence_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).silence),
s_response_time'length);
s_turnaround_time'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Response_and_Silence_Time_Counter_Arg: process(s_prod_wait_resp_time, s_response_time, s_cons_wait_FSS,
Response_and_Silence_Time_Counter_Arg: process (s_prod_wait_resp_time, s_turnaround_time, s_cons_wait_FSS,
s_silence_time, s_id_dat_frame_ok, s_produce_or_consume)
begin
if s_id_dat_frame_ok = '1' and s_produce_or_consume = "10" then
s_load_time_c <= '1'; -- counter loads
s_time_counter_top <= s_response_time;
s_time_counter_top <= s_turnaround_time;
elsif s_id_dat_frame_ok = '1' and s_produce_or_consume = "01" then
s_load_time_c <= '1'; -- counter loads
......@@ -659,7 +672,7 @@ Response_and_Silence_Time_Counter: WF_decr_counter
--! specified station address matches the SUBS configuration.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
id_dat_var_identifier: process(rx_byte_i)
id_dat_var_identifier: process (rx_byte_i)
begin
s_var_id <= var_whatever;
for I in c_VARS_ARRAY'range loop
......@@ -675,12 +688,12 @@ Response_and_Silence_Time_Counter: WF_decr_counter
s_load_var <= s_prod_wait_resp_time or s_consuming;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
id_dat_var: process(uclk_i)
id_dat_var: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_var <= var_whatever;
s_var_aux <= var_whatever;
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_var <= var_whatever;
s_var_aux <= var_whatever;
else
if s_idle_state = '1' then
......@@ -691,10 +704,10 @@ Response_and_Silence_Time_Counter: WF_decr_counter
end if;
if s_idle_state = '1' then
s_var <= var_whatever;
s_var <= var_whatever;
elsif s_load_var = '1' then
s_var <= s_var_aux;
s_var <= s_var_aux;
end if;
end if;
end if;
......@@ -708,7 +721,7 @@ Response_and_Silence_Time_Counter: WF_decr_counter
--!@brief: Combinatorial process Var_Characteristics: managment of the signals
--! s_produce_or_consume and s_broadcast_var, accroding to the value of s_var_aux.
Var_Characteristics: process(s_var_aux)
Var_Characteristics: process (s_var_aux)
begin
s_produce_or_consume <= "00";
s_broadcast_var <= '0';
......@@ -737,10 +750,10 @@ Response_and_Silence_Time_Counter: WF_decr_counter
---------------------------------------------------------------------------------------------------
--!@brief: essential buffering of output signals tx_last_byte_p_o, tx_byte_ready_p_o, tx_start_produce_p_o
process(uclk_i)
process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
tx_last_byte_p_o <= '0';
s_tx_last_byte_p_d <= '0';
s_tx_byte_ready_p_d1 <= '0';
......@@ -757,20 +770,19 @@ Response_and_Silence_Time_Counter: WF_decr_counter
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tx_start_produce_p_o <= s_tx_start_prod_p;
s_tx_byte_ready_p <= s_producing and (tx_request_byte_p_i or s_tx_start_prod_p);
tx_start_produce_p_o <= s_tx_start_prod_p;
s_tx_byte_ready_p <= s_producing and (tx_request_byte_p_i or s_tx_start_prod_p);
tx_byte_ready_p_o <= s_tx_byte_ready_p_d2;
tx_byte_ready_p_o <= s_tx_byte_ready_p_d2;
s_tx_last_byte_p <= s_producing and s_tx_data_length_match and tx_request_byte_p_i;
rst_status_bytes_o <= s_producing and s_tx_byte_ready_p_d2 and tx_sending_mps_i;
s_tx_last_byte_p <= s_producing and s_tx_data_length_match and tx_request_byte_p_i;
rst_status_bytes_o <= s_producing and s_tx_byte_ready_p_d2 and tx_sending_mps_i;
rx_byte_ready_p_o <= s_consuming and rx_byte_ready_p_i;
rx_byte_ready_p_o <= s_consuming and rx_byte_ready_p_i;
rst_rx_unit_p_o <= s_idle_state and rx_byte_ready_p_i;
rst_rx_unit_p_o <= s_idle_state and rx_byte_ready_p_i;
---------------------------------------------------------------------------------------------------
......
wf_incr_counter.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -24,17 +24,18 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
---------------------------------------------------------------------------------------------------
--
--
--! @brief Fully synchronous increasing counter with a reset, a reinitialise & an enable signal
--! @brief Synchronous increasing counter with a reset, a reinitialise and an increase
--! enable signal.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 06/2010
--! @date 10/2010
--
--
--! @version v0.02
--! @version v0.01
--
--
--! @details \n
......@@ -43,7 +44,6 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
......@@ -62,24 +62,25 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
entity WF_incr_counter is
generic(counter_length : natural);
generic (g_counter_lgth : natural := 4); --! default length
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from any unit
reinit_counter_i : in std_logic; --! reinitializes counter to 0
incr_counter_i: in std_logic; --! increment enable
reinit_counter_i : in std_logic; --! reinitializes counter to 0
incr_counter_i : in std_logic; --! increment enable
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned(counter_length-1 downto 0); --! counter
counter_is_full_o : out std_logic --! all counter bits at '1'
);
counter_o : out unsigned(g_counter_lgth-1 downto 0); --! counter
counter_is_full_o : out std_logic --! counter full indication
); --! (all bits to '1')
end entity WF_incr_counter;
......@@ -88,35 +89,39 @@ end entity WF_incr_counter;
--=================================================================================================
architecture rtl of WF_incr_counter is
signal s_counter, s_counter_full : unsigned(counter_length-1 downto 0);
signal c_COUNTER_FULL : unsigned(g_counter_lgth-1 downto 0);
signal s_counter : unsigned(g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
c_COUNTER_FULL <= (others => '1');
s_counter_full <= (others => '1');
---------------------------------------------------------------------------------------------------
Incr_Counter: process(uclk_i)
-- Synchronous process Incr_Counter
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_counter <= (others => '0');
if nfip_urst_i = '1' then
s_counter <= (others => '0');
elsif reinit_counter_i = '1' then
s_counter <= (others => '0');
s_counter <= (others => '0');
elsif incr_counter_i = '1' then
s_counter <= s_counter + 1;
s_counter <= s_counter + 1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter= s_counter_full
else '0';
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
end architecture rtl;
--=================================================================================================
......
wf_inputs_synchronizer.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_inputs_synchronizer.vhd
---------------------------------------------------------------------------------------------------
......@@ -10,26 +18,26 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_inputs_synchronizer --
-- --
-- CERN, BE/CO/HT --
-- WF_inputs_synchronizer --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief -- 1st flip-flop not considered (metastability)
-- transition on input signal of less than 2 clock cycles are not considered
--! @brief The unit synchronises all the input signals with to the uclk or wb_clk, to be used
-- by all the other units of nanoFIP; a set of 3ple buffers is used for each signal.
-- Note: Because of the 3ple buffering, transitions on input signals of less than 2
-- clk cycles are not considered.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 09/12/2010
--
--
--! @version v0.02
......@@ -38,6 +46,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -46,6 +55,11 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 10/2010 v0.01 EG First version
--! 12/2010 v0.02 EG fd_rxcdn added;
--! in nanoFIP input fd_rxd we also see the nanoFIP output fd_txd; in order to
--! get only the receiver's data, we filter fd_rxd with the reception activity
--! detection fd_rxcdn.
--
---------------------------------------------------------------------------------------------------
--
......@@ -54,6 +68,12 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_inputs_synchronizer
......@@ -63,63 +83,79 @@ entity WF_inputs_synchronizer is
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- User Interface WISHBONE slave
wbclk_i : in std_logic; --! WISHBONE clock
wb_rst_a_i : in std_logic; --! WISHBONE reset
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Rest of input signals
rstin_a_i : in std_logic;
slone_a_i : in std_logic;
nostat_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
wb_cyc_a_i : in std_logic;
wb_we_a_i : in std_logic;
wb_stb_a_i : in std_logic;
wb_adr_a_i : in std_logic_vector(9 downto 0);
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
dat_a_i : in std_logic_vector(15 downto 0);
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
m_id_a_i : in std_logic_vector(3 downto 0);
c_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0);
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock
rstin_a_i : in std_logic;
slone_a_i : in std_logic;
nostat_a_i : in std_logic;
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP WorldFIP Settings
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
m_id_a_i : in std_logic_vector(3 downto 0);
c_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
clk_wb_i : in std_logic; --! WISHBONE clock
wb_rst_a_i : in std_logic; --! WISHBONE reset
wb_cyc_a_i : in std_logic;
wb_we_a_i : in std_logic;
wb_stb_a_i : in std_logic;
wb_adr_a_i : in std_logic_vector(9 downto 0);
dat_a_i : in std_logic_vector(15 downto 0);
-- nanoFIP User Interface, non WISHBONE
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
-- nanoFIP FIELDRIVE
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_rxcdn_a_i : in std_logic;
-- OUTPUTS
-- Signals to nanofip
rsti_o : out std_logic; -- rstin_a_i synchronized to uclk
urst_r_edge_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
fd_wdgn_o : out std_logic;
fd_txer_o : out std_logic;
fd_rxd_o : out std_logic;
fd_rxd_edge_o : out std_logic;
fd_rxd_r_edge_o : out std_logic;
fd_rxd_f_edge_o : out std_logic;
wb_cyc_o : out std_logic;
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_adri_o : out std_logic_vector(9 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
slone_dati_o : out std_logic_vector(15 downto 0);
rate_o : out std_logic_vector(1 downto 0);
subs_o : out std_logic_vector(7 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0)
-- nanoFIP User Interface, General signals
rsti_o : out std_logic;
urst_r_edge_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
-- nanoFIP WorldFIP Settings
rate_o : out std_logic_vector(1 downto 0);
subs_o : out std_logic_vector(7 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0);
-- nanoFIP User Interface, WISHBONE Slave
wb_cyc_o : out std_logic;
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_adri_o : out std_logic_vector(9 downto 0);
-- nanoFIP User Interface, non WISHBONE
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
slone_dati_o : out std_logic_vector(15 downto 0);
-- nanoFIP FIELDRIVE
fd_wdgn_o : out std_logic;
fd_txer_o : out std_logic;
fd_rxd_o : out std_logic;
fd_rxd_edge_p_o : out std_logic;
fd_rxd_r_edge_p_o : out std_logic;
fd_rxd_f_edge_p_o : out std_logic
);
end entity WF_inputs_synchronizer;
......@@ -129,48 +165,47 @@ end entity WF_inputs_synchronizer;
--=================================================================================================
architecture rtl of WF_inputs_synchronizer is
signal s_wb_we_d3, s_wb_cyc_d1, s_wb_cyc_d2, s_wb_cyc_d3, s_fd_rxd_f_edge : std_logic;
signal s_var1_access_d1, s_var2_access_d1, s_var3_access_d1, s_fd_rxd_r_edge : std_logic;
signal s_var1_access_d2, s_var2_access_d2, s_var3_access_d2 : std_logic;
signal s_var1_access_d3, s_var2_access_d3, s_var3_access_d3 : std_logic;
signal s_wb_stb_d1, s_wb_stb_d2, s_wb_stb_d3, s_wb_stb_d4, s_wb_we_d1, s_wb_we_d2 : std_logic;
signal s_wb_we_d3, s_wb_cyc_d1, s_wb_cyc_d2, s_wb_cyc_d3, s_fd_rxd_f_edge : std_logic;
signal s_var1_access_d1, s_var2_access_d1, s_var3_access_d1, s_fd_rxd_r_edge : std_logic;
signal s_var1_access_d2, s_var2_access_d2, s_var3_access_d2 : std_logic;
signal s_var1_access_d3, s_var2_access_d3, s_var3_access_d3 : std_logic;
signal s_wb_stb_d1, s_wb_stb_d2, s_wb_stb_d3, s_wb_stb_d4, s_wb_we_d1, s_wb_we_d2 : std_logic;
signal s_mid_d1, s_mid_d2, s_mid_d3, s_cid_d1, s_cid_d2, s_cid_d3 : std_logic_vector(3 downto 0);
signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3 : std_logic_vector(2 downto 0);
signal s_u_rst_d3 : std_logic_vector(3 downto 0);--:= "0000";
signal s_nostat_d3, s_slone_d3 : std_logic_vector(2 downto 0);
signal s_wb_adr_d1, s_wb_adr_d2, s_wb_adr_d3 : std_logic_vector(9 downto 0);
signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0);
signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0);
signal s_wb_dati_d1, s_wb_dati_d2, s_wb_dati_d3 : std_logic_vector(7 downto 0);
signal s_slone_dati_d1, s_slone_dati_d3, s_slone_dati_d2 : std_logic_vector(15 downto 0);
signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3, s_fd_rxcdn_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3 : std_logic_vector(2 downto 0);
signal s_u_rst_d3 : std_logic_vector(3 downto 0);
signal s_nostat_d3, s_slone_d3 : std_logic_vector(2 downto 0);
signal s_wb_adr_d1, s_wb_adr_d2, s_wb_adr_d3 : std_logic_vector(9 downto 0);
signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0);
signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0);
signal s_wb_dati_d1, s_wb_dati_d2, s_wb_dati_d3 : std_logic_vector(7 downto 0);
signal s_slone_dati_d1, s_slone_dati_d3, s_slone_dati_d2 :std_logic_vector(15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
rstin_synchronisation_with_uclk: process (uclk_i)
RSTIN_synchronisation_with_uclk: process (uclk_i)
begin
if rising_edge(uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (2 downto 0) & (not rstin_a_i);
if rising_edge (uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (2 downto 0) & (not rstin_a_i);
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rsti_o <= s_u_rst_d3(2); -- active high
urst_r_edge_o <= not s_u_rst_d3(3) and s_u_rst_d3(2);
rsti_o <= s_u_rst_d3(2); -- active high
urst_r_edge_o <= not s_u_rst_d3(3) and s_u_rst_d3(2);
---------------------------------------------------------------------------------------------------
User_interf_general_signals_synchronisation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_slone_d3 <= (others => '0');
s_nostat_d3 <= (others => '0');
else
......@@ -180,45 +215,47 @@ architecture rtl of WF_inputs_synchronizer is
end if;
end if;
end process;
slone_o <= s_slone_d3(2);
nostat_o <= s_nostat_d3(2);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
slone_o <= s_slone_d3(2);
nostat_o <= s_nostat_d3(2);
---------------------------------------------------------------------------------------------------
fieldrive_inputs_synchronisation: process(uclk_i)
FIELDRIVE_inputs_synchronisation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_fd_rxd_d3 <= (others => '0');
s_fd_wdgn_d3 <= (others => '0');
s_fd_txer_d3 <= (others => '0');
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_fd_rxd_d3 <= (others => '0');
s_fd_wdgn_d3 <= (others => '0');
s_fd_txer_d3 <= (others => '0');
else
s_fd_rxd_d3 <= s_fd_rxd_d3 (1 downto 0) & fd_rxd_a_i;
s_fd_wdgn_d3 <= s_fd_wdgn_d3(1 downto 0) & fd_wdgn_a_i;
s_fd_txer_d3 <= s_fd_txer_d3(1 downto 0) & fd_txer_a_i;
s_fd_rxd_d3 <= s_fd_rxd_d3 (1 downto 0) & fd_rxd_a_i;
s_fd_wdgn_d3 <= s_fd_wdgn_d3(1 downto 0) & fd_wdgn_a_i;
s_fd_txer_d3 <= s_fd_txer_d3(1 downto 0) & fd_txer_a_i;
s_fd_rxcdn_d3 <= s_fd_rxcdn_d3(1 downto 0) & fd_rxcdn_a_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
fd_wdgn_o <= s_fd_wdgn_d3(2);
fd_txer_o <= s_fd_txer_d3(2);
fd_rxd_o <= s_fd_rxd_d3 (2) and (not s_fd_rxcdn_d3(2)); -- to clean rxd from txd
fd_wdgn_o <= s_fd_wdgn_d3(2);
fd_txer_o <= s_fd_txer_d3(2);
fd_rxd_o <= s_fd_rxd_d3(2);
s_fd_rxd_r_edge <= (not s_fd_rxd_d3(2)) and (s_fd_rxd_d3(1)) and (not s_fd_rxcdn_d3(2));
s_fd_rxd_f_edge <= (s_fd_rxd_d3(2)) and (not s_fd_rxd_d3(1)) and (not s_fd_rxcdn_d3(2));
s_fd_rxd_r_edge <= (not s_fd_rxd_d3(2)) and (s_fd_rxd_d3(1));
s_fd_rxd_f_edge <= (s_fd_rxd_d3(2)) and (not s_fd_rxd_d3(1));
fd_rxd_r_edge_p_o <= s_fd_rxd_r_edge;
fd_rxd_f_edge_p_o <= s_fd_rxd_f_edge;
fd_rxd_edge_p_o <= s_fd_rxd_r_edge or s_fd_rxd_f_edge;
fd_rxd_r_edge_o <= s_fd_rxd_r_edge;
fd_rxd_f_edge_o <= s_fd_rxd_f_edge;
fd_rxd_edge_o <= s_fd_rxd_r_edge or s_fd_rxd_f_edge;
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronisation: process(uclk_i)
VAR_ACC_synchronisation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nFIP_urst_i = '1' then
if nfip_urst_i = '1' then
s_var1_access_d1 <= '0';
s_var1_access_d2 <= '0';
s_var1_access_d3 <= '0';
......@@ -245,71 +282,72 @@ architecture rtl of WF_inputs_synchronizer is
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
var1_access_o <= s_var1_access_d3;
var2_access_o <= s_var2_access_d3;
var3_access_o <= s_var3_access_d3;
var1_access_o <= s_var1_access_d3;
var2_access_o <= s_var2_access_d3;
var3_access_o <= s_var3_access_d3;
---------------------------------------------------------------------------------------------------
WISHBONE_inputs_synchronisation: process(wbclk_i)
WISHBONE_inputs_synchronisation: process (clk_wb_i)
begin
if rising_edge(wbclk_i) then
if rising_edge (clk_wb_i) then
if wb_rst_a_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_dati_d1 <= (others => '0');
s_wb_dati_d2 <= (others => '0');
s_wb_dati_d3 <= (others => '0');
s_wb_adr_d1 <= (others => '0');
s_wb_adr_d2 <= (others => '0');
s_wb_adr_d3 <= (others => '0');
s_wb_stb_d1 <= '0';
s_wb_stb_d2 <= '0';
s_wb_stb_d3 <= '0';
s_wb_we_d1 <= '0';
s_wb_we_d2 <= '0';
s_wb_we_d3 <= '0';
s_wb_cyc_d1 <= '0';
s_wb_cyc_d2 <= '0';
s_wb_cyc_d3 <= '0';
s_wb_dati_d1 <= (others => '0');
s_wb_dati_d2 <= (others => '0');
s_wb_dati_d3 <= (others => '0');
s_wb_adr_d1 <= (others => '0');
s_wb_adr_d2 <= (others => '0');
s_wb_adr_d3 <= (others => '0');
s_wb_stb_d1 <= '0';
s_wb_stb_d2 <= '0';
s_wb_stb_d3 <= '0';
s_wb_we_d1 <= '0';
s_wb_we_d2 <= '0';
s_wb_we_d3 <= '0';
s_wb_cyc_d1 <= '0';
s_wb_cyc_d2 <= '0';
s_wb_cyc_d3 <= '0';
else
s_wb_dati_d3 <= s_wb_dati_d2;
s_wb_dati_d2 <= s_wb_dati_d1;
s_wb_dati_d1 <= dat_a_i(7 downto 0);
s_wb_dati_d1 <= dat_a_i (7 downto 0);
s_wb_adr_d3 <= s_wb_adr_d2;
s_wb_adr_d2 <= s_wb_adr_d1;
s_wb_adr_d1 <= wb_adr_a_i;
s_wb_adr_d3 <= s_wb_adr_d2;
s_wb_adr_d2 <= s_wb_adr_d1;
s_wb_adr_d1 <= wb_adr_a_i;
s_wb_stb_d1 <= wb_stb_a_i;
s_wb_stb_d2 <= s_wb_stb_d1;
s_wb_stb_d3 <= s_wb_stb_d2;
s_wb_stb_d4 <= s_wb_stb_d3;
s_wb_stb_d1 <= wb_stb_a_i;
s_wb_stb_d2 <= s_wb_stb_d1;
s_wb_stb_d3 <= s_wb_stb_d2;
s_wb_stb_d4 <= s_wb_stb_d3;
s_wb_we_d1 <= wb_we_a_i;
s_wb_we_d2 <= s_wb_we_d1;
s_wb_we_d3 <= s_wb_we_d2;
s_wb_we_d1 <= wb_we_a_i;
s_wb_we_d2 <= s_wb_we_d1;
s_wb_we_d3 <= s_wb_we_d2;
s_wb_cyc_d1 <= wb_cyc_a_i;
s_wb_cyc_d2 <= s_wb_cyc_d1;
s_wb_cyc_d3 <= s_wb_cyc_d2;
s_wb_cyc_d1 <= wb_cyc_a_i;
s_wb_cyc_d2 <= s_wb_cyc_d1;
s_wb_cyc_d3 <= s_wb_cyc_d2;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- --
wb_dati_o <= s_wb_dati_d3;
wb_adri_o <= s_wb_adr_d3;
wb_cyc_o <= s_wb_cyc_d3;
wb_we_o <= s_wb_we_d3;
wb_stb_o <= s_wb_stb_d3;
wb_stb_r_edge_o <= (not s_wb_stb_d4) and s_wb_stb_d3;
wb_dati_o <= s_wb_dati_d3;
wb_adri_o <= s_wb_adr_d3;
wb_cyc_o <= s_wb_cyc_d3;
wb_we_o <= s_wb_we_d3;
wb_stb_o <= s_wb_stb_d3;
wb_stb_r_edge_o <= (not s_wb_stb_d4) and s_wb_stb_d3;
--------------------------------------------------------------------------------------------------
Slone_dat_i_synchronization: process(uclk_i)
Slone_dat_i_synchronization: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_slone_dati_d1 <= (others => '0');
s_slone_dati_d2 <= (others => '0');
s_slone_dati_d3 <= (others => '0');
......@@ -322,13 +360,15 @@ architecture rtl of WF_inputs_synchronizer is
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- --
slone_dati_o <= s_slone_dati_d3;
slone_dati_o <= s_slone_dati_d3;
--------------------------------------------------------------------------------------------------
WFIP_settings_synchronisation: process(uclk_i)
WorldFIP_Settings_synchronisation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_rate_d1 <= (others => '0');
s_rate_d2 <= (others => '0');
s_rate_d3 <= (others => '0');
......@@ -369,12 +409,14 @@ architecture rtl of WF_inputs_synchronizer is
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- --
rate_o <= s_rate_d3;
subs_o <= s_subs_d3;
m_id_o <= s_mid_d3;
c_id_o <= s_cid_d3;
p3_lgth_o <= s_p3_lgth_d3;
rate_o <= s_rate_d3;
subs_o <= s_subs_d3;
m_id_o <= s_mid_d3;
c_id_o <= s_cid_d3;
p3_lgth_o <= s_p3_lgth_d3;
--------------------------------------------------------------------------------------------------
end architecture rtl;
......
wf_manch_code_viol_check.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd
--! @file WF_manch_code_viol_check.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
......@@ -27,10 +27,19 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--
--! @brief The unit follows an incoming serial signal and outputs a pulse
--! if a manchester 2 code violation is detected.
--! It is assumed that a violation happens if after half reception period
--! plus 2 uclck periods, the incoming signal has not had a transition.
--! @brief The unit follows the incoming deglitched serial signal and outputs a pulse if a
--! Manchester 2 (manch.) code violation is detected.
--! It is assumed that a violation happens if after a half-bit-clock period (plus 2 uclk
--! periods), the incoming signal has not had a transition.
--! Note: the term sample_manch_bit_p refers to the moments when a manch. encoded bit
--! should be sampled (before and after a significant edge), whereas the
--! sample_bit_p includes only the sampling of the 1st part, before the transition.
--! Example:
--! bit : 0
--! manch. encoded : _|-
--! sample_manch_bit_p : ^ ^
--! sample_bit_p : ^ (this sampling will give the 0)
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
......@@ -54,6 +63,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 12/12/2010 v0.02 EG cleaning-up+commenting
--
---------------------------------------------------------------------------------------------------
--
......@@ -70,21 +80,21 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
entity WF_manch_code_viol_check is
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from WF_rx
serial_input_signal_i : in std_logic; --! input signal
sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the wf_rx_deserializer
serial_input_signal_i : in std_logic; --! input signal
sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit
-- OUTPUTS
-- Signal to WF_rx
manch_code_viol_p_o : out std_logic --! pulse indicating a code violation
-- Signal to the wf_rx_deserializer
manch_code_viol_p_o : out std_logic --! pulse indicating a code violation
);
end entity WF_manch_code_viol_check;
......@@ -99,32 +109,29 @@ signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_si
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Check_Code_Violations:in order to check the existance code violations
--! the input signal is delayed by half reception period.
--! The signal check_code_viol_p is a pulse with period the reception period. The pulse occurs
--! 2 uclk periods after a manch. transition is expected.
--!@brief Synchronous process Check_Code_Violations: in order to check for code violations, the
--! input signal is delayed by half-bit-clock period (serial_input_signal_d).
--! The signal check_code_viol_p is a pulse occuring 2 uclk periods after a manch. transition is
--! expected.
--! As the following drawing roughly indicates, a violation exists if the signal and its delayed
--! version are identical on the s_check_code_viol_p moments.
--! version are identical on the check_code_viol_p moments.
-- 0 V- 1
-- rxd_filtered_o: __|--|____|--|__
-- s_serial_input_signal_d: __|--|____|--|__
-- s_check_code_viol_p: ^ ^ ^
-- 0 V- 1
-- rxd_filtered : __|--|____|--|__
-- serial_input_signal_d : __|--|____|--|__
-- check_code_viol : ^ ^ ^
Check_code_violations: process(uclk_i)
Check_code_violations: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nFIP_urst_i = '1' then
s_check_code_viol_p <='0';
s_sample_bit_p_d1 <='0';
s_sample_bit_p_d2 <='0';
s_serial_input_signal_d <='0';
if nfip_urst_i = '1' then
s_check_code_viol_p <= '0';
s_sample_bit_p_d1 <= '0';
s_sample_bit_p_d2 <= '0';
s_serial_input_signal_d <= '0';
else
......@@ -132,16 +139,17 @@ signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_si
s_serial_input_signal_d <= serial_input_signal_i;
end if;
s_check_code_viol_p <= s_sample_bit_p_d2; -- small delay
s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i;
s_check_code_viol_p <= s_sample_bit_p_d2; -- 2 uclk ticks delay
s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
manch_code_viol_p_o <= s_check_code_viol_p and
(not (serial_input_signal_i xor s_serial_input_signal_d));
-- Concurrent signal assignment
manch_code_viol_p_o <= s_check_code_viol_p and
(not (serial_input_signal_i xor s_serial_input_signal_d));
end architecture rtl;
......
wf_manch_encoder.vhd
View file @ c0ef0386
--=================================================================================================
--! @file wf_manch_encoder.vhd
--=================================================================================================
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_manch_encoder.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
......@@ -9,26 +17,25 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
---------------------------------------------------------------------------------------------------
-- --
-- wf_manch_encoder --
-- --
-- CERN, BE/CO/HT --
-- WF_manch_encoder --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief
--! @brief Encoding of a word to its Manchester 2 (manch.) equivalent.
--! This code ensures that there is one transition for each bit.
--! bit : "0" "1"
--! manch. encoded : "0 1" "1 0"
--! scheme : _|- -|_
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 10/12/2010
--
--
--! @version v0.02
......@@ -39,12 +46,15 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n<b>Dependencies:</b>\n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! \n<b>Modified by:</b> \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG 1st version \n
--! -> 12/2010 v0.02 EG cleaned-up, commented \n
--!
--
---------------------------------------------------------------------------------------------------
--
......@@ -53,21 +63,26 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for wf_manch_encoder
--=================================================================================================
entity wf_manch_encoder is
generic(word_length : natural);
generic (word_length : natural := 8); --! default length: 8
port (
-- INPUT
word_i : in std_logic_vector(word_length-1 downto 0);
word_i : in std_logic_vector(word_length-1 downto 0); --! input word
-- OUTPUT
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0)
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0) --! output encoded word
);
end entity wf_manch_encoder;
......@@ -79,20 +94,24 @@ architecture rtl of wf_manch_encoder is
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--! @brief combinatorial process Manchester_Encoder_byte: The process takes a byte (8 bits) and
--! creates its manchester encoded equivalent (16 bits). Each bit '1' is replaced by '10' and each
--! bit '0' by '01'.
--! @brief Combinatorial process Manchester_Encoder: The process takes a word (ex. 8 bits) and
--! creates its manchester encoded equivalent (ex. 16 bits).
--! Each bit '1' is replaced by '10' and each bit '0' by '01'.
Manchester_Encoder_byte: process(word_i)
Manchester_Encoder: process (word_i)
begin
for I in word_i'range loop
word_manch_o(I*2) <= not word_i(I);
word_manch_o(I*2+1) <= word_i(I);
end loop;
end process;
......
wf_model_constr_decoder.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -17,6 +17,8 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
......@@ -38,13 +40,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! Vcc 11
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)\n
--! Evangelia Gousiou (evangelia.gousiou@cern.ch) \n
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--! @date 08/2010
--! @date 06/10/2010
--
--
--! @version v0.02
--! @version v0.03
--
--
--! @details\n
......@@ -55,15 +57,17 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/09/2009 v0.01 EB First version \n
--! -> 11/09/2009 v0.01 PAS First version \n
--! -> 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1
--! "for" loop replaced with signals concatenation;
--! Counter is of C_RELOAD_MID_CID bits; Code cleaned-up \n
--! Counter is of c_RELOAD_MID_CID bits; Code cleaned-up \n
--! -> 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed;
--! separate processes for counter and the rest
--
---------------------------------------------------------------------------------------------------
--
......@@ -72,8 +76,8 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\--------------------------/!\--
-- Sunplify Premier Warnings --
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
......@@ -83,28 +87,27 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! Entity declaration for WF_model_constr_decoder
--=================================================================================================
entity WF_model_constr_decoder is
generic (C_RELOAD_MID_CID : natural); --! reloading of model & constructor
--! every 2^(C_RELOAD_MID_CID) uclk ticks
port (
-- INPUTS
-- User Interface general signal
uclk_i : in std_logic; --! 40 Mhz clock
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 Mhz clock
-- Signal from the WF_reset_unit
nFIP_urst_i : in std_logic; --! nanoFIP internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- WorldFIP settings
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
-- nanoFIP WorldFIP Settings (synchronised with uclk_i)
model_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
constr_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
-- OUTPUTS
-- WorldFIP settings nanoFIP output
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- nanoFIP WorldFIP Settings output
select_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- Output to WF_prod_bytes_to_tx
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
-- Signal to the wf_prod_bytes_retriever
model_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
constr_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
);
end entity WF_model_constr_decoder;
......@@ -118,10 +121,10 @@ end entity WF_model_constr_decoder;
architecture rtl of WF_model_constr_decoder is
signal s_load_model_constr_p : std_logic;
signal s_counter, s_counter_full : unsigned (C_RELOAD_MID_CID-1 downto 0);
signal s_model_even, s_model_odd : std_logic_vector (3 downto 0);
signal s_constr_even, s_constr_odd : std_logic_vector (3 downto 0);
signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0);
--=================================================================================================
......@@ -129,65 +132,74 @@ architecture rtl of WF_model_constr_decoder is
--=================================================================================================
begin
s_counter_full <= (others => '1');
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Model_Constructor_Decoder:
--! For M_ID and C_ID to be decoded, 2 uclk periods are needed: on the first uclk tick, the values
--! of all the odd bits of M_ID and C_ID are loaded on the registers s_model_odd/ s_constr_odd
--! and on the second uclk tick, the values of all the even bits are loaded on the registers
--! s_model_even/ s_constr_even.
--! The signal s_load_model_constr_p signals the recalculation of the model and constructor.
--! It is activated every 2^(C_RELOAD_MID_CID) uclk periods. At those moments, the odd and even
--! parts are concatenated to form the m_id_dec_o and c_id_dec_o decoded outputs.
Model_Constructor_Decoder: process(uclk_i)
--! For M_ID and C_ID to be loaded, 2 uclk periods are needed: on the first uclk tick, the values
--! of all the odd bits of M_ID & C_ID are loaded on the registers s_model_stage1/ s_constr_stage1
--! and on the second uclk tick, the values of the odd bits move to the registers s_model_stage2/
--! s_constr_stage2, giving place to all the even bits to be loaded to the s_model_stage1/
--! s_constr_stage1. On a third uclk tick the loaded odd and even values are combined to give
--! the decoded outputs (model_id_dec_o & constr_id_dec_o).
Model_Constructor_Decoder: process (uclk_i)
begin
if rising_edge(uclk_i) then -- initializations
if nFIP_urst_i = '1' then
s_counter <= (others => '0');
m_id_dec_o <= (others => '0');
c_id_dec_o <= (others => '0');
s_model_odd <= (others => '0');
s_model_even <= (others => '0');
s_constr_odd <= (others => '0');
s_constr_even <= (others => '0');
if rising_edge (uclk_i) then -- initializations
if nfip_urst_i = '1' then
model_id_dec_o <= (others => '0');
constr_id_dec_o <= (others => '0');
s_model_stage1 <= (others => '0');
s_model_stage2 <= (others => '0');
s_constr_stage1 <= (others => '0');
s_constr_stage2 <= (others => '0');
else
s_model_stage1 <= model_id_i; -- after 2 uclk ticks stage1 keeps the even bits
s_model_stage2 <= s_model_stage1; -- and stage2 the odd ones
s_counter <= s_counter +1; -- when the counter is full, the C_ID
-- and M_ID are recalculated
s_model_odd <= m_id_i; -- 1st clock tick for the loading of the
s_model_even <= s_model_odd; -- odd bits; 2nd clock tick for the even
s_constr_stage1 <= constr_id_i; -- same for the constructor
s_constr_stage2 <= s_constr_stage1;
s_constr_odd <= c_id_i; -- same for the constructor
s_constr_even <= s_constr_odd;
if s_counter="10" then
if s_load_model_constr_p = '1' then
model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together
s_model_stage2(2) & s_model_stage1(2) & -- odd and even bits
s_model_stage2(1) & s_model_stage1(1) &
s_model_stage2(0) & s_model_stage1(0);
m_id_dec_o <= s_model_even(3) & s_model_odd(3) &-- putting together odd and even bits
s_model_even(2) & s_model_odd(2) &
s_model_even(1) & s_model_odd(1) &
s_model_even(0) & s_model_odd(0);
constr_id_dec_o <= s_constr_stage1(3) & s_constr_stage2(3) &
s_constr_stage1(2) & s_constr_stage2(2) &
s_constr_stage1(1) & s_constr_stage2(1) &
s_constr_stage1(0) & s_constr_stage2(0);
end if;
c_id_dec_o <= s_constr_even(3) & s_constr_odd(3) &
s_constr_even(2) & s_constr_odd(2) &
s_constr_even(1) & s_constr_odd(1) &
s_constr_even(0) & s_constr_odd(0);
end if;
end if;
end if;
end process;
s_load_model_constr_p <= '1' when s_counter = s_counter_full
else '0'; -- recalculation of C_ID and M_ID
-- when the counter fills up
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of a counter WF_incr_counter
Free_Counter: WF_incr_counter
generic map(g_counter_lgth => 2)
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
reinit_counter_i => '0',
incr_counter_i => '1',
-----------------------------------------
counter_o => s_counter,
counter_is_full_o => s_counter_is_full);
-----------------------------------------
-- 2 opposite clocks generated using
-- the LSB of the counter
s_id_o <= ((not s_counter(0)) & s_counter(0)); -- S_ID0: |--|__|--|__|--|__|--|__
-- S_ID1: __|--|__|--|__|--|__|--|
---------------------------------------------------------------------------------------------------
--!@brief Concurrent signal assignment for the output select_id_o
select_id_o <= ((not s_counter(0)) & s_counter(0)); -- 2 opposite clocks generated using
-- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___
-- S_ID1 : |____|----|____|----|____|---
end architecture rtl;
......
wf_package.vhd
View file @ c0ef0386
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
-- Purpose: This package defines supplemental types, subtypes, constants, and functions
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> egousiou: base_addr unsigned(8 downto 0) instead of std_logic_vector (9 downto 0),
--! to simplify calculations
--! turnaround times
--! broadcast: 91 instead of 04
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
use ieee.numeric_std.all;
package WF_package is
constant C_QUARTZ_PERIOD : real := 25.0;
constant C_TXCLKBUFFLENTGTH : natural := 4;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant c_QUARTZ_PERIOD : real := 25.0;
constant C_RELOAD_MID_CID : natural := 8;
constant c_TX_CLK_BUFF_LGTH : natural := 4;
constant c_RELOAD_MID_CID : natural := 8;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the CRC calcutator
constant c_GENERATOR_POLY_length : natural:= 16;
-- Constants regarding the CRC calculator
-- shift register xor mask
constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length- 1 downto 0) :=
"0001110111001111";
constant c_GENERATOR_POLY_length : natural := 16;
-- Shift register xor mask
constant c_GENERATOR_POLY : std_logic_vector (c_GENERATOR_POLY_length- 1 downto 0) :=
"0001110111001111";
-- CRC check mask
constant c_VERIFICATION_MASK:std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
constant c_VERIFICATION_MASK : std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
"0001110001101011";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the manchester coding
constant VP : std_logic_vector (1 downto 0) := "11";
constant VN : std_logic_vector (1 downto 0) := "00";
constant ONE : std_logic_vector (1 downto 0) := "10";
-- Constants regarding the Manchester 2 coding
constant VP : std_logic_vector (1 downto 0) := "11";
constant VN : std_logic_vector (1 downto 0) := "00";
constant ONE : std_logic_vector (1 downto 0) := "10";
constant ZERO : std_logic_vector (1 downto 0) := "01";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the ID_DAT and RP_DAT frame structure
constant PREAMBLE : std_logic_vector (15 downto 0) := ONE&ZERO&ONE&ZERO&ONE&ZERO&ONE&ZERO;
constant FRAME_START : std_logic_vector (15 downto 0) := ONE&VP&VN&ONE&ZERO&VN&VP&ZERO;
constant FRAME_END : std_logic_vector (15 downto 0) := ONE&VP&VN&VP&VN&ONE&ZERO&ONE;
constant FSS : std_logic_vector (31 downto 0) := PREAMBLE&FRAME_START;
-- Constants regarding the ID_DAT and RP_DAT frame structure
constant PRE : std_logic_vector (15 downto 0) := ONE & ZERO & ONE & ZERO & ONE & ZERO & ONE & ZERO;
constant FSD : std_logic_vector (15 downto 0) := ONE & VP & VN & ONE & ZERO & VN & VP & ZERO;
constant FES : std_logic_vector (15 downto 0) := ONE & VP & VN & VP & VN & ONE & ZERO & ONE;
constant FSS : std_logic_vector (31 downto 0) := PRE & FSD;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants concerning the control byte of an ID_DAT and RP_DAT frames and the PDU_TYPE byte of
-- a condumed or produced variable
constant c_ID_DAT_CTRL_BYTE : std_logic_vector (7 downto 0) := "00000011";
constant c_RP_DAT_CTRL_BYTE : std_logic_vector (7 downto 0) := "00000010";
-- Constants concerning the control byte of an ID_DAT and RP_DAT frames and the PDU_TYPE byte of
-- a consumed or produced variable
constant c_ID_DAT_CTRL_BYTE : std_logic_vector (7 downto 0) := "00000011";
constant c_RP_DAT_CTRL_BYTE : std_logic_vector (7 downto 0) := "00000010";
constant c_PROD_CONS_PDU_TYPE_BYTE : std_logic_vector (7 downto 0) := "01000000";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the nanoFIP status bits
-- Constants concerning the nanoFIP status bits
constant c_U_CACER_INDEX : integer := 2;
constant c_U_PACER_INDEX : integer := 3;
constant c_R_BNER_INDEX : integer := 4;
constant c_R_TLER_INDEX : integer := 4;
constant c_R_FCSER_INDEX : integer := 5;
constant c_T_TXER_INDEX : integer := 6;
constant c_T_WDER_INDEX : integer := 7;
constant c_T_TXER_INDEX : integer := 6;
constant c_T_WDER_INDEX : integer := 7;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the MPS status bits
constant c_REFRESHMENT_INDEX : integer := 0;
-- Constants concerning the MPS status bits
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the position of certain bytes in the frame structure
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LENGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
-- Constants concerning the position of certain bytes in the frame structure
constant c_CTRL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000000"; -- 0
constant c_PDU_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000001"; -- 1
constant c_LENGTH_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000010"; -- 2
constant c_1st_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3
constant c_2nd_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000100"; -- 4
constant c_CONSTR_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000110"; -- 6
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
constant c_CONSTR_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000110"; -- 6
constant c_MODEL_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000111"; -- 7
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table for the P3_LGTH[2:0] settings
-- Construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(0 to 7) :=
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000010" -- reserved
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000010" -- reserved
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- calculations of the number of uclk ticks equivalent to the reception/ transmission period
constant C_PERIODS_COUNTER_LENGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
-- period is 32000ns and can be measured after
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LENGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- transmission/reception periods.
-- transmission/ reception periods.
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit:unsigned:=
to_unsigned((32000/ integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit:unsigned:=
to_unsigned((1000/ integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit:unsigned:=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned :=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),C_PERIODS_COUNTER_LENGTH);
-- formation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks(3 downto 0):=
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table with the timeout and silence times for each bit rate
-- the table contains the number of uclk tick corresponding to the respone/ silence times
-- Construction of a table with the turnaround and silence times for each bit rate.
-- The table contains the number of uclk ticks corresponding to the turnaround/ silence times.
type t_timeouts is
record
response : integer;
silence : integer;
turnaround : integer;
silence : integer;
end record;
constant c_31K25_INDEX : integer := 0;
constant c_1M_INDEX : integer := 1;
constant c_2M5_INDEX : integer := 2;
constant c_31K25_INDEX : integer := 0;
constant c_1M_INDEX : integer := 1;
constant c_2M5_INDEX : integer := 2;
constant c_RESERVE_INDEX : integer := 3;
type t_timeouts_table is array (natural range <>) of t_timeouts;
......@@ -144,47 +159,46 @@ package WF_package is
constant c_TIMEOUTS_TABLE : t_timeouts_table(0 to 3) :=
(c_31K25_INDEX => (response => integer(640000.0/C_QUARTZ_PERIOD),
silence => integer(5160000.0/C_QUARTZ_PERIOD)),
(c_31K25_INDEX => (turnaround => integer (760000.0 / c_QUARTZ_PERIOD),
silence => integer (5160000.0 / c_QUARTZ_PERIOD)),
c_1M_INDEX => (response => integer(45000.0/C_QUARTZ_PERIOD),
silence => integer(150000.0/C_QUARTZ_PERIOD)),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
silence => integer (150000.0 / c_QUARTZ_PERIOD)),
c_2M5_INDEX => (response => integer(16000.0/C_QUARTZ_PERIOD),
silence => integer(100000.0/C_QUARTZ_PERIOD)),
c_2M5_INDEX => (turnaround => integer (6000.0 / c_QUARTZ_PERIOD),
silence => integer (100000.0 / c_QUARTZ_PERIOD)),
c_RESERVE_INDEX => (response => integer(640000.0/C_QUARTZ_PERIOD),
silence => integer(5160000.0/C_QUARTZ_PERIOD))
c_RESERVE_INDEX => (turnaround => integer (760000.0 /C_QUARTZ_PERIOD),
silence => integer (5160000.0 /C_QUARTZ_PERIOD))
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table with that gathers all the main information for all the variables
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_whatever);
-- Construction of a table that gathers main information for all the variables
type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_whatever);
type t_byte_array is array (natural range <>) of std_logic_vector (7 downto 0);
type t_var_response is (produce, consume, reset);
type t_var_record is record
response : t_var_response;
hexvalue : std_logic_vector (7 downto 0);
var : t_var;
base_addr : unsigned (8 downto 0);
last_addr : unsigned (8 downto 0);
var : t_var;
hexvalue : std_logic_vector (7 downto 0);
response : t_var_response;
base_addr : unsigned (8 downto 0);
array_length : unsigned (7 downto 0);
byte_array : t_byte_array (0 to 15);
byte_array : t_byte_array (0 to 15);
end record;
type t_var_array is array (natural range <>) of t_var_record;
constant c_VAR_PRESENCE_INDEX : integer := 0;
constant c_VAR_IDENTIF_INDEX : integer := 1;
constant c_VAR_3_INDEX : integer := 2;
constant c_VAR_1_INDEX : integer := 3;
constant c_VAR_2_INDEX : integer := 4;
constant c_VAR_RST_INDEX : integer := 5;
constant c_VAR_IDENTIF_INDEX : integer := 1;
constant c_VAR_3_INDEX : integer := 2;
constant c_VAR_1_INDEX : integer := 3;
constant c_VAR_2_INDEX : integer := 4;
constant c_VAR_RST_INDEX : integer := 5;
constant c_VARS_ARRAY : t_var_array(0 to 5) :=
......@@ -193,7 +207,6 @@ package WF_package is
hexvalue => x"14",
response => produce,
base_addr => "---------",
last_addr => "---------",
array_length => "00000111", -- 8 bytes in total including the Control byte
-- (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
......@@ -204,10 +217,9 @@ package WF_package is
c_VAR_IDENTIF_INDEX => (var => var_identif,
hexvalue => x"10",
response => produce,
base_addr => "---------",
array_length => "00001010", -- 11 bytes in total including the Control byte
-- (counting starts from 0)
base_addr => "---------",
last_addr => "---------",
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00", 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00", 9 => x"00", 10 => x"00",
......@@ -218,18 +230,16 @@ package WF_package is
hexvalue => x"06",
response => produce,
base_addr => "100000000",
last_addr => "101111101",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
c_VAR_1_INDEX => (var => var_1,
c_VAR_1_INDEX => (var => var_1,
hexvalue => x"05",
response => consume,
base_addr => "000000000",
last_addr => "001111111",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
......@@ -237,20 +247,18 @@ package WF_package is
c_VAR_2_INDEX => (var => var_2,
hexvalue => x"04",
hexvalue => x"91", --------------
response => consume,
base_addr => "010000000",
last_addr => "011111111",
array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")),
c_VAR_RST_INDEX => (var => var_rst,
c_VAR_RST_INDEX => (var => var_rst,
hexvalue => x"e0",
response => reset,
base_addr => "010000000",
last_addr => "011111111",
base_addr => "---------",
array_length => "00000001", -- only the Control byte is predefined
-- (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
......@@ -259,326 +267,389 @@ package WF_package is
---------------------------------------------------------------------------------------------------
-- Components definitions: --
-- Components Declaration: --
---------------------------------------------------------------------------------------------------
component WF_inputs_synchronizer is
component WF_inputs_synchronizer is
port (
uclk_i : in std_logic;
wbclk_i : in std_logic;
nFIP_urst_i : in std_logic;
rstin_a_i : in std_logic;
wb_rst_a_i : in std_logic;
slone_a_i : in std_logic;
nostat_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
wb_cyc_a_i : in std_logic;
wb_we_a_i : in std_logic;
wb_stb_a_i : in std_logic;
wb_adr_a_i : in std_logic_vector(9 downto 0);
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
dat_a_i : in std_logic_vector(15 downto 0);
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
m_id_a_i : in std_logic_vector(3 downto 0);
c_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0);
rsti_o : out std_logic;
urst_r_edge_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
fd_wdgn_o : out std_logic;
fd_txer_o : out std_logic;
fd_rxd_o : out std_logic;
fd_rxd_edge_o : out std_logic;
fd_rxd_r_edge_o : out std_logic;
fd_rxd_f_edge_o : out std_logic;
wb_cyc_o : out std_logic;
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_adri_o : out std_logic_vector(9 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
slone_dati_o : out std_logic_vector(15 downto 0);
rate_o : out std_logic_vector(1 downto 0);
subs_o : out std_logic_vector(7 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0)
);
uclk_i : in std_logic;
clk_wb_i : in std_logic;
nfip_urst_i : in std_logic;
rstin_a_i : in std_logic;
wb_rst_a_i : in std_logic;
slone_a_i : in std_logic;
nostat_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_rxcdn_a_i : in std_logic;
wb_cyc_a_i : in std_logic;
wb_we_a_i : in std_logic;
wb_stb_a_i : in std_logic;
wb_adr_a_i : in std_logic_vector(9 downto 0);
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
dat_a_i : in std_logic_vector(15 downto 0);
rate_a_i : in std_logic_vector(1 downto 0);
subs_a_i : in std_logic_vector(7 downto 0);
m_id_a_i : in std_logic_vector(3 downto 0);
c_id_a_i : in std_logic_vector(3 downto 0);
p3_lgth_a_i : in std_logic_vector(2 downto 0);
-----------------------------------------------------------------
rsti_o : out std_logic;
urst_r_edge_o : out std_logic;
slone_o : out std_logic;
nostat_o : out std_logic;
fd_wdgn_o : out std_logic;
fd_txer_o : out std_logic;
fd_rxd_o : out std_logic;
fd_rxd_edge_p_o : out std_logic;
fd_rxd_r_edge_p_o : out std_logic;
fd_rxd_f_edge_p_o : out std_logic;
wb_cyc_o : out std_logic;
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_stb_r_edge_o : out std_logic;
wb_dati_o : out std_logic_vector(7 downto 0);
wb_adri_o : out std_logic_vector(9 downto 0);
var1_access_o : out std_logic;
var2_access_o : out std_logic;
var3_access_o : out std_logic;
slone_dati_o : out std_logic_vector(15 downto 0);
rate_o : out std_logic_vector(1 downto 0);
subs_o : out std_logic_vector(7 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0)
-----------------------------------------------------------------
);
end component WF_inputs_synchronizer;
---------------------------------------------------------------------------------------------------
component WF_rx
component wf_rx_deserializer
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
rst_rx_unit_p_i : in std_logic;
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
rxd_r_edge_i : in std_logic;
rxd_f_edge_i : in std_logic;
rxd_filtered_o : in std_logic;
rxd_filtered_f_edge_p_i: in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
CRC_wrong_p_o : out std_logic;
FSS_CRC_FES_viol_ok_p_o : out std_logic;
FSS_received_p_o : out std_logic;
rst_rx_osc_o : out std_logic
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
rst_rx_unit_p_i : in std_logic;
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
rxd_r_edge_p_i : in std_logic;
rxd_f_edge_p_i : in std_logic;
rxd_filtered_i : in std_logic;
rxd_filtered_f_edge_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
-----------------------------------------------------------------
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
crc_wrong_p_o : out std_logic;
fss_crc_fes_viol_ok_p_o : out std_logic;
fss_received_p_o : out std_logic;
rst_rx_osc_o : out std_logic
-----------------------------------------------------------------
);
end component WF_rx;
end component wf_rx_deserializer;
---------------------------------------------------------------------------------------------------
component WF_tx
generic (C_TXCLKBUFFLENTGTH : natural);
component wf_tx_serializer
generic (c_TX_CLK_BUFF_LGTH : natural);
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_clk_p_buff_i : in std_logic_vector (C_TXCLKBUFFLENTGTH -1 downto 0);
request_byte_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
start_prod_p_i : in std_logic;
byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
-------------------------------------------------------------------------
request_byte_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic
-------------------------------------------------------------------------
);
end component WF_tx;
end component wf_tx_serializer;
---------------------------------------------------------------------------------------------------
component WF_rx_tx_osc
generic (C_PERIODS_COUNTER_LENGTH : natural;
C_QUARTZ_PERIOD : real;
C_TXCLKBUFFLENTGTH : natural);
c_TX_CLK_BUFF_LGTH : natural);
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nFIP_urst_i : in std_logic;
rxd_edge_i : in std_logic;
rxd_f_edge_i : in std_logic;
rst_rx_osc_i : in std_logic;
rx_manch_clk_p_o : out std_logic;
rx_bit_clk_p_o : out std_logic;
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nfip_urst_i : in std_logic;
rxd_edge_i : in std_logic;
rst_rx_osc_i : in std_logic;
-------------------------------------------------------------------------
rx_manch_clk_p_o : out std_logic;
rx_bit_clk_p_o : out std_logic;
rx_signif_edge_window_o : out std_logic;
rx_adjac_bits_window_o : out std_logic;
tx_clk_o : out std_logic;
tx_clk_p_buff_o : out std_logic_vector (C_TXCLKBUFFLENTGTH -1 downto 0)
);
rx_adjac_bits_window_o : out std_logic;
tx_clk_o : out std_logic;
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0)
-------------------------------------------------------------------------
);
end component WF_rx_tx_osc;
---------------------------------------------------------------------------------------------------
component WF_tx_rx
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
nFIP_urst_i : in std_logic;
rst_rx_unit_p_i : in std_logic;
start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic;
fd_rxd : in std_logic;
fd_rxd_edge_i : in std_logic;
fd_rxd_r_edge_i : in std_logic;
fd_rxd_f_edge_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
request_byte_p_o : out std_logic;
tx_enable_o : out std_logic;
d_clk_o : out std_logic;
tx_data_o : out std_logic;
byte_ready_p_o : out std_logic;
CRC_wrong_p_o : out std_logic;
FSS_received_p_o : out std_logic;
FSS_CRC_FES_viol_ok_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0)
);
end component WF_tx_rx;
component wf_cons_bytes_processor
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_urst_i : in std_logic;
clk_wb_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
cons_ctrl_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_lgth_byte_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
end component wf_cons_bytes_processor;
---------------------------------------------------------------------------------------------------
component WF_cons_bytes_from_rx
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nFIP_urst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector (7 downto 0);
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
rx_Ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_PDU_byte_o : out std_logic_vector (7 downto 0);
rx_Length_byte_o : out std_logic_vector (7 downto 0);
rx_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
rx_var_rst_byte_2_o : out std_logic_vector (7 downto 0)
);
end component WF_cons_bytes_from_rx;
---------------------------------------------------------------------------------------------------
component WF_slone_bytes_to_DATO is
component wf_cons_bytes_to_dato is
port (
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
transfer_byte_p_i : in std_logic_vector (1 downto 0);
byte_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
slone_data_o : out std_logic_vector(15 downto 0)
---------------------------------------------------------------
);
end component wf_cons_bytes_to_dato;
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
transfer_byte_p_i: in std_logic_vector (1 downto 0);
byte_i : in std_logic_vector (7 downto 0);
slone_data_o : out std_logic_vector(15 downto 0)
);
end component WF_slone_bytes_to_DATO;
---------------------------------------------------------------------------------------------------
component wf_consumption is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_urst_i : in std_logic;
fd_rxd_i : in std_logic;
fd_rxd_r_edge_p_i : in std_logic;
fd_rxd_f_edge_p_i : in std_logic;
clk_wb_i : in std_logic;
wb_adr_i : in std_logic_vector(9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
var_i : in t_var;
byte_ready_p_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
rst_rx_unit_p_i : in std_logic;
signif_edge_window_i : in std_logic;
adjac_bits_window_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
---------------------------------------------------------------
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
byte_ready_p_o : out std_logic;
fss_received_p_o : out std_logic;
crc_wrong_p_o : out std_logic;
fss_crc_fes_viol_ok_p_o : out std_logic;
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0);
cons_ctrl_byte_o : out std_logic_vector (7 downto 0);
cons_pdu_byte_o : out std_logic_vector (7 downto 0);
cons_lgth_byte_o : out std_logic_vector (7 downto 0);
rst_rx_osc_o : out std_logic
---------------------------------------------------------------
);
end component wf_consumption;
---------------------------------------------------------------------------------------------------
component WF_prod_bytes_to_tx is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nFIP_urst_i : in std_logic;
m_id_dec_i : in std_logic_vector (7 downto 0);
c_id_dec_i : in std_logic_vector (7 downto 0);
wb_clk_i : in std_logic;
wb_data_i : in std_logic_vector (7 downto 0);
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_we_p_i : in std_logic;
wb_cyc_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
nFIP_status_byte_i : in std_logic_vector (7 downto 0);
mps_status_byte_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
data_length_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
var3_rdy_i : in std_logic;
sending_mps_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
wb_ack_prod_p_o : out std_logic
);
end component WF_prod_bytes_to_tx;
component wf_production is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nfip_urst_i : in std_logic;
clk_wb_i : in std_logic;
wb_data_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
slone_data_i : in std_logic_vector(15 downto 0);
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
var_i : in t_var;
data_length_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
start_prod_p_i : in std_logic;
byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic;
rst_status_bytes_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0);
--------------------------------------------------------------------------
request_byte_p_o : out std_logic;
sending_mps_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
wb_ack_prod_p_o : out std_logic
--------------------------------------------------------------------------
);
end component wf_production;
---------------------------------------------------------------------------------------------------
component WF_slone_DATI_bytes_sampler is
component wf_prod_bytes_retriever is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
nfip_urst_i : in std_logic;
model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0);
clk_wb_i : in std_logic;
wb_data_i : in std_logic_vector (7 downto 0);
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
nFIP_status_byte_i : in std_logic_vector (7 downto 0);
mps_status_byte_i : in std_logic_vector (7 downto 0);
var_i : in t_var;
data_length_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
var3_rdy_i : in std_logic;
---------------------------------------------------------------
sending_mps_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
wb_ack_prod_p_o : out std_logic
---------------------------------------------------------------
);
end component wf_prod_bytes_retriever;
---------------------------------------------------------------------------------------------------
component wf_prod_bytes_from_dati is
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
slone_byte_o : out std_logic_vector (7 downto 0)
);
end component WF_slone_DATI_bytes_sampler;
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
slone_data_i : in std_logic_vector (15 downto 0);
var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
slone_byte_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
end component wf_prod_bytes_from_dati;
---------------------------------------------------------------------------------------------------
component WF_engine_control
generic( C_QUARTZ_PERIOD : real);
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
tx_request_byte_p_i : in std_logic;
rx_FSS_received_p_i : in std_logic;
rx_byte_ready_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_CRC_FES_ok_p_i : in std_logic;
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
tx_sending_mps_i : in std_logic;
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_PDU_byte_i : in std_logic_vector (7 downto 0);
rx_Length_byte_i : in std_logic_vector (7 downto 0);
var1_rdy_o: out std_logic;
var2_rdy_o: out std_logic;
var3_rdy_o: out std_logic;
tx_byte_ready_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
tx_data_length_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
rst_status_bytes_o : out std_logic;
rst_rx_unit_p_o : out std_logic;
var_o : out t_var;
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic
);
generic ( c_QUARTZ_PERIOD : real);
port (
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
slone_i : in std_logic;
nostat_i : in std_logic;
tx_request_byte_p_i : in std_logic;
rx_FSS_received_p_i : in std_logic;
rx_crc_wrong_p_i : in std_logic;
rx_byte_ready_p_i : in std_logic;
rx_byte_i : in std_logic_vector (7 downto 0);
rx_CRC_FES_ok_p_i : in std_logic;
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
tx_sending_mps_i : in std_logic;
rx_ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_pdu_byte_i : in std_logic_vector (7 downto 0);
rx_length_byte_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
tx_byte_ready_p_o : out std_logic;
tx_last_byte_p_o : out std_logic;
tx_start_produce_p_o : out std_logic;
tx_rx_byte_index_o : out std_logic_vector (7 downto 0);
tx_data_length_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
rst_status_bytes_o : out std_logic;
rst_rx_unit_p_o : out std_logic;
var_o : out t_var;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
nfip_status_r_fcser_p_o : out std_logic;
nfip_status_r_tler_o : out std_logic
---------------------------------------------------------------
);
end component WF_engine_control;
---------------------------------------------------------------------------------------------------
component WF_reset_unit
port (
uclk_i : in std_logic;
urst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
urst_r_edge_i : in std_logic;
var_i : in t_var;
subs_i : in std_logic_vector (7 downto 0);
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
rston_o : out std_logic;
nFIP_rst_o : out std_logic;
fd_rstn_o : out std_logic
);
port (
uclk_i : in std_logic;
urst_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
urst_r_edge_i : in std_logic;
var_i : in t_var;
subs_i : in std_logic_vector (7 downto 0);
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
---------------------------------------------------------------
rston_o : out std_logic;
nFIP_rst_o : out std_logic;
fd_rstn_o : out std_logic
---------------------------------------------------------------
);
end component WF_reset_unit;
---------------------------------------------------------------------------------------------------
component WF_DualClkRAM_clka_rd_clkb_wr
generic (C_RAM_DATA_LGTH : integer;
C_RAM_ADDR_LGTH : integer);
c_RAM_ADDR_LGTH : integer);
port (
clk_A_i : in std_logic;
addr_A_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
clk_B_i : in std_logic;
addr_B_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_B_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
write_en_B_i : in std_logic;
data_A_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (C_RAM_ADDR_LGTH - 1 downto 0);
data_portb_i : in std_logic_vector (C_RAM_DATA_LGTH - 1 downto 0);
write_en_portb_i : in std_logic;
--------------------------------------------------------------------------
data_porta_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
--------------------------------------------------------------------------
);
end component WF_DualClkRAM_clka_rd_clkb_wr;
......@@ -587,247 +658,272 @@ end component WF_slone_DATI_bytes_sampler;
component WF_crc
generic (c_GENERATOR_POLY_length : natural := 16);
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
start_CRC_p_i : in std_logic;
data_bit_i : in std_logic;
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
start_crc_p_i : in std_logic;
data_bit_i : in std_logic;
data_bit_ready_p_i : in std_logic;
CRC_ok_p : out std_logic;
CRC_o : out std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0)
--------------------------------------------------------------------------
crc_ok_p : out std_logic;
crc_o : out std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0)
--------------------------------------------------------------------------
);
end component WF_crc;
---------------------------------------------------------------------------------------------------
component WF_manch_encoder is
generic(word_length : natural);
component WF_manch_encoder is
generic (word_length : natural);
port (
word_i : in std_logic_vector(word_length-1 downto 0);
word_i : in std_logic_vector(word_length-1 downto 0);
---------------------------------------------------------------
word_manch_o : out std_logic_vector((2*word_length)-1 downto 0)
);
end component WF_manch_encoder;
---------------------------------------------------------------
);
end component WF_manch_encoder;
---------------------------------------------------------------------------------------------------
component WF_manch_code_viol_check is
component WF_manch_code_viol_check is
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
serial_input_signal_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
manch_code_viol_p_o : out std_logic
);
end component WF_manch_code_viol_check;
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
serial_input_signal_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
---------------------------------------------------------------
manch_code_viol_p_o : out std_logic
---------------------------------------------------------------
);
end component WF_manch_code_viol_check;
---------------------------------------------------------------------------------------------------
component WF_rx_deglitcher
generic (C_ACULENGTH : integer := 10);
generic (c_DEGLITCH_LGTH : integer := 10);
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
sample_manch_bit_p_o : out std_logic;
rxd_filtered_o : out std_logic;
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
rxd_i : in std_logic;
sample_manch_bit_p_i : in std_logic;
sample_bit_p_i : in std_logic;
---------------------------------------------------------------
sample_manch_bit_p_o : out std_logic;
rxd_filtered_o : out std_logic;
rxd_filtered_f_edge_p_o : out std_logic;
sample_bit_p_o : out std_logic
sample_bit_p_o : out std_logic
---------------------------------------------------------------
);
end component WF_rx_deglitcher;
---------------------------------------------------------------------------------------------------
component WF_status_bytes_gen
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nFIP_urst_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_txer_i : in std_logic;
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
var_i : in t_var;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
crc_wrong_p_i : in std_logic;
rst_status_bytes_i : in std_logic;
nFIP_status_byte_o : out std_logic_vector (7 downto 0);
mps_status_byte_o : out std_logic_vector (7 downto 0)
);
port (
uclk_i : in std_logic;
slone_i : in std_logic;
nfip_urst_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_txer_i : in std_logic;
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
rst_status_bytes_i : in std_logic;
---------------------------------------------------------------
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
nFIP_status_byte_o : out std_logic_vector (7 downto 0);
mps_status_byte_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
end component WF_status_bytes_gen;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component WF_bits_to_txd
generic (C_TXCLKBUFFLENTGTH : natural := 4);
generic (c_TX_CLK_BUFF_LGTH : natural := 4);
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
txd_bit_index_i : in unsigned(4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
sending_FSS_i : in std_logic;
sending_data_i : in std_logic;
sending_crc_i : in std_logic;
sending_QUEUE_i : in std_logic;
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
txd_bit_index_i : in unsigned(4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0);
sending_fss_i : in std_logic;
sending_data_i : in std_logic;
sending_crc_i : in std_logic;
sending_fes_i : in std_logic;
stop_transmission_i : in std_logic;
tx_clk_p_buff_i : in std_logic_vector (C_TXCLKBUFFLENTGTH -1 downto 0);
txd_o : out std_logic;
tx_enable_o : out std_logic
);
end component WF_bits_to_txd;
tx_clk_p_i : in std_logic;
---------------------------------------------------------------
txd_o : out std_logic;
tx_enable_o : out std_logic
---------------------------------------------------------------
);
end component WF_bits_to_txd;
---------------------------------------------------------------------------------------------------
component nanofip
port (
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
fd_wdgn_i : in std_logic;
fd_txer_i : in std_logic;
fx_rxa_i : in std_logic;
fx_rxd_i : in std_logic;
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
rstin_i : in std_logic;
var1_acc_i: in std_logic;
var2_acc_i: in std_logic;
var3_acc_i: in std_logic;
wbclk_i : in std_logic;
DAT_I : in std_logic_vector (15 downto 0);
adr_i : in std_logic_vector ( 9 downto 0);
rst_i : in std_logic;
stb_i : in std_logic;
cyc_i : in std_logic;
we_i : in std_logic;
rston_o : out std_logic;
s_id_o : out std_logic_vector (1 downto 0);
fd_rstn_o : out std_logic;
fd_txena_o: out std_logic;
fd_txck_o : out std_logic;
fx_txd_o : out std_logic;
var1_rdy_o: out std_logic;
var2_rdy_o: out std_logic;
var3_rdy_o: out std_logic;
ack_o : out std_logic;
DAT_O : out std_logic_vector (15 downto 0)
rate_i : in std_logic_vector (1 downto 0);
subs_i : in std_logic_vector (7 downto 0);
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
p3_lgth_i : in std_logic_vector (2 downto 0);
fd_wdgn_i : in std_logic;
fd_txer_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
uclk_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
rstin_i : in std_logic;
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
clk_wb_i : in std_logic;
dat_i : in std_logic_vector (15 downto 0);
adr_i : in std_logic_vector ( 9 downto 0);
rst_i : in std_logic;
stb_i : in std_logic;
cyc_i : in std_logic;
we_i : in std_logic;
---------------------------------------------------------------
rston_o : out std_logic;
s_id_o : out std_logic_vector (1 downto 0);
fd_rstn_o : out std_logic;
fd_txena_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
u_cacer_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
r_fcser_o : out std_logic;
ack_o : out std_logic;
dat_o : out std_logic_vector (15 downto 0)
---------------------------------------------------------------
);
end component nanofip;
---------------------------------------------------------------------------------------------------
component WF_model_constr_decoder
generic (C_RELOAD_MID_CID : natural);
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
m_id_i : in std_logic_vector (3 downto 0);
c_id_i : in std_logic_vector (3 downto 0);
s_id_o : out std_logic_vector (1 downto 0);
m_id_dec_o : out std_logic_vector (7 downto 0);
c_id_dec_o : out std_logic_vector (7 downto 0)
);
end component WF_model_constr_decoder;
---------------------------------------------------------------------------------------------------
component WF_decr_counter is
generic(counter_length : natural := 5);
component WF_model_constr_decoder
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
counter_top : in unsigned (counter_length-1 downto 0);
counter_load_i : in std_logic;
counter_decr_p_i : in std_logic;
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
model_id_i : in std_logic_vector (3 downto 0);
constr_id_i : in std_logic_vector (3 downto 0);
---------------------------------------------------------------
select_id_o : out std_logic_vector (1 downto 0);
model_id_dec_o : out std_logic_vector (7 downto 0);
constr_id_dec_o : out std_logic_vector (7 downto 0)
---------------------------------------------------------------
);
end component WF_model_constr_decoder;
counter_o : out unsigned (counter_length-1 downto 0);
counter_is_zero_o : out std_logic
);
end component WF_decr_counter;
---------------------------------------------------------------------------------------------------
component WF_incr_counter is
generic(counter_length : natural := 8);
component WF_decr_counter is
generic (g_counter_lgth : natural := 5);
port (
uclk_i : in std_logic;
nFIP_urst_i : in std_logic;
reinit_counter_i : in std_logic;
incr_counter_i: in std_logic;
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
counter_top : in unsigned (g_counter_lgth-1 downto 0);
counter_load_i : in std_logic;
counter_decr_p_i : in std_logic;
---------------------------------------------------------------
counter_o : out unsigned (g_counter_lgth-1 downto 0);
counter_is_zero_o : out std_logic
---------------------------------------------------------------
);
end component WF_decr_counter;
counter_o : out unsigned(counter_length-1 downto 0);
counter_is_full_o : out std_logic
);
end component WF_incr_counter;
---------------------------------------------------------------------------------------------------
component WF_incr_counter is
generic (g_counter_lgth : natural := 8);
port (
uclk_i : in std_logic;
nfip_urst_i : in std_logic;
reinit_counter_i : in std_logic;
incr_counter_i : in std_logic;
---------------------------------------------------------------
counter_o : out unsigned(g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic
---------------------------------------------------------------
);
end component WF_incr_counter;
---------------------------------------------------------------------------------------------------
component WF_prod_data_lgth_calc is
component WF_prod_data_lgth_calc is
port (
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i: in t_var;
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
var_i : in t_var;
---------------------------------------------------------------
tx_data_length_o : out std_logic_vector(7 downto 0)
---------------------------------------------------------------
);
end component WF_prod_data_lgth_calc;
tx_data_length_o : out std_logic_vector(7 downto 0)
);
end component WF_prod_data_lgth_calc;
---------------------------------------------------------------------------------------------------
component WF_cons_frame_validator is
component WF_cons_frame_validator is
port (
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_PDU_byte_i : in std_logic_vector (7 downto 0);
rx_Length_byte_i : in std_logic_vector (7 downto 0);
rx_FSS_CRC_FES_viol_ok_p_i : in std_logic;
var_i: in t_var;
rx_byte_index_i : in unsigned(7 downto 0);
cons_frame_ok_p_o : out std_logic
);
end component WF_cons_frame_validator;
rx_ctrl_byte_i : in std_logic_vector (7 downto 0);
rx_pdu_byte_i : in std_logic_vector (7 downto 0);
rx_length_byte_i : in std_logic_vector (7 downto 0);
rx_crc_wrong_p_i : in std_logic;
rx_fss_crc_fes_viol_ok_p_i : in std_logic;
var_i : in t_var;
rx_byte_index_i : in unsigned(7 downto 0);
---------------------------------------------------------------
cons_frame_ok_p_o : out std_logic;
nfip_status_r_fcser_p_o : out std_logic;
nfip_status_r_tler_o : out std_logic
---------------------------------------------------------------
);
end component WF_cons_frame_validator;
---------------------------------------------------------------------------------------------------
component WF_VAR_RDY_generator is
component WF_var_rdy_generator is
port (
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nFIP_urst_i : in std_logic;
cons_frame_ok_p_i : in std_logic;
var_i : in t_var;
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic
);
end component WF_VAR_RDY_generator;
uclk_i : in std_logic;
slone_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0);
nfip_urst_i : in std_logic;
cons_frame_ok_p_i : in std_logic;
var_i : in t_var;
rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0);
rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0);
---------------------------------------------------------------
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic;
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic
---------------------------------------------------------------
);
end component WF_var_rdy_generator;
---------------------------------------------------------------------------------------------------
end WF_package;
package body WF_package is
end WF_package;
--=================================================================================================
......
wf_prod_bytes_to_tx.vhd → wf_prod_bytes_retriever.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_prod_bytes_to_tx.vhd
--! @file wf_prod_bytes_retriever.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -10,218 +18,226 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_bytes_to_tx --
-- --
-- CERN, BE/CO/HT --
-- wf_prod_bytes_retriever --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief After an ID_DAT frame requesting for a variable to be produced, this unit provides
--! to the transmitter (WF_tx) one by one, \n all the bytes of data needed for the
--! RP_DAT frame (apart from FSS, fcs and FES bytes).
--! @brief After an ID_DAT frame requesting for a variable to be produced, the unit provides
--! to the wf_tx_serializer unit one by one, \n all the bytes of data needed for the
--! RP_DAT frame (apart from the FSS, FCS and FES bytes).
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 06/2010
--! @date 04/01/2011
--
--
--! @version v0.02
--! @version v0.05
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_status_bytes_gen \n
--! WF_reset_unit \n
--! WF_status_bytes_gen \n
--! WF_model_constr_decoder\n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> egousiou: subs_i is not sent in the RP_DAT frames \n
--! -> egousiou: signal s_wb_we includes the wb_stb_r_edge_p_i \n
--! -> egousiou: signal s_mem_byte was not in sensitivity list in v0.01! by adding it,
--! changes were essential in the timing of the tx (WF_osc, WF_tx,
--! WF_engine_control and the configuration of the memory needed few changes)
--! -> 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames
--! signal s_wb_we includes the wb_stb_r_edge_p_i
--! cleaner structure
--! -> 06/2010 v0.03 EG signal s_mem_byte was not in sensitivity list in v0.01! by adding it
--! changes were essential in the timing of the tx (WF_osc, wf_tx,
--! WF_engine_control and the configuration of the memory needed changes)
--! -> 11/2010 v0.04 EG for simplification, new unit Slone_Data_Sampler created
--! -> 4/1/2011 v0.05 EG unit renamed from wf_prod_bytes_to_tx to wf_prod_bytes_retriever;
--! clening-up+commenting
--
---------------------------------------------------------------------------------------------------
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--!
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL246 Input port bits 0, 1, 3, 4 of var_i(0 to 6) are unused" --
-- var_i is one-hot encoded and has 7 values. --
-- The unit is treating only the produced variables presence, identification and var_3. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_prod_bytes_to_tx
--! Entity declaration for wf_prod_bytes_retriever
--=================================================================================================
entity WF_prod_bytes_to_tx is
entity wf_prod_bytes_retriever is
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode
nostat_i : in std_logic; --! if negated, nFIP status is sent
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! stand-alone mode
nostat_i : in std_logic; --! if negated, nFIP status is sent
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- User Interface WISHBONE Slave
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
wb_clk_i : in std_logic; --! WISHBONE clock
-- note: may be indipendant of uclk
clk_wb_i : in std_logic; --! WISHBONE clock
-- note: may be indipendant of uclk
wb_data_i : in std_logic_vector (7 downto 0); --! WISHBONE data bus
wb_data_i : in std_logic_vector (7 downto 0); --! WISHBONE data bus
wb_adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address to memory
wb_stb_r_edge_p_i : in std_logic; --! rising edge of WISHBONE strobe
wb_we_i : in std_logic; --! WISHBONE write enable
wb_cyc_i : in std_logic; --! WISHBONE cycle
wb_adr_i : in std_logic_vector (9 downto 0); --! WISHBONE address to memory
-- note: msb allways 0!
wb_stb_r_edge_p_i : in std_logic; --! WISHBONE strobe
-- (buffered once with wb_clk)
-- note: indication that the
-- master is ready to transfer data
wb_we_p_i : in std_logic; --! WISHBONE write enable
-- note: indicates a write cycle of master
-- nanoFIP User Interface, NON WISHBONE (synchronized with uclk)
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
wb_cyc_i : in std_logic; --! WISHBONE cycle
-- note:indicates a valid cycle in progress
-- Signals from the WF_engine_control
var_i : in t_var; --! variable type that is being treated
-- User Interface Non WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- (buffered twice with uclk)
-- Signals from WF_engine_control
var_i : in t_var; --! variable received from ID_DAT
data_length_i: in std_logic_vector (7 downto 0); --! # bytes of Conrol&Data fields of RP_DAT
-- includes 1 byte for the RP_DAT.Control,
-- 1 byte for RP_DAT.Data.PDU_type,
-- 1 byte for RP_DAT.Data.LENGTH
-- 0-124 bytes of RP_DAT.Data,
--1 byte for RP_DAT.Data.MPS and optionally
-- 1 byte for RP_DAT.Data.nanoFIP_status
data_length_i : in std_logic_vector (7 downto 0); --!# bytes of the Conrol&Data fields of
-- the RP_DAT frame; includes:
-- 1 byte RP_DAT.Control,
-- 1 byte RP_DAT.Data.PDU_type,
-- 1 byte RP_DAT.Data.LENGTH
-- 0-124 bytes of RP_DAT.Data,
-- 1 byte RP_DAT.Data.MPS_status &
-- optionally 1 byte for the
-- RP_DAT.Data.nanoFIP_status
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- includes RP_DAT.Control and RP_DAT.Data
var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to frame bytes
-- (RP_DAT.Control & RP_DAT.Data bytes)
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
-- Signals from WF_status_bytes_gen
nFIP_status_byte_i : in std_logic_vector (7 downto 0); --! nanoFIP status byte
mps_status_byte_i : in std_logic_vector (7 downto 0); --! MPS status byte
-- Signals from the WF_status_bytes_gen
nFIP_status_byte_i : in std_logic_vector (7 downto 0); --! nanoFIP status byte
mps_status_byte_i : in std_logic_vector (7 downto 0); --! MPS status byte
-- Signals from the WF_model_constr_decoder unit
m_id_dec_i : in std_logic_vector (7 downto 0); --! model identification settings (decoded)
c_id_dec_i : in std_logic_vector (7 downto 0); --! constructor id settings (decoded)
model_id_dec_i : in std_logic_vector (7 downto 0); --! decoded model id settings
constr_id_dec_i : in std_logic_vector (7 downto 0); --! decoded constructor id settings
-- OUTPUTS
-- Signal to WF_status_bytes_gen
sending_mps_o : out std_logic; --!indication: mps byte being sent
-- Signal to the WF_status_bytes_gen
sending_mps_o : out std_logic; --!indicates that MPS byte is being sent
-- Signal to WF_tx
byte_o : out std_logic_vector (7 downto 0); --! output byte to be serialized and sent
-- Signal to the wf_tx_serializer
byte_o : out std_logic_vector (7 downto 0); --! output byte to be serialized & sent
-- nanoFIP output
wb_ack_prod_p_o : out std_logic --! WISHBONE acknowledge
-- response to master's strobe signal
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_prod_p_o : out std_logic --! WISHBONE acknowledge
-- response to master's strobe
);
end entity WF_prod_bytes_to_tx;
end entity wf_prod_bytes_retriever;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_prod_bytes_to_tx is
signal s_wb_ack_prod_p : std_logic;
signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0);
signal s_byte_index_aux : integer range 0 to 15;
signal s_mem_wr_en_B_d3 : std_logic_vector (2 downto 0);
signal s_length, s_mem_byte, s_slone_byte: std_logic_vector (7 downto 0);
signal s_byte_index : std_logic_vector (7 downto 0);
signal s_mem_addr_A : std_logic_vector (8 downto 0);
architecture rtl of wf_prod_bytes_retriever is
signal s_wb_ack_prod_p : std_logic;
signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0);
signal s_byte_index_aux : integer range 0 to 15;
signal s_mem_wr_en_B_d3 : std_logic_vector (2 downto 0);
signal s_length, s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0);
signal s_byte_index : std_logic_vector (7 downto 0);
signal s_mem_addr_A : std_logic_vector (8 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
-- !@brief Instantiation of the Data Sampler unit for the sampling of the input data bus DAT(15:0)
--! on the stand-alone operation. The sampling takes place on the 1st clock cycle after the
--! VAR3_RDY has been deasserted.
Slone_Data_Sampler: WF_slone_DATI_bytes_sampler
port map( uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
slone_data_i => slone_data_i,
var3_rdy_i => var3_rdy_i,
byte_index_i => byte_index_i,
slone_byte_o => s_slone_byte
);
--!@brief Instantiation of the unit that in stand-alone mode is responsible for the sampling of the
--! input data bus DAT_I(15:0). The sampling takes place on the 1st clock cycle after the VAR3_RDY
--! has been de-asserted.
Produced_Bytes_From_DATI: wf_prod_bytes_from_dati
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
slone_data_i => slone_data_i,
var3_rdy_i => var3_rdy_i,
byte_index_i => byte_index_i,
------------------------------
slone_byte_o => s_slone_byte);
------------------------------
---------------------------------------------------------------------------------------------------
-- !@brief Instantiation of a "Produced ram"
production_dpram: WF_DualClkRAM_clka_rd_clkb_wr
generic map (C_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
C_RAM_ADDR_LGTH => 9) -- 2^9: depth of produced ram
-- first 2 bits: identification of memory block
--remaining 7: address of a byte inside the blck
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of a Produced Dual Port RAM
Produced_Bytes_From_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map(
c_RAM_DATA_LGTH => 8, -- 8 bits: length of data word
c_RAM_ADDR_LGTH => 9) -- 2^9: depth of produced ram
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
-- port A corresponds to: nanoFIP that reads from the Produced ram & B to: WISHBONE that writes
port map (clk_A_i => uclk_i, -- 40 MHz clck
addr_A_i => s_mem_addr_A, -- address of byte to be read from memory
data_A_o => s_mem_byte, -- output byte read
port map(
clk_porta_i => uclk_i, -- 40 MHz clock
addr_porta_i => s_mem_addr_A, -- address of byte to be read from memory
------------------------------------------------------------------------------------
data_porta_o => s_mem_byte, -- output byte read
------------------------------------------------------------------------------------
clk_portb_i => clk_wb_i, -- WISHBONE clock
addr_portb_i => wb_adr_i (8 downto 0),-- address of byte to be written
data_portb_i => wb_data_i, -- byte to be written
write_en_portb_i => s_mem_wr_en_B_d3(2)); -- WISHBONE write enable
clk_B_i => wb_clk_i, -- WISHBONE clck
addr_B_i => wb_adr_i (8 downto 0),-- address of byte to be written
data_B_i => wb_data_i, -- byte to be written
write_en_B_i => s_mem_wr_en_B_d3(2) -- WISHBONE write enable
);
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Bytes_Generation: Generation of bytes for the Control and Data
--! fields of an RP_DAT frame:\n If the variable requested in the ID_DAT is of "produced" type(id/
--! presence/ var3) the process prepares accordingly, one by one, bytes of data to be sent. \n The
--! pointer "byte_index_i" indicates which byte of the frame is to be sent. Some of the bytes are
--! defined in the WF_package, the rest come either from the memory (if slone=0) or from the the
--! input bus data_i or from the WF_status_gen or WF_model_constr_decoder units.\n
--! The output byte "byte_o" is sent to the transmitter(WF_tx)for serialization
--! fields of an RP_DAT frame:\n If the variable requested in the ID_DAT is of "produced" type
--! (identification/ presence/ var3) the process prepares accordingly, one by one, bytes of data
--! to be sent. \n The pointer "s_byte_index" (or "s_byte_index_aux") indicates which byte of the
--! frame is to be sent. Some of the bytes are defined in the WF_package, the rest come either from
--! the memory (if slone = 0) or from the the input bus data_i (if slone = 1) or from the
--! WF_status_bytes_gen or the WF_model_constr_decoder units.\n The output byte "byte_o" is sent to
--! the wf_tx_serializer unit for manchester encoding and serialization.
Bytes_Generation: process (var_i, s_byte_index, data_length_i, c_id_dec_i, m_id_dec_i,
Bytes_Generation: process (var_i, s_byte_index, data_length_i, constr_id_dec_i, model_id_dec_i,
nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_length,
s_mem_byte, slone_i, s_byte_index_aux, nostat_i, s_byte_index_aux)
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- generation of bytes according to the type of produced var
-- generation of bytes according to the type of produced var:
case var_i is
-- case: presence variable
-- all the bytes for the RP_DAT.Control and RP_DAT.Data fields of the RP_DAT frame to be sent,
-- are predefined in the c_VARS_ARRAY(0).byte_array matrix
-- are predefined in the c_VARS_ARRAY matrix.
when var_presence =>
byte_o <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).byte_array(s_byte_index_aux);
......@@ -232,17 +248,16 @@ architecture rtl of WF_prod_bytes_to_tx is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--case: identification variable
-- The Constructor and Model bytes of the identification variable arrive from the decoding unit
-- (WF_model_constr_decoder), wereas all the rest are predefined in the c_VARS_ARRAY matrix
-- case: identification variable
-- The Constructor and Model bytes of the identification variable arrive from the
-- WF_model_constr_decoder, wereas all the rest are predefined in the c_VARS_ARRAY matrix.
when var_identif =>
if s_byte_index = c_CONSTR_BYTE_INDEX then
byte_o <= c_id_dec_i;
byte_o <= constr_id_dec_i;
elsif s_byte_index = c_MODEL_BYTE_INDEX then
byte_o <= m_id_dec_i;
byte_o <= model_id_dec_i;
else
byte_o <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).byte_array(s_byte_index_aux);
......@@ -257,21 +272,21 @@ architecture rtl of WF_prod_bytes_to_tx is
-- case: variable 3 (06h)
-- For a var3 there is a separation according to the operational mode (stand-alone or memory)
-- In general, few of the bytes are predefined in the c_VARS_ARRAY matrix, wereas the rest come
-- either from the memory or from the data_i bus or from status_generator unit (WF_status_gen)
-- either from the memory/ data_i bus or from status_generator unit (WF_status_gen).
when var_3 =>
---------------------------------------------------------------------------------------------
-- In memory mode:
if slone_i = '0' then
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_addr; --retreival of info for mem base address
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_addr; -- retreival of base address info
-- for the memory from the WF_package
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (RP_DAT.Control) and second (PDU type) bytes to be sent
-- The first (Control) and second (PDU_TYPE) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then
if unsigned(s_byte_index) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less or eq
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux);
sending_mps_o <= '0';
......@@ -305,16 +320,16 @@ architecture rtl of WF_prod_bytes_to_tx is
end if;
---------------------------------------------------------------------------------------------
-- In standalone mode:
-- In stand-alone mode:
else
s_base_addr <= (others => '0'); -- no access in memory needed
s_base_addr <= (others => '0'); -- no memory access needed
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (RP_DAT.Control) and second (PDU type) bytes to be sent
-- The first (Control) and second (PDU type) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less equal than
if unsigned(s_byte_index) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less or equal
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux);
sending_mps_o <= '0';
......@@ -337,7 +352,7 @@ architecture rtl of WF_prod_bytes_to_tx is
-- The last byte is the MPS status
elsif s_byte_index = data_length_i then
byte_o <= mps_status_byte_i;
sending_mps_o <= '1'; -- indication: MPS byte is being sent
sending_mps_o <= '1'; -- indication that MPS byte is being sent
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The rest of the bytes come from the input bus data_i(15:0)
......@@ -350,6 +365,15 @@ architecture rtl of WF_prod_bytes_to_tx is
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when var_1 | var_2 | var_rst | var_whatever =>
sending_mps_o <= '0';
byte_o <= (others => '0');
s_base_addr <= (others => '0');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
sending_mps_o <= '0';
byte_o <= (others => '0');
......@@ -360,14 +384,14 @@ architecture rtl of WF_prod_bytes_to_tx is
---------------------------------------------------------------------------------------------------
--!@brief Generate_wb_ack_prod_p_o: Generation of the wb_ack_prod_p_o signal
--! (acknowledgement from WISHBONE slave of the write cycle, as a response to the master's storbe).
--! wb_ack_prod_p_o is asserted two wb_clk cycles after the assertion of the input strobe signal
--! (reminder: stb_i is buffered once in the input stage), if the WISHBONE input address
--! corresponds to the Produced memory block and the WISHBONE write enable is asserted.
--! (acknowledgement from WISHBONE Slave of the write cycle, as a response to the master's storbe).
--! wb_ack_prod_p_o is 1 wclk-wide pulse asserted 3 wclk cycles after the assertion of the
--! asynchronous strobe signal, if the wb_cyc and wb_we are asserted and the WISHBONE input address
--! corresponds to an address in the Produced memory block.
Generate_wb_ack_prod_p_o: s_wb_ack_prod_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 7) = "010") and
(wb_we_p_i = '1') and
(wb_we_i = '1') and
(wb_cyc_i = '1'))
else '0';
......@@ -377,54 +401,58 @@ architecture rtl of WF_prod_bytes_to_tx is
---------------------------------------------------------------------------------------------------
-- auxiliary signals generation:
-- address of the byte to be read from memory: base_address(from WF_package) + byte_index_i - 1
-- (the -1 is because when byte_index_i is on the 4th byte (control, pdu and length have
-- preceeded and a byte from the memory is now requested), the 3rd byte from the memory has to
-- be retrieved (in cell 00000010) etc)
s_mem_addr_A <= std_logic_vector (s_base_addr + s_mem_addr_offset - 1);
-- address of the byte to be read from memory: base_address(from WF_package) + byte_index_i - 1
-- (the -1 is because the byte_index_i counts also the Control byte, that is not part of the
-- memory (for example when byte_index_i is 3 which means that the Control, PDU_TYPE and Length
-- bytes have preceeded and a byte from the memory is now requested, the byte from the memory cell
-- 2 (00000010) has to be retrieved).
s_mem_addr_offset <= (resize((unsigned(byte_index_i)), s_mem_addr_offset'length));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_byte_index_aux <= (to_integer(unsigned(s_byte_index(3 downto 0))));
s_byte_index_aux <= (to_integer(unsigned(s_byte_index(3 downto 0))));
-- index of byte to be sent(range restricted)
-- used to retreive bytes from the matrix
-- c_VARS_ARRAY.byte_array, with a predefined
-- width of 15 bytes
s_length <= std_logic_vector (resize((unsigned(data_length_i)-2),byte_o'length));
--signal used for the RP_DAT.Data.LENGTH byte
-- it represents the # bytes of user-data
-- (P3_LGTH) plus 1 byte of RP_DAT.Data.MPS
-- plus 1 byte of RP_DAT.Data.nanoFIP_status,
-- if applicable
s_length <= std_logic_vector (resize((unsigned(data_length_i)-2),byte_o'length));
-- represents the RP_DAT.Data.LENGTH byte
-- it includes the # bytes of user-data
-- (P3_LGTH) plus 1 byte of MPS_status
-- plus 1 byte of nanoFIP_status, if
-- applicable. It does not include the
-- Control byte and itself.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!synchronous process Delay_mem_wr_en_and_addr: since the input buses wb_data_i and
--! wb_addr_i are the triply buffered versions of the DAT_I and ADR_I, the signal wb_write_enable
--! has to be delayed too.
Delay_mem_wr_en_and_addr: process(wb_clk_i)
--!@brief Synchronous process Delay_mem_wr_en: since the input buses wb_data_i and wb_addr_i are
--! the triply buffered versions of the DAT_I and ADR_I, the signal write_en_portb_i has to be delayed
--! too. As write_en_portb_i we use the wb_ack_prod_p signal.
Delay_mem_wr_en: process (clk_wb_i)
begin
if rising_edge(wb_clk_i) then
if rising_edge (clk_wb_i) then
s_mem_wr_en_B_d3 <= s_mem_wr_en_B_d3(1 downto 0) & s_wb_ack_prod_p ;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! synchronous process Delay_index_offset_i: in the combinatorial process Bytes_Generation,
--! according to the value of the signal s_byte_index, a byte is retrieved either from the memory,
--! or from the WF_package or from the WF_status_bytes_gen or dec_m_ids units.
--! Since the memory needs one clock cycle to output its data the signal s_byte_index has to be a
--! delayed version of the byte_index_i (byte_index_i is the signal used as address for the mem)
Delay_index_offset_i: process(uclk_i)
--!@briedf Synchronous process Delay_byte_index_i: in the combinatorial process Bytes_Generation,
--! according to the value of the signal s_byte_index, a byte is retrieved either from the memory,
--! or from the WF_package or from the WF_status_bytes_gen or WF_model_constr_decoder units.
--! Since the memory needs one clock cycle to output its data (as opposed to the other units that
--! have them ready) the signal s_byte_index has to be a delayed version of the byte_index_i
--! (byte_index_i is the signal used as address for the mem; s_byte_index is the delayed one
--! used for the other units).
Delay_byte_index_i: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_byte_index <= (others=> '0');
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_byte_index <= (others => '0');
else
s_byte_index <= byte_index_i; -- index of byte to be sent
......
wf_slone_DATI_bytes_sampler.vhd → wf_prod_bytes_to_dati.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_slone_DATI_bytes_sampler.vhd
--! @file wf_prod_bytes_from_dati.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -10,27 +18,25 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_slone_DATI_bytes_sampler --
-- --
-- CERN, BE/CO/HT --
-- wf_prod_bytes_from_dati --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Unit responsible for the sampling of the DAT_I bus for the stand-alone operation.
--! Following to the functional specs page 14, in stand-alone mode, nanoFIP samples the
--! data onthe first clock cycle after the deassertion of VAR3_RDY.
--! @brief Unit responsible for the sampling of the DAT_I bus in stand-alone operation.
--! Following to the functional specs page 15, in stand-alone mode, the nanoFIP
--! samples the data on the first clock cycle after the deassertion of VAR3_RDY.
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 06/2010
--! @date 04/01/2011
--
--
--! @version v0.02
......@@ -39,6 +45,8 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -47,6 +55,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 11/2010 v0.01 EG unit created
--! -> 4/1/2011 v0.02 EG unit renamed from WF_slone_prod_dati_bytes_sampler to
--! wf_prod_bytes_from_dati; cleaning-up + commenting
--!
--
---------------------------------------------------------------------------------------------------
--
......@@ -55,77 +67,84 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_slone_DATI_bytes_sampler
--! Entity declaration for wf_prod_bytes_from_dati
--=================================================================================================
entity WF_slone_DATI_bytes_sampler is
entity wf_prod_bytes_from_dati is
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- User Interface Non WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- (triply buffered with uclk)
-- Signals from WF_engine_control
var3_rdy_i : in std_logic;
-- nanoFIP User Interface, NON-WISHBONE
slone_data_i : in std_logic_vector (15 downto 0); --! input data bus for stand-alone mode
-- (synchronised with uclk)
-- Signals from the WF_engine_control
var3_rdy_i : in std_logic; --! nanoFIP output VAR3_RDY
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- includes RP_DAT.Control and RP_DAT.Data
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- OUTPUTS
-- Signal to WF_prod_bytes_to_tx
slone_byte_o : out std_logic_vector (7 downto 0)
-- OUTPUTS
-- Signal to the wf_prod_bytes_retriever
slone_byte_o : out std_logic_vector (7 downto 0) --! byte to be sent
);
end entity WF_slone_DATI_bytes_sampler;
end entity wf_prod_bytes_from_dati;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_slone_DATI_bytes_sampler is
architecture rtl of wf_prod_bytes_from_dati is
signal s_var3_rdy_d4 : std_logic_vector (3 downto 0);
signal s_var3_rdy_d4 : std_logic_vector (3 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Sample_Data_i: the sampling of DAT_I has to take place on the first
--! clock cycle after the deassettion of VAR3_RDY.
-- Since slone_data_i is the triply buffered version of the input bus DAT_I, the signal VAR3_RDY
-- has to be delayed too.
--!@brief Synchronous process Sample_DAT_I_bus: the sampling of the DAT_I bus in stand-alone mode
--! has to take place on the first clock cycle after the de-assertion of VAR3_RDY.
--! Note: Since slone_data_i is the triply buffered version of the bus DAT_I (for synchronisation),
--! the signal VAR3_RDY has to be (internally) delayed for 3 uclk cycles too, before the sampling;
--! the 4th delay is added in order to achieve the sampling 1 uclk AFTER the de-assertion.
Sample_Data_i: process(uclk_i)
Sample_DAT_I_bus: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_var3_rdy_d4 <= (others=>'0');
s_sampled_data <= (others=>'0');
else
s_var3_rdy_d4 <= s_var3_rdy_d4(2 downto 0) & var3_rdy_i;
if s_var3_rdy_d4(3) = '1' then -- data latching
s_sampled_data <= slone_data_i;
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_var3_rdy_d4 <= (others=>'0');
s_sampled_data <= (others=>'0');
else
s_var3_rdy_d4 <= s_var3_rdy_d4(2 downto 0) & var3_rdy_i;
if s_var3_rdy_d4(3) = '1' then -- data latching
s_sampled_data <= slone_data_i;
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
slone_byte_o <= s_sampled_data(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX
else s_sampled_data(15 downto 8);
slone_byte_o <= s_sampled_data(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX
else s_sampled_data(15 downto 8);
end architecture rtl;
--=================================================================================================
......
wf_prod_data_lgth_calc.vhd
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_prod_data_lgth_calc.vhd
---------------------------------------------------------------------------------------------------
......@@ -10,27 +18,25 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_data_lgth_calc --
-- --
-- CERN, BE/CO/HT --
-- WF_prod_data_lgth_calc --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief Calculation of the total amount of data bytes that have to be transferreed when a
--! variable is produced (including the RP_DAT.Control, RP_DAT.Data.mps and
--! RP_DAT.Data.nanoFIPstatus bytes)
--! variable is produced (including the RP_DAT.Control, RP_DAT.Data.MPS_status and
--! RP_DAT.Data.nanoFIP_status bytes)
--
--
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 06/2010
--! @date 09/12/2010
--
--
--! @version v0.02
......@@ -39,6 +45,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_engine_control \n
--
--
--! \n<b>Modified by:</b>\n
......@@ -46,7 +53,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 12/2010 v0.02 EG code cleaned-up+commented
--
---------------------------------------------------------------------------------------------------
--
......@@ -55,6 +65,12 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_prod_data_lgth_calc
......@@ -64,16 +80,16 @@ entity WF_prod_data_lgth_calc is
port (
-- INPUTS
-- User Interface general signals (synchronized)
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
-- nanoFIP User Interface, General signals (synchronized with uclk)
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
-- Signals from WF_engine_control
var_i: in t_var;
-- Signal from the WF_engine_control
var_i : in t_var; --! variable type that is being treated
-- OUTPUT
-- Signal to WF_engine_control
-- Signal to the WF_engine_control
tx_data_length_o : out std_logic_vector(7 downto 0)
);
end entity WF_prod_data_lgth_calc;
......@@ -85,22 +101,22 @@ end entity WF_prod_data_lgth_calc;
architecture rtl of WF_prod_data_lgth_calc is
signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief:Combinatorial process data_length_calcul: calculation of the total amount of data
--!@brief: Combinatorial process data_length_calcul: calculation of the total amount of data
--! bytes that have to be transferreed when a variable is produced, including the RP_DAT.Control as
--! well as the RP_DAT.Data.mps and RP_DAT.Data.nanoFIPstatus bytes. In the case of the presence
--! and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation.
data_length_calcul: process ( var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i )
--! well as the RP_DAT.Data.MPS_status and RP_DAT.Data.nanoFIP_status bytes. In the case of the
--! presence and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation.
data_length_calcul: process (var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i)
begin
s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
case var_i is
......@@ -121,18 +137,18 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
when var_3 =>
-- data length calculation according to the operational mode (memory or stand-alone)
-- in slone mode 2 bytes of user-data are produced
-- in slone mode 2 bytes of user-data are produced(independantly of p3_lgth)
-- to these there should be added: 1 byte RP_DAT.Control
-- 1 byte PDU
-- 1 byte Length
-- 1 byte MPS
-- 1 byte MPS status
-- optionally 1 byte nFIP status
-- in memory mode the signal "s_p3_length_decoded" indicates the amount of user-data
-- to these, there should be added 1 byte RP_DAT.Control
-- 1 byte PDU
-- 1 byte Length
-- 1 byte MPS
-- 1 byte MPS status
-- optionally 1 byte nFIP status
if slone_i = '1' then
......@@ -147,30 +163,26 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
else
if nostat_i = '0' then
s_tx_data_length <= s_p3_length_decoded + 4; -- (bytes counting starts from 0)
s_tx_data_length <= s_p3_length_decoded + 4; -- (counting starts from 0)
else
s_tx_data_length <= s_p3_length_decoded + 3; -- (bytes counting starts from 0)
s_tx_data_length <= s_p3_length_decoded + 3; -- (counting starts from 0)
end if;
end if;
when var_1 =>
s_tx_data_length <= (others => '0');
when var_2 =>
s_tx_data_length <= (others => '0');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_rst =>
s_tx_data_length <= (others => '0');
when var_1 | var_2 | var_rst => -- to avoid Warnings from Synthesiser
s_tx_data_length <= (others => '0');
when others =>
s_tx_data_length <= (others => '0');
s_tx_data_length <= (others => '0');
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tx_data_length_o <= std_logic_vector (s_tx_data_length);
-- Concurrent signal assignment for the output
tx_data_length_o <= std_logic_vector (s_tx_data_length);
end architecture rtl;
......
wf_production.vhd 0 → 100644
View file @ c0ef0386
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file wf_production.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- wf_production --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 11/01/2011
--
--
--! @version v0.01
--
--
--! @details \n
--
--! \n<b>Dependencies:</b> \n
--! wf_prod_bytes_retriever \n
--! WF_status_bytes_gen \n
--! wf_tx_serializer \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! \n\n<b>Last changes:</b>\n
--! ->
--
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--! ->
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings! --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for wf_production
--=================================================================================================
entity wf_production is
port (
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic;
--! wf_prod_bytes_retriever : for the selection of data bytes from the RAM or the DATI bus
--! WF_status_bytes_gen : the MPS status byte is different according to the operational mode
slone_i : in std_logic;
--! wf_prod_bytes_retriever : for the delivery or not of the nanoFIP status byte
nostat_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit unit
nfip_urst_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave (synchronized with wb_clk)
--! wf_prod_bytes_retriever : for the managment of the Production RAM
clk_wb_i : in std_logic;
wb_data_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(9 downto 0);
wb_stb_r_edge_p_i : in std_logic;
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, NON-WISHBONE (synchronized with uclk)
--! wf_prod_bytes_retriever : for the bytes retreival in stand-alone mode
slone_data_i : in std_logic_vector(15 downto 0);
--! WF_status_bytes_gen : for the nanoFIP status byte, bits 2, 3
var1_acc_i : in std_logic;
var2_acc_i : in std_logic;
var3_acc_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP FIELDRIVE
--! WF_status_bytes_gen : for the nanoFIP status byte, bits 6, 7
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_engine_control
--! wf_prod_bytes_retriever : for the definition of the bytes to be delivered
var_i : in t_var;
data_length_i : in std_logic_vector (7 downto 0);
byte_index_i : in std_logic_vector (7 downto 0);
--! wf_tx_serializer : for the delivery coordination
start_prod_p_i : in std_logic;
byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic;
--! WF_status_bytes_gen : for the reseting of the nanoFIP & MPS status bytes
--! and the generation of the nanoFIP status byte, bits 2, 3, 4, 5
rst_status_bytes_i : in std_logic;
nfip_status_r_tler_i : in std_logic;
nfip_status_r_fcser_p_i : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic; --! wf_prod_bytes_retriever : determines the sampling
--! moment of the DATI bus, in stand-alone mode
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_rx_tx_osc
-- wf_tx_serializer : for the transmission synchronization
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_model_constr_decoder unit
--! wf_prod_bytes_retriever : for the production of a var_identif
model_id_dec_i : in std_logic_vector (7 downto 0);
constr_id_dec_i : in std_logic_vector (7 downto 0);
-------------------------------------------------------------------------------------------------
-- OUTPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_engine_control
request_byte_p_o : out std_logic;
sending_mps_o : out std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; --! transmitter data
tx_enable_o : out std_logic; --! transmitter enable
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, NON-WISHBONE outputs
u_cacer_o : out std_logic; --! nanoFIP status byte, bit 2
u_pacer_o : out std_logic; --! nanoFIP status byte, bit 3
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_prod_p_o : out std_logic --! WISHBONE acknowledge
);
end entity wf_production;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture struc of wf_production is
signal s_byte_to_tx, s_stat, s_mps : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the wf_tx_serializer unit
production_level_0: wf_tx_serializer
generic map(c_TX_CLK_BUFF_LGTH => c_TX_CLK_BUFF_LGTH)
PORT MAP(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
start_prod_p_i => start_prod_p_i,
byte_ready_p_i => byte_ready_p_i,
byte_i => s_byte_to_tx,
last_byte_p_i => last_byte_p_i,
tx_clk_p_buff_i => tx_clk_p_buff_i,
-----------------------------------------------
tx_data_o => tx_data_o,
request_byte_p_o => request_byte_p_o,
tx_enable_o => tx_enable_o
-----------------------------------------------
);
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the wf_prod_bytes_retriever unit
production_level_1 : wf_prod_bytes_retriever
port map(
uclk_i => uclk_i,
model_id_dec_i => model_id_dec_i,
constr_id_dec_i => constr_id_dec_i,
slone_i => slone_i,
nostat_i => nostat_i,
nfip_urst_i => nfip_urst_i,
clk_wb_i => clk_wb_i,
wb_adr_i => wb_adr_i,
wb_stb_r_edge_p_i => wb_stb_r_edge_p_i,
wb_cyc_i => wb_cyc_i,
wb_we_i => wb_we_i,
nFIP_status_byte_i => s_stat,
mps_status_byte_i => s_mps,
var_i => var_i,
byte_index_i => byte_index_i,
data_length_i => data_length_i,
wb_data_i => wb_data_i,
slone_data_i => slone_data_i,
var3_rdy_i => var3_rdy_i,
-----------------------------------------------
sending_mps_o => sending_mps_o,
byte_o => s_byte_to_tx,
wb_ack_prod_p_o => wb_ack_prod_p_o
-----------------------------------------------
);
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_status_bytes_gen unit
status_bytes_gen : WF_status_bytes_gen
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
slone_i => slone_i,
fd_wdgn_i => fd_wdgn_i,
fd_txer_i => fd_txer_i,
nfip_status_r_fcser_p_i => nfip_status_r_fcser_p_i,
var1_rdy_i => var1_rdy_i,
var2_rdy_i => var2_rdy_i,
var3_rdy_i => var3_rdy_i,
var1_acc_i => var1_acc_i,
var2_acc_i => var2_acc_i,
var3_acc_i => var3_acc_i,
nfip_status_r_tler_i => nfip_status_r_tler_i,
rst_status_bytes_i => rst_status_bytes_i,
-----------------------------------------------
u_cacer_o => u_cacer_o,
u_pacer_o => u_pacer_o,
r_tler_o => r_tler_o,
r_fcser_o => r_fcser_o,
nFIP_status_byte_o => s_stat,
mps_status_byte_o => s_mps
-----------------------------------------------
);
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_reset_unit.vhd
View file @ c0ef0386
......@@ -10,7 +10,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
......@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
......@@ -40,12 +40,12 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_cons_bytes_from_rx\n
--! \n<b>Dependencies:</b> \n
--! wf_cons_bytes_processor \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) \n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
......@@ -69,28 +69,28 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
entity WF_reset_unit is
port (
-- INPUTS
-- User Interface general signals (synchronized) (after synchronization)
uclk_i : in std_logic; --! 40 MHz clock
urst_i : in std_logic; --! initialisation control, active low
urst_r_edge_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding
rate_i : in std_logic_vector (1 downto 0);
-- nanoFIP User Interface, General signals (synchronized with uclk) (after synchronization)
uclk_i : in std_logic; --! 40 MHz clock
urst_i : in std_logic; --! initialisation control, active low
urst_r_edge_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding
rate_i : in std_logic_vector (1 downto 0);
-- Signal from the central control unit WF_engine_control
var_i : in t_var; --! variable type
var_i : in t_var; --! variable type that is being treated
rst_nFIP_and_FD_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
assert_RSTON_p_i : in std_logic;
-- OUTPUTS
-- nanoFIP internal reset
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
-- nanoFIP output to the User Interface
rston_o : out std_logic; --! reset output, active low
-- nanoFIP User Interface output
rston_o : out std_logic; --! reset output, active low
-- nanoFIP output to FIELDRIVE
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
-- nanoFIP FIELDRIVE output
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
);
end entity WF_reset_unit;
......@@ -108,7 +108,7 @@ architecture rtl of WF_reset_unit is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process s_rst_creation: the process follows the (buffered) input signal rstin
......@@ -117,7 +117,7 @@ architecture rtl of WF_reset_unit is
s_rst_creation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
if (urst_i = '1') then -- when the rstin in ON
if (s_rstin_c(s_rstin_c'left) = '0') then -- counter counts until 16 (then stays at 16)
......@@ -153,13 +153,13 @@ end process;
--! is received and the 1st byte contains the station address.
--!The signal reset_nFIP_and_FD stays asserted until the end of the transmission of the RP_DAT frame
--! fd_rstn_o: fieldrive reset, active low; active when a reset variable is received and the 1st
--! fd_rstn_o: FIELDRIVE reset, active low; active when a reset variable is received and the 1st
--! byte contains the station address.
--! The signal reset_nFIP_and_FD_i stays asserted until a new variable for this station is received
Reset_Outputs: process (uclk_i)
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
rston_o <= not assert_RSTON_p_i;
nFIP_rst_o <= s_rst or rst_nFIP_and_FD_p_i;
......
wf_rx_deglitcher.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -24,74 +24,85 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name eglitcher
--
--! @brief Glitch filter. 1 pulse adapted filter.
--! @brief The unit applies a glitch filter; it follows each manchester bit of the input signal
--! fd_rxd (synchronized with uclk), counts the number of zeros and ones throughout
--! its duration and finally outputs the majority. The output deglitched signal is one
--! half-bit-clock period later that the input, synchronised fd_rxd.
--! Note: the term sample_manch_bit_p refers to the moments when a manch. encoded bit
--! should be sampled (before and after a significant edge), whereas the
--! sample_bit_p includes only the sampling of the 1st part, before the transition.
--! Example:
--! bit : 0
--! manch. encoded : _|-
--! sample_manch_bit_p : ^ ^
--! sample_bit_p : ^ (this sampling will give the 0)
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
-- @date 08/2010
-- @date 23/08/2010
--
--
--! @version v0.03
--! @version v0.02
--
--
--! @details
--
--! \n<b>Dependencies:</b>\n
--! WF_osc \n
--! WF_reset_unit \n
--! WF_osc \n
--! WF_reset_unit \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content
--! 23/08/2010 v0.03 EG Signal names changed, delayed signals changed, code cleaned-up
--! -> 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content
--! -> 23/08/2010 v0.02 EG code cleaned-up+commented
--
---------------------------------------------------------------------------------------------------
--
--! @todo
-- more comments
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_deglitcher
--! Entity declaration for wf_rx_deglitcher
--=================================================================================================
entity WF_rx_deglitcher is
generic (C_ACULENGTH : integer := 10);
generic (c_DEGLITCH_LGTH : integer := 10);
port(
-- INPUTS
-- User interface general signal
uclk_i : in std_logic; --! 40 MHz clock
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- FIELDRIVE input signal
rxd_i : in std_logic; --! buffered fd_rxd
-- nanoFIP FIELDRIVE (synchronized with uclk)
rxd_i : in std_logic; --! ____|--------|________|--------|________
-- Signals from the WF_osc unit
sample_bit_p_i : in std_logic; --! pulsed signal signaling a new bit
sample_manch_bit_p_i : in std_logic; --! pulsed signal signaling a new manchestered bit
sample_bit_p_i : in std_logic; --! ____|-|_______________|-|_______________
sample_manch_bit_p_i : in std_logic; --! ____|-|______|-|______|-|______|-|______
-- OUTPUTS
-- Output signals needed for the receiverWF_rx
sample_bit_p_o : out std_logic;
rxd_filtered_o : out std_logic;
rxd_filtered_f_edge_p_o : out std_logic;
sample_manch_bit_p_o : out std_logic
-- Signals to the wf_rx_deserializer
rxd_filtered_o : out std_logic; --! filtered output signal
rxd_filtered_f_edge_p_o : out std_logic; --! indicates a falling edge on the filtered signal
sample_bit_p_o : out std_logic; --! same as sample_bit_p_i
sample_manch_bit_p_o : out std_logic --! same as sample_manch_bit_p_i
);
end WF_rx_deglitcher;
......@@ -102,11 +113,10 @@ end WF_rx_deglitcher;
--=================================================================================================
architecture Behavioral of WF_rx_deglitcher is
signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0);
signal s_rxd_filtered : std_logic;
signal s_rxd_filtered_d : std_logic;
signal s_rxd_filtered : std_logic;
signal s_rxd_filtered_d : std_logic;
signal s_rxd_filtered_buff : std_logic_vector (1 downto 0);
signal s_zeros_and_ones_c : signed (c_DEGLITCH_LGTH - 1 downto 0);
--=================================================================================================
......@@ -116,21 +126,24 @@ begin
---------------------------------------------------------------------------------------------------
process(uclk_i)
begin
if rising_edge(uclk_i) then
--! Synchronous process: Zeros_and_Ones_counter: For each manchester bit (between two
--! sample_manch_bit_p_i pulses) at each uclk tick, the signed counter decreases by one if rxd is
--! one or increases by one if rxd is zero.
if nFIP_urst_i = '1' then
s_count_ones_c <= (others =>'0');
Zeros_and_Ones_counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_zeros_and_ones_c <= (others =>'0');
else
if sample_manch_bit_p_i = '1' then -- arrival of a new manchester bit
s_count_ones_c <= (others =>'0'); -- counter initialized
if sample_manch_bit_p_i = '1' then -- arrival of a new manchester bit
s_zeros_and_ones_c <= (others =>'0'); -- counter initialized
elsif rxd_i = '1' then -- counting the number of ones
s_count_ones_c <= s_count_ones_c - 1;
elsif rxd_i = '1' then
s_zeros_and_ones_c <= s_zeros_and_ones_c - 1;
else
s_count_ones_c <= s_count_ones_c + 1;
s_zeros_and_ones_c <= s_zeros_and_ones_c + 1;
end if;
end if;
......@@ -138,55 +151,55 @@ process(uclk_i)
end process;
---------------------------------------------------------------------------------------------------
process(uclk_i)
begin
if rising_edge(uclk_i) then
--! Synchronous process Filtering: On the arrival of a new manchester bit, if the number of ones
--! that has been measured (for the bit that has already passed) is more than the number of zeros,
--! the filtered output signal is zero (until the new manchester bit), otherwise one.
--! The filtered signal is one half-bit-clock cycle (+2 uclk cycles) late with respect to the
--! synchronized fd_rxd.
if nFIP_urst_i = '1' then
s_rxd_filtered <= '0';
Filtering: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_rxd_filtered <= '0';
s_rxd_filtered_d <= '0';
else
if sample_manch_bit_p_i = '1' then
s_rxd_filtered <= s_count_ones_c (s_count_ones_c'left); -- if the ones are more than
-- the zeros, the output is 1
-- otherwise, 0
end if;
s_rxd_filtered_d <= s_rxd_filtered;
s_rxd_filtered <= s_zeros_and_ones_c (s_zeros_and_ones_c'left);-- if the ones are more than
-- the zeros, the output is
end if; -- 1 otherwise, 0
end if;
s_rxd_filtered_d <= s_rxd_filtered; -- 1 uclk period delay, so that the pulses sample_bit_p
-- and sample_manch_bit_p arrive 2 uclk periods before
end if; -- the rxd_filtered edges
end if;
end process;
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Detect_f_edge_rx_data_filtered: detection of a falling edge on the
--! deglitched input signal (rx_data_filtered). A buffer is used to store the last 2 bits of the
--! signal. A falling edge is detected if the last bit of the buffer (new bit) is a zero and the
--! first (old) is a one.
Detect_f_edge_rx_data_filtered: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_rxd_filtered_buff <= (others => '0');
rxd_filtered_f_edge_p_o <= '0';
else
-- buffer s_rxd_filtered_buff keeps the last 2 bits of s_rxd_filtered_d
s_rxd_filtered_buff <= s_rxd_filtered_buff(0) & s_rxd_filtered_d;
-- falling edge detected if last bit is a 0 and previous was a 1
rxd_filtered_f_edge_p_o <= s_rxd_filtered_buff(1)and(not s_rxd_filtered_buff(0));
end if;
end if;
end process;
--!@brief synchronous process Detect_f_edge_rxd_filtered: detection of a falling edge on the
--! deglitched input signal(rxd_filtered). A buffer is used to store the last 2 bits of the signal.
Detect_f_edge_rxd_filtered: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_rxd_filtered_buff <= (others => '0');
---------------------------------------------------------------------------------------------------
else
-- buffer s_rxd_filtered_buff keeps the last 2 bits of s_rxd_filtered_d
s_rxd_filtered_buff <= s_rxd_filtered_buff(0) & s_rxd_filtered_d;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signals assignments
rxd_filtered_f_edge_p_o <= s_rxd_filtered_buff(1) and (not s_rxd_filtered_buff(0));
rxd_filtered_o <= s_rxd_filtered_d;
sample_bit_p_o <= sample_bit_p_i;
sample_manch_bit_p_o <= sample_manch_bit_p_i;
rxd_filtered_o <= s_rxd_filtered_d;
sample_manch_bit_p_o <= sample_manch_bit_p_i;
sample_bit_p_o <= sample_bit_p_i;
end Behavioral;
......
wf_rx.vhd → wf_rx_deserializer.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -7,7 +7,7 @@
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_rx.vhd |
--! @file wf_rx_deserializer.vhd |
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -18,17 +18,17 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx --
-- wf_rx_deserializer --
-- --
---------------------------------------------------------------------------------------------------
--
--
--! @brief De-serialization of the input signal fd_rxd and construction of bytes of data
--! to be provided to the WF_cons_bytes_from_rx unit.
--! to be provided to the wf_cons_bytes_processor unit.
--
--! Remark: We refer to a significant edge for an edge of a Manchester 2 (manch.)
--! encoded bit (eg: bit0: _|-, bit 1: -|_) and to a transition between adjacent bits
......@@ -38,43 +38,53 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! The term sample_manch_bit_p refers to the moments when a manch. encoded bit
--! should be sampled (before and after a significant edge), whereas the
--! sample_bit_p includes only the sampling of the 1st part, before the transition.
--! Example:
--! bit : 0
--! manch. encoded : _|-
--! sample_manch_bit_p : ^ ^
--! sample_bit_p : ^ (this sampling will give the 0)
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 08/2010
--! @date 9/12/2010
--
--
--! @version v0.02
--! @version v0.03
--
--
--! @details \n
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_rx_tx_osc \n
--! WF_deglitcher \n
--! WF_engine_control \n
--! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n
--! WF_rx_tx_osc \n
--! wf_rx_deglitcher \n
--! WF_engine_control \n
--! WF_inputs_synchronizer\n
--
--
--! \n<b>Modified by:</b>\n
--! Erik van der Bij \n
--! Pablo Alvarez Sanchez\n
--! \n<b>Modified by:</b> \n
--! Pablo Alvarez Sanchez \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! -> 09/2009 v0.01 PS First version \n
--! -> 10/2010 v0.02 EG state switch_to_deglitched added;
--! output signal rst_rx_osc_o added; signals renamed;
--! state machine rewritten (mealy style);
--! units WF_manch_code_viol_check and Incoming_Bits_Index created;
--! each manch bit of FES checked (bf was just each bit, so any D5 was FES)
--! code cleaned-up + commented.\n
--! -> 09/2009 v0.01 PAS First version \n
--! -> 10/2010 v0.02 EG state switch_to_deglitched added;
--! output signal rst_rx_osc_o added; signals renamed;
--! state machine rewritten (mealy style);
--! units WF_manch_code_viol_check and Incoming_Bits_Index created;
--! each manch bit of FES checked (bf was just each bit, so any D5 was FES)
--! code cleaned-up + commented.\n
--! -> 12/2010 v0.02 EG CRC_ok pulse transfered 16 bits later to match the FES;
--! like this we confirm that the CRC_ok_p arrived just before the FES,
--! and any 2 bytes that could by chanche be seen as CRC, are neglected.
--! FSM data_field_byte state: redundant code removed:
--! "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle"
--! code(more!)cleaned-up
--
---------------------------------------------------------------------------------------------------
--
......@@ -83,89 +93,90 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\--------------------------/!\--
-- Sunplify Premier Warnings --
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_rx
--! Entity declaration for wf_rx_deserializer
--=================================================================================================
entity WF_rx is
entity wf_rx_deserializer is
port (
-- INPUTS
-- User interface general signal
uclk_i : in std_logic; --! 40MHz clock
-- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit
nFIP_urst_i : in std_logic; --! internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_engine_control
rst_rx_unit_p_i : in std_logic; --! signals that more bytes than expected are being
--! received (ex: ID_DAT > 8 bytes etc) and the unit
--! has to be reset
rst_rx_unit_p_i : in std_logic; --! reset of the unit
--! in cases when more bytes than expected are being
--! received (ex: ID_DAT > 8 bytes etc)
-- Signals from the WF_rx_tx_osc
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
--! bits is expected
-- Signals from WF_inputs_synchronizer
rxd_r_edge_i : in std_logic; --! indicates a rising edge on fd_rxd
rxd_f_edge_i : in std_logic; --! indicates a falling edge on fd_rxd
-- Signals from the WF_inputs_synchronizer
rxd_r_edge_p_i : in std_logic; --! indicates a rising edge on fd_rxd
rxd_f_edge_p_i : in std_logic; --! indicates a falling edge on fd_rxd
-- Signals from the WF_deglitcher
rxd_filtered_o : in std_logic; --! deglitched fd_rxd
-- Signals from the wf_rx_deglitcher
rxd_filtered_i : in std_logic; --! deglitched fd_rxd
rxd_filtered_f_edge_p_i : in std_logic; --! falling edge on the deglitched fd_rxd
sample_manch_bit_p_i : in std_logic; --! pulse indicating a valid sampling time for a manch. bit
sample_bit_p_i : in std_logic; --! pulse indicating a valid sampling time for a bit
sample_manch_bit_p_i : in std_logic; --! pulse indicating the sampling of a manch. bit
sample_bit_p_i : in std_logic; --! pulse indicating the sampling of a bit
-- OUTPUTS
-- Signals to the WF_consumed and WF_engine_control
byte_o : out std_logic_vector (7 downto 0) ; --! retrieved data byte
byte_ready_p_o : out std_logic; --! pulse indicating a valid retrieved data byte
byte_o : out std_logic_vector (7 downto 0) ; --! retrieved data byte
byte_ready_p_o : out std_logic; --! pulse indicating a valid retrieved data byte
-- Signals to the WF_engine_control
FSS_CRC_FES_viol_ok_p_o : out std_logic; --! indication of a frame with a correct FSS,FES,CRC
--! and with no unexpected manch code violations
CRC_wrong_p_o : out std_logic; --! indication of a wrong CRC reception
FSS_received_p_o : out std_logic; --! indication of a correct FSS reception
fss_crc_fes_viol_ok_p_o : out std_logic; --! indication of a frame with a correct FSS,FES,CRC
--! and with no unexpected manch. code violations
crc_wrong_p_o : out std_logic; --! indication of a wrong CRC reception
fss_received_p_o : out std_logic; --! pulse after the reception of a correct FSS
-- Signal to the WF_rx_tx_osc
rst_rx_osc_o : out std_logic --! resets the clock recovery procedure of the rx_osc
rst_rx_osc_o : out std_logic --! reset of the clock recovery procedure of rx_osc
);
end entity WF_rx;
end entity wf_rx_deserializer;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_rx is
architecture rtl of wf_rx_deserializer is
-- states of the receiver's state machine
type rx_st_t is (idle, preamble_field_first_f_edge, preamble_field_r_edge,preamble_field_f_edge,
frame_start_field, switch_to_deglitched, data_field_byte);
signal rx_st, nx_rx_st : rx_st_t;
signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok : std_logic;
signal s_frame_start_last_bit, s_frame_end_wrong_bit : std_logic;
signal s_frame_end_detected_p, s_frame_end_detection : std_logic;
signal s_manch_code_violations, s_switching_to_deglitched : std_logic;
signal s_receiving_FSS, s_receiving_bytes, s_receiving_preamble : std_logic;
signal s_decr_bit_index_p, s_bit_index_load, s_bit_index_is_zero : std_logic;
signal s_byte_ready_p, s_write_bit_to_byte, s_idle : std_logic;
signal s_bit_r_edge,s_FSS_bit,s_FES_bit, s_frame_start_wrong_bit : std_logic;
signal s_manch_r_edge, s_manch_f_edge,s_edge_outside_manch_window: std_logic;
signal s_bit_index, s_bit_index_top : unsigned(3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
type rx_st_t is (idle, pre_field_first_f_edge, pre_field_r_edge, pre_field_f_edge,
fsd_field, switch_to_deglitched, data_fcs_fes_fields);
signal rx_st, nx_rx_st : rx_st_t;
signal s_manch_code_viol_p, s_CRC_ok_p, s_CRC_ok_p_d16 : std_logic;
signal s_fsd_last_bit, s_fes_wrong_bit, s_sample_manch_bit_p_d1 : std_logic;
signal s_fes_detected_p, s_fes_detection_window : std_logic;
signal s_manch_code_violations, s_switching_to_deglitched : std_logic;
signal s_receiving_fsd, s_receiving_bytes, s_receiving_pre : std_logic;
signal s_decr_manch_bit_index_p, s_manch_bit_index_load : std_logic;
signal s_manch_bit_index_is_zero, s_edge_outside_manch_window_p : std_logic;
signal s_byte_ready_p, s_write_bit_to_byte, s_idle : std_logic;
signal s_bit_r_edge_p,s_fsd_bit,s_fes_bit, s_fsd_wrong_bit : std_logic;
signal s_manch_r_edge_p, s_manch_f_edge_p : std_logic;
signal s_manch_bit_index, s_manch_bit_index_top : unsigned(3 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_CRC_ok_p_buff : std_logic_vector (14 downto 0);
--=================================================================================================
......@@ -177,20 +188,20 @@ architecture rtl of WF_rx is
--!@brief Receiver's state machine: the state machine is divided in three parts (a clocked process
--! to store the current state, a combinatorial process to manage state transitions and finally a
--! combinatorial process to manage the output signals), which are the three processes that follow.
--! The unit, is firstly following the input data stream for monitoring the preamble field, and
--! then switches to following the deglitched signal for the rest of the data. It is responsible
--! for the detection of the the preamble, FSS and FES of a received ID_DAT or consumed
--! RP_DAT frame, as well as for the formation of bytes of data.
--! The unit starts by following directly the input data stream (fd_rxd) for the identification of
--! the preamble field (PRE), and then switches to following the filtered signal rxd_filtered,
--! until the end of the frame. It is responsible for the detection of the the PRE, FSD and FES
--! of a received ID_DAT or consumed RP_DAT frame, as well as for the formation of bytes of data.
--! The main outputs of the unit (byte_o and byte_ready_p_o) are the main inputs of the unit
--! WF_cons_bytes_from_rx.
--! wf_cons_bytes_processor.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Receiver_FSM_Sync: storage of the current state of the FSM
--!@brief Synchronous process Receiver_FSM_Sync: storage of the current state of the FSM
Receiver_FSM_Sync: process(uclk_i)
Receiver_FSM_Sync: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
rx_st <= idle;
else
rx_st <= nx_rx_st;
......@@ -203,101 +214,103 @@ architecture rtl of WF_rx is
--!@brief Combinatorial process Receiver_FSM_Comb_StateTransitions:
--! definition of the state transitions of the FSM.
Receiver_FSM_Comb_State_Transitions: process (s_manch_code_viol_p,s_bit_r_edge, s_manch_r_edge,
s_frame_start_last_bit, rxd_filtered_f_edge_p_i,
s_frame_start_wrong_bit, s_manch_f_edge, rx_st,
s_frame_end_detected_p, s_frame_end_wrong_bit,
rxd_f_edge_i, s_edge_outside_manch_window,
rst_rx_unit_p_i)
Receiver_FSM_Comb_State_Transitions: process (s_bit_r_edge_p, s_edge_outside_manch_window_p,
s_fsd_wrong_bit, s_manch_f_edge_p, rx_st,
s_fsd_last_bit, rxd_filtered_f_edge_p_i,
s_fes_detected_p, rst_rx_unit_p_i,
rxd_f_edge_p_i, s_manch_r_edge_p)
begin
nx_rx_st <= idle;
case rx_st is
-- For the monitoring of the preamble, the unit is following the rising and falling edges of
-- fd_rxd. For the rest of the frame, the deglitched signal (rxd_filtered) is used.
-- During the PRE, the rx_osc (in the WF_osc_rx_tx unit) is trying to synchronize to the
-- transmitter's clock, therefore the signal is expected to be clean and every edge detected
-- is taken into account. For the rest of the frame, the unit uses the filtered version of the
-- signal, cleaned of faulty edges/ glitches.
when idle => -- in idle state until falling
if rxd_f_edge_i = '1' then -- edge detection
nx_rx_st <= preamble_field_first_f_edge;
when idle => -- in idle state until falling
if rxd_f_edge_p_i = '1' then -- edge detection
nx_rx_st <= pre_field_first_f_edge;
else
nx_rx_st <= idle;
end if;
when preamble_field_first_f_edge=>
if s_manch_r_edge = '1' then -- arrival of a manch.
nx_rx_st <= preamble_field_r_edge; -- rising edge
when pre_field_first_f_edge=>
if s_manch_r_edge_p = '1' then -- arrival of a "manch."
nx_rx_st <= pre_field_r_edge; -- rising edge
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
elsif s_edge_outside_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
nx_rx_st <= preamble_field_first_f_edge;
nx_rx_st <= pre_field_first_f_edge;
end if;
when preamble_field_r_edge =>
if s_manch_f_edge = '1' then -- arrival of a manch. falling edge
nx_rx_st <= preamble_field_f_edge; -- note: several loops between
-- a rising and a falling edge are
-- expected for the preamble
when pre_field_r_edge =>
if s_manch_f_edge_p = '1' then -- arrival of a "manch."falling edge
nx_rx_st <= pre_field_f_edge; -- note: several loops between
-- a rising and a falling edge are
-- expected for the PRE
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
elsif s_edge_outside_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
nx_rx_st <= preamble_field_r_edge;
nx_rx_st <= pre_field_r_edge;
end if;
when preamble_field_f_edge =>
if s_manch_r_edge = '1' then -- arrival of a manch. rising edge
nx_rx_st <= preamble_field_r_edge;
elsif s_bit_r_edge = '1' then -- arrival of a bit rising edge,
nx_rx_st <= switch_to_deglitched; -- signaling the beginning of the
-- first V+ violation
when pre_field_f_edge =>
if s_manch_r_edge_p = '1' then -- arrival of a "manch." rising edge
nx_rx_st <= pre_field_r_edge;
elsif s_bit_r_edge_p = '1' then -- arrival of a "bit" rising edge,
nx_rx_st <= switch_to_deglitched; -- signaling the beginning of the
-- first V+ violation of the FSD
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
elsif s_edge_outside_manch_window_p = '1' then -- arrival of any other edge
nx_rx_st <= idle;
else
nx_rx_st <= preamble_field_f_edge;
nx_rx_st <= pre_field_f_edge;
end if;
-- A small delay is expected between the rxd and the rxd_filtered (output of the
-- WF_rx_deglitcher) which means that the last falling edge of the preamble of rxd arrives
-- There is a half-bit-clock period of delay between the rxd and the rxd_filtered (output of the
-- WF_rx_deglitcher) which means that the last falling edge of the PRE of rxd arrives
-- earlier than the one of the rxd_filtered. The state switch_to_deglitched is used for
-- this purpose.
when switch_to_deglitched =>
if rxd_filtered_f_edge_p_i = '1' then
nx_rx_st <= frame_start_field;
nx_rx_st <= fsd_field;
else
nx_rx_st <= switch_to_deglitched;
end if;
-- For the monitoring of the frame start delimiter, the unit is sampling each manch. bit of
-- the incoming filtered signal and it is comparing it to the nominal bit of the frame start
-- delimiter. If a wrong bit is received, the state machine jumps back to idle, whereas if
-- the complete byte is correctly received, it jumps to the data_field_byte state.
-- For the monitoring of the FSD, the unit is sampling each manch. bit of the incoming
-- filtered signal and it is comparing it to the nominal bit of the FSD (through the signal
-- s_fsd_wrong_bit). If a wrong bit is received, the state machine jumps back to idle,
-- whereas if the complete byte is correctly received, it jumps to the data_fcs_fes_fields state.
when frame_start_field =>
if s_frame_start_last_bit = '1' then -- reception of the last(15th)
nx_rx_st <= data_field_byte; -- FSS bit
when fsd_field =>
if s_fsd_last_bit = '1' then -- reception of the last(15th)
nx_rx_st <= data_fcs_fes_fields; -- FSD bit
elsif s_frame_start_wrong_bit = '1' then -- wrong bit
elsif s_fsd_wrong_bit = '1' then -- wrong bit
nx_rx_st <= idle;
else
nx_rx_st <= frame_start_field;
nx_rx_st <= fsd_field;
end if;
when data_field_byte =>
if s_frame_end_detected_p = '1' or rst_rx_unit_p_i = '1' then
-- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length
-- (not predefined) up to 134 bytes (FSS+Ctrl+124_data_bytes+nanoFIP_status+MPS+FCS+FES).
-- The control_engine unit is the one following the amount of data bytes being received.
-- Therefore, the Receiver_FSM stays in the data_fcs_fes_fields state until the arrival of a
-- correct FES, or until the arrival of a reset signal(rst_rx_unit_p_i)from the control_engine.
when data_fcs_fes_fields =>
if s_fes_detected_p = '1' or rst_rx_unit_p_i = '1' then
nx_rx_st <= idle;
elsif s_frame_end_wrong_bit = '1' and s_manch_code_viol_p = '1' then
nx_rx_st <= idle;
else
nx_rx_st <= data_field_byte;
nx_rx_st <= data_fcs_fes_fields;
end if;
when others =>
......@@ -306,7 +319,7 @@ architecture rtl of WF_rx is
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief combinatorial process Receiver_FSM_Comb_Output_Signals:
--!@brief Combinatorial process Receiver_FSM_Comb_Output_Signals:
--! definition of the output signals of the FSM
Receiver_FSM_Comb_Output_Signals: process (rx_st)
......@@ -317,54 +330,54 @@ architecture rtl of WF_rx is
when idle =>
s_idle <= '1';
s_receiving_preamble <= '0';
s_receiving_pre <= '0';
s_switching_to_deglitched <= '0';
s_receiving_FSS <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when preamble_field_first_f_edge | preamble_field_r_edge | preamble_field_f_edge =>
when pre_field_first_f_edge | pre_field_r_edge | pre_field_f_edge =>
s_idle <= '0';
s_receiving_preamble <= '1';
s_receiving_pre <= '1';
s_switching_to_deglitched <= '0';
s_receiving_FSS <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when switch_to_deglitched =>
s_idle <= '0';
s_receiving_preamble <= '0';
s_receiving_pre <= '0';
s_switching_to_deglitched <= '1';
s_receiving_FSS <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
when frame_start_field =>
when fsd_field =>
s_idle <= '0';
s_receiving_preamble <= '0';
s_receiving_pre <= '0';
s_switching_to_deglitched <= '0';
s_receiving_FSS <= '1';
s_receiving_fsd <= '1';
s_receiving_bytes <= '0';
when data_field_byte =>
when data_fcs_fes_fields =>
s_idle <= '0';
s_receiving_preamble <= '0';
s_receiving_pre <= '0';
s_switching_to_deglitched <= '0';
s_receiving_FSS <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '1';
when others =>
s_idle <= '0';
s_receiving_preamble <= '0';
s_receiving_pre <= '0';
s_switching_to_deglitched <= '0';
s_receiving_FSS <= '0';
s_receiving_fsd <= '0';
s_receiving_bytes <= '0';
end case;
......@@ -373,82 +386,85 @@ architecture rtl of WF_rx is
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of a counter that manages the position of an incoming deglitched bit
--! inside a manch encoded byte (16 bits)
Incoming_Bits_Index: WF_decr_counter
generic map(counter_length => 4)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_bit_index_p,
counter_o => s_bit_index,
counter_is_zero_o => s_bit_index_is_zero);
--! inside a manch. encoded byte (16 bits)
Incoming_Bits_Index: WF_decr_counter
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
nfip_urst_i => nfip_urst_i,
counter_top => s_manch_bit_index_top,
counter_load_i => s_manch_bit_index_load,
counter_decr_p_i => s_decr_manch_bit_index_p,
---------------------------------------------------
counter_o => s_manch_bit_index,
counter_is_zero_o => s_manch_bit_index_is_zero);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process that according to the state of the FSM sets the values to the
-- Combinatorial process that according to the state of the FSM sets values to the
-- Incoming_Bits_Index inputs
Bit_Index: process (s_idle,s_receiving_preamble, s_switching_to_deglitched, s_receiving_FSS,
s_receiving_bytes, s_bit_index_is_zero,sample_manch_bit_p_i)
Bit_Index: process (s_idle,s_receiving_pre, s_switching_to_deglitched, s_receiving_fsd,
s_receiving_bytes, s_manch_bit_index_is_zero,sample_manch_bit_p_i)
begin
if s_idle ='1' then -- counter re-initialization after a reception
s_bit_index_top <= to_unsigned (0, s_bit_index_top'length);
s_bit_index_load <= '1';
s_decr_bit_index_p <= '0';
if s_idle ='1' then -- counter re-initialization after a reception
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load <= '1';
s_decr_manch_bit_index_p <= '0';
elsif s_receiving_preamble = '1' then -- no action
s_bit_index_top <= to_unsigned (0, s_bit_index_top'length);
s_bit_index_load <= '0';
s_decr_bit_index_p <= '0';
elsif s_receiving_pre = '1' then -- no action
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load <= '0';
s_decr_manch_bit_index_p <= '0';
elsif s_switching_to_deglitched = '1' then -- preparation for FSS
s_bit_index_top <= to_unsigned(FRAME_START'left-1,s_bit_index_top'length);
s_bit_index_load <= s_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_bit_index_p <= '0';
elsif s_switching_to_deglitched = '1' then -- preparation for the fsd_field byte
-- FSD'left-1: bc the 1st bit of the FSD has been covered at the state PRE_field_f_edge
s_manch_bit_index_top <= to_unsigned(FSD'left-1,s_manch_bit_index_top'length);
s_manch_bit_index_load <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_manch_bit_index_p <= '0';
elsif s_receiving_FSS = '1' then -- counting FSS bits
s_bit_index_top <= to_unsigned (0, s_bit_index_top'length);
s_bit_index_load <= '0';
s_decr_bit_index_p <= sample_manch_bit_p_i;
elsif s_receiving_fsd = '1' then -- counting FSD manch. encoded bits
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load <= '0';
s_decr_manch_bit_index_p <= sample_manch_bit_p_i;
elsif s_receiving_bytes = '1' then -- preparation for FSS & counting data bits
s_bit_index_top <= to_unsigned (FRAME_END'left, s_bit_index_top'length);
s_bit_index_load <= s_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_bit_index_p <= sample_manch_bit_p_i;
elsif s_receiving_bytes = '1' then -- counting manch. encoded data bits
s_manch_bit_index_top <= to_unsigned (15, s_manch_bit_index_top'length);
s_manch_bit_index_load <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_decr_manch_bit_index_p <= sample_manch_bit_p_i;
else
s_bit_index_top <= to_unsigned (0, s_bit_index_top'length);
s_bit_index_load <= '0';
s_decr_bit_index_p <= '0';
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load <= '0';
s_decr_manch_bit_index_p <= '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- aux signals concurrent assignments:
s_FSS_bit <= s_receiving_FSS and FRAME_START (to_integer(s_bit_index));
s_FES_bit <= s_receiving_bytes and FRAME_END (to_integer(resize(s_bit_index,4)));
s_fsd_bit <= s_receiving_fsd and FSD (to_integer(s_manch_bit_index));
s_fes_bit <= s_receiving_bytes and FES (to_integer(s_manch_bit_index));
s_frame_start_wrong_bit <= (s_FSS_bit xor rxd_filtered_o) and sample_manch_bit_p_i;
s_frame_start_last_bit <= s_bit_index_is_zero and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor rxd_filtered_i) and sample_manch_bit_p_i;
s_fsd_last_bit <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_frame_end_wrong_bit <= (s_FES_bit xor rxd_filtered_o) and sample_manch_bit_p_i;
s_frame_end_detected_p <= s_frame_end_detection and sample_manch_bit_p_i and s_bit_index_is_zero;
s_fes_wrong_bit <= (s_fes_bit xor rxd_filtered_i) and sample_manch_bit_p_i;
s_fes_detected_p <=s_fes_detection_window and sample_manch_bit_p_i and s_manch_bit_index_is_zero;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Append_Bit_To_Byte: creation of bytes of data.
--! a new bit of the deglitched input signal is appended to the output
--! a new bit of the (deglitched) input signal is appended to the output
--! byte when s_write_bit_to_byte is enabled.
Append_Bit_To_Byte: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
byte_ready_p_o <='0';
s_byte <= (others => '0');
else
......@@ -456,7 +472,7 @@ architecture rtl of WF_rx is
byte_ready_p_o <= s_byte_ready_p;
if s_write_bit_to_byte = '1' then
s_byte <= s_byte(6 downto 0) & rxd_filtered_o;
s_byte <= s_byte(6 downto 0) & rxd_filtered_i;
end if;
end if;
......@@ -464,8 +480,8 @@ architecture rtl of WF_rx is
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_write_bit_to_byte <= s_receiving_bytes and sample_bit_p_i;
s_byte_ready_p <= s_receiving_bytes and s_bit_index_is_zero and sample_manch_bit_p_i
and (not s_frame_end_detected_p);
s_byte_ready_p <= s_receiving_bytes and s_manch_bit_index_is_zero and sample_manch_bit_p_i
and (not s_fes_detected_p);
---------------------------------------------------------------------------------------------------
......@@ -474,51 +490,47 @@ architecture rtl of WF_rx is
generic map(c_GENERATOR_POLY_length => 16)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
start_CRC_p_i => s_receiving_FSS,
nfip_urst_i => nfip_urst_i,
start_crc_p_i => s_receiving_fsd,
data_bit_ready_p_i => s_write_bit_to_byte,
data_bit_i => rxd_filtered_o,
CRC_o => open,
CRC_ok_p => s_CRC_ok_p);
data_bit_i => rxd_filtered_i,
crc_o => open,
--------------------------------------------
crc_ok_p => s_CRC_ok_p);
--------------------------------------------
---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the unit that checks for code violations
Check_code_violations: WF_manch_code_viol_check
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
serial_input_signal_i => rxd_filtered_o,
nfip_urst_i => nfip_urst_i,
serial_input_signal_i => rxd_filtered_i,
sample_bit_p_i => sample_bit_p_i,
sample_manch_bit_p_i => sample_manch_bit_p_i,
-----------------------------------------------
manch_code_viol_p_o => s_manch_code_viol_p);
-----------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that manages the signals regarding CRC errors and code violations.
--! If the calculated CRC is correct the signal s_CRC_ok stays asserted until the end of the
--! corresponding frame.
--! Similarly, if at any point after the FSS and before the FES a code violation appears, the
--!@brief Synchronous process that manages the code violations signal.
--! If at any point after the FSS and before the FES a code violation appears, the
--! signal s_manch_code_violations stays asserted until the end of the corresponding frame.
CRC_Code_viol_signals: process(uclk_i)
Code_viol: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_CRC_ok <= '0';
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_manch_code_violations <= '0';
else
if s_receiving_bytes = '0' then
s_CRC_ok <= '0';
if s_receiving_bytes = '0' then -- after the FSS
s_manch_code_violations <= '0';
else
if s_CRC_ok_p = '1' then
s_CRC_ok <= '1';
end if;
if s_manch_code_viol_p ='1' and s_frame_end_wrong_bit ='1' then
if s_manch_code_viol_p ='1' and s_fes_wrong_bit ='1' then
s_manch_code_violations <= '1'; -- if a code violation appears
-- that doesn't belong to the FES
end if;
......@@ -529,22 +541,59 @@ architecture rtl of WF_rx is
end process;
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process that manages the CRC signal.
--! The crc_ok_p coming from the CRC calculator unit is delayed for 16 manch. encoded bits.
--! The matching of this delayed pulse with the end of frame pulse (s_fes_detected_p), would
--! confirm that the two last bytes received before the FES were the correct CRC.
CRC_OK_pulse_delay: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_CRC_ok_p_buff <= (others => '0');
s_sample_manch_bit_p_d1 <= '0';
else
s_sample_manch_bit_p_d1 <= sample_manch_bit_p_i; -- delay for the synch of s_crc_ok_p
-- with s_sample_manch_bit_p_d1
if s_receiving_bytes = '0' then
s_CRC_ok_p_buff <= (others => '0');
else
if s_sample_manch_bit_p_d1 = '1' then -- a delay is added to s_CRC_ok_p with
-- each manch. bit arrival. In total 15
-- delays have to be added in order to
-- arrive to the FES.
s_CRC_ok_p_buff <= s_CRC_ok_p_buff(13 downto 0) & s_CRC_ok_p;
end if;
end if;
end if;
end if;
end process;
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(14); -- pulse 1 half-bit-clock period long
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process FES_Detector: creation of a window that is activated at the
--! beginning of an incoming byte and stays active as long as 16 incoming manch. bits match the FES.
FES_Detector: process(uclk_i)
FES_Detector: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_frame_end_detection <= '1';
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_fes_detection_window <= '1';
else
if s_bit_index_is_zero = '1' and sample_manch_bit_p_i = '1' then
s_frame_end_detection <= '1';
if s_manch_bit_index_is_zero = '1' and sample_manch_bit_p_i = '1' then
s_fes_detection_window <= '1';
elsif s_frame_end_wrong_bit = '1' then
s_frame_end_detection <= '0';
elsif s_fes_wrong_bit = '1' then
s_fes_detection_window <= '0';
end if;
end if;
......@@ -554,18 +603,18 @@ architecture rtl of WF_rx is
---------------------------------------------------------------------------------------------------
-- aux signals concurrent assignments:
s_manch_r_edge <= signif_edge_window_i and rxd_r_edge_i;
s_manch_f_edge <= signif_edge_window_i and rxd_f_edge_i;
s_bit_r_edge <= adjac_bits_window_i and ( rxd_r_edge_i);
s_edge_outside_manch_window <= (not signif_edge_window_i)and(rxd_r_edge_i or rxd_f_edge_i);
s_manch_r_edge_p <= signif_edge_window_i and rxd_r_edge_p_i;
s_manch_f_edge_p <= signif_edge_window_i and rxd_f_edge_p_i;
s_bit_r_edge_p <= adjac_bits_window_i and ( rxd_r_edge_p_i);
s_edge_outside_manch_window_p <= (not signif_edge_window_i)and(rxd_r_edge_p_i or rxd_f_edge_p_i);
---------------------------------------------------------------------------------------------------
-- output signals:
byte_o <= s_byte;
rst_rx_osc_o <= s_idle;
FSS_received_p_o <= s_receiving_FSS and s_frame_start_last_bit;
CRC_wrong_p_o <= s_frame_end_detected_p and (not s_CRC_ok);
FSS_CRC_FES_viol_ok_p_o <= s_frame_end_detected_p and s_CRC_ok and (not s_manch_code_violations);
-- output signals concurrent assignments:
byte_o <= s_byte;
rst_rx_osc_o <= s_idle;
fss_received_p_o <= s_receiving_fsd and s_fsd_last_bit;
crc_wrong_p_o <= s_fes_detected_p and (not s_crc_ok_p_d16);
fss_crc_fes_viol_ok_p_o <= s_fes_detected_p and s_crc_ok_p_d16 and (not s_manch_code_violations);
end architecture rtl;
--=================================================================================================
......
wf_rx_tx_osc.vhd
View file @ c0ef0386
--________________________________________________________________________________________________|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_tx_osc --
......@@ -27,7 +27,8 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--
-- unit name WF_rx_tx_osc
--
--! @brief Generation the clock signals needed for the receiver(WF_rx)and transmiter(WF_tx)\n
--! @brief Generation the clock signals needed for the receiver (wf_rx_deglitcher and
--! wf_rx_deserializer)and transmiter(wf_tx_serializer)\n
--!
--! Concerning the reception, even if the bit rate of the communication is known, jitter
--! is expected to affect the arriving time of the incoming signal. The main idea of the
......@@ -51,24 +52,24 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--
--! @date 07/2010
--! @date 08/12/2010
--
--
--! @version v0.02
--! @version v0.03
--
--
--! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n
--! WF_synchronizer\n
--! WF_rx \n
--! WF_reset_unit \n
--! WF_synchronizer \n
--! wf_rx_deserializer \n
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez\n
--! Evangelia Gousiou \n
--! Evangelia Gousiou \n
--
---------------------------------------------------------------------------------------------------
--
......@@ -76,8 +77,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--! -> 08/2009 v0.01 PS Entity Ports added, start of architecture content \n
--! -> 07/2010 v0.02 EG tx, rx counter changed from 20 bits signed, to 11 bits unsigned;
--! rx clk generation depends on edge detection; code cleaned-up+commented
--! C_TXCLKBUFFLENTGTH got 1 bit more\n
--! c_TX_CLK_BUFF_LGTH got 1 bit more\n
--! rst_rx_osc signal clearified
--! -> 12/2010 v0.03 EG code cleaned-up
--
---------------------------------------------------------------------------------------------------
--
......@@ -85,8 +87,8 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\--------------------------/!\--
-- Sunplify Premier Warnings --
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- No Warnings --
---------------------------------------------------------------------------------------------------
......@@ -97,47 +99,54 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, co
--=================================================================================================
entity WF_rx_tx_osc is
generic (C_PERIODS_COUNTER_LENGTH : natural;
C_QUARTZ_PERIOD : real;
C_TXCLKBUFFLENTGTH : natural);
generic (C_PERIODS_COUNTER_LENGTH : natural := 11; -- 2^ c_PERIODS_COUNTER_LENGTH: # uclk ticks
-- equivalent to the reception/ transmission
-- period. In the slowest bit rate (31.25kbps)
-- the period is 32000ns and can be measured
-- after 1280 uclk ticks. Therefore a counter
-- of 11 bits is the max needed for counting
-- transmission/ reception periods.
c_TX_CLK_BUFF_LGTH : natural := 4); -- length of tx_clk_p_buff_o (default 4)
port (
-- INPUTS
-- User interface general signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! bit rate
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! bit rate
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_reset_unit
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_synchronizer
rxd_edge_i : in std_logic; --! indication of an edge on rxd_i
rxd_f_edge_i : in std_logic; --! indication of a falling edge on rxd_i
-- Signal from the WF_synchronizer
rxd_edge_i : in std_logic; --! indication of an edge on fd_rxd
-- Signal from WF_rx
rst_rx_osc_i : in std_logic; --! resets the clock recovery procedure of the rx_osc
-- Signal from wf_rx_deserializer
rst_rx_osc_i : in std_logic; --! resets the clock recovery procedure of the rx_osc
-- OUTPUTS
-- Output signals needed in the reception
-- Outputs to WF_rx and WF_rx_deglitcher
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
-- Signals to the wf_rx_deserializer and the wf_rx_deglitcher
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! 1) on a significant edge
--! 2) between adjacent bits
--! ____|-|___|-|___|-|___
rx_bit_clk_p_o : out std_logic; --! signal with uclk-wide pulses
rx_bit_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! between adjacent bits
--! __________|-|_________
rx_signif_edge_window_o : out std_logic; --! time window where a significant edge is expected
rx_adjac_bits_window_o : out std_logic; --! time window where a transition between adjacent
rx_adjac_bits_window_o : out std_logic; --! time window where a transition between adjacent
--! bits is expected
-- Output signals needed in the transmission
-- nanoFIP output
tx_clk_o : out std_logic; --! line driver half bit clock
-- Output to the WF_tx
tx_clk_p_buff_o : out std_logic_vector (C_TXCLKBUFFLENTGTH -1 downto 0)
-- nanoFIP FIELDRIVE output
tx_clk_o : out std_logic; --! line driver half bit clock
-- Signal to the wf_tx_serializer
tx_clk_p_buff_o : out std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0)
--! buffer keeping the last values of tx_clk_o
);
end entity WF_rx_tx_osc;
......@@ -149,20 +158,18 @@ end entity WF_rx_tx_osc;
--=================================================================================================
architecture rtl of WF_rx_tx_osc is
signal s_counter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_rx_counter, s_tx_counter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_period, s_jitter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_counter_full, s_half_period : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_one_forth_period : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector (C_TXCLKBUFFLENTGTH -1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_rx_bit_clk, s_rx_manch_clk_d1 : std_logic;
signal s_rx_bit_clk_d1, s_rx_manch_clk : std_logic;
signal s_adjac_bits_edge_found : std_logic;
signal s_signif_edge_found : std_logic;
signal s_rxd_signif_edge_window : std_logic;
signal s_rx_adjac_bits_window : std_logic;
signal s_rx_counter, s_tx_counter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_period, s_jitter : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_counter_full, s_half_period : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_one_forth_period : unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH -1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_rx_bit_clk, s_rx_manch_clk_d1 : std_logic;
signal s_rx_bit_clk_d1, s_rx_manch_clk : std_logic;
signal s_adjac_bits_edge_found : std_logic;
signal s_signif_edge_found : std_logic;
signal s_rxd_signif_edge_window : std_logic;
signal s_rx_adjac_bits_window : std_logic;
--=================================================================================================
......@@ -170,7 +177,9 @@ architecture rtl of WF_rx_tx_osc is
--=================================================================================================
begin
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i))); -- # uclock ticks for a period
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
-- # uclock ticks for a period
s_half_period <= s_period srl 1; -- s_period shifted 1 bit
s_one_forth_period <= s_period srl 2; -- s_period shifted 2 bits
s_jitter <= s_period srl 3; -- jitter defined as 1/8 of
......@@ -182,20 +191,21 @@ begin
-- rx_osc
---------------------------------------------------------------------------------------------------
-- Synchronous process rx_periods_count:
-- in this process the rx_counter stops being initialized after a falling edge of the rxd
-- (according to the signal rst_rx_osc_i from the WF_rx_unit); this edge should be representing
-- the 1st Manchester (manch.) encoded bit '1' of the preamble.
-- the rx_counter starts counting after a falling edge on the fd_rxd (indicated by the signal
-- rst_rx_osc_i from the wf_rx_deserializer unit); this edge should be representing the 1st
-- Manchester (manch.) encoded bit '1' of the preamble.
-- Starting from this edge, other falling or rising significant edges, are expected around one
-- period later. A time window around the expected arrival time is set and its length is defined
-- as 1/4th of the period (1/8th before and 1/8th after the expected time). When the actual edge
-- arrives, the counter resets.
-- If on the other hand, that edge is proven not to belong to a valid preambe, the signal
-- arrives, the counter is reset.
-- If that first falling edge of fd_rxd is finally proven not to belong to a valid preambe
-- (the state machine of the wf_rx_deserializer unit is checking that and generating the
-- rst_rx_osc_i), the counter is reinitialialized.
rx_periods_count: process (uclk_i)
begin
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_rx_counter <= (others => '0');
else
......@@ -209,13 +219,13 @@ begin
-- counter counting
else
if (s_rxd_signif_edge_window = '1') and (rxd_edge_i ='1') then
s_rx_counter <= (others => '0'); -- when an edge appears inside
-- the expected window, the
-- counter is reinitialized
if (s_rxd_signif_edge_window = '1') and (rxd_edge_i = '1') then
s_rx_counter <= (others => '0'); -- when an edge appears inside
-- the expected window, the
-- counter is reinitialized
elsif (s_rx_counter=s_counter_full) then -- otherwise, it continues counting
s_rx_counter <= (others => '0'); -- complete nominal periods
elsif (s_rx_counter = s_counter_full) then -- otherwise, it continues counting
s_rx_counter <= (others => '0'); -- complete nominal periods
else
s_rx_counter <= s_rx_counter + 1 ;
......@@ -227,37 +237,35 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignments concerning the receiver:
--creation of the windows where significant edges and adjacent bits transitions are expected on the
-- input signal
-- reminder:in principle, s_rx_counter is initialized after the detection of a significant edge and
-- it is counting a complete period, according to the bit rate.
-- creation of the windows where "significant edges" and "adjacent bits transitions" are expected
-- on the input signal.
-- s_rxd_signif_edge_window extends s_jitter uclk ticks before and s_jitter uclk ticks after the
-- completion of a period, where significant edges are expected
-- s_rx_adjac_bits_window extends s_jitter uclk ticks before and s_jitter uclk ticks after the
-- middle of a period, where transitions between adjacent bits are expected
-- s_rxd_signif_edge_window: extends s_jitter uclk ticks before and s_jitter uclk ticks after the
-- completion of a period, where significant edges are expected.
-- s_rx_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after the
-- middle of a period, where transitions between adjacent bits are expected.
s_rxd_signif_edge_window <= '1' when ((s_rx_counter < s_jitter) or
(s_rx_counter > s_counter_full - s_jitter-1))
else '0';
(s_rx_counter > s_counter_full - s_jitter-1))
else '0';
s_rx_adjac_bits_window <= '1' when ((s_rx_counter >= s_half_period-s_jitter-1) and
(s_rx_counter < s_half_period+s_jitter))
s_rx_adjac_bits_window <= '1' when ((s_rx_counter >= s_half_period-s_jitter-1) and
(s_rx_counter < s_half_period+s_jitter))
else '0';
else '0';
---------------------------------------------------------------------------------------------------
-- Synchronous process rx_clk:
-- the process rx_clk is following the edges that appear on the input signal and constructs two
-- clock signals: rx_manch_clk and rx_bit_clk.
-- the process rx_clk is following the edges that appear on the input signal fd_rxd and constructs
-- two clock signals: rx_manch_clk and rx_bit_clk.
-- In detail, the process is looking for moments:
-- 1) of significant edges
-- 2) between boundary bits
-- the signal rx_manch_clk is inverted on each significant edge,as well as between adjacent bits
-- the signal rx_bit_clk is inverted only between adjacent bits
-- the signal rx_manch_clk: is inverted on each significant edge,as well as between adjacent bits
-- the signal rx_bit_clk : is inverted only between adjacent bits
-- The significant edges are normally expected inside the signif_edge_window. In the cases of a
-- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk
......@@ -270,9 +278,9 @@ begin
rx_clk: process (uclk_i)
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
-- initializations:
if (nFIP_urst_i = '1') then
if (nfip_urst_i = '1') then
s_rx_manch_clk <='0';
s_rx_bit_clk <='0';
s_rx_bit_clk_d1 <='0';
......@@ -282,42 +290,49 @@ begin
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding significant edges:
if (s_rxd_signif_edge_window='1') then -- looking for a significant edge
if (rxd_edge_i='1') then -- inside the corresponding window
s_rx_manch_clk <= not s_rx_manch_clk;
s_signif_edge_found <= '1'; -- indication that the edge was found
-- looking for a significant edge inside the corresponding window
if (s_rxd_signif_edge_window = '1') and (rxd_edge_i = '1') then
s_rx_manch_clk <= not s_rx_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
end if;
elsif (s_signif_edge_found='0')and(s_rx_counter=s_jitter) then
-- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_rx_counter = s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk;
--if a significant edge is not found where
-- expected (code violation), the
-- rx_manch_clk is inverted right after the
-- end of the signif_edge_window
s_adjac_bits_edge_found <= '0'; -- re-initialization before the
-- next cycle
s_adjac_bits_edge_found <= '0'; -- re-initialization before the next cycle
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- regarding edges between adjacent bits:
elsif (s_rx_adjac_bits_window='1') then -- looking for an edge inside
if (rxd_edge_i='1') then -- the corresponding window
-- looking for an edge inside the corresponding window
elsif (s_rx_adjac_bits_window = '1') and (rxd_edge_i = '1') then
s_rx_manch_clk <= not s_rx_manch_clk;-- inversion of rx_manch_clk
s_rx_bit_clk <= not s_rx_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
elsif (s_adjac_bits_edge_found='0')and(s_rx_counter=s_half_period+s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk; -- if no edge occurs inside the
s_rx_bit_clk <= not s_rx_bit_clk; --adjac_bits_edge_window,both clks are
-- inverted right after the end of it
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_rx_counter = s_half_period + s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk;
s_rx_bit_clk <= not s_rx_bit_clk;
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_rx_manch_clk_d1 <= s_rx_manch_clk;
-- s_rx_manch_clk: ____|-----|_____|-----|____
-- s_rx_manch_clk_d1: ______|-----|_____|-----|__
......@@ -338,43 +353,53 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process tx_periods_count: implementation of a counter counting transmission periods.
tx_periods_count: process(uclk_i)
tx_periods_count: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_tx_counter <= (others => '0');
s_tx_clk_d1 <= '0';
s_tx_clk_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
-- free counter measuring transmission periods
if (s_tx_counter = s_counter_full) then
if (s_tx_counter = s_counter_full) then
s_tx_counter <= (others => '0');
else
s_tx_counter <= s_tx_counter + 1 ;
end if;
-- clk signals:
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left -1 downto 0) & s_tx_clk_p;--buffer
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left -1 downto 0) & s_tx_clk_p;
-- buffering the s_tx_clk_p pulses
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- concurrent signal assignments concerning the transmitter:
-- creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_tx_counter < s_one_forth_period) or
((s_tx_counter > (2*s_one_forth_period)-1) and (s_tx_counter < 3*s_one_forth_period)))
else '0';
-- creation of a pulse starting 1 uclk period before s_tx_clk_o (s_tx_clk_d1)
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk: __|-----|_____|-----|_____
-- s_tx_clk_o: ____|-----|_____|-----|___
-- not s_tx_clk_d1: ----|_____|-----|_____|---
-- s_tx_clk_p: __|-|___|-|___|-|___|-|___
-- Concurrent signal assignments concerning the transmitter:
-- creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_tx_counter < s_one_forth_period) or
((s_tx_counter > (2*s_one_forth_period)-1) and
(s_tx_counter < 3*s_one_forth_period)))
else '0';
-- transm. period : _|----------|__________|--
-- tx_counter : 0 1/4 1/2 3/4 1
-- s_tx_clk : _|----|_____|----|_____|--
-- creation of a pulse starting 1 uclk period before tx_clk_o
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk : __|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1 : ____|-----|_____|-----|___
-- not s_tx_clk_d1 : ----|_____|-----|_____|---
-- s_tx_clk_p : __|-|___|-|___|-|___|-|___
---------------------------------------------------------------------------------------------------
-- Output signals construction:
......
wf_status_bytes_gen.vhd
View file @ c0ef0386
......@@ -10,7 +10,7 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
......@@ -23,18 +23,19 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
-- unit name WF_status_bytes_gen
--
--
--! @brief Generation of the NanoFIP status, as well as the MPS status bytes.
--! @brief Generation of the nanoFIP status and MPS status bytes.
--! The unit is also responsible for outputting the nanoFIP signals U_CACER, U_PACER,
--! R_TLER, R_FCSER
--
--
--! @author Erik van der Bij (Erik.van.der.Bij@cern.ch)
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 07/2010
--! @date 10/01/2011
--
--
--! @version v0.01
--! @version v0.03
--
--
--! @details\n
......@@ -47,23 +48,35 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--
--
--! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n
--! 07/07/2009 v0.01 EB First version \n
--! 08/2010 v0.02 EG code violation & CRC errors considered
--! only during a concumed var reception
--! extended var_rdy
--!
--! -> 07/07/2009 v0.01 PA First version \n
--! -> 08/2010 v0.02 EG code violation & CRC errors considered
--! only during a concumed var reception.
--! -> 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status
--! errors few cycles after var_rdy deactivation
--! -> 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_i
--! for nanoFIP status bit 4; var_i input not needed as the signals
--! nfip_status_r_fcser_p_i and nfip_status_r_tler_i check the var
--
---------------------------------------------------------------------------------------------------
--
--! @todo bits 6 and 7 reset only when nanoFIP is reset...
--! @todo
--
---------------------------------------------------------------------------------------------------
---/!\----------------------------/!\----------------------------/!\-------------------------/!\---
-- Sunplify Premier D-2009.12 Warnings --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "W CL189 Register bits s_nFIP_status_byte(0), s_nFIP_status_byte(1) are always 0, optimizing" --
-- "W CL260 Pruning Register bits 0 and 1 of s_nFIP_status_byte(7 downto 0)" --
-- Bits 0 and 1 of nanoFIP status byte are reserved for future ideas. --
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Entity declaration for WF_status_bytes_gen
......@@ -72,40 +85,43 @@ entity WF_status_bytes_gen is
port (
-- INPUTS
-- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40 MHz Clock
slone_i : in std_logic; --! Stand-alone mode
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40 MHz Clock
slone_i : in std_logic; --! stand-alone mode
-- Signal from the reset_logic unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signals from the fieldrive interface
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
-- Signals from the non-WISHBONE user interface
var1_acc_i : in std_logic; --! Variable 1 access (asynchronous)
var2_acc_i : in std_logic; --! Variable 2 access (asynchronous)
var3_acc_i : in std_logic; --! Variable 3 access (asynchronous)
-- Signal from the receiver WF_rx
crc_wrong_p_i : in std_logic;
-- Signals from the central control unit WF_engine_control
var_i : in t_var; --! variable type
var1_rdy_i : in std_logic; --! Variable 1 ready
var2_rdy_i : in std_logic; --! Variable 2 ready
var3_rdy_i : in std_logic; --! Variable 3 ready
-- Signal from nanofip
rst_status_bytes_i : in std_logic; --! both status bytes are reinitialized
--! right after having been delivered
nfip_urst_i : in std_logic; --! nanaoFIP internal reset
-- nanoFIP FIELDRIVE
fd_wdgn_i : in std_logic; --! watchdog on transmitter
fd_txer_i : in std_logic; --! transmitter error
-- nanoFIP User Interface, NON-WISHBONE (synchronized with uclk)
var1_acc_i : in std_logic; --! variable 1 access
var2_acc_i : in std_logic; --! variable 2 access
var3_acc_i : in std_logic; --! variable 3 access
-- Signal from the receiver wf_rx_deserializer
nfip_status_r_fcser_p_i : in std_logic;
-- Signals from the central control unit WF_engine_control
var1_rdy_i : in std_logic; --! variable 1 ready
var2_rdy_i : in std_logic; --! variable 2 ready
var3_rdy_i : in std_logic; --! variable 3 ready
nfip_status_r_tler_i : in std_logic; --! wrong PDU_TYPE, Control or Length bytes received
rst_status_bytes_i : in std_logic; --! both status bytes are reinitialized
--! right after having been delivered
-- OUTPUTS
-- Output to WF_prod_bytes_to_tx
nFIP_status_byte_o : out std_logic_vector (7 downto 0); --! status byte
mps_status_byte_o : out std_logic_vector (7 downto 0) --! mps byte
-- nanoFIP User Interface, NON-WISHBONE outputs
u_cacer_o : out std_logic; --! nanoFIP status byte, bit 2
u_pacer_o : out std_logic; --! nanoFIP status byte, bit 3
r_tler_o : out std_logic; --! nanoFIP status byte, bit 4
r_fcser_o : out std_logic; --! nanoFIP status byte, bit 5
-- Signal to the wf_prod_bytes_retriever
nFIP_status_byte_o : out std_logic_vector (7 downto 0); --! nanoFIP status byte
mps_status_byte_o : out std_logic_vector (7 downto 0) --! MPS status byte
);
end entity WF_status_bytes_gen;
......@@ -114,9 +130,11 @@ end entity WF_status_bytes_gen;
--=================================================================================================
architecture rtl of WF_status_bytes_gen is
signal s_refreshment, s_VAR1_RDY_incr_c, s_VAR1_RDY_extended : std_logic;
signal s_VAR2_RDY_incr_c, s_VAR2_RDY_extended, s_VAR3_RDY_incr_c, s_VAR3_RDY_extended : std_logic;
signal s_VAR1_RDY_c, s_VAR2_RDY_c, s_VAR3_RDY_c : unsigned (3 downto 0);
signal s_refreshment : std_logic;
signal s_nFIP_status_byte : std_logic_vector (7 downto 0);
--signal s_var1_rdy_incr_c, s_var1_rdy_extended : std_logic;
--signal s_var2_rdy_incr_c, s_var2_rdy_extended, s_var3_rdy_incr_c, s_var3_rdy_extended : std_logic;
--signal s_var1_rdy_c, s_var2_rdy_c, s_var3_rdy_c : unsigned (3 downto 0);
--=================================================================================================
......@@ -124,128 +142,173 @@ signal s_VAR1_RDY_c, s_VAR2_RDY_c, s_VAR3_RDY_c : unsi
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
--! @brief Synchronous process Status_byte_Formation: Formation of the nanoFIP status byte
--! according to the definitions in Table 8 of specs.
nFIP_status_byte_generation: process(uclk_i)
nFIP_status_byte_generation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if rising_edge (uclk_i) then
if ((nFIP_urst_i = '1') or (rst_status_bytes_i = '1')) then -- bytes reinitialized
nFIP_status_byte_o <= (others => '0'); -- after having been delivered
if (nfip_urst_i = '1') then
s_nFIP_status_byte <= (others => '0');
else
if ((s_VAR1_RDY_extended = '0' and var1_acc_i = '1') or -- since the last time the status
(s_VAR2_RDY_extended = '0' and var2_acc_i = '1')) then -- byte was delivered,
nFIP_status_byte_o(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cosmd
end if; -- variable when it was not ready
if (s_VAR3_RDY_extended = '0' and var3_acc_i = '1') then -- since the last time the status
nFIP_status_byte_o(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
end if; -- the user logic accessed a prod
-- variable when it was not ready
if ((var_i = var_1 or var_i = var_2) and (crc_wrong_p_i = '1')) then -------------------------------------------------------------
nFIP_status_byte_o(c_R_BNER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
end if; -- a consumed var arrived for
-- this station with a manch. code
-- violation (on the RP_DAT.Data)
if ((var_i = var_1 or var_i = var_2)and(crc_wrong_p_i = '1')) then
nFIP_status_byte_o(c_R_FCSER_INDEX) <= '1'; -- since the last time the status
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reinitialisation after the transmission of a produced variable
if (rst_status_bytes_i = '1') then -- bits 0 to 5 reinitialised
s_nFIP_status_byte(5 downto 0) <= (others => '0'); -- after having been delivered
-- bits 6 and 7 are only reset
-- when nanoFIP is reset
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_cacer
if ((var1_rdy_i = '0' and var1_acc_i = '1') or
(var2_rdy_i = '0' and var2_acc_i = '1')) then -- since the last time the status
-- byte was delivered,
end if; -- a consumed var with a wrong CRC
-- arrived for this station
if (fd_wdgn_i = '0') then -- since the last time the status
nFIP_status_byte_o(c_T_TXER_INDEX) <= '1'; -- byte was delivered,
end if; -- there has been a signal for
-- a FIELDRIVE transmission error
if (fd_txer_i = '1') then -- since the last time the status
nFIP_status_byte_o(c_T_WDER_INDEX) <= '1'; -- byte was delivered,
end if; -- there has been a signal for a
-- FIELDRIVE watchdog timer problem
s_nFIP_status_byte(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cons.
-- var. when it was not ready
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_pacer
if (VAR3_RDY_i = '0' and var3_acc_i = '1') then
-- since the last time the status
s_nFIP_status_byte(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
-- the user logic accessed a prod.
-- var. when it was not ready
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_txer
if (fd_wdgn_i = '0') then -- FIELDRIVE transmission error
s_nFIP_status_byte(c_T_TXER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_wder
if (fd_txer_i = '1') then -- FIELDRIVE watchdog timer problem
s_nFIP_status_byte(c_T_WDER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
s_nFIP_status_byte(c_R_TLER_INDEX) <= nfip_status_r_tler_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
s_nFIP_status_byte(c_R_FCSER_INDEX) <= nfip_status_r_fcser_p_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
-- if ((var_i = var_1 or var_i = var_2) and (nfip_status_r_tler_i = '1')) then
-- s_nFIP_status_byte(c_R_TLER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
-- a cons. var. arrived for this
-- station with wrong PDU_TYPE,
-- Control or Length bytes
-- end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
-- if ((var_i = var_1 or var_i = var_2) and (nfip_status_r_fcser_p_i = '1')) then
-- s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
-- a cons. var. with a wrong
-- CRC arrived for this station
-- end if;
end if;
end if;
end if;
end process;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
--! @brief Concurrent signal assignments
nFIP_status_byte_o <= s_nFIP_status_byte;
u_cacer_o <= s_nFIP_status_byte(c_U_CACER_INDEX);
u_pacer_o <= s_nFIP_status_byte(c_U_PACER_INDEX);
r_tler_o <= s_nFIP_status_byte(c_R_TLER_INDEX);
r_fcser_o <= s_nFIP_status_byte(c_R_FCSER_INDEX);
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process
Extend_VAR1_RDY: WF_incr_counter
generic map (counter_length => 4)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
reinit_counter_i => VAR1_RDY_i,
incr_counter_i => s_VAR1_RDY_incr_c,
counter_o => s_VAR1_RDY_c,
counter_is_full_o => open);
s_VAR1_RDY_incr_c <= '1' when s_VAR1_RDY_c < "1111"
else '0';
s_VAR1_RDY_extended <= '1' when VAR1_RDY_i= '1' or s_VAR1_RDY_incr_c = '1'
else '0';
---------------------------------------------------------------------------------------------------
Extend_VAR2_RDY: WF_incr_counter
generic map (counter_length => 4)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
reinit_counter_i => VAR2_RDY_i,
incr_counter_i => s_VAR2_RDY_incr_c,
counter_o => s_VAR2_RDY_c,
counter_is_full_o => open);
-- Extend_VAR1_RDY: WF_incr_counter
-- generic map (g_counter_lgth => 4)
-- port map(
-- uclk_i => uclk_i,
-- nfip_urst_i => nfip_urst_i,
-- reinit_counter_i => var1_rdy_i,
-- incr_counter_i => s_var1_rdy_incr_c,
-- counter_o => s_var1_rdy_c,
-- counter_is_full_o => open);
-- s_var1_rdy_incr_c <= '1' when s_var1_rdy_c < "1111"
-- else '0';
-- s_var1_rdy_extended <= '1' when var1_rdy_i= '1' or s_var1_rdy_incr_c = '1'
-- else '0';
-------------------------------------------------------------------------------------------------
-- Extend_VAR2_RDY: WF_incr_counter
-- generic map (g_counter_lgth => 4)
-- port map(
-- uclk_i => uclk_i,
-- nfip_urst_i => nfip_urst_i,
-- reinit_counter_i => var2_rdy_i,
-- incr_counter_i => s_var2_rdy_incr_c,
-- counter_o => s_var2_rdy_c,
-- counter_is_full_o => open);
-- s_var2_rdy_incr_c <= '1' when s_var1_rdy_c < "1111"
-- else '0';
-- s_var2_rdy_extended <= '1' when var2_rdy_i= '1' or s_var2_rdy_incr_c = '1'
-- else '0';
-------------------------------------------------------------------------------------------------
-- Extend_VAR3_RDY: WF_incr_counter
-- generic map (g_counter_lgth => 4)
-- port map(
-- uclk_i => uclk_i,
-- nfip_urst_i => nfip_urst_i,
-- reinit_counter_i => VAR3_RDY_i,
-- incr_counter_i => s_var3_rdy_incr_c,
-- counter_o => s_var3_rdy_c,
-- counter_is_full_o => open);
-- s_var3_rdy_incr_c <= '1' when s_var3_rdy_c < "1111"
-- else '0';
-- s_var3_rdy_extended <= '1' when VAR3_RDY_i= '1' or s_var3_rdy_incr_c = '1'
-- else '0';
s_VAR2_RDY_incr_c <= '1' when s_VAR1_RDY_c < "1111"
else '0';
s_VAR2_RDY_extended <= '1' when VAR2_RDY_i= '1' or s_VAR2_RDY_incr_c = '1'
else '0';
---------------------------------------------------------------------------------------------------
Extend_VAR3_RDY: WF_incr_counter
generic map (counter_length => 4)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
reinit_counter_i => VAR3_RDY_i,
incr_counter_i => s_VAR3_RDY_incr_c,
counter_o => s_VAR3_RDY_c,
counter_is_full_o => open);
s_VAR3_RDY_incr_c <= '1' when s_VAR3_RDY_c < "1111"
else '0';
s_VAR3_RDY_extended <= '1' when VAR3_RDY_i= '1' or s_VAR3_RDY_incr_c = '1'
else '0';
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Refreshment_bit_Formation: Formation of the refreshment bit (used in
--! the mps status byte). It is set to 1 if the user has updated the produced variable (var3_access
--! has been asserted since the last time a variable was produced).
--!@brief Synchronous process Refreshment_bit_Creation: Creation of the refreshment bit (used in
--! the MPS status byte). The bit is set to 1 if the user has updated the produced variable since
--! its last transmission. The process is checking if the signal var3_access has been asserted
--! since the last production of a variable.
refreshment_bit_formation: process(uclk_i)
Refreshment_bit_Creation: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' or rst_status_bytes_i = '1' then -- the bit is reinitialized
s_refreshment <= '0'; -- after having been delivered
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_refreshment <= '0';
else
if (var3_acc_i = '1') then -- indication that the memory has been accessed
if rst_status_bytes_i = '1' then -- the bit is reinitialized
s_refreshment <= '0';
elsif (var3_acc_i = '1') then -- indication that the memory has been accessed
s_refreshment <= '1';
end if;
......@@ -254,10 +317,10 @@ end process;
end process;
---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process MPS_byte_Formation: Formation of the MPS byte according to the
--!@brief Combinatorial process MPS_byte_Creation: Creation of the MPS byte according to the
--! definitions in the Table 2 of the specs.
MPS_byte_formation: process (slone_i, s_refreshment)
MPS_byte_Creation: process (slone_i, s_refreshment)
begin
if slone_i='1' then
......
wf_tx_rx.vhd deleted 100644 → 0
View file @ 24c51736
---------------------------------------------------------------------------------------------------
--! @file WF_tx_rx.vhd
---------------------------------------------------------------------------------------------------
--! standard library
library IEEE;
--! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx_rx --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: WF_tx_rx
--
--! @brief Serializes and deserializes the WorldFIP data.
--!
--! Used in the NanoFIP design. \n
--! On reception it depacketises the data and only presents the actual data
--! contents. It also verifies the FCS (Frame Checksum, CRC).\n
--! On transmission it packetises the data and adds the FCS.
--! The unit WF_rx_tx_osc recovers the carrier clock during
--!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--
--! @date 07/07/2009
--
--! @version v0.01
--
--! @details
--!
--! <b>Dependencies:</b>\n
--! WF_engine \n
--! tx_engine \n
--! clk_gen \n
--! WF_reset_unit \n
--! consumed_ram \n
--!
--!
--! <b>References:</b>\n
--!
--!
--!
--! <b>Modified by:</b>\n
--! Author: Pablo Alvarez Sanchez
---------------------------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/07/2009 v0.01 PAAS First version \n
--!
---------------------------------------------------------------------------------------------------
--! @todo Define I/O signals \n
--!
---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for WF_tx_rx
--=================================================================================================
entity WF_tx_rx is
port (
uclk_i : in std_logic; --! User Clock
nFIP_urst_i : in std_logic;
rst_rx_unit_p_i : in std_logic;
start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0);
last_byte_p_i : in std_logic;
fd_rxd : in std_logic;
fd_rxd_edge_i : in std_logic;
fd_rxd_r_edge_i : in std_logic;
fd_rxd_f_edge_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
request_byte_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
d_clk_o : out std_logic;
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector (7 downto 0);
FSS_received_p_o : out std_logic;
CRC_wrong_p_o : out std_logic;
FSS_CRC_FES_viol_ok_p_o : out std_logic
);
end entity WF_tx_rx;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_tx_rx is
signal s_d_filtered, s_first_fe : std_logic;
signal s_rx_data_filtered_f_edge_p : std_logic;
signal s_rx_bit_clk_p, s_rx_manch_clk_p : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_signif_edge_window, s_adjac_bits_window : std_logic;
signal s_clk_fixed_carrier_p_d : std_logic_vector (C_TXCLKBUFFLENTGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
tx: WF_tx
generic map(C_TXCLKBUFFLENTGTH => C_TXCLKBUFFLENTGTH)
PORT MAP(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
start_produce_p_i => start_produce_p_i,
byte_ready_p_i => byte_ready_p_i,
byte_i => byte_i,
last_byte_p_i => last_byte_p_i,
tx_clk_p_buff_i => s_clk_fixed_carrier_p_d,
tx_data_o => tx_data_o,
request_byte_p_o => request_byte_p_o,
tx_enable_o => tx_enable_o
);
---------------------------------------------------------------------------------------------------
rx: WF_rx
PORT MAP(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
rst_rx_unit_p_i => rst_rx_unit_p_i,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
rxd_f_edge_i => fd_rxd_f_edge_i,
rxd_r_edge_i => fd_rxd_r_edge_i,
rxd_filtered_o => s_d_filtered,
rxd_filtered_f_edge_p_i => s_rx_data_filtered_f_edge_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
byte_ready_p_o => byte_ready_p_o,
byte_o => byte_o,
FSS_CRC_FES_viol_ok_p_o => FSS_CRC_FES_viol_ok_p_o,
rst_rx_osc_o => s_first_fe,
FSS_received_p_o => FSS_received_p_o,
CRC_wrong_p_o => CRC_wrong_p_o
);
---------------------------------------------------------------------------------------------------
rx_tx_osc :WF_rx_tx_osc
generic map(C_PERIODS_COUNTER_LENGTH => 11,
C_QUARTZ_PERIOD => 24.8,
C_TXCLKBUFFLENTGTH => 4)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
rxd_edge_i => fd_rxd_edge_i,
rxd_f_edge_i => fd_rxd_f_edge_i,
rst_rx_osc_i => s_first_fe,
rate_i => rate_i,
tx_clk_p_buff_o => s_clk_fixed_carrier_p_d,
tx_clk_o => d_clk_o,
rx_manch_clk_p_o => s_rx_manch_clk_p,
rx_bit_clk_p_o => s_rx_bit_clk_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window
);
---------------------------------------------------------------------------------------------------
deglitcher : WF_rx_deglitcher
generic map (C_ACULENGTH => 10)
Port map( uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
rxd_i => fd_rxd,
sample_bit_p_i => s_rx_bit_clk_p,
sample_manch_bit_p_i => s_rx_manch_clk_p,
rxd_filtered_o => s_d_filtered,
rxd_filtered_f_edge_p_o => s_rx_data_filtered_f_edge_p,
sample_manch_bit_p_o => s_sample_manch_bit_p,
sample_bit_p_o => s_sample_bit_p
);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
wf_tx.vhd → wf_tx_serializer.vhd
View file @ c0ef0386
---------------------------------------------------------------------------------------------------
--! @file WF_tx.vhd
--! @file wf_tx_serializer.vhd
---------------------------------------------------------------------------------------------------
--! standard library
......@@ -10,17 +10,17 @@ use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
use work.WF_PACKAGE.all; --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx --
-- wf_tx_serializer --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name: WF_tx
-- unit name: wf_tx_serializer
--
--
--! @brief Serializes the WorldFIP data.
......@@ -55,7 +55,8 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n\n<b>Last changes:</b>\n
--! -> v0.02 PAS Entity Ports added, start of architecture content
--! -> v0.03 EG timing changes; tx_clk_p_buff_i got 1 more bit
--! briefly byte_index_i needed to arrive 1 clock tick earlier
--! briefly byte_index_i needed to arrive 1 clock tick earlier
--! renamed from tx to tx_serializer
--
---------------------------------------------------------------------------------------------------
--
......@@ -67,18 +68,18 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--=================================================================================================
--! Entity declaration for WF_tx_rx
--=================================================================================================
entity WF_tx is
generic(C_TXCLKBUFFLENTGTH: natural);
entity wf_tx_serializer is
generic (c_TX_CLK_BUFF_LGTH: natural);
port (
-- INPUTS
-- User Interface general signals (synchronized)
-- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
nfip_urst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_engine_control
start_produce_p_i : in std_logic; --! indication that WF_engine_control is in prod_watchdog state
start_prod_p_i : in std_logic; --! indication that WF_engine_control is in prod_watchdog state
-- a correct ID_DAT asking for a produced var has been
-- received and ............
......@@ -86,32 +87,32 @@ entity WF_tx is
last_byte_p_i : in std_logic; --! indication that it is the last byte of data
-- CRC bytes follow
-- Signals from the WF_prod_bytes_to_tx
-- Signals from the wf_prod_bytes_retriever
byte_i : in std_logic_vector (7 downto 0);
--! data byte to be delivered
-- Signal from the WF_rx_tx_osc
tx_clk_p_buff_i : in std_logic_vector (C_TXCLKBUFFLENTGTH-1 downto 0);
tx_clk_p_buff_i : in std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
--! clk for transmission synchronization
-- OUTPUTS
-- Signal to WF_engine_control
-- Signal to the WF_engine_control
request_byte_p_o : out std_logic;
-- nanoFIP output signals
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; --! transmitter serial data
tx_enable_o : out std_logic --! transmitter enable
);
end entity WF_tx;
end entity wf_tx_serializer;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture rtl of WF_tx is
architecture rtl of wf_tx_serializer is
type tx_state_t is (idle, send_fss, send_data_byte, send_crc_bytes, send_queue, stop_transmission);
......@@ -137,7 +138,7 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Transmitter's state machine: the state machine is divided in three parts (a clocked
--!@brief Serializer's state machine: the state machine is divided in three parts (a clocked
--! process to store the current state, a combinatorial process to manage state transitions and
--! finally a combinatorial process to manage the output signals), which are the 3 processes that
--! follow.
......@@ -160,7 +161,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "idle state": signals initializations
-- jump to "send_fss" state after a pulse on the signal start_produce_p_i (controlled by the
-- jump to "send_fss" state after a pulse on the signal start_prod_p_i (controlled by the
-- WF_engine_control)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -176,7 +177,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_data_byte" state: delivery of manchester encoded bits of data that arrive from the
-- WF_prod_bytes_to_tx unit (byte_i), with the coordination of the WF_engine_control (byte_ready_p_i)
-- wf_prod_bytes_retriever unit (byte_i), with the coordination of the WF_engine_control (byte_ready_p_i)
-- request of a new byte on tx_clk_p_buff (0) assertion (with s_bit_index = 0)
-- bit delivery after tx_clk_p_buff (1) assertion
-- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1))
......@@ -184,8 +185,8 @@ begin
-- (between 0 and 16 for each byte, until the
-- last_byte_p_i gives a pulse)
-- the first data byte from the WF_prod_bytes_to_tx unit is already available after the assertion of the
-- start_produce_p_i signal; for the rest, there is a request of a new byte when the s_bit_index
-- the first data byte from the wf_prod_bytes_retriever unit is already available after the assertion of the
-- start_prod_p_i signal; for the rest, there is a request of a new byte when the s_bit_index
-- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal
-- triggers the WF_control_engine to send a new address to the memory of the produced_vars unit (new
-- address available on tx_clk_p_buff (1)), which in turn will give an output one uclk cycle later
......@@ -214,10 +215,10 @@ begin
--!@brief synchronous process Receiver_FSM_Sync:
Transmitter_FSM_Sync: process(uclk_i)
Transmitter_FSM_Sync: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
tx_state <= idle;
else
tx_state <= nx_tx_state;
......@@ -230,21 +231,21 @@ begin
--! definition of the state transitions of the FSM
Transmitter_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
start_produce_p_i, tx_clk_p_buff_i)
start_prod_p_i, tx_clk_p_buff_i)
begin
nx_tx_state <= idle;
case tx_state is
when idle =>
if start_produce_p_i = '1' then
if start_prod_p_i = '1' then
nx_tx_state <= send_fss;
else
nx_tx_state <= idle;
end if;
when send_fss =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1) = '1' then
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1) = '1' then
nx_tx_state <= send_data_byte;
else
nx_tx_state <= send_fss;
......@@ -258,21 +259,21 @@ begin
end if;
when send_crc_bytes =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-2) = '1' then
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= send_queue;
else
nx_tx_state <= send_crc_bytes;
end if;
when send_queue =>
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-2) = '1' then
if s_bit_index_is_zero = '1' and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= stop_transmission;
else
nx_tx_state <= send_queue;
end if;
when stop_transmission =>
if tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-2) = '1' then
if tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-2) = '1' then
nx_tx_state <= idle;
else
nx_tx_state <= stop_transmission;
......@@ -404,19 +405,19 @@ crc_bytes_manc_encoder: WF_manch_encoder
c_GENERATOR_POLY_length => 16)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
start_CRC_p_i => s_start_crc_p,
nfip_urst_i => nfip_urst_i,
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_data_bit_to_crc_p,
data_bit_i => s_txd,
CRC_o => s_crc_bytes,
CRC_ok_p => open);
crc_o => s_crc_bytes,
crc_ok_p => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- concurrent signals assignement for the crc_generator inputs
s_start_crc_p <= s_sending_FSS and s_bit_index_is_zero and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_start_crc_p <= s_sending_FSS and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
-- the CRC calculation starts when at the end of the FSS (beginning of data bytes delivery)
s_data_bit_to_crc_p <= s_sending_data and s_bit_index(0) and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_data_bit_to_crc_p <= s_sending_data and s_bit_index(0) and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
-- only the 1st part of a manchester encoded bit goes to the CRC calculator
......@@ -427,10 +428,10 @@ crc_bytes_manc_encoder: WF_manch_encoder
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a bits counter:
Outgoing_Bits_Index: WF_decr_counter
generic map(counter_length => 5)
generic map(g_counter_lgth => 5)
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
nfip_urst_i => nfip_urst_i,
counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_index_p,
......@@ -453,23 +454,23 @@ crc_bytes_manc_encoder: WF_manch_encoder
elsif s_sending_FSS = '1' then
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_data = '1' then
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_crc = '1' then
s_bit_index_top <= to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
elsif s_sending_QUEUE = '1' then
s_bit_index_top <= to_unsigned (FRAME_END'length - 1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-1);
s_bit_index_top <= to_unsigned (FES'length - 1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
s_decr_index_p <= tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-1);
else
s_bit_index_top <= to_unsigned (FSS'length - 1, s_bit_index'length);
......@@ -486,24 +487,24 @@ crc_bytes_manc_encoder: WF_manch_encoder
bits_to_txd: WF_bits_to_txd
port map(
uclk_i => uclk_i,
nFIP_urst_i => nFIP_urst_i,
nfip_urst_i => nfip_urst_i,
txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch,
sending_FSS_i => s_sending_FSS,
sending_fss_i => s_sending_FSS,
sending_data_i => s_sending_data,
sending_crc_i => s_sending_crc,
sending_QUEUE_i => s_sending_queue,
sending_fes_i => s_sending_queue,
stop_transmission_i => s_stop_transmission,
tx_clk_p_buff_i => tx_clk_p_buff_i,
tx_clk_p_i => tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-3),
txd_o => s_txd,
tx_enable_o => tx_enable_o);
--------------------------------------------------------------------------------------------------
Input_Byte_Sampling: process(uclk_i)
Input_Byte_Sampling: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
if rising_edge (uclk_i) then
if nfip_urst_i = '1' then
s_byte <= (others => '0');
else
......@@ -520,8 +521,8 @@ Input_Byte_Sampling: process(uclk_i)
---------------------------------------------------------------------------------------------------
tx_data_o <= s_txd;
request_byte_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(C_TXCLKBUFFLENTGTH-4);
-- request for a new byte from the WF_prod_bytes_to_tx unit (passing from WF_engine_control)
request_byte_p_o <= s_sending_data and s_bit_index_is_zero and tx_clk_p_buff_i(c_TX_CLK_BUFF_LGTH-4);
-- request for a new byte from the wf_prod_bytes_retriever unit (passing from WF_engine_control)
end architecture rtl;
......
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