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nanoFIP - Gateware
Commit cdabc78f authored by egousiou's avatar egousiou
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inputs cyc and fd_rxa deleted from pinlist and design 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@59 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 02c4dba5
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NanoFip.pdc
View file @ cdabc78f
......@@ -105,10 +105,10 @@ set_io {c_id_i[3]} \
-DIRECTION Input
set_io cyc_i \
-pinname 75 \
-fixed yes \
-DIRECTION Input
#set_io cyc_i \
# -pinname 75 \
# -fixed yes \
# -DIRECTION Input
set_io {dat_i[0]} \
......@@ -333,10 +333,10 @@ set_io fd_wdgn_i \
-DIRECTION Input
set_io fx_rxa_i \
-pinname 121 \
-fixed yes \
-DIRECTION Input
#set_io fx_rxa_i \
# -pinname 121 \
# -fixed yes \
# -DIRECTION Inout
set_io fx_rxd_i \
......@@ -560,98 +560,3 @@ set_io we_i \
# Non IO constraints
#
#
# Old IO constraints, commented out for reference
#
# set_io ack_o -pinname 77 -fixed yes -DIRECTION Output
# set_io {adr_i[0]} -pinname 3 -fixed yes -DIRECTION Input
# set_io {adr_i[1]} -pinname 4 -fixed yes -DIRECTION Input
# set_io {adr_i[2]} -pinname 5 -fixed yes -DIRECTION Input
# set_io {adr_i[3]} -pinname 6 -fixed yes -DIRECTION Input
# set_io {adr_i[4]} -pinname 7 -fixed yes -DIRECTION Input
# set_io {adr_i[5]} -pinname 8 -fixed yes -DIRECTION Input
# set_io {adr_i[6]} -pinname 10 -fixed yes -DIRECTION Input
# set_io {adr_i[7]} -pinname 11 -fixed yes -DIRECTION Input
# set_io {adr_i[8]} -pinname 12 -fixed yes -DIRECTION Input
# set_io {adr_i[9]} -pinname 13 -fixed yes -DIRECTION Input
# set_io {c_id_i[0]} -pinname 179 -fixed yes -DIRECTION Input
# set_io {c_id_i[1]} -pinname 180 -fixed yes -DIRECTION Input
# set_io {c_id_i[2]} -pinname 181 -fixed yes -DIRECTION Input
# set_io {c_id_i[3]} -pinname 182 -fixed yes -DIRECTION Input
# set_io cyc_i -pinname 75 -fixed yes -DIRECTION Input
# set_io {dat_i[0]} -pinname 205 -fixed yes -DIRECTION Input
# set_io {dat_i[1]} -pinname 204 -fixed yes -DIRECTION Input
# set_io {dat_i[2]} -pinname 203 -fixed yes -DIRECTION Input
# set_io {dat_i[3]} -pinname 202 -fixed yes -DIRECTION Input
# set_io {dat_i[4]} -pinname 201 -fixed yes -DIRECTION Input
# set_io {dat_i[5]} -pinname 199 -fixed yes -DIRECTION Input
# set_io {dat_i[6]} -pinname 198 -fixed yes -DIRECTION Input
# set_io {dat_i[7]} -pinname 197 -fixed yes -DIRECTION Input
# set_io {dat_i[8]} -pinname 196 -fixed yes -DIRECTION Input
# set_io {dat_i[9]} -pinname 194 -fixed yes -DIRECTION Input
# set_io {dat_i[10]} -pinname 193 -fixed yes -DIRECTION Input
# set_io {dat_i[11]} -pinname 192 -fixed yes -DIRECTION Input
# set_io {dat_i[12]} -pinname 191 -fixed yes -DIRECTION Input
# set_io {dat_i[13]} -pinname 190 -fixed yes -DIRECTION Input
# set_io {dat_i[14]} -pinname 189 -fixed yes -DIRECTION Input
# set_io {dat_i[15]} -pinname 188 -fixed yes -DIRECTION Input
# set_io {dat_o[0]} -pinname 48 -fixed yes -DIRECTION Output
# set_io {dat_o[1]} -pinname 49 -fixed yes -DIRECTION Output
# set_io {dat_o[2]} -pinname 55 -fixed yes -DIRECTION Output
# set_io {dat_o[3]} -pinname 56 -fixed yes -DIRECTION Output
# set_io {dat_o[4]} -pinname 57 -fixed yes -DIRECTION Output
# set_io {dat_o[5]} -pinname 58 -fixed yes -DIRECTION Output
# set_io {dat_o[6]} -pinname 59 -fixed yes -DIRECTION Output
# set_io {dat_o[7]} -pinname 60 -fixed yes -DIRECTION Output
# set_io {dat_o[8]} -pinname 61 -fixed yes -DIRECTION Output
# set_io {dat_o[9]} -pinname 63 -fixed yes -DIRECTION Output
# set_io {dat_o[10]} -pinname 64 -fixed yes -DIRECTION Output
# set_io {dat_o[11]} -pinname 66 -fixed yes -DIRECTION Output
# set_io {dat_o[12]} -pinname 68 -fixed yes -DIRECTION Output
# set_io {dat_o[13]} -pinname 69 -fixed yes -DIRECTION Output
# set_io {dat_o[14]} -pinname 70 -fixed yes -DIRECTION Output
# set_io {dat_o[15]} -pinname 73 -fixed yes -DIRECTION Output
# set_io fd_rstn_o -pinname 118 -fixed yes -DIRECTION Output
# set_io fd_txck_o -pinname 129 -fixed yes -DIRECTION Output
# set_io fd_txena_o -pinname 119 -fixed yes -DIRECTION Output
# set_io fd_txer_i -pinname 128 -fixed yes -DIRECTION Input
# set_io fd_wdgn_i -pinname 120 -fixed yes -DIRECTION Input
# set_io fx_rxa_i -pinname 121 -fixed yes -DIRECTION Input
# set_io fx_rxd_i -pinname 127 -fixed yes -DIRECTION Input
# set_io fx_txd_o -pinname 131 -fixed yes -DIRECTION Output
# set_io {m_id_i[0]} -pinname 172 -fixed yes -DIRECTION Input
# set_io {m_id_i[1]} -pinname 173 -fixed yes -DIRECTION Input
# set_io {m_id_i[2]} -pinname 174 -fixed yes -DIRECTION Input
# set_io {m_id_i[3]} -pinname 175 -fixed yes -DIRECTION Input
# set_io nostat_i -pinname 185 -fixed yes -DIRECTION Input
# set_io {p3_lgth_i[0]} -pinname 166 -fixed yes -DIRECTION Input
# set_io {p3_lgth_i[1]} -pinname 167 -fixed yes -DIRECTION Input
# set_io {p3_lgth_i[2]} -pinname 168 -fixed yes -DIRECTION Input
# set_io {rate_i[0]} -pinname 111 -fixed yes -DIRECTION Input
# set_io {rate_i[1]} -pinname 112 -fixed yes -DIRECTION Input
# set_io rst_i -pinname 92 -fixed yes -DIRECTION Input
# set_io rstin_i -pinname 93 -fixed yes -DIRECTION Input
# set_io rston_o -pinname 94 -fixed yes -DIRECTION Output
# set_io {s_id_o[0]} -pinname 176 -fixed yes -DIRECTION Output
# set_io {s_id_o[1]} -pinname 177 -fixed yes -DIRECTION Output
# set_io slone_i -pinname 184 -fixed yes -DIRECTION Input
# set_io stb_i -pinname 76 -fixed yes -DIRECTION Input
# set_io {subs_i[0]} -pinname 149 -fixed yes -DIRECTION Input
# set_io {subs_i[1]} -pinname 150 -fixed yes -DIRECTION Input
# set_io {subs_i[2]} -pinname 151 -fixed yes -DIRECTION Input
# set_io {subs_i[3]} -pinname 152 -fixed yes -DIRECTION Input
# set_io {subs_i[4]} -pinname 153 -fixed yes -DIRECTION Input
# set_io {subs_i[5]} -pinname 158 -fixed yes -DIRECTION Input
# set_io {subs_i[6]} -pinname 159 -fixed yes -DIRECTION Input
# set_io {subs_i[7]} -pinname 160 -fixed yes -DIRECTION Input
# set_io uclk_i -pinname 136 -fixed yes -DIRECTION Input
# set_io var1_acc_i -pinname 82 -fixed yes -DIRECTION Input
# set_io var1_rdy_o -pinname 83 -fixed yes -DIRECTION Output
# set_io var2_acc_i -pinname 84 -fixed yes -DIRECTION Input
# set_io var2_rdy_o -pinname 86 -fixed yes -DIRECTION Output
# set_io var3_acc_i -pinname 87 -fixed yes -DIRECTION Input
# set_io var3_rdy_o -pinname 90 -fixed yes -DIRECTION Output
# set_io wclk_i -pinname 28 -fixed yes -DIRECTION Input
# set_io we_i -pinname 74 -fixed yes -DIRECTION Input
dpblockram_clka_rd_clkb_wr.vhd deleted 100644 → 0
View file @ 02c4dba5
-------------------------------------------------------------------------------
--! @file dpblockram.vhd
-------------------------------------------------------------------------------
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- --
-- CERN, BE --
-- --
-------------------------------------------------------------------------------
--
-- unit name: dpblockram.vhd
--
--! @brief The dpblockram implements a template for a true dual port ram clocked on both ports by the same clock.
--!
--! @author <Pablo Alvarez(pablo.alvarez.sanchez@cern.ch)>
--
--! @date 24\01\2009
--
--! @version 1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--!
--!
--! <b>References:</b>\n
--! <reference one> \n
--! <reference two>
--!
--! <b>Modified by:</b>\n
--! Author: <name>
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 24\01\2009 paas header included\n
--! <extended description>
-------------------------------------------------------------------------------
--! @todo Adapt vhdl sintax to ohr standard\n
--! <another thing to do> \n
--
-------------------------------------------------------------------------------
entity dpblockram_clka_rd_clkb_wr is
generic (c_dl : integer := 42; -- Length of the data word
c_al : integer := 10); -- Number of words
-- 'nw' has to be coherent with 'c_al'
port (clka_i : in std_logic; -- Global Clock
aa_i : in std_logic_vector(c_al - 1 downto 0);
da_o : out std_logic_vector(c_dl -1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(c_al - 1 downto 0);
db_i : in std_logic_vector(c_dl - 1 downto 0);
web_i : in std_logic);
end dpblockram_clka_rd_clkb_wr;
--library synplify;
--use synplify.attributes.all;
architecture beh of dpblockram_clka_rd_clkb_wr is
type t_ram is array (2**c_al - 1 downto 0) of std_logic_vector (c_dl - 1 downto 0);
shared variable s_ram : t_ram := (others => (others => '0'));
--attribute syn_ramstyle : string;
--attribute syn_ramstyle of s_ram : variable is "block_ram";
--attribute syn_ramstyle of RAM : signal is "select_ram";
--attribute syn_ramstyle of RAM : signal is "area ";
begin
process (clkb_i)
begin
if (clkb_i'event and clkb_i = '1') then
if (web_i = '1') then
s_ram(to_integer(unsigned(ab_i))) := db_i;
end if;
end if;
end process;
process (clka_i)
begin
if (clka_i'event and clka_i = '1') then
da_o <= s_ram(to_integer(unsigned(aa_i)));
end if;
end process;
end beh;
\ No newline at end of file
dpblockram_clka_rd_clkb_wr_syn.vhd
View file @ cdabc78f
......@@ -111,19 +111,19 @@ memory_triplication: for I in 0 to 2 generate
UDualClkRam : DualClkRam
port map ( DINA => s_zeros,
ADDRA => addr_A_i,
RWA => one,
CLKA => clk_A_i,
ADDRA => addr_A_i,
RWA => one,
CLKA => clk_A_i,
DINB => data_B_i,
ADDRB => addr_B_i,
RWB => s_rwB,
CLKB => clk_B_i,
DINB => data_B_i,
ADDRB => addr_B_i,
RWB => s_rwB,
CLKB => clk_B_i,
RESETn => one,
RESETn => one,
DOUTA => data_o_A_array(I),
DOUTB => open) ;
DOUTA => data_o_A_array(I),
DOUTB => open) ;
end generate;
......
nanofip.vhd
View file @ cdabc78f
......@@ -147,7 +147,7 @@ entity nanofip is
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fx_txd_o : out std_logic; --! Transmitter data
fx_rxa_i : in std_logic; --! Reception activity detection
-- fx_rxa_i : inout std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
......@@ -225,7 +225,7 @@ entity nanofip is
rst_i : in std_logic; --! Wishbone reset. Does not reset other internal logic.
stb_i : in std_logic; --! Strobe
ack_o : out std_logic; --! Acknowledge
cyc_i : in std_logic;
-- cyc_i : inout std_logic;
we_i : in std_logic --! Write enable
);
......@@ -281,8 +281,7 @@ architecture struc of nanofip is
signal fss_decoded_p_from_rx : std_logic;
signal s_stat : std_logic_vector(7 downto 0);
signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_stat_sent_p, s_sending_stat: std_logic;
signal s_mps_sent_p: std_logic;
signal s_reset_status_bytes, s_sending_mps: std_logic;
signal s_code_violation_p : std_logic;
signal s_crc_bad_p : std_logic;
signal s_var1_rdy : std_logic;
......@@ -291,7 +290,7 @@ architecture struc of nanofip is
signal s_mps : std_logic_vector(7 downto 0);
signal s_wb_d_d : std_logic_vector(15 downto 0);
signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector(7 downto 0);
signal s_stb_d, s_we_d, s_fx_rxa : std_logic;
signal s_stb_d, s_we_d : std_logic;
signal s_adr_d : std_logic_vector ( 9 downto 0);
begin
......@@ -304,7 +303,8 @@ begin
rston_o => rston_o,
var_i => s_var_from_control,
rst_o => s_rst
rst_o => s_rst,
fd_rst_o => fd_rstn_o
);
---------------------------------------------------------------------------------------------------
......@@ -398,7 +398,7 @@ begin
slone_i => slone_i,
nostat_i => nostat_i,
subs_i => subs_i,
sending_stat_o => s_sending_stat,
sending_mps_o => s_sending_mps,
stat_i => s_stat,
mps_i => s_mps,
var_i => s_var_from_control,
......@@ -429,25 +429,13 @@ begin
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
stat_sent_p_i => s_stat_sent_p,
mps_sent_p_i => s_mps_sent_p,
reset_status_bytes_i => s_reset_status_bytes,
stat_o => s_stat,
mps_o => s_mps
);
---------------------------------------------------------------------------------------------------
ack_o <= (s_ack_produced or s_ack_consumed) and stb_i;
s_ack_o <= s_ack_produced or s_ack_consumed;
s_stat_sent_p <= s_sending_stat and s_byte_to_tx_ready_p;
s_mps_sent_p <= s_sending_stat and s_byte_to_tx_ready_p;
--fd_rstn_o <= cyc_i and fx_rxa_i;
--s_fx_rxa <= fx_rxa_i;
-- s_id_o <= "0" & fx_rxa_i; -- I connect fx_rxa_i to s_id_o just to test the pinout
fd_rstn_o <= fd_wdgn_i and cyc_i and fx_rxa_i; -- just to check place+route; as to be changed!!!!!!!
---------------------------------------------------------------------------------------------------
Uwf_dec_m_ids : wf_dec_m_ids
Uwf_dec_m_ids : wf_dec_m_ids
port map(
uclk_i => uclk_i,
rst_i => s_rst,
......@@ -477,6 +465,20 @@ begin
end if;
end process;
---------------------------------------------------------------------------------------------------
ack_o <= (s_ack_produced or s_ack_consumed) and stb_i;
s_ack_o <= s_ack_produced or s_ack_consumed;
s_reset_status_bytes <= s_sending_mps and s_byte_to_tx_ready_p;
-- fx_rxa_i <= 'Z';
-- cyc_i <= 'Z';
-- s_id_o <= "0" & fx_rxa_i; -- I connect fx_rxa_i to s_id_o just to test the pinout
---------------------------------------------------------------------------------------------------
end architecture struc;
--============================================================================
--============================================================================
......
reset_logic.vhd
View file @ cdabc78f
......@@ -59,22 +59,24 @@ use work.wf_package.all;
--! Entity declaration for reset_logic
--============================================================================
entity reset_logic is
generic(c_reset_length : integer := 4); --! Reset counter length. 4==> 16 uclk_i ticks
generic(c_reset_length : integer := 4); --! Reset counter length. 4==> 16 uclk_i ticks
port (
uclk_i : in std_logic; --! User Clock
port (
uclk_i : in std_logic; --! 40MHz clock
rstin_i : in std_logic; --! Initialisation control, active low
var_i : in t_var; --! Received variable
rstin_i : in std_logic; --! Initialisation control, active low
--! Reset output, active low. Active when the reset variable is received
--! and the second byte contains the station address.
rston_o : out std_logic; --! Reset output, active low
rston_o : out std_logic; --! Reset output, active low.
-- Active when the reset variable is received
-- and the second byte contains the station address.
var_i : in t_var; --! Received variable
rst_o : out std_logic --! Reset ouput active high
rst_o : out std_logic; --! Reset ouput active high
);
fd_rst_o : out std_logic --! fieldrive reset, active low
-- Active when the reset variable is received
-- and the first byte contains the station address.
);
end entity reset_logic;
-------------------------------------------------------------------------------
......@@ -83,35 +85,63 @@ end entity reset_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture rtl of reset_logic is
--attribute syn_radhardlevel : string;
--attribute syn_radhardlevel of rtl: architecture is "tmr";
signal s_rstin_d : std_logic_vector(1 downto 0);
signal s_rst_c : unsigned(4 downto 0);
signal s_reload_rst_c : std_logic;
begin
process(s_rstin_d,var_i)
begin
if (var_i = c_var_array(c_reset_var_pos).var) then
s_reload_rst_c <= '1';
else
s_reload_rst_c <= s_rstin_d(s_rstin_d'left);
end if;
end process;
process(uclk_i)
begin
if rising_edge(uclk_i) then
s_rstin_d <= s_rstin_d(0) & (not rstin_i);
if (s_reload_rst_c = '1') then
s_rst_c <= to_unsigned(0, s_rst_c'length);
elsif s_rst_c(s_rst_c'left) = '0' then
s_rst_c <= s_rst_c + 1;
signal s_rstin_buff : std_logic_vector(1 downto 0);
signal s_rst_c, s_rstin_c : unsigned(4 downto 0);
signal s_reload_rst_c, rst_o2, s_rstin_c_start, s_reset : std_logic;
begin
process(s_rstin_buff,var_i)
begin
if (var_i = c_var_array(c_reset_var_pos).var) then
s_reload_rst_c <= '1';
else
s_reload_rst_c <= s_rstin_buff(s_rstin_buff'left);
end if;
rst_o <= not s_rst_c(s_rst_c'left);
rston_o <= s_rst_c(s_rst_c'left);
end if;
end process;
process(uclk_i)
begin
if rising_edge(uclk_i) then
s_rstin_buff <= s_rstin_buff(0) & (not rstin_i);
if (s_reload_rst_c = '1') then
s_rst_c <= to_unsigned(0, s_rst_c'length);
elsif s_rst_c(s_rst_c'left) = '0' then
s_rst_c <= s_rst_c + 1;
end if;
rst_o <= not s_rst_c(s_rst_c'left);
rston_o <= s_rst_c(s_rst_c'left);
fd_rst_o <= s_rst_c(s_rst_c'left);
---------------------------------------------------------------------------------------------------
-- if (s_rstin_buff(0) = '1') and (s_rstin_buff(1) /= '1') then
-- s_rstin_c_start <= '1';
-- s_rstin_c <= to_unsigned(0, s_rstin_c'length);
-- end if;
-- if s_rstin_c_start = '1' then
-- if rstin_i = '0' then
-- s_rstin_c <= s_rstin_c+1;
-- end if;
-- end if;
-- if s_rstin_c(s_rstin_c'left) = '1' then
-- s_rstin_c_start <='0';
-- s_reset <= rstin_i;
-- else
-- s_reset <= '1';
-- end if;
-- rst_o2 <= not (s_reset);
end if;
end process;
......
status_gen.vhd
View file @ cdabc78f
......@@ -63,56 +63,25 @@ use work.wf_package.all;
entity status_gen is
port (
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
uclk_i : in std_logic; --! User Clock
rst_i : in std_logic;
-------------------------------------------------------------------------------
-- Connections to wf_tx_rx (WorldFIP received data)
-------------------------------------------------------------------------------
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
fd_wdgn_i : in std_logic; --! Watchdog on transmitter
fd_txer_i : in std_logic; --! Transmitter error
code_violation_p_i : in std_logic;
crc_bad_p_i : in std_logic;
-------------------------------------------------------------------------------
-- Connections to wf_engine
-------------------------------------------------------------------------------
--! Signals new data is received and can safely be read (Consumed
--! variable 05xyh). In stand-alone mode one may sample the data on the
--! first clock edge VAR1_RDY is high.
var1_rdy_i: in std_logic; --! Variable 1 ready
--! Signals new data is received and can safely be read (Consumed
--! broadcast variable 04xyh). In stand-alone mode one may sample the
--! data on the first clock edge VAR1_RDY is high.
var2_rdy_i: in std_logic; --! Variable 2 ready
--! Signals that the variable can safely be written (Produced variable
--! 06xyh). In stand-alone mode, data is sampled on the first clock after
--! VAR_RDY is deasserted.
var3_rdy_i: in std_logic; --! Variable 3 ready
var1_access_a_i: in std_logic; --! Variable 1 access
var2_access_a_i: in std_logic; --! Variable 2 access
var3_access_a_i: in std_logic; --! Variable 3 access
-- reset_var1_access_o : out std_logic; --! Reset Variable 1 access flag
-- reset_var2_access_o : out std_logic; --! Reset Variable 2 access flag
-- reset_var3_access_o : out std_logic; --! Reset Variable 2 access flag
stat_sent_p_i : in std_logic;
mps_sent_p_i : in std_logic;
stat_o : out std_logic_vector(7 downto 0);
mps_o : out std_logic_vector(7 downto 0)
-------------------------------------------------------------------------------
-- Connections to data_if
-------------------------------------------------------------------------------
code_violation_p_i : in std_logic;
crc_bad_p_i : in std_logic;
var1_rdy_i : in std_logic; --! Variable 1 ready
var2_rdy_i : in std_logic; --! Variable 2 ready
var3_rdy_i : in std_logic; --! Variable 3 ready
var1_access_a_i : in std_logic; --! Variable 1 access
var2_access_a_i : in std_logic; --! Variable 2 access
var3_access_a_i : in std_logic; --! Variable 3 access
reset_status_bytes_i : in std_logic;
stat_o : out std_logic_vector(7 downto 0);
mps_o : out std_logic_vector(7 downto 0)
);
......@@ -124,8 +93,7 @@ end entity status_gen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture rtl of status_gen is
--attribute syn_radhardlevel : string;
--attribute syn_radhardlevel of rtl: architecture is "tmr";
signal s_stat : std_logic_vector(7 downto 0);
signal s_refreshment : std_logic;
signal s_var1_access: std_logic_vector(1 downto 0); --! Variable 1 access
......@@ -135,65 +103,71 @@ signal s_var3_access: std_logic_vector(1 downto 0); --! Variable 3 access
begin
process(uclk_i)
begin
if rising_edge(uclk_i) then
s_var1_access(0) <= var1_access_a_i;
s_var2_access(0) <= var2_access_a_i;
s_var3_access(0) <= var3_access_a_i;
s_var1_access(1) <= s_var1_access(0);
s_var2_access(1) <= s_var2_access(0);
s_var3_access(1) <= s_var3_access(0);
end if;
end process;
process(uclk_i)
begin
if rising_edge(uclk_i) then
if rst_i = '1' or stat_sent_p_i = '1' then
s_stat <= (others => '0');
else
process(uclk_i)
begin
if rising_edge(uclk_i) then
s_var1_access(0) <= var1_access_a_i;
s_var2_access(0) <= var2_access_a_i;
s_var3_access(0) <= var3_access_a_i;
s_var1_access(1) <= s_var1_access(0);
s_var2_access(1) <= s_var2_access(0);
s_var3_access(1) <= s_var3_access(0);
end if;
end process;
process(uclk_i)
begin
if rising_edge(uclk_i) then
if rst_i = '1' or reset_status_bytes_i = '1' then
s_stat <= (others => '0');
else -- value of s_var1_access on the previous clock tick should be 0
if (var1_rdy_i = '0' and s_var1_access(1) = '1') or (var2_rdy_i = '0' and s_var2_access(1) = '1') then
s_stat(c_u_cacer_pos) <= '1';
end if;
if ((var3_rdy_i = '0') and (s_var3_access(1) = '1')) then
s_stat(c_u_pacer_pos) <= '1';
end if;
if code_violation_p_i = '1' then
s_stat(c_r_bner_pos) <= '1';
end if;
if crc_bad_p_i = '1' then
s_stat(c_r_fcser_pos) <= '1';
end if;
if fd_wdgn_i = '1' then
s_stat(c_t_txer_pos) <= '1';
end if;
if fd_txer_i = '1' then
s_stat(c_t_wder_pos) <= '1';
end if;
end if;
if rst_i = '1' or mps_sent_p_i = '1' then
if rst_i = '1' or reset_status_bytes_i = '1' then
s_refreshment <= '0';
else
if (var3_access_a_i = '1') then
s_refreshment <= '1';
end if;
end if;
-- reset_var1_access_o <= var1_access_a_i;
-- reset_var2_access_o <= var2_access_a_i;
-- reset_var3_access_o <= var3_access_a_i;
end if;
end process;
process(s_refreshment)
begin
mps_o <= (others => '0');
mps_o(c_refreshment_pos) <= s_refreshment;
mps_o(c_significance_pos) <= s_refreshment;
end process;
process(s_refreshment)
begin
mps_o <= (others => '0');
mps_o(c_refreshment_pos) <= s_refreshment;
mps_o(c_significance_pos) <= s_refreshment;
end process;
stat_o <= s_stat;
stat_o <= s_stat;
end architecture rtl;
-------------------------------------------------------------------------------
......
wf_crc.vhd
View file @ cdabc78f
......@@ -105,6 +105,7 @@ begin
if rising_edge(uclk_i) then
if rst_i = '1' then
s_q <= (others => '1');
else
if start_p_i = '1' then
s_q <= (others => '1');
......
wf_engine_control.vhd
View file @ cdabc78f
......@@ -66,7 +66,7 @@ use work.wf_package.all;
--! Entity declaration for wf_engine_control
--=================================================================================================
entity wf_engine_control is
generic( C_QUARTZ_PERIOD : real := 25.0);
generic( C_QUARTZ_PERIOD : real := 24.8);
port (
uclk_i : in std_logic; --! 40MHz clock
......@@ -265,7 +265,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief synchronous process Receiver_FSM_Sync: storage of the current state of the FSM
--!@brief synchronous process Central_Control_FSM_Comb_Output_Signals:
Central_Control_FSM_Comb_Output_Signals: process (control_st, frame_ok_p_i, s_bytes_c,
s_produce_or_consume, s_start_produce_p_d1,
......@@ -417,14 +417,15 @@ begin
end process;
---------------------------------------------------------------------------------------------------
--! The following two processes: id_dat_var_concurrent and ... manage the values of the signals
--! s_var_aux_concurr, s_var_aux and s_var. All of them are used to keep the value of the
--! The following two processes: id_dat_var_concurrent and id_dat_var_specific_moments manage the
--! signals s_var_aux_concurr, s_var_aux and s_var. All of them are used to keep the value of the
--! ID_DAT.Identifier.Variable byte of the incoming ID_DAT frame, but change their value on
--! different moments:
--! s_var_aux_concurr: is constantly following the incoming byte byte_i
--! s_var_aux: locks to the value of s_var_aux_concurr when the ID_DAT.Identifier.Variable byte
--! is received (s_load_temp_var = 1)
--! s_var: locks to the value of s_var_aux at the end of the id_dat frame (s_load_var = 1)
--! s_var: locks to the value of s_var_aux at the end of the id_dat frame (s_load_var = 1) if the
--! specified station address matches the SUBS configuration.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
id_dat_var_concurrent: process(byte_i)
......@@ -464,10 +465,13 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
var_o <= s_var; -- var_o takes a value at the end of the id_dat
---------------------------------------------------------------------------------------------------
--!@brief: Combinatorial process Identify_Broadcast_Var: signal s_broadcast_var is enabled if the
--! variable received from the id_dat, s_var_aux, is a variable 2 (04h).
--!@brief: Combinatorial process Var_Characteristics: managment of the signals
--! s_produce_or_consume and s_broadcast_var, accroding to the value of s_var_aux.
Var_Characteristics: process(s_var_aux)
begin
......@@ -494,11 +498,13 @@ begin
end process;
---------------------------------------------------------------------------------------------------
--!@brief: Combinatorial process data_length_calculation: calculation of the total amount of data
--! bytes that have to be transferreed when an rp_dat (produced variable) has to be sent,
--! including the rp_dat.Control as well as the rp_dat.Data.mps and rp_dat.Data.nanoFIPstatus bytes.
--!@brief:Combinatorial process data_length_calcul_produce: calculation of the total amount of data
--! bytes that have to be transferreed when a variable is produced, including the rp_dat.Control as
--! well as the rp_dat.Data.mps and rp_dat.Data.nanoFIPstatus bytes. In the case of presence and
--! identification variables, the data length is predefined in the wf_package.
--! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation
data_length_calculation: process(s_var, s_p3_length_decoded, slone_i, nostat_i)
data_length_calcul_produce: process(s_var, s_p3_length_decoded, slone_i, nostat_i)
variable v_nostat : std_logic_vector(1 downto 0);
begin
s_append_status <= not nostat_i;
......@@ -507,7 +513,7 @@ begin
s_p3_length_decoded'length);
case s_var is
when c_presence_var => -- data_length including rp_dat.control and rp_dat.data fields
when c_presence_var =>
s_data_length<=to_unsigned(c_var_array(c_presence_var_pos).array_length-1,s_data_length'length);
when c_identif_var =>
......@@ -542,8 +548,8 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Bytes_Counter:Managing the counter that counts the number of produced
--! or consumed bytes of data.
--!@brief Synchronous process Bytes_Counter: Managment of the counter that counts the number of
--! produced or consumed bytes of data.
Bytes_Counter: process(uclk_i)
begin
......@@ -560,8 +566,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- when s_data_length bytes have been counted, the signal data_length_match is activated
data_length_match <= '1' when s_bytes_c = s_data_length else '0';
---------------------------------------------------------------------------------------------------
-- retrieval of response and silence times information (in equivalent number of uclk ticks) from
-- the c_timeouts_table declared in the wf_package unit.
......@@ -587,34 +593,9 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- when the response or silence time is reached, the signal s_respon_silen_c_is_zero is activated.
-- when the response or silence time is reached, the signal s_respon_silen_c_is_zero is activated
s_respon_silen_c_is_zero <= '1' when s_respon_silen_c = 0 else '0';
---------------------------------------------------------------------------------------------------
--!@brief: buffering the output signals last_byte_p_o and byte_ready_p_o and start_produce_p_o
process(uclk_i)
begin
if rising_edge(uclk_i) then
if rst_i = '1' then
last_byte_p_o <= '0';
byte_ready_p_o <= '0';
else
last_byte_p_o <= s_last_byte_p;
byte_ready_p_o <= s_byte_ready_p;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
process(uclk_i)
begin
if rising_edge(uclk_i) then
s_start_produce_p_d1 <= s_start_produce_p;
end if;
end process;
start_produce_p_o <= s_start_produce_p_d1;
---------------------------------------------------------------------------------------------------
--!@brief:synchronous process VAR_RDY_Generation: managment of the nanoFIP output signals VAR1_RDY,
......@@ -667,7 +648,29 @@ begin
end if;
end process;
var_o <= s_var; --var_o takes a value at the end of the id_dat
---------------------------------------------------------------------------------------------------
--!@brief: essential buffering of output signals last_byte_p_o, byte_ready_p_o, start_produce_p_o
process(uclk_i)
begin
if rising_edge(uclk_i) then
if rst_i = '1' then
last_byte_p_o <= '0';
byte_ready_p_o <= '0';
s_start_produce_p_d1 <= '0';
else
last_byte_p_o <= s_last_byte_p;
byte_ready_p_o <= s_byte_ready_p;
s_start_produce_p_d1 <= s_start_produce_p;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
start_produce_p_o <= s_start_produce_p_d1;
---------------------------------------------------------------------------------------------------
end architecture rtl;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
......
wf_package.vhd
View file @ cdabc78f
......@@ -13,7 +13,7 @@ USE ieee.numeric_std.ALL;
package wf_package is
constant C_QUARTZ_PERIOD : real := 25.0;
constant C_QUARTZ_PERIOD : real := 24.8;
......@@ -175,7 +175,7 @@ package wf_package is
slone : std_logic) return std_logic_vector;
component wf_rx_osc
generic (C_COUNTER_LENGTH : integer := 7;
generic (C_COUNTER_LENGTH : integer := 11;
C_QUARTZ_PERIOD : real := 24.8;
C_CLKFCDLENTGTH : natural := 3
);
......@@ -291,8 +291,8 @@ package wf_package is
component dpblockram_clka_rd_clkb_wr
generic (c_data_length : integer := 42; -- Length of the data word
c_addr_length : integer := 10); -- Number of words
generic (c_data_length : integer := 8; -- Length of the data word
c_addr_length : integer := 9); -- Number of words
-- 'nw' has to be coherent with 'c_addr_length'
port (clk_A_i : in std_logic; -- Global Clock
......@@ -306,7 +306,7 @@ package wf_package is
end component dpblockram_clka_rd_clkb_wr;
component wf_engine_control
generic( C_QUARTZ_PERIOD : real := 25.0);
generic( C_QUARTZ_PERIOD : real := 24.8);
port (
uclk_i : in std_logic; --! User Clock
......@@ -467,7 +467,7 @@ package wf_package is
stat_i : in std_logic_vector(7 downto 0); --! NanoFIP status
mps_i : in std_logic_vector(7 downto 0);
sending_stat_o : out std_logic; --! The status register is being adressed
sending_mps_o : out std_logic;
-- var3_access_wb_clk_o: out std_logic; --! Variable 2 access flag
......@@ -567,8 +567,7 @@ package wf_package is
-- reset_var3_access_o : out std_logic; --! Reset Variable 2 access flag
stat_sent_p_i : in std_logic;
mps_sent_p_i : in std_logic;
reset_status_bytes_i : in std_logic;
stat_o : out std_logic_vector(7 downto 0);
mps_o : out std_logic_vector(7 downto 0)
......@@ -593,7 +592,8 @@ package wf_package is
rston_o : out std_logic; --! Reset output, active low
var_i : in t_var; --! Received variable
rst_o : out std_logic --! Reset ouput active high
rst_o : out std_logic; --! Reset ouput active high
fd_rst_o : out std_logic
);
......@@ -658,7 +658,7 @@ package wf_package is
fd_txena_o: out std_logic; --! Transmitter enable
fd_txck_o : out std_logic; --! Line driver half bit clock
fx_txd_o : out std_logic; --! Transmitter data
fx_rxa_i : in std_logic; --! Reception activity detection
fx_rxa_i : inout std_logic; --! Reception activity detection
fx_rxd_i : in std_logic; --! Receiver data
......
wf_produced_vars.vhd
View file @ cdabc78f
......@@ -110,10 +110,10 @@ entity wf_produced_vars is
-- Outputs
-- signal to status_gen
sending_stat_o : out std_logic; --!indication:nanoFIP status byte being sent
sending_mps_o : out std_logic; --!indication: mps byte being sent
-- signal to wf_tx
byte_o : out std_logic_vector(7 downto 0); --! output byte to be serialized and sent
byte_o : out std_logic_vector(7 downto 0);--! output byte to be serialized and sent
-- nanoFIP output
wb_ack_p_o : out std_logic --! wishbone acknowledge
......@@ -227,8 +227,8 @@ architecture rtl of wf_produced_vars is
s_base_addr <= (others => '0'); -- specifies the ram block
-- corresponding to each variable
sending_stat_o <= '0'; -- indicates that nanoFIP status
-- is being sent
sending_mps_o <= '0'; -- indicates that mps status byte
-- is being sent
---------------------------------------------------------------------------------------------------
......@@ -274,10 +274,11 @@ architecture rtl of wf_produced_vars is
elsif s_byte_adr = (unsigned(data_length_i) - 1) and nostat_i = '0' then --one but last byte:
s_byte <= stat_i; --nanoFIP status;only sent if nostat negated
sending_stat_o <= '1'; -- indication that status byte is being sent
elsif s_byte_adr = (unsigned(data_length_i))then -- last byte: mps status
s_byte <= mps_i;
sending_mps_o <= '1'; -- indication that mps byte is being sent
elsif slone_i='0' and s_byte_adr = c_pdu_byte_add then -- in memory mode operation,
s_byte <= c_var_array(c_var_3_pos).byte_array(s_byte_adr_aux); -- PDU byte is being sent
......
wf_rx.vhd
View file @ cdabc78f
......@@ -13,7 +13,7 @@ use work.wf_package.all;
---------------------------------------------------------------------------------------------------
-- --
-- wf_rx --
-- wf_rx --
-- --
-- CERN, BE/CO/HT --
-- --
......@@ -27,19 +27,20 @@ use work.wf_package.all;
--!
--!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--!
--! @date 10/08/2009
--! @date 08/2010
--
--! @version v0.01
--! @version v0.02
--
--! @details
--!
--! <b>Dependencies:</b>\n
--! wf_engine \n
--! tx_engine \n
--! clk_gen \n
--! reset_logic \n
--! consumed_ram \n
--! wf_rx_tx_osc\n
--! wf_deglitcher\n
--! wf_tx_rx\n
--!
--!
--!
--!
--! <b>References:</b>\n
......@@ -49,10 +50,14 @@ use work.wf_package.all;
--! <b>Modified by:</b>\n
--! Author: Erik van der Bij
--! Pablo Alvarez Sanchez
--! Evangelia Gousiou
---------------------------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/08/2009 v0.02 PAAS Entity Ports added, start of architecture content
--!
--! 07/10 state switch_to_deglitched added
--! output signal wait_d_first_f_edge_o added
--! signals renamed
--! code cleaned-up + commented
--!
---------------------------------------------------------------------------------------------------
--! @todo Define I/O signals \n
--!
......@@ -68,21 +73,21 @@ entity wf_rx is
port (
-- Inputs
-- user interface general signals
uclk_i : in std_logic; --! 40MHz clock
rst_i : in std_logic; --! global reset
uclk_i : in std_logic; --! 40MHz clock
rst_i : in std_logic; --! global reset
-- signals from the wf_rx_tx_osc
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
--! bits is expected
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
adjac_bits_window_i : in std_logic; --! time window where a transition between adjacent
--! bits is expected
-- signals from wf_tx_rx
rx_data_r_edge_i : in std_logic;--!indicates a rising edge on the buffered rxd (rx_data_i)
rx_data_f_edge_i : in std_logic; --! indicates a falling edge on the d_1
rx_data_r_edge_i : in std_logic; --!indicates a rising edge on the buffered rxd(rx_data_i)
rx_data_f_edge_i : in std_logic; --! indicates a falling edge on the d_1
-- signal from the wf_deglitcher
rx_data_filtered_i : in std_logic; --! deglitched serial input signal
rx_data_filtered_i : in std_logic; --! deglitched serial input signal
sample_manch_bit_p_i: in std_logic; --!
sample_bit_p_i : in std_logic; --!
......@@ -91,7 +96,7 @@ entity wf_rx is
-- needed by the wf_consumed and wf_engine_control
byte_ready_p_o : out std_logic; --! indication of a valid data byte
byte_o : out std_logic_vector(7 downto 0) ; --! retreived data byte
byte_o : out std_logic_vector(7 downto 0) ; --! retreived data byte
-- needed by the wf_engine_control
crc_ok_p_o : out std_logic;
......@@ -100,11 +105,11 @@ entity wf_rx is
last_byte_p_o : out std_logic;
-- needed by the status_gen
code_violation_p_o : out std_logic; --! indicator of a manchester 2 code violation
code_violation_p_o : out std_logic; --! indicator of a manchester 2 code violation
-- needed by the wf_rx_tx_osc
wait_d_first_f_edge_o : out std_logic --! indicator of the rx state machine being in idle
-- state, expecting for the first falling edge of the preamble
--state, expecting for the preamble's 1st falling edge
);
end entity wf_rx;
......@@ -409,6 +414,7 @@ architecture rtl of wf_rx is
s_queue_bit <= FRAME_END(to_integer(resize(pointer,4)));
code_violation_p_o <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '1';
s_frame_start_bit <= '0';
......@@ -457,6 +463,7 @@ architecture rtl of wf_rx is
if rising_edge(uclk_i) then
if rst_i = '1' then
s_frame_end_detection <= '1';
elsif s_pointer_is_zero = '1' and sample_manch_bit_p_i = '1' then
s_frame_end_detection <= '1';
elsif s_frame_end_wrong_bit = '1' then
......@@ -475,6 +482,7 @@ architecture rtl of wf_rx is
if rst_i = '1' then
pointer <= (others => '0');
else
if s_load_pointer = '1' then
pointer <= s_start_pointer;
elsif s_decr_pointer = '1' then
......@@ -492,9 +500,14 @@ architecture rtl of wf_rx is
Append_Bit_To_Byte: process (uclk_i)
begin
if rising_edge(uclk_i) then
if s_write_bit_to_byte = '1' then
s_byte <= s_byte(6 downto 0) & rx_data_filtered_i;
end if;
if rst_i = '1' then
s_byte <= (others => '0');
else
if s_write_bit_to_byte = '1' then
s_byte <= s_byte(6 downto 0) & rx_data_filtered_i;
end if;
end if;
end if;
end process;
......@@ -503,12 +516,15 @@ architecture rtl of wf_rx is
begin
if rising_edge(uclk_i) then
if rst_i = '1' then
s_crc_ok <= '0';
elsif s_calculate_crc='0' then
s_crc_ok <= '0';
elsif s_crc_ok_p = '1' and s_calculate_crc='1' then
s_crc_ok <= '1';
end if;
s_crc_ok <= '0';
else
if s_calculate_crc='0' then
s_crc_ok <= '0';
elsif s_crc_ok_p = '1' and s_calculate_crc='1' then
s_crc_ok <= '1';
end if;
end if;
end if;
end process;
......@@ -521,10 +537,11 @@ architecture rtl of wf_rx is
Detect_f_edge_rx_data_filtered: process(uclk_i)
begin
if rising_edge(uclk_i) then
-- initializations:
if rst_i = '1' then
s_rx_data_filtered_buff <= (others => '0');
s_rx_data_filtered_f_edge <= '0';
else
-- buffer s_rx_data_filtered_buff keeps the last 2 bits of rx_data_filtered_i
s_rx_data_filtered_buff <= s_rx_data_filtered_buff(0) & rx_data_filtered_i;
-- falling edge detected if last bit is a 0 and previous was a 1
......
wf_rx_osc.vhd
View file @ cdabc78f
......@@ -40,9 +40,9 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--!
--! @date 06/06/2010
--! @date 07/2010
--
--! @version v0.02
--! @version v0.03
--
--! @details
--!
......@@ -56,10 +56,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--!
--! <b>Modified by:</b>\n
--! Author: Pablo Alvarez Sanchez
--! Evangelia Gousiou
---------------------------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 07/08/2009 v0.02 PAAS Entity Ports added, start of architecture content
--!
--! 08/2009 v0.02 PAAS Entity Ports added, start of architecture content
--! 07/2010 v0.03 tx, rx counter changed from 20 bits signed, to 11 bits unsigned
--! rx clk generation depends on edges detection
--! code cleaned-up + commented
---------------------------------------------------------------------------------------------------
--! @todo Define I/O signals \n
--!
......@@ -72,11 +75,11 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--=================================================================================================
entity wf_rx_osc is
generic (C_COUNTER_LENGTH : integer := 12; -- in the slowest bit rate (31.25kbps), the period is
generic (C_COUNTER_LENGTH : integer := 11; -- in the slowest bit rate (31.25kbps), the period is
-- 32000ns and can be measured after 1280 uclk ticks.
-- Therefore a counter of 12 bits is the max needed
-- Therefore a counter of 11 bits is the max needed
-- for counting transmission/reception periods.
C_QUARTZ_PERIOD : real := 25.0; -- 40 MHz clock period
C_QUARTZ_PERIOD : real := 24.8; -- 40 MHz clock period
C_CLKFCDLENTGTH : natural := 3
);
......@@ -126,8 +129,8 @@ end entity wf_rx_osc;
architecture rtl of wf_rx_osc is
-- calculations of the number of uclk ticks equivalent to the reception/ transmission period
constant c_uclk_ticks_31_25kbit:unsigned:=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),C_COUNTER_LENGTH);
constant c_uclk_ticks_31_25kbit:unsigned:=
to_unsigned((32000/ integer(C_QUARTZ_PERIOD)),C_COUNTER_LENGTH);
constant c_uclk_ticks_1_mbit:unsigned:=
to_unsigned((1000/ integer(C_QUARTZ_PERIOD)),C_COUNTER_LENGTH);
constant c_uclk_ticks_2_5mbit:unsigned:=
......@@ -144,18 +147,18 @@ architecture rtl of wf_rx_osc is
-- auxiliary signals declarations
signal s_counter_rx, s_counter_tx, s_period, s_jitter : unsigned (C_COUNTER_LENGTH-1 downto 0);
signal s_counter_full, s_one_forth_period, s_half_period :unsigned (C_COUNTER_LENGTH-1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector(C_CLKFCDLENTGTH -1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_rx_bit_clk, s_rx_bit_clk_d1, s_rx_manch_clk, s_rx_manch_clk_d1 : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
signal s_rx_signif_edge_window, s_rx_adjac_bits_window : std_logic;
signal s_tx_clk_p_buff : std_logic_vector(C_CLKFCDLENTGTH -1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_rx_bit_clk, s_rx_bit_clk_d1, s_rx_manch_clk, s_rx_manch_clk_d1 : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
signal s_rx_signif_edge_window, s_rx_adjac_bits_window : std_logic;
begin
s_period <= C_UCLK_TICKS(to_integer(unsigned(rate_i))); -- s_period: # uclock ticks for a period
s_half_period <= (s_period srl 1); -- s_period shifted 1 bit
s_one_forth_period <= s_period srl 2; -- s_period shifted 2 bits
......@@ -178,7 +181,6 @@ begin
periods_count: process(uclk_i)
begin
if rising_edge(uclk_i) then
-- initializations:
if rst_i = '1' then
s_counter_tx <= (others => '0');
s_counter_rx <= (others => '0');
......
wf_tx.vhd
View file @ cdabc78f
......@@ -398,8 +398,12 @@ begin
process(uclk_i)
begin
if rising_edge(uclk_i) then
if byte_ready_p_i = '1' then
s_byte <= byte_i;
if rst_i = '1' then
s_byte <= (others => '0');
else
if byte_ready_p_i = '1' then
s_byte <= byte_i;
end if;
end if;
end if;
end process;
......@@ -440,10 +444,15 @@ begin
Bits_Delivery: process(uclk_i)
begin
if rising_edge(uclk_i) then
if tx_clk_p_buff_i(0) = '1' then
tx_data_o <= s_data_bit;
end if;
if rst_i = '1' then
tx_data_o <= '0';
tx_enable_o <= '0';
else
if tx_clk_p_buff_i(0) = '1' then
tx_data_o <= s_data_bit;
end if;
tx_enable_o <= s_tx_enable;
end if;
end if;
end process;
......@@ -454,10 +463,15 @@ begin
Outgoing_Bits_Pointer: process(uclk_i)
begin
if rising_edge(uclk_i) then
if s_load_pointer = '1' then
s_pointer <= s_top_pointer;
elsif s_decr_pointer = '1' then
s_pointer <= s_pointer - 1;
if rst_i = '1' then
s_pointer <= (others => '0');
else
if s_load_pointer = '1' then
s_pointer <= s_top_pointer;
elsif s_decr_pointer = '1' then
s_pointer <= s_pointer - 1;
end if;
end if;
end if;
end process;
......
wf_tx_rx.vhd
View file @ cdabc78f
......@@ -116,7 +116,7 @@ architecture rtl of wf_tx_rx is
signal s_clk_carrier_p : std_logic;
signal s_clk_bit_180_p, s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_edge_window, edge_180_window : std_logic;
signal s_d_edge : std_logic;
signal s_d_edge, s_code_violation : std_logic;
signal s_clk_fixed_carrier_p_d : std_logic_vector(C_CLKFCDLENTGTH - 1 downto 0);
begin
......@@ -167,18 +167,19 @@ begin
rx_data_filtered_i => s_d_filtered,
sample_manch_bit_p_i => s_sample_manch_bit_p,
wait_d_first_f_edge_o=> s_first_fe,
code_violation_p_o => code_violation_p_o,
crc_wrong_p_o => crc_wrong_p_o,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => s_edge_window,
adjac_bits_window_i => edge_180_window
);
uwf_rx_osc :wf_rx_osc
generic map(C_COUNTER_LENGTH => 7,
generic map(C_COUNTER_LENGTH => 11,
C_QUARTZ_PERIOD => 24.8,
C_CLKFCDLENTGTH => C_CLKFCDLENTGTH)
......
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