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nanoFIP - Gateware
Commit e1bd8403 authored by egousiou's avatar egousiou
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wf_cons_outcome: bug on var1/2_rdy generation corrected 

top level nanofip comments on structure updated

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@177 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 297713da
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nanofip.vhd
View file @ e1bd8403
...@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! the stations connected to the same network segment. Figure 1 shows the structure of an ID_DAT --! the stations connected to the same network segment. Figure 1 shows the structure of an ID_DAT
--! frame: --! frame:
--! ___________ ______ _______ ______ ___________ _______ --! ___________ ______ _______ ______ ___________ _______
--! |____FSS____|_Ctrl_||__Var__|_Subs_||____FCS____|__FES__| --! |____FSS____|_Ctrl_||__Var__|_SUBS_||____FCS____|__FES__|
--! --!
--! Figure 1 : ID_DAT frame structure --! Figure 1 : ID_DAT frame structure
--! --!
...@@ -86,54 +86,48 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -86,54 +86,48 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! validated by station address as data --! validated by station address as data
--! --!
--! nanoFIP's main building blocks are (Figure 3): --! nanoFIP's main building blocks are (Figure 3):
--! o WF_inputs_synchronizer : for the synchronization of the input signals with the user --!
--! or the WISHBONE clock. --! o WF_reset_unit : for the treatment of the reset input signals & the generation
--! o WF_reset_unit : for the treatment of the reset input signals and the generation --! of the reset outputs
--! of the reset outputs. --!
--! o WF_tx_rx_osc : for the generation of the clocks used by the transmitter and --! o WF_consumption : for the processing, storage & validation of consumed RP_DAT frames
--! receiver for the data serialization and deserialization. --!
--! o WF_consumption : for the processing of consumed variables, from the deserialization --! o WF_fd_receiver : for the deserialization of the FIELDRIVE input and the formation
--! to the bytes storage and validation. --! of ID_DAT or RP_DAT bytes of data
--! o WF_production : for the processing of produced variables, from the bytes --!
--! retrieval to the serialization. --! o WF_production : for the retreival of the bytes that form produced RP_DAT frames
--!
--! o WF_fd_transmitter : for the serialization of produced RP_DAT frames
--!
--! o WF_engine_control : for the processing of the ID_DAT frames and the coordination of the --! o WF_engine_control : for the processing of the ID_DAT frames and the coordination of the
--! WF_consumption and WF_production units. --! WF_consumption, WF_fd_receiver, WF_production & WF_fd_transmitter units
--!
--! o WF_model_constr_dec : for the decoding of the WorldFIP settings M_ID and C_ID and the --! o WF_model_constr_dec : for the decoding of the WorldFIP settings M_ID and C_ID and the
--! generation of the S_ID. --! generation of the S_ID
--!
--! o WF_wb_controller : for the handling of the "User Interface WISHBONE Slave" control --! o WF_wb_controller : for the handling of the "User Interface WISHBONE Slave" control
--! signals. --! signals.
--! --!
--! _____________ __________________________ _____________ --! _____________ ____________________________________________________
--! | | | | | | --! | | | WF_WB_controller |
--! | | | WF_tx_rx_osc | | | --! | | |____________________________________________________|
--! | | | | | | --! | | _____________ _____________
--! | | |__________________________| | | --! | | | | ______________ | |
--! | | | |
--! | WF_inputs_ | ___________ ____________ |
--! | synchroniser| | | | | | |
--! | | | | | | | |
--! | | | | | | | |
--! | | | | | | | |
--! | | | | | | | |
--! | | | | | | | |
--! | | | | | | | WF_engine |
--! |_____________| | | | | | _control |
--! | | | | | |
--! _____________ | WF_ | | WF_ | | |
--! | | |consumption| | production | | |
--! | | | | | | | |
--! | WF_reset | | | | | | | --! | WF_reset | | | | | | |
--! | _unit | | | | | | | --! | _unit | | WF_ | | | | WF_ |
--! | | | consumption | | | | production |
--! | | | | | | | |
--! | | | | | | | | --! | | | | | | | |
--! |_____________| | | | | | | --! | | |_____________| | WF_ | |_____________|
--! |_____________| _____________ |engine_control| _____________
--! | | | | | | --! | | | | | |
--! _____________ | | | | | | --! _____________ | | | | | |
--! | | | | | | | | --! | | | | | | | |
--! | | |___________| |____________| | | --! | | | WF_FD_ | | | | WF_FD_ |
--! | WF_model_ | | | --! | WF_model_ | | receiver | | | | transmitter |
--! | constr_dec | ___________________________ | | --! | constr_dec | | | | | | |
--! | | | WF_wb_controller | | | --! | | | | | | | |
--! |_____________| |___________________________| |_____________| --! |_____________| |_____________| |______________| |_____________|
--! --!
--! Figure 3: nanoFIP block diagram --! Figure 3: nanoFIP block diagram
--! --!
...@@ -300,34 +294,28 @@ end entity nanofip; ...@@ -300,34 +294,28 @@ end entity nanofip;
architecture struc of nanofip is architecture struc of nanofip is
--------------------------------------------------------------------------------------------------- -- WF_reset_unit iutputs
-- Triple Module Redundancy -- signal s_nfip_intern_rst, s_wb_rst : std_logic;
--------------------------------------------------------------------------------------------------- -- WF_consumption outputs
attribute syn_radhardlevel : string; -- signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic;
attribute syn_radhardlevel of struc : architecture is "tmr"; -- signal s_assert_RSTON_p, s_reset_nFIP_and_FD_p, s_nfip_status_r_tler : std_logic;
--------------------------------------------------------------------------------------------------- -- WF_fd_receiver outputs
signal s_rx_fss_received_p, s_rx_fss_crc_fes_manch_ok_p, s_rx_crc_or_manch_wrong_p : std_logic;
signal s_rx_byte_ready_p : std_logic;
component CLKBUF signal s_rx_byte : std_logic_vector (7 downto 0);
port (PAD : in std_logic; -- WF_production outputs
Y : out std_logic); signal s_byte_to_tx : std_logic_vector (7 downto 0);
end component; -- WF_fd_transmitter outputs
signal s_tx_last_byte_p : std_logic;
-- WF_engine_control outputs
signal s_rst, s_rx_byte_ready, s_start_tx_p, s_prod_request_byte_p : std_logic; signal s_tx_start_p, s_tx_request_byte_p, s_byte_request_accepted_p : std_logic;
signal s_prod_last_byte_p, s_rst_tx_p : std_logic; signal s_rx_rst_p : std_logic;
signal s_fss_crc_fes_manch_ok_p, s_rx_fss_decoded_p, s_wb_rst : std_logic; signal s_var : t_var;
signal s_crc_or_manch_wrong_p, s_reset_nFIP_and_FD_p : std_logic; signal s_prod_data_lgth, s_prod_cons_byte_index : std_logic_vector (7 downto 0);
signal s_var1_rdy, s_var2_rdy, s_var3_rdy, s_assert_RSTON_p, s_wb_ack_prod : std_logic; -- WF_model_constr_dec outputs
signal s_rx_rst_p, s_nfip_status_r_tler : std_logic; signal s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_prod_byte_ready_p : std_logic; -- WF_wb_controller outputs
signal s_var_from_control : t_var; signal s_wb_ack_prod : std_logic;
signal s_data_lgth_from_control : std_logic_vector (7 downto 0);
signal s_rx_byte, s_byte_to_tx, s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_cons_prod_byte_index_from_control : std_logic_vector (7 downto 0);
--================================================================================================= --=================================================================================================
...@@ -349,12 +337,12 @@ begin ...@@ -349,12 +337,12 @@ begin
rst_i => rst_i, rst_i => rst_i,
rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p, rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p,
assert_RSTON_p_i => s_assert_RSTON_p, assert_RSTON_p_i => s_assert_RSTON_p,
--------------------------------------------------------- -------------------------------------------------------------
nFIP_rst_o => s_rst, nFIP_rst_o => s_nfip_intern_rst,
wb_rst_o => s_wb_rst, wb_rst_o => s_wb_rst,
rston_o => rston_o, rston_o => rston_o,
fd_rstn_o => fd_rstn_o); fd_rstn_o => fd_rstn_o);
--------------------------------------------------------- -------------------------------------------------------------
...@@ -365,24 +353,24 @@ begin ...@@ -365,24 +353,24 @@ begin
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
slone_i => slone_i, slone_i => slone_i,
nfip_rst_i => s_rst, nfip_rst_i => s_nfip_intern_rst,
subs_i => subs_i, subs_i => subs_i,
rx_byte_i => s_rx_byte, rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready, rx_byte_ready_p_i => s_rx_byte_ready_p,
rx_fss_crc_fes_manch_ok_p_i => s_fss_crc_fes_manch_ok_p, rx_fss_crc_fes_manch_ok_p_i => s_rx_fss_crc_fes_manch_ok_p,
rx_crc_or_manch_wrong_p_i => s_crc_or_manch_wrong_p, rx_crc_or_manch_wrong_p_i => s_rx_crc_or_manch_wrong_p,
wb_clk_i => wclk_i, wb_clk_i => wclk_i,
wb_adr_i => adr_i (8 downto 0), wb_adr_i => adr_i (8 downto 0),
var_i => s_var_from_control, var_i => s_var,
byte_index_i => s_cons_prod_byte_index_from_control, byte_index_i => s_prod_cons_byte_index,
--------------------------------------------------------- -------------------------------------------------------------
var1_rdy_o => s_var1_rdy, var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy, var2_rdy_o => s_var2_rdy,
data_o => dat_o, data_o => dat_o,
nfip_status_r_tler_p_o => s_nfip_status_r_tler, nfip_status_r_tler_p_o => s_nfip_status_r_tler,
assert_rston_p_o => s_assert_RSTON_p, assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p); rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p);
--------------------------------------------------------- -------------------------------------------------------------
...@@ -394,15 +382,15 @@ begin ...@@ -394,15 +382,15 @@ begin
uclk_i => uclk_i, uclk_i => uclk_i,
rate_i => rate_i, rate_i => rate_i,
fd_rxd_a_i => fd_rxd_i, fd_rxd_a_i => fd_rxd_i,
nfip_rst_i => s_rst, nfip_rst_i => s_nfip_intern_rst,
rx_rst_p_i => s_rx_rst_p, rx_rst_p_i => s_rx_rst_p,
--------------------------------------------------------- -------------------------------------------------------------
rx_byte_o => s_rx_byte, rx_byte_o => s_rx_byte,
rx_byte_ready_p_o => s_rx_byte_ready, rx_byte_ready_p_o => s_rx_byte_ready_p,
rx_fss_crc_fes_manch_ok_p_o => s_fss_crc_fes_manch_ok_p, rx_fss_crc_fes_manch_ok_p_o => s_rx_fss_crc_fes_manch_ok_p,
rx_fss_received_p_o => s_rx_fss_decoded_p, rx_fss_received_p_o => s_rx_fss_received_p,
rx_crc_or_manch_wrong_p_o => s_crc_or_manch_wrong_p); rx_crc_or_manch_wrong_p_o => s_rx_crc_or_manch_wrong_p);
--------------------------------------------------------- -------------------------------------------------------------
...@@ -414,7 +402,7 @@ begin ...@@ -414,7 +402,7 @@ begin
uclk_i => uclk_i, uclk_i => uclk_i,
slone_i => slone_i, slone_i => slone_i,
nostat_i => nostat_i, nostat_i => nostat_i,
nfip_rst_i => s_rst, nfip_rst_i => s_nfip_intern_rst,
wb_clk_i => wclk_i, wb_clk_i => wclk_i,
wb_data_i => dat_i(7 downto 0), wb_data_i => dat_i(7 downto 0),
wb_adr_i => adr_i(8 downto 0), wb_adr_i => adr_i(8 downto 0),
...@@ -425,24 +413,24 @@ begin ...@@ -425,24 +413,24 @@ begin
var3_acc_a_i => var3_acc_i, var3_acc_a_i => var3_acc_i,
fd_txer_a_i => fd_txer_i, fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i, fd_wdgn_a_i => fd_wdgn_i,
var_i => s_var_from_control, var_i => s_var,
data_lgth_i => s_data_lgth_from_control, data_lgth_i => s_prod_data_lgth,
byte_index_i => s_cons_prod_byte_index_from_control, byte_index_i => s_prod_cons_byte_index,
byte_request_accept_p_i => s_prod_byte_ready_p, byte_request_accept_p_i => s_byte_request_accepted_p,
nfip_status_r_tler_p_i => s_nfip_status_r_tler, nfip_status_r_tler_p_i => s_nfip_status_r_tler,
nfip_status_r_fcser_p_i => s_crc_or_manch_wrong_p, nfip_status_r_fcser_p_i => s_rx_crc_or_manch_wrong_p,
var1_rdy_i => s_var1_rdy, var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy, var2_rdy_i => s_var2_rdy,
model_id_dec_i => s_model_id_dec, model_id_dec_i => s_model_id_dec,
constr_id_dec_i => s_constr_id_dec, constr_id_dec_i => s_constr_id_dec,
--------------------------------------------------------- -------------------------------------------------------------
byte_o => s_byte_to_tx, byte_o => s_byte_to_tx,
u_cacer_o => u_cacer_o, u_cacer_o => u_cacer_o,
u_pacer_o => u_pacer_o, u_pacer_o => u_pacer_o,
r_tler_o => r_tler_o, r_tler_o => r_tler_o,
r_fcser_o => r_fcser_o, r_fcser_o => r_fcser_o,
var3_rdy_o => s_var3_rdy); var3_rdy_o => s_var3_rdy);
--------------------------------------------------------- -------------------------------------------------------------
...@@ -453,17 +441,17 @@ begin ...@@ -453,17 +441,17 @@ begin
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
rate_i => rate_i, rate_i => rate_i,
nfip_rst_i => s_rst, nfip_rst_i => s_nfip_intern_rst,
tx_byte_i => s_byte_to_tx, tx_byte_i => s_byte_to_tx,
tx_byte_request_accept_p_i => s_prod_byte_ready_p, tx_byte_request_accept_p_i => s_byte_request_accepted_p,
tx_last_byte_p_i => s_prod_last_byte_p, tx_last_byte_p_i => s_tx_last_byte_p,
tx_start_p_i => s_start_tx_p, tx_start_p_i => s_tx_start_p,
--------------------------------------------------------- -------------------------------------------------------------
tx_byte_request_p_o => s_prod_request_byte_p, tx_byte_request_p_o => s_tx_request_byte_p,
tx_data_o => fd_txd_o, tx_data_o => fd_txd_o,
tx_enable_o => fd_txena_o, tx_enable_o => fd_txena_o,
tx_clk_o => fd_txck_o); tx_clk_o => fd_txck_o);
--------------------------------------------------------- -------------------------------------------------------------
...@@ -474,27 +462,27 @@ begin ...@@ -474,27 +462,27 @@ begin
engine_control : WF_engine_control engine_control : WF_engine_control
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_rst_i => s_rst, nfip_rst_i => s_nfip_intern_rst,
tx_byte_request_p_i => s_prod_request_byte_p, tx_byte_request_p_i => s_tx_request_byte_p,
rx_fss_received_p_i => s_rx_fss_decoded_p, rx_fss_received_p_i => s_rx_fss_received_p,
rx_byte_i => s_rx_byte, rx_byte_i => s_rx_byte,
rx_byte_ready_p_i => s_rx_byte_ready, rx_byte_ready_p_i => s_rx_byte_ready_p,
rx_fss_crc_fes_manch_ok_p_i => s_fss_crc_fes_manch_ok_p, rx_fss_crc_fes_manch_ok_p_i => s_rx_fss_crc_fes_manch_ok_p,
rx_crc_or_manch_wrong_p_i => s_crc_or_manch_wrong_p, rx_crc_or_manch_wrong_p_i => s_rx_crc_or_manch_wrong_p,
rate_i => rate_i, rate_i => rate_i,
subs_i => subs_i, subs_i => subs_i,
p3_lgth_i => p3_lgth_i, p3_lgth_i => p3_lgth_i,
slone_i => slone_i, slone_i => slone_i,
nostat_i => nostat_i, nostat_i => nostat_i,
--------------------------------------------------------- -------------------------------------------------------------
var_o => s_var_from_control, var_o => s_var,
tx_start_p_o => s_start_tx_p , tx_start_p_o => s_tx_start_p,
tx_byte_request_accept_p_o => s_prod_byte_ready_p, tx_byte_request_accept_p_o => s_byte_request_accepted_p,
tx_last_byte_p_o => s_prod_last_byte_p, tx_last_byte_p_o => s_tx_last_byte_p,
prod_cons_byte_index_o => s_cons_prod_byte_index_from_control, prod_cons_byte_index_o => s_prod_cons_byte_index,
prod_data_lgth_o => s_data_lgth_from_control, prod_data_lgth_o => s_prod_data_lgth,
rx_rst_p_o => s_rx_rst_p); rx_rst_p_o => s_rx_rst_p);
--------------------------------------------------------- -------------------------------------------------------------
var1_rdy_o <= s_var1_rdy; var1_rdy_o <= s_var1_rdy;
var2_rdy_o <= s_var2_rdy; var2_rdy_o <= s_var2_rdy;
...@@ -508,15 +496,14 @@ begin ...@@ -508,15 +496,14 @@ begin
model_constr_decoder : WF_model_constr_decoder model_constr_decoder : WF_model_constr_decoder
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_rst_i => s_rst, nfip_rst_i => s_nfip_intern_rst,
model_id_i => m_id_i, model_id_i => m_id_i,
constr_id_i => c_id_i, constr_id_i => c_id_i,
--------------------------------------------------------- -------------------------------------------------------------
select_id_o => s_id_o, select_id_o => s_id_o,
model_id_dec_o => s_model_id_dec, model_id_dec_o => s_model_id_dec,
constr_id_dec_o => s_constr_id_dec); constr_id_dec_o => s_constr_id_dec);
--------------------------------------------------------- -------------------------------------------------------------
...@@ -526,20 +513,15 @@ begin ...@@ -526,20 +513,15 @@ begin
WISHBONE_controller: WF_wb_controller WISHBONE_controller: WF_wb_controller
port map ( port map (
wb_clk_i => wclk_i, wb_clk_i => wclk_i,
wb_rst_i => rst_i, wb_rst_i => s_wb_rst,
wb_stb_i => stb_i, wb_stb_i => stb_i,
wb_cyc_i => cyc_i, wb_cyc_i => cyc_i,
wb_we_i => we_i, wb_we_i => we_i,
wb_adr_id_i => adr_i (9 downto 7), wb_adr_id_i => adr_i (9 downto 7),
--------------------------------------------------------------- -------------------------------------------------------------
wb_ack_prod_p_o => s_wb_ack_prod, wb_ack_prod_p_o => s_wb_ack_prod,
wb_ack_p_o => ack_o); wb_ack_p_o => ack_o);
--------------------------------------------------------------- -------------------------------------------------------------
---------------------------------------------------------------------------------------------------
end architecture struc; end architecture struc;
......
wf_cons_outcome.vhd
View file @ e1bd8403
...@@ -84,6 +84,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -84,6 +84,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! -> 01/2010 v0.04 EG Unit WF_var_rdy_generator separated in WF_cons_outcome --! -> 01/2010 v0.04 EG Unit WF_var_rdy_generator separated in WF_cons_outcome
--! (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3) --! (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3)
--! -> 02/2010 v0.05 EG Added here functionality of wf_cons_frame_validator --! -> 02/2010 v0.05 EG Added here functionality of wf_cons_frame_validator
--! Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received
--! was always set to 1!)
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -156,8 +158,7 @@ end entity WF_cons_outcome; ...@@ -156,8 +158,7 @@ end entity WF_cons_outcome;
--================================================================================================= --=================================================================================================
architecture rtl of WF_cons_outcome is architecture rtl of WF_cons_outcome is
signal s_var_type_match, s_cons_frame_ok_p : std_logic; signal s_cons_frame_ok_p : std_logic;
signal s_var1_received, s_var2_received : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic; signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
...@@ -260,52 +261,38 @@ begin ...@@ -260,52 +261,38 @@ begin
if nfip_rst_i = '1' then if nfip_rst_i = '1' then
var1_rdy_o <= '0'; var1_rdy_o <= '0';
var2_rdy_o <= '0'; var2_rdy_o <= '0';
s_var1_received <= '0';
s_var2_received <= '0';
else else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
case var_i is
when var_1 => -- nanoFIP consuming
--------------------
var1_rdy_o <= '0'; -- while consuming a var_1, VAR1_RDY is 0
var2_rdy_o <= s_var2_received; -- VAR2_RDY retains its value
-- -- -- -- -- -- -- -- -- -- --
if s_cons_frame_ok_p = '1' then -- only if the received RP_DAT frame is correct,
-- the nanoFIP signals the user to retreive data
s_var1_received <= '1'; -- note:the signal s_var1_received remains asser-
-- ted after the end of the cons_frame_ok_p pulse
end if;
-- VAR1_RDY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (var_i = var_1) and (s_cons_frame_ok_p = '1') then
-- only if the received var_1 RP_DAT frame is correct
var1_rdy_o <= '1'; -- the nanoFIP signals the user to retreive data
-- note: the signal var1_rdy_o remains asserted
-- until the beginning of the arrival of a new var_1
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- elsif (var_i = var_1) then
when var_2 => -- nanoFIP consuming broadcast
------------------------------
var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is 0
var1_rdy_o <= s_var1_received; -- VAR1_RDY retains its value
if slone_i = '0' and s_cons_frame_ok_p = '1' then var1_rdy_o <= '0'; -- while consuming a var_1, VAR1_RDY is 0
-- only in memory mode and if the received RP_DAT
s_var2_received <= '1'; -- frame is correct, the nanoFIP signals the user
-- to retreive data.
-- note:the signal s_var2_received remains asser-
end if; -- ted after the end of the cons_frame_ok_p pulse
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VAR2_RDY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (var_i = var_2) and (s_cons_frame_ok_p = '1') and (slone_i = '0') then
-- only in memory mode and if the received var_2
var2_rdy_o <= '1'; -- RP_DAT is correct the nanoFIP signals the user
-- to retreive data
-- note: the signal var2_rdy_o remains asserted
-- until the beginning of the arrival of a new var_2
when others => elsif (var_i = var_2) then
var1_rdy_o <= s_var1_received; var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is 0
var2_rdy_o <= s_var2_received;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end case;
end if; end if;
end if; end if;
end process; end process;
......
wf_engine_control.vhd
View file @ e1bd8403
...@@ -38,7 +38,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -38,7 +38,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! --!
--! ID_DAT frame structure : --! ID_DAT frame structure :
--! ___________ ______ _______ ______ ___________ _______ --! ___________ ______ _______ ______ ___________ _______
--! |____FSS____|_Ctrl_||__Var__|_Subs_||____FCS____|__FES__| --! |____FSS____|_Ctrl_||__Var__|_SUBS_||____FCS____|__FES__|
--! --!
--! --!
--! Produced RP_DAT frame structure : --! Produced RP_DAT frame structure :
...@@ -208,7 +208,7 @@ architecture rtl of WF_engine_control is ...@@ -208,7 +208,7 @@ architecture rtl of WF_engine_control is
signal control_st, nx_control_st : control_st_t; signal control_st, nx_control_st : control_st_t;
signal s_var_aux, s_var : t_var; signal s_var_aux, s_var : t_var;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_subs_byte : std_logic; signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte : std_logic;
signal s_id_dat_frame_ok, s_cons_wait_FSS, s_consuming, s_prod_wait_turnar_time : std_logic; signal s_id_dat_frame_ok, s_cons_wait_FSS, s_consuming, s_prod_wait_turnar_time : std_logic;
signal s_producing, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic; signal s_producing, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
signal s_rst_rx_bytes_counter, s_inc_rx_bytes_counter, s_var_identified : std_logic; signal s_rst_rx_bytes_counter, s_inc_rx_bytes_counter, s_var_identified : std_logic;
...@@ -457,7 +457,6 @@ begin ...@@ -457,7 +457,6 @@ begin
--------------------------------- ---------------------------------
s_id_dat_ctrl_byte <= '0'; s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0'; s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0'; s_cons_wait_FSS <= '0';
...@@ -472,7 +471,6 @@ begin ...@@ -472,7 +471,6 @@ begin
s_id_dat_ctrl_byte <= '1'; s_id_dat_ctrl_byte <= '1';
--------------------------------- ---------------------------------
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0'; s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0'; s_cons_wait_FSS <= '0';
...@@ -487,7 +485,6 @@ begin ...@@ -487,7 +485,6 @@ begin
--------------------------------- ---------------------------------
s_id_dat_var_byte <= '1'; s_id_dat_var_byte <= '1';
--------------------------------- ---------------------------------
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0'; s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0'; s_cons_wait_FSS <= '0';
...@@ -500,9 +497,6 @@ begin ...@@ -500,9 +497,6 @@ begin
s_idle_state <= '0'; s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0'; s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
---------------------------------
s_id_dat_subs_byte <= '1';
---------------------------------
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0'; s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0'; s_cons_wait_FSS <= '0';
...@@ -515,7 +509,6 @@ begin ...@@ -515,7 +509,6 @@ begin
s_idle_state <= '0'; s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0'; s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
--------------------------------- ---------------------------------
s_id_dat_frame_ok <= '1'; s_id_dat_frame_ok <= '1';
--------------------------------- ---------------------------------
...@@ -530,7 +523,6 @@ begin ...@@ -530,7 +523,6 @@ begin
s_idle_state <= '0'; s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0'; s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
--------------------------------- ---------------------------------
s_prod_wait_turnar_time <= '1'; s_prod_wait_turnar_time <= '1';
...@@ -545,7 +537,6 @@ begin ...@@ -545,7 +537,6 @@ begin
s_idle_state <= '0'; s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0'; s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0'; s_prod_wait_turnar_time <= '0';
--------------------------------- ---------------------------------
...@@ -560,7 +551,6 @@ begin ...@@ -560,7 +551,6 @@ begin
s_idle_state <= '0'; s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0'; s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0'; s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0'; s_cons_wait_FSS <= '0';
...@@ -575,7 +565,6 @@ begin ...@@ -575,7 +565,6 @@ begin
s_idle_state <= '0'; s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0'; s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0'; s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0'; s_cons_wait_FSS <= '0';
...@@ -592,7 +581,6 @@ begin ...@@ -592,7 +581,6 @@ begin
--------------------------------- ---------------------------------
s_id_dat_ctrl_byte <= '0'; s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0'; s_id_dat_var_byte <= '0';
s_id_dat_subs_byte <= '0';
s_id_dat_frame_ok <= '0'; s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0'; s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0'; s_cons_wait_FSS <= '0';
...@@ -649,7 +637,7 @@ begin ...@@ -649,7 +637,7 @@ begin
--! being received by the WF_rx_deserializer unit. The same counter is used for the bytes of an --! being received by the WF_rx_deserializer unit. The same counter is used for the bytes of an
--! ID_DAT frame or a consumed RP_DAT frame (that is why the name of the counter is s_rx_bytes_c --! ID_DAT frame or a consumed RP_DAT frame (that is why the name of the counter is s_rx_bytes_c
--! and not s_cons_bytes_c!) --! and not s_cons_bytes_c!)
--! Regarding an ID_DAT frame : the FSS,Control, var and subs bytes are being followed by the state --! Regarding an ID_DAT frame : the FSS,Control, var and SUBS bytes are being followed by the state
--! machine and the counter is used for the counting of the bytes from then on until the arrival --! machine and the counter is used for the counting of the bytes from then on until the arrival
--! of a FES. Therefore, the counter is reset at the "id_dat_subs_byte" state and counts bytes --! of a FES. Therefore, the counter is reset at the "id_dat_subs_byte" state and counts bytes
--! following the "rx_byte_ready_p_i" pulse in the "id_dat_frame_ok" state. --! following the "rx_byte_ready_p_i" pulse in the "id_dat_frame_ok" state.
...@@ -905,7 +893,7 @@ begin ...@@ -905,7 +893,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment (needed by the FSM) -- Concurrent signal assignment (used by the FSM)
s_var_identified <= '1' when rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue or s_var_identified <= '1' when rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue or rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue or
......
wf_model_constr_decoder.vhd
View file @ e1bd8403
...@@ -112,7 +112,6 @@ end entity WF_model_constr_decoder; ...@@ -112,7 +112,6 @@ end entity WF_model_constr_decoder;
--================================================================================================= --=================================================================================================
architecture rtl of WF_model_constr_decoder is architecture rtl of WF_model_constr_decoder is
signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0); signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0); signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0); signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0);
...@@ -179,9 +178,9 @@ begin ...@@ -179,9 +178,9 @@ begin
uclk_i => uclk_i, uclk_i => uclk_i,
reinit_counter_i => nfip_rst_i, reinit_counter_i => nfip_rst_i,
incr_counter_i => '1', incr_counter_i => '1',
counter_is_full_o => open,
----------------------------------------- -----------------------------------------
counter_o => s_counter, counter_o => s_counter);
counter_is_full_o => s_counter_is_full);
----------------------------------------- -----------------------------------------
......
wf_package.vhd
View file @ e1bd8403
...@@ -236,16 +236,16 @@ package WF_package is ...@@ -236,16 +236,16 @@ package WF_package is
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) := constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD), (c_31K25_INDEX => (turnaround => integer (480000.0 / c_QUARTZ_PERIOD),
silence => integer (5160000.0 / c_QUARTZ_PERIOD)), silence => integer (4096000.0 / c_QUARTZ_PERIOD)),
c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD), c_1M_INDEX => (turnaround => integer (14000.0 / c_QUARTZ_PERIOD),
silence => integer (150000.0 / c_QUARTZ_PERIOD)), silence => integer (150000.0 / c_QUARTZ_PERIOD)),
c_2M5_INDEX => (turnaround => integer (6000.0 / c_QUARTZ_PERIOD), c_2M5_INDEX => (turnaround => integer (6000.0 / c_QUARTZ_PERIOD),
silence => integer (100000.0 / c_QUARTZ_PERIOD)), silence => integer (96000.0 / c_QUARTZ_PERIOD)),
c_RESERVE_INDEX => (turnaround => integer (480000.0 /C_QUARTZ_PERIOD), c_RESERVE_INDEX => (turnaround => integer (480000.0 /C_QUARTZ_PERIOD),
silence => integer (5160000.0 /C_QUARTZ_PERIOD))); silence => integer (4096000.0 /C_QUARTZ_PERIOD)));
......
wf_rx_deglitcher.vhd
View file @ e1bd8403
...@@ -103,7 +103,6 @@ architecture Behavioral of WF_rx_deglitcher is ...@@ -103,7 +103,6 @@ architecture Behavioral of WF_rx_deglitcher is
signal s_rxd_filtered, s_rxd_filtered_d1 : std_logic; signal s_rxd_filtered, s_rxd_filtered_d1 : std_logic;
signal s_rxd_filtered_r_edge_p : std_logic; signal s_rxd_filtered_r_edge_p : std_logic;
signal s_rxd_filtered_f_edge_p : std_logic; signal s_rxd_filtered_f_edge_p : std_logic;
signal s_fd_rxd_no_activity : std_logic;
signal s_deglitch_c : unsigned (3 downto 0); signal s_deglitch_c : unsigned (3 downto 0);
signal s_fd_rxd_synch : std_logic_vector (1 downto 0); signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
......
wf_rx_osc.vhd
View file @ e1bd8403
...@@ -126,8 +126,8 @@ end entity WF_rx_osc; ...@@ -126,8 +126,8 @@ end entity WF_rx_osc;
--================================================================================================= --=================================================================================================
architecture rtl of WF_rx_osc is architecture rtl of WF_rx_osc is
signal s_period_c, s_period, s_jitter : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0); signal s_period_c, s_period, s_margin : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_half_period, s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0); signal s_half_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_reinit_counter, s_counter_is_full : std_logic; signal s_reinit_counter, s_counter_is_full : std_logic;
signal s_adjac_bits_window, s_signif_edge_window : std_logic; signal s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic; signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
...@@ -144,8 +144,8 @@ begin ...@@ -144,8 +144,8 @@ begin
s_counter_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator s_counter_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
s_half_period <= s_period srl 1; -- 1/2 s_period s_half_period <= s_period srl 1; -- 1/2 s_period
s_one_forth_period <= s_period srl 2; -- 1/4 s_period s_margin <= s_period srl 3; -- margin for jitter defined
s_jitter <= s_period srl 3; -- jitter defined as 1/8 s_period -- as 1/8 s_period
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -176,7 +176,8 @@ begin ...@@ -176,7 +176,8 @@ begin
-- if the rx_osc_rst_i is active or -- if the rx_osc_rst_i is active or
-- if an edge is detected in the expected window or -- if an edge is detected in the expected window or
-- if it fills up -- if it fills up
s_reinit_counter <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i) or s_counter_is_full; s_reinit_counter <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i)
or s_counter_is_full;
...@@ -216,7 +217,7 @@ begin ...@@ -216,7 +217,7 @@ begin
-- regarding significant edges: -- regarding significant edges:
-- looking for a significant edge inside the corresponding window -- looking for a significant edge inside the corresponding window
if (s_signif_edge_window = '1') and (fd_rxd_edge_p_i = '1') and (s_signif_edge_found = '0') then if (s_signif_edge_window='1') and (fd_rxd_edge_p_i='1') and (s_signif_edge_found='0') then
s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found s_signif_edge_found <= '1'; -- indication that the edge was found
...@@ -224,7 +225,7 @@ begin ...@@ -224,7 +225,7 @@ begin
-- if a significant edge is not found where expected (code violation), the rx_manch_clk -- if a significant edge is not found where expected (code violation), the rx_manch_clk
-- is inverted right after the end of the signif_edge_window. -- is inverted right after the end of the signif_edge_window.
elsif (s_signif_edge_found = '0') and (s_period_c = s_jitter) then elsif (s_signif_edge_found = '0') and (s_period_c = s_margin) then
s_manch_clk <= not s_manch_clk; s_manch_clk <= not s_manch_clk;
s_adjac_bits_edge_found <= '0'; -- re-initialization before the s_adjac_bits_edge_found <= '0'; -- re-initialization before the
...@@ -246,7 +247,7 @@ begin ...@@ -246,7 +247,7 @@ begin
-- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right -- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
-- after the end of it -- after the end of it
elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_jitter) then elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_margin) then
s_manch_clk <= not s_manch_clk; s_manch_clk <= not s_manch_clk;
s_bit_clk <= not s_bit_clk; s_bit_clk <= not s_bit_clk;
...@@ -274,17 +275,17 @@ begin ...@@ -274,17 +275,17 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Concurrent signal assignments: creation of the windows where --!@brief Concurrent signal assignments: creation of the windows where
--! "significant edges" and "adjacent bits transitions" are expected on the input signal. --! "significant edges" and "adjacent bits transitions" are expected on the input signal.
--! o s_signif_edge_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after --! o s_signif_edge_window : extends s_margin uclk ticks before and s_margin uclk ticks after
--! the completion of a period, where significant edges are expected. --! the completion of a period, where significant edges are expected.
--! o s_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after --! o s_adjac_bits_window : extends s_margin uclk ticks before and s_margin uclk ticks after
--! the middle of a period, where transitions between adjacent bits are expected. --! the middle of a period, where transitions between adjacent bits are expected.
s_signif_edge_window <= '1' when ((s_period_c < s_jitter) or s_signif_edge_window <= '1' when ((s_period_c < s_margin) or
(s_period_c > s_period-1 - s_jitter-1)) (s_period_c > s_period-1 - s_margin-1))
else '0'; else '0';
s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_jitter-1) and s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_margin-1) and
(s_period_c < s_half_period+s_jitter)) (s_period_c < s_half_period+s_margin))
else '0'; else '0';
......
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