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nanoFIP - Gateware
Commit e91158c9 authored by egousiou's avatar egousiou
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LGPL header added to all source files 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@230 7f0067c9-7624-46c7-bd39-3fb5400c0213
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DualClkRAM.vhd
View file @ e91158c9
......@@ -4,58 +4,58 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File DualClkRAM.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- ProASIC3 library
library PROASIC3; -- component specific library
-- ProASIC3 packages
use PROASIC3.all;
---------------------------------------------------------------------------------------------------
-- --
-- DualClkRAM --
-- --
---------------------------------------------------------------------------------------------------
--
-- File DualClkRAM.vhd
--
-- Description Instantiation of a template ProAsic3 RAM4K9 memory component with
-- o word width : 8 bits and
-- o depth : 512 bytes.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 15/12/2010
--
--
-- Version v0.02
--
-- Depends on ProASIC3 lib
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
-- address is given (otherwise it was 2 clock cycles later) slack
-- checked and is ok! code cleaned-up and commented
-- ->15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up
-- 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
-- address is given (otherwise it was 2 clock cycles later) slack
-- checked and is ok! code cleaned-up and commented
-- 15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......
nanofip.vhd
View file @ e91158c9
......@@ -4,37 +4,21 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- @file nanofip.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- nanoFIP --
-- nanoFIP --
-- --
---------------------------------------------------------------------------------------------------
-- File nanofip.vhd
--
--
-- Description
-- The nanoFIP is an FPGA component implementing the WorldFIP protocol that can be used in field
-- devices. The nanoFIP is designed to be radiation tolerant by using different single event upset
-- mitigation techniques such as Triple Module Redundancy and several reset possibilities. The
-- nanoFIP design is to be implemented in an Actel ProASIC3 Flash family FPGA that is preserving
-- its configuration and has high tolerance to total dose radiation effects. The device is used
-- in conjunction with a FIELDRIVE chip and FIELDTR insulating transformer, both available from
-- the company ALSTOM.
-- Description The nanoFIP is an FPGA component implementing the WorldFIP protocol that can be
-- used in field devices. The nanoFIP is designed to be radiation tolerant by using different
-- single event upset mitigation techniques such as Triple Module Redundancy and several reset
-- possibilities. The nanoFIP design is to be implemented in an Actel ProASIC3 Flash family FPGA
-- that is preserving its configuration and has high tolerance to total dose radiation effects.
-- The device is used in conjunction with a FIELDRIVE chip and FIELDTR insulating transformer,
-- both available from the company ALSTOM.
--
-- In the WorldFIP protocol, the master of the bus, Bus Arbitrer (BA) initiates all the activity
-- in the bus. The BA is broadcasting ID_DAT frames, requesting for a particular variable, to all
......@@ -138,14 +122,8 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Authors Erik Van der Bij (Erik.Van.der.Bij@cern.ch)
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 15/01/2011
--
--
-- Version v0.04
--
--
-- Date 20/01/2011
-- Version v0.05
-- Depends on WF_reset_unit
-- WF_model_constr_dec
-- WF_tx_rx_osc
......@@ -153,23 +131,45 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- WF_production
-- WF_engine_control
-- WF_wb_controller
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 30/06/2009 v0.010 EB First version
-- -> 06/07/2009 v0.011 EB Dummy blocks
-- -> 07/07/2009 v0.011 EB Comments
-- -> 15/09/2009 v0.v2 PA
-- -> 09/12/2010 v0.v3 EG Logic removed (new unit inputs_synchronizer added)
-- -> 7/01/2011 v0.04 EG major restructuring; only 7 units on top level
-- -> 20/01/2011 v0.05 EG new unit WF_wb_controller(removes the or gate from top level)
--
-- 30/06/2009 v0.010 EB First version
-- 06/07/2009 v0.011 EB Dummy blocks
-- 07/07/2009 v0.011 EB Comments
-- 15/09/2009 v0.v2 PA
-- 09/12/2010 v0.v3 EG Logic removed (new unit inputs_synchronizer added)
-- 7/01/2011 v0.04 EG major restructuring; only 7 units on top level
-- 20/01/2011 v0.05 EG new unit WF_wb_controller(removes the or gate from top level)
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP
--=================================================================================================
......@@ -218,6 +218,7 @@ entity nanofip is
-- User Interface, WISHBONE Slave
wclk_i : in std_logic; -- WISHBONE clock; may be independent of uclk
adr_i : in std_logic_vector (9 downto 0); -- WISHBONE address
cyc_i : in std_logic; -- WISHBONE cycle
......@@ -233,8 +234,8 @@ entity nanofip is
-- User Interface, JTAG Controller
jc_tdo_i : in std_logic;
jc_tdo_i : in std_logic;
......@@ -279,14 +280,6 @@ entity nanofip is
-- User Interface, JTAG Controller
TP10 : out std_logic;
TP11 : out std_logic;
TP12 : out std_logic;
TP13 : out std_logic;
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
......@@ -340,7 +333,7 @@ architecture struc of nanofip is
signal s_jc_mem_adr_rd : std_logic_vector (8 downto 0);
signal s_jc_tdo_byte : std_logic_vector (7 downto 0);
signal s_jc_tdi_o, s_jc_tms_o, s_jc_tck_o, s_fd_txd_o, s_fd_rstn_o : std_logic;
signal s_jc_tdi_o, s_jc_tms_o, s_jc_tck_o, s_fd_txd_o,s_rston : std_logic;
--=================================================================================================
......@@ -366,10 +359,12 @@ begin
-------------------------------------------------------------
nFIP_rst_o => s_nfip_intern_rst,
wb_rst_o => s_wb_rst,
rston_o => rston_o,
fd_rstn_o => s_fd_rstn_o);
rston_o => s_rston,
fd_rstn_o => fd_rstn_o);
-------------------------------------------------------------
rston_o <= s_rston;
---------------------------------------------------------------------------------------------------
......@@ -421,12 +416,6 @@ begin
rx_byte_ready_p_o => s_rx_byte_ready_p,
rx_fss_crc_fes_ok_p_o => s_rx_fss_crc_fes_ok_p,
rx_fss_received_p_o => s_rx_fss_received_p,
TP14 => TP14,
TP15 => TP15,
TP16 => TP16,
TP39 => TP39,
rx_crc_wrong_p_o => s_rx_crc_wrong_p);
-------------------------------------------------------------
......@@ -498,10 +487,10 @@ begin
fd_txd_o <= s_fd_txd_o;
---------------------------------------------------------------------------------------------------
-- WF_JTAG_player --
-- WF_jtag_controller --
---------------------------------------------------------------------------------------------------
JTAG_player: WF_jtag_player
JTAG_controller: WF_jtag_controller
port map (
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
......@@ -509,28 +498,14 @@ begin
jc_start_p_i => s_jc_start_p,
jc_tdo_i => jc_tdo_i,
-----------------------------------------------------------------
jc_tms_o => s_jc_tms_o,
jc_tdi_o => s_jc_tdi_o,
jc_tck_o => s_jc_tck_o,
jc_tms_o => jc_tms_o,
jc_tdi_o => jc_tdi_o,
jc_tck_o => jc_tck_o,
jc_tdo_byte_o => s_jc_tdo_byte,
jc_mem_adr_rd_o => s_jc_mem_adr_rd);
-----------------------------------------------------------------
-- TP39 <= jc_tdo_i;
TP10 <= fd_wdgn_i; --s_jc_tck_o;--s_jc_tms_o;
TP11 <= not (s_fd_rstn_o);-- s_jc_tdi_o;
TP12 <= s_nfip_intern_rst;--s_rx_crc_wrong_p;--s_jc_tck_o;
TP13 <= fd_txer_i; --s_rx_crc_wrong_p;
-- TP14 <= s_rx_fss_received_p;
-- TP15 <= s_rx_fss_crc_fes_ok_p;
fd_rstn_o <= s_fd_rstn_o;
jc_tms_o <= s_jc_tms_o;
jc_tdi_o <= s_jc_tdi_o;
jc_tck_o <= s_jc_tck_o;
---------------------------------------------------------------------------------------------------
-- WF_engine_control --
......
wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ e91158c9
......@@ -6,25 +6,12 @@
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_DualClkRAM_clka_rd_clkb_wr.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_DualClkRAM_clka_rd_clkb_wr --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_DualClkRAM_clka_rd_clkb_wr.vhd
--
-- Description The unit provides the memory triplication, transparently to the outside world.
-- The component DualClkRam (512 bytes) is triplicated: each incoming byte is written
......@@ -37,24 +24,40 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 10/12/2010
--
--
-- Version v0.02
--
--
-- Depends on DualClkRAM.vhd
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 12/2010 v0.02 EG code cleaned-up+commented
--
-- 12/2010 v0.02 EG code cleaned-up+commented
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......
wf_bits_to_txd.vhd
View file @ e91158c9
......@@ -4,59 +4,62 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_bits_to_txd.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_bits_to_txd --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_bits_to_txd.vhd
--
-- Description According to the state of the FSM of the WF_tx_serializer, the unit is responsible
-- for putting in nanoFIP's output FD_TXD one by one all the bits required for the
-- formation of the RP_DAT frame (that is: manch. encoded FSS, data, CRC and FES bits).
-- The unit also manages the output FD_TXENA.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 07/01/2011
--
--
-- Version v0.03
--
--
-- Depends on WF_reset_unit
-- WF_tx_osc
-- WF_tx_serializer
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 8/2010 v0.02 EG tx_enable has to be synched with txd! sending_fss not enough;
-- need for tx_sched_p_buff signal
-- -> 7/1/2011 v0.03 EG tx_enable now starts 1 uclk tick earlier, at the same moment as txd
-- becomes 1 for the 1st bit of preamble
-- signals s_tx_enable & s_start_tx_enable removed for simplification
-- 8/2010 v0.02 EG tx_enable has to be synched with txd! sending_fss not enough;
-- need for tx_sched_p_buff signal
-- 7/1/2011 v0.03 EG tx_enable now starts 1 uclk tick earlier, at the same moment as txd
-- becomes 1 for the 1st bit of preamble
-- signals s_tx_enable & s_start_tx_enable removed for simplification
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......
wf_cons_bytes_processor.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_cons_bytes_processor.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_bytes_processor --
-- --
-- |
-- WF_cons_bytes_processor |
-- |
---------------------------------------------------------------------------------------------------
--
-- File WF_cons_bytes_processor.vhd
--
-- Description The unit is consuming the RP_DAT data bytes that are arriving from the
-- WF_fd_receiver, according to the following:
......@@ -59,38 +45,52 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- |-----to DAT_O-----|
-- |---to Reset Unit--|
--
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 15/12/2010
--
--
-- Version v0.03
--
--
-- Depends on WF_reset_unit
-- WF_fd_receiver
-- WF_engine_control
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 11/09/2009 v0.01 EB First version
-- -> 09/2010 v0.02 EG Treatment of reset variable added; Bytes_Transfer_To_DATO unit
-- creation for simplification; Signals renamed;
-- Ctrl, PDU_TYPE, Length bytes registered;
-- Code cleaned-up & commented.
-- -> 15/12/2010 v0.03 EG Unit renamed from WF_cons_bytes_from_rx to WF_cons_bytes_processor
-- byte_ready_p comes from the rx_deserializer (no need to pass from
-- the engine) Code cleaned-up & commented (more!)
--
-- 11/09/2009 v0.01 EB First version
-- 09/2010 v0.02 EG Treatment of reset variable added; Bytes_Transfer_To_DATO unit
-- creation for simplification; Signals renamed;
-- Ctrl, PDU_TYPE, Length bytes registered;
-- Code cleaned-up & commented.
-- 15/12/2010 v0.03 EG Unit renamed from WF_cons_bytes_from_rx to WF_cons_bytes_processor
-- byte_ready_p comes from the rx_deserializer (no need to pass from
-- the engine) Code cleaned-up & commented (more!)
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------- |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_cons_bytes_processor
......@@ -122,7 +122,7 @@ port (
var_i : in t_var; -- variable type that is being treated
-- Signals from the WF_jtag_player unit
-- Signals from the WF_jtag_controller unit
jc_mem_adr_rd_i : in std_logic_vector (8 downto 0);
......@@ -130,7 +130,7 @@ port (
-- nanoFIP User Interface, WISHBONE Slave output
data_o : out std_logic_vector (15 downto 0); -- data out bus
-- Signals to the WF_jtag_player unit
-- Signals to the WF_jtag_controller unit
jc_mem_data_o : out std_logic_vector (7 downto 0);
-- Signals to the WF_cons_outcome unit
......@@ -140,7 +140,6 @@ port (
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 1st data byte
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0) -- received var_rst RP_DAT, 2nd data byte
);
end entity WF_cons_bytes_processor;
......@@ -193,7 +192,7 @@ begin
---------------------------------------------------------------------------------------------------
-- JTAG Consumed RAM --
-- Storage (by this unit) & retreival (by the JTAG_player unit) of consumed bytes --
-- Storage (by this unit) & retreival (by the JTAG_controller unit) of consumed bytes --
---------------------------------------------------------------------------------------------------
-- Instantiation of a Dual Port Consumed RAM (for both the consumed and consumed broadcast vars).
-- Port A is connected to the WISHBONE interface for the readings from the user and
......@@ -491,7 +490,7 @@ end process;
s_cons_lgth_byte <= (others => '0');
else
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_jc1) then -- only for consumed vars
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_jc1)then -- only for consumed vars
if (byte_index_i = c_CTRL_BYTE_INDEX) and (byte_ready_p_i='1') then
cons_ctrl_byte_o <= byte_i;
......
wf_cons_outcome.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_cons_outcome.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_outcome --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_cons_outcome.vhd
--
-- Description The unit starts by validating a consumed RP_DAT frame with respect to the
-- correctness of:
......@@ -55,37 +41,53 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 22/02/2011
--
--
-- Version v0.05
--
--
-- Depends on WF_reset_unit
-- WF_engine_control
-- WF_fd_receiver
-- WF_consumption
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 10/2010 v0.01 EG First version
-- -> 11/2010 v0.02 EG Treatment of reset vars added to the unit
-- Correction on var1_rdy, var2_rdy for slone
-- -> 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting
-- -> 01/2010 v0.04 EG Unit WF_var_rdy_generator separated in WF_cons_outcome
-- (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3)
-- -> 02/2010 v0.05 EG Added here functionality of wf_cons_frame_validator
-- Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received
-- was always set to 1!)
-- Added check of Ctrl byte for rtler
-- Added cons_bytes_excess_i for tracking of too long RP_DATs
--
-- 10/2010 v0.01 EG First version
-- 11/2010 v0.02 EG Treatment of reset vars added to the unit
-- Correction on var1_rdy, var2_rdy for slone
-- 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting
-- 01/2010 v0.04 EG Unit WF_var_rdy_generator separated in WF_cons_outcome
-- (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3)
-- 02/2010 v0.05 EG Added here functionality of wf_cons_frame_validator
-- Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received
-- was always set to 1!)
-- Added check of Ctrl byte for rtler
-- Added cons_bytes_excess_i for tracking of too long RP_DATs
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......@@ -131,7 +133,7 @@ entity WF_cons_outcome is
var1_rdy_o : out std_logic; -- signals new data is received and can safely be read
var2_rdy_o : out std_logic; -- signals new data is received and can safely be read
-- Signal to the WF_JTAG_player unit
-- Signal to the WF_jtag_controller unit
jc_start_p_o : out std_logic;
-- Signal to the WF_status_bytes_gen unit
......@@ -317,7 +319,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- JTAG_player -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- JTAG_controller -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (var_i = var_jc1) and (s_cons_frame_ok_p = '1') then
jc_start_p_o <= '1';
......
wf_consumption.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_consumption.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_consumption --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_consumption.vhd
--
-- Description The unit groups the main actions that regard data consumption.
-- It instantiates the units:
......@@ -72,26 +58,42 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 11/01/2011
--
--
-- Version v0.01
--
--
-- Depends on WF_reset_unit
-- WF_fd_receiver
-- WF_engine_control
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- ->
--
-- 01/2011 EG v0.01 first version
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......@@ -161,7 +163,7 @@ entity WF_consumption is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_jtag_player unit
-- Signal from the WF_jtag_controller unit
jc_mem_adr_rd_i : in std_logic_vector (8 downto 0);
......@@ -172,7 +174,7 @@ entity WF_consumption is
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
-- Signals to the WF_JTAG_player
-- Signals to the WF_jtag_controller
jc_start_p_o : out std_logic;
-- nanoFIP User Interface, WISHBONE Slave outputs
......@@ -185,7 +187,7 @@ entity WF_consumption is
assert_rston_p_o : out std_logic;
rst_nfip_and_fd_p_o : out std_logic;
-- Signals to the WF_jtag_player unit
-- Signals to the WF_jtag_controller unit
jc_mem_data_o : out std_logic_vector (7 downto 0)
);
......
wf_crc.vhd
View file @ e91158c9
......@@ -4,61 +4,61 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_crc.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_crc --
-- --
---------------------------------------------------------------------------------------------------
--
--
-- File WF_crc.vhd
-- Description The unit creates the modules for:
-- o the generation of the CRC of serial data,
-- o the verification of an incoming CRC syndrome.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--
--
-- Date 23/02/2011
--
--
-- Version v0.04
--
--
-- Depends on WF_reset_unit
-- WF_rx_deserializer
-- WF_tx_serializer
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content
-- -> 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
-- variable v_q_check_mask replaced with a signal,
-- code cleaned-up+commented
-- -> 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list!
-- xor replaced with if(Syndrome_Verification); processes rewritten;
-- delay on data_bit_ready_p_i removed.
--
-- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content
-- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
-- variable v_q_check_mask replaced with a signal,
-- code cleaned-up+commented
-- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list!
-- xor replaced with if(Syndrome_Verification); processes rewritten;
-- delay on data_bit_ready_p_i removed.
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_crc
......
wf_decr_counter.vhd
View file @ e91158c9
......@@ -4,49 +4,52 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- file WF_decr_counter.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- WF_decr_counter --
-- --
---------------------------------------------------------------------------------------------------
--
--
-- Description Decreasing counter with synchronous reset, load enable and decrease enable.
--
--
-- File WF_decr_counter.vhd
-- Description Decreasing counter with synchronous reset, load enable and decrease enable
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 10/2010
--
--
-- Version v0.01
--
--
-- Depends on WF_reset_unit
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
--
-- 10/2010 EG v0.01 first version
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_decr_counter
--=================================================================================================
......
wf_engine_control.vhd
View file @ e91158c9
......@@ -4,28 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_engine_control.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_engine_control --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_engine_control.vhd
--
-- Description The WF_engine_control is following the reception of an incoming ID_DAT frame and
-- o identifies the variable to be treated
......@@ -58,24 +43,14 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Silence time : Maximum time that nanoFIP waits for a consumed RP_DAT frame after
-- the reception of an ID_DAT frame indicating a variable to be consumed.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch),
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 15/01/2011
--
--
-- Version v0.04
--
--
-- Version v0.06
-- Depends on WF_reset_unit
-- WF_fd_transmitter
-- WF_fd_receiver
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- 07/2009 v0.01 EB First version
-- 08/2010 v0.02 EG E0 added as broadcast
......@@ -94,11 +69,37 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- cons_bytes_excess_o added
-- tx_completed_p_i added (bf for the engine ctrl production was finished
-- after the delivery of the last data byte (MPS))
--
-- 07/2011 v0.06 EG rst_rx state added
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_engine_control
--=================================================================================================
......@@ -164,8 +165,9 @@ entity WF_engine_control is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the WF_fd_receiver
rx_rst_o : out std_logic; -- reset during production or
-- reset pulse when consumption is lasting more than
-- expected (ID_DAT > 8 bytes, RP_DAT > 133 bytes)
-- reset pulse when during reception a frame is rejected
-- (example: ID_DAT > 8 bytes, RP_DAT > 133 bytes,
-- wrong ID_DAT Ctrl, variable, subs bytes)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the WF_consumption unit
......@@ -237,10 +239,12 @@ begin
-- o if the variable byte corresponds to a defined variable,
-- o if the subscriber byte matches the station's address, or if the variable is a broadcast
-- o and if the frame finishes with a correct CRC and FES.
-- If the received variable is a produced (var_presence, var_identif, var_3, var_jc3) the FSM stays
-- in the "produce_wait_turnar_time" state until the expiration of the turnaround time and then
-- jumps to the "produce" state, waiting for the WF_fd_serializer to finish the transmission;
-- then it goes back to idle.
-- If any of the bytes above has been different than the expected, the FSM goes back to idle after
-- resetting the WF_fd_receiver.
-- If the ID_DAT frame has been correct and the received variable is a produced (var_presence,
-- var_identif, var_3, var_jc3) the FSM stays in the "produce_wait_turnar_time" state until the
-- expiration of the turnaround time and then jumps to the "produce" state, waiting for the
-- WF_fd_serializer to finish the transmission; then it goes back to idle.
-- If the received variable is a consumed (var_1, var_2, var_rst, var_jc1) the FSM stays in the
-- "consume_wait_FSS" state until the arrival of a FSS or the expiration of the silence time.
-- After the arrival of a FSS the FSM jumps to the "consume" state, where it stays until the
......@@ -279,7 +283,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when idle =>
if rx_fss_received_p_i = '1' then -- FSS arrived
if rx_fss_received_p_i = '1' then -- new frame FSS detected
nx_control_st <= id_dat_control_byte;
else
......@@ -291,13 +295,13 @@ begin
when id_dat_control_byte =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= idle; --rst_rx;
nx_control_st <= rst_rx;
elsif (rx_byte_ready_p_i = '1') and (rx_byte_i(5 downto 0) = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte; -- check of ID_DAT Control byte
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= idle;-- rst_rx; -- byte different than the expected ID_DAT Control
nx_control_st <= rst_rx; -- byte different than the expected ID_DAT Control
else
nx_control_st <= id_dat_control_byte;-- ID_DAT Control byte being arriving
......@@ -308,13 +312,13 @@ begin
when id_dat_var_byte =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= idle;--rst_rx;
nx_control_st <= rst_rx;
elsif (rx_byte_ready_p_i = '1') and (s_var_identified = '1') then
nx_control_st <= id_dat_subs_byte; -- check of the ID_DAT variable
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= idle;--rst_rx; -- byte not corresponding to an expected variable
nx_control_st <= rst_rx; -- byte not corresponding to an expected variable
else
nx_control_st <= id_dat_var_byte; -- ID_DAT variable byte being arriving
......@@ -325,7 +329,7 @@ begin
when id_dat_subs_byte =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= idle;--rst_rx;
nx_control_st <= rst_rx;
elsif (rx_byte_ready_p_i = '1') and ((rx_byte_i = subs_i) or (s_broadcast_var = '1')) then
nx_control_st <= id_dat_frame_ok; -- check of the ID_DAT subscriber
......@@ -336,7 +340,7 @@ begin
-- also in stand-alone mode.
elsif rx_byte_ready_p_i = '1' then -- not the station's address, neither a broadcast
nx_control_st <= idle;--rst_rx;
nx_control_st <= rst_rx;
else
nx_control_st <= id_dat_subs_byte; -- ID_DAT subscriber byte being arriving
......@@ -347,7 +351,7 @@ begin
when id_dat_frame_ok =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= idle;--rst_rx;
nx_control_st <= rst_rx;
elsif (rx_fss_crc_fes_ok_p_i = '1') and (s_prod_or_cons = "10") then
nx_control_st <= produce_wait_turnar_time; -- ID_DAT frame ok! station has to produce
......@@ -356,7 +360,7 @@ begin
nx_control_st <= consume_wait_FSS; -- ID_DAT frame ok! station has to consume
elsif (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber
nx_control_st <= idle;--rst_rx; -- byte, a FES has not been detected
nx_control_st <= rst_rx; -- byte, a FES has not been detected
else
nx_control_st <= id_dat_frame_ok; -- CRC & FES bytes being arriving
......@@ -367,7 +371,7 @@ begin
when produce_wait_turnar_time =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= idle;--rst_rx;
nx_control_st <= idle;
elsif s_time_c_is_zero = '1' then -- turnaround time passed
nx_control_st <= produce;
......@@ -381,13 +385,13 @@ begin
when consume_wait_FSS =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= idle;
nx_control_st <= rst_rx;
elsif rx_fss_received_p_i = '1' then -- FSS of the consumed RP_DAT arrived
nx_control_st <= consume;
elsif s_time_c_is_zero = '1' then -- if the FSS of the consumed RP_DAT frame doesn't
nx_control_st <= idle;--rst_rx; -- arrive before the expiration of the silence time,
nx_control_st <= rst_rx; -- arrive before the expiration of the silence time,
-- the engine goes back to idle
else
nx_control_st <= consume_wait_FSS; -- counting silence time
......@@ -398,13 +402,14 @@ begin
when consume =>
if s_session_timedout = '1' then -- independent timeout
nx_control_st <= idle;--rst_rx;
nx_control_st <= rst_rx;
elsif (rx_fss_crc_fes_ok_p_i = '1') or -- the cons frame arrived to the end, as expected
(rx_crc_wrong_p_i = '1') or -- FES detected but wrong CRC or wrong # bits
(s_rx_bytes_c > 130) then -- no FES detected after the max number of bytes
(rx_crc_wrong_p_i = '1') then -- FES detected but wrong CRC or wrong # bits
nx_control_st <= idle;
nx_control_st <= idle;--rst_rx; -- back to idle
elsif (s_rx_bytes_c > c_MAX_FRAME_BYTES) then -- no FES detected after the max number of bytes
nx_control_st <= rst_rx;
else
nx_control_st <= consume; -- consuming bytes
......@@ -564,7 +569,7 @@ begin
s_producing <= '0';
when produce =>
when rst_rx =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -576,10 +581,10 @@ begin
---------------------------------
s_rst_rx_p <= '1';
---------------------------------
s_producing <= '1';
s_producing <= '0';
when rst_rx =>
when produce =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
......@@ -985,18 +990,20 @@ begin
-- index of the byte being consumed or produced
prod_cons_byte_index_o <= s_prod_byte_index when s_producing = '1' else s_rx_byte_index;
-- The WF_rx_deserializer is reset if the number of bytes that have arrived exceeds the expected
-- one (ID_DAT >8 bytes and consumed RP_DAT > 133 bytes).
-- It also stays reset during a production session.
-- Note: the first 5 bytes of an ID_DAT and 2 bytes of an RP_DAT have been covered in the other
-- states of the Engine_Control_FSM and the s_rx_bytes_c starts counting from 0!
rx_rst_o <= '1' when --s_rst_rx_p = '1' or
(s_id_dat_frame_ok = '1'and (s_rx_bytes_c > 2)) or
((s_consuming = '1') and (s_rx_bytes_c > 130)) or
(s_prod_wait_turnar_time = '1' or s_producing = '1') else '0';
-- The WF_fd_receiver receives a 1 uclk long reset pulse if during the reception of an ID or an
-- RP_DAT the engine control FSM goes back to idle.
-- This may happen if : any of the Ctrl, variable, subs bytes of an ID_DAT frame are wrong or
-- an ID_DAT is lasting more than 8 bytes or
-- an RP_DAT is lasting more than 133 bytes or
-- the silence times expires --------------------------------------------------------------------------------
-- the engine control FSM times out
-- The receiver discards the frame that was being received and restarts looking for the FSS of a new one.
-- The WF_fd_receiver also stays reset during a production session.
rx_rst_o <= '1' when (s_rst_rx_p = '1') or
(s_prod_wait_turnar_time = '1') or (s_producing = '1') else '0';
-- indication of a consumed RP_DAT frame with more than 133 bytes
cons_bytes_excess_o <= '1' when (s_consuming = '1') and (s_rx_bytes_c > 130) else '0';
cons_bytes_excess_o <= '1' when (s_consuming = '1') and (s_rx_bytes_c > c_MAX_FRAME_BYTES) else '0';
-- production starts after the expiration of the turnaround time
tx_start_p_o <= s_tx_start_prod_p;
......
wf_fd_receiver.vhd
View file @ e91158c9
......@@ -5,25 +5,12 @@
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_fd_receiver.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_fd_receiver --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_fd_receiver.vhd
--
-- Description The unit groups the main actions that regard FIELDRIVE data reception.
-- It instantiates the units:
......@@ -65,27 +52,43 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 15/02/2011
--
--
-- Version v0.01
--
--
-- Depends on WF_reset_unit
-- WF_engine_control
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- ->
--
-- 02/2011 v0.01 EG First version
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_fd_receiver
--=================================================================================================
......@@ -120,16 +123,9 @@ entity WF_fd_receiver is
rx_crc_wrong_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- wrong CRC; pulse upon FES detection
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
-- Signals to the WF_engine_control
rx_fss_received_p_o : out std_logic -- pulse upon FSS detection (ID/ RP_DAT)
);
end entity WF_fd_receiver;
......@@ -210,12 +206,6 @@ begin
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p_o,
rx_osc_rst_o => s_rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
TP14 => TP14,
TP15 => TP15,
TP16 => TP16,
TP39 => TP39,
crc_wrong_p_o => rx_crc_wrong_p_o);
------------------------------------------------------
......
wf_fd_transmitter.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_fd_transmitter.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_fd_transmitter --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_fd_transmitter.vhd
--
-- Description The unit groups the main actions that regard FIELDRIVE data transmission.
-- It instantiates the units:
......@@ -62,32 +48,45 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- 0_____________________________FIELDBUS______________________________O
--
--
--
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 11/01/2011
--
--
-- Version v0.01
--
--
-- Depends on WF_reset_unit
-- WF_production
-- WF_engine_control
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- ->
--
-- 01/2011 EG v0.01 first version
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_fd_transmitter
......
wf_incr_counter.vhd
View file @ e91158c9
......@@ -4,50 +4,52 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_incr_counter.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- WF_incr_counter --
-- --
---------------------------------------------------------------------------------------------------
--
--
-- Description Increasing counter with synchronous reset, reinitialise and increase enable.
--
--
-- File WF_incr_counter.vhd
-- Description Increasing counter with synchronous reset, reinitialise and increase enable
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 10/2010
--
--
-- Version v0.01
--
--
-- Depends on
--
--
---------------------------------------------------------------------------------------------------
--
-- Date 01/2011
-- Version v0.011
----------------
-- Last changes
-- -> 01/2011 EG v0.011 counter_full became a constant
--
-- 10/2010 EG v0.01 first version
-- 01/2011 EG v0.011 counter_full became a constant
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_incr_counter
--=================================================================================================
......
wf_jtag_controller.vhd 0 → 100644
View file @ e91158c9
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_jtag_controller --
-- --
---------------------------------------------------------------------------------------------------
-- File WF_jtag_controller.vhd
--
-- Description After the reception and validation of a consumed var_jc1 RP_DAT frame, the unit is
-- responsible for driving the "nanoFIP, User Interface, JTAG Controller" signals
-- JC_TCK, JC_TMS, JC_TDI and for sampling the JC_TDO input.
-- o JC_TCK is a 5 MHz clock generated by the 40 MHz uclk; a cycle is created for
-- every JC_TMS/ JC_TDI pair.
-- o JC_TMS and JC_TDI are being retreived from the JC_consumed memory and are
-- put to the corresponding outputs on each falling edge of the JC_TCK.
-- Bytes 0 and 1 of the JC_consumed memory do not contain JC_TMS and JC_TDI bits,
-- but are used to indicate, in big indian order, the amount of JC_TMS and JC_TDI
-- bits that have to be output.
--
-- o the JC_TDO input is sampled on the rising edge of JC_TCK; only the last sampled
-- JC_TDO bit is significant and it is registered and sent at the next var_jc2
-- produced frame.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 07/07/2011
-- Version v0.01
-- Depends on WF_reset_unit
-- WF_consumption
----------------
-- Last changes
-- 07/07/2011 v0.01 EG First version
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_jtag_controller
--=================================================================================================
entity WF_jtag_controller is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- nanoFIP User Interface, JTAG Controller signal
jc_tdo_i : in std_logic; -- JTAG TDO input
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the WF_consumption unit
jc_mem_data_i : in std_logic_vector (7 downto 0); -- byte retreived from the JC_cons memory
jc_start_p_i : in std_logic; -- pulse upon validation of a jc_var1 RP_DAT frame
-- OUTPUTS
-- nanoFIP User Interface, JTAG Controller signals
jc_tms_o : out std_logic; -- JTAG TMS output
jc_tdi_o : out std_logic; -- JTAG TDI output
jc_tck_o : out std_logic; -- JTAG TCK output
-- Signal to the WF_production unit
jc_tdo_byte_o : out std_logic_vector (7 downto 0);-- byte containing the TDO sample
-- Signal to the WF_consumption unit
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0) -- address of byte to be retreived from the JC_cons memory
);
end entity WF_jtag_controller;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_jtag_controller is
type jc_st_t is (idle, get_byte, play_byte, set_address);
signal jc_st, nx_jc_st : jc_st_t;
signal s_idle, s_get_byte, s_play_byte, s_set_adr : std_logic;
signal s_bytes_c_reinit, s_bytes_c_incr : std_logic;
signal s_bytes_c, s_bytes_c_d1 : unsigned (6 downto 0);
signal s_frame_bits_lsb, s_frame_bits_msb : std_logic_vector (7 downto 0);
signal s_frame_bits, s_bits_so_far : unsigned (15 downto 0);
signal s_tck_c_reinit, s_tck_c_incr, s_tck_c_is_full: std_logic;
signal s_tck : std_logic;
signal s_tck_c, s_tck_period, s_tck_four_periods : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
signal s_tck_half_period, s_tck_quarter_period : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FSM --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process JC_FSM_Sync: storage of the current state of the FSM
JC_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_st <= idle;
else
jc_st <= nx_jc_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process JC_FSM_Comb_State_Transitions: Definition of the state
-- transitions of the FSM.
-- 2 first bytes : big indian number of bits to be considered in this frame
-- s_bits_so_far : number of treated TMS and TDI bits
-- (s_frame_bits - s_bits_so_far) srl 1 : remaining number of TMS/ TDI pairs
-- 2 ^ (c_JC_TCK_DIV'left) : number of uclk cycles for 1 JC_TCK period
JC_FSM_Comb_State_Transitions: process (jc_st, s_bytes_c, s_frame_bits, s_bits_so_far,
jc_start_p_i, s_tck_c, s_tck_c_is_full)
begin
case jc_st is
when idle =>
if jc_start_p_i = '1' then -- consumed jc_var1 frame validated
nx_jc_st <= set_address;
else
nx_jc_st <= idle;
end if;
when set_address =>
nx_jc_st <= get_byte; -- 1 uclk cycle for the setting of the memory
-- address; byte available at the next cycle
when get_byte =>
if s_bytes_c < 2 then -- 2 first bytes: number of jc_TMS & JC_TDI bits
nx_jc_st <= set_address;
else -- the rest of the bytes have to be output
nx_jc_st <= play_byte;
end if;
when play_byte =>
if s_frame_bits = 0 or s_frame_bits > c_MAX_FRAME_BITS then -- outside expected limits
nx_jc_st <= idle;
elsif s_frame_bits - s_bits_so_far > 8 then -- full bytes still available
if s_tck_c_is_full = '1' then -- byte completed
nx_jc_st <= set_address;
else -- byte being output
nx_jc_st <= play_byte;
end if;
elsif s_frame_bits - s_bits_so_far = 8 then -- last full byte
if s_tck_c_is_full = '1' then -- byte completed
nx_jc_st <= idle;
else -- byte being output
nx_jc_st <= play_byte;
end if;
else -- bits of last byte
if s_tck_c < (((s_frame_bits - s_bits_so_far) srl 1) sll c_JC_TCK_DIV'left) -1 then
nx_jc_st <= play_byte;
else
nx_jc_st <= idle;
end if;
end if;
when others =>
nx_jc_st <= idle;
end case;
end process;
JCtrler_FSM_Comb_Output_Signals: process (jc_st)
begin
case jc_st is
when idle =>
---------------------------------
s_idle <= '1';
---------------------------------
s_set_adr <= '0';
s_get_byte <= '0';
s_play_byte <= '0';
when set_address =>
s_idle <= '0';
---------------------------------
s_set_adr <= '1';
---------------------------------
s_get_byte <= '0';
s_play_byte <= '0';
when get_byte =>
s_idle <= '0';
s_set_adr <= '0';
---------------------------------
s_get_byte <= '1';
---------------------------------
s_play_byte <= '0';
when play_byte =>
s_idle <= '0';
s_set_adr <= '0';
s_get_byte <= '0';
---------------------------------
s_play_byte <= '1';
---------------------------------
end case;
end process;
---------------------------------------------------------------------------------------------------
-- JC_TCK generation --
---------------------------------------------------------------------------------------------------
-- Instantiation of a WF_incr_counter used for the generation of the 5 MHz JC_TCK output clock.
-- The counter is filled up after having counted 4 JC_TCK periods; this corresponds to the amount
-- of periods needed for outputting a full JC_TMS/ JC_TDI byte;
JC_TCK_periods_counter: WF_incr_counter
generic map (g_counter_lgth => c_FOUR_JC_TCK_C_LGTH)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_tck_c_reinit,
incr_counter_i => s_tck_c_incr,
counter_is_full_o => s_tck_c_is_full,
------------------------------------------
counter_o => s_tck_c);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
JC_TCK_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_tck <= '1';
else
if (s_tck_c >= s_tck_quarter_period and s_tck_c < s_tck_half_period+s_tck_quarter_period) or
(s_tck_c >= (2*s_tck_half_period) +s_tck_quarter_period and s_tck_c < (3*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c >= (4*s_tck_half_period) +s_tck_quarter_period and s_tck_c < (5*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c >= (6*s_tck_half_period) +s_tck_quarter_period and s_tck_c < (7*s_tck_half_period) +s_tck_quarter_period) then
s_tck <= '0';
else
s_tck <= '1';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_tck_four_periods <= (others => '1'); -- # uclk ticks for 4 JC_TCK periods i.e delivery of 1 byte
s_tck_period <= (s_tck_four_periods srl 2)+1; -- # uclk ticks for 1 JC_TCK period
s_tck_half_period <= (s_tck_four_periods srl 3)+1; -- # uclk ticks for 1/2 JC_TCK period
s_tck_quarter_period <= (s_tck_four_periods srl 4)+1; -- # uclk ticks for 1/4 JC_TCK period
jc_tck_o <= s_tck;
---------------------------------------------------------------------------------------------------
-- Bytes counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a WF_incr_counter for the bytes that are being retreived from the JC_cons memory.
JC_bytes_count: WF_incr_counter
generic map (g_counter_lgth => 7)
port map (
uclk_i => uclk_i,
reinit_counter_i => s_bytes_c_reinit,
incr_counter_i => s_bytes_c_incr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_bytes_c);
------------------------------------------
jc_mem_adr_rd_o <= std_logic_vector (resize((s_bytes_c + 2), jc_mem_adr_rd_o'length));
-- "+2" is bc the first 2 bytes in the memory (PDU_TYPE and Lenght) are not read
s_bits_so_far <= (resize((s_bytes_c-2), s_frame_bits'length)) sll 3;
-- "-2" is bc the first 2 bytes read from the memory, represent the number of TMS
-- and TDI bits and are not to be played
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process that according to the state of the FSM sets values to the
-- JC_TCK_periods_counter and JC_bytes_count inputs.
Bit_Index: process (s_idle, s_set_adr, s_get_byte, s_play_byte)
begin
--------------------------------------
if s_idle ='1' then
-- bytes counter reinitialization
s_bytes_c_reinit <= '1';
s_bytes_c_incr <= '0';
-- JC_TCK counter reinitialization
s_tck_c_reinit <= '1';
s_tck_c_incr <= '0';
--------------------------------------
elsif s_set_adr = '1' then
-- bytes counter counting
s_bytes_c_reinit <= '0';
s_bytes_c_incr <= '1';
-- JC_TCK counter reinitialization
s_tck_c_reinit <= '1';
s_tck_c_incr <= '0';
--------------------------------------
elsif s_get_byte = '1' then
-- bytes counter retains previous value
s_bytes_c_reinit <= '0';
s_bytes_c_incr <= '0';
-- JC_TCK counter reinitialization
s_tck_c_reinit <= '1';
s_tck_c_incr <= '0';
--------------------------------------
elsif s_play_byte = '1' then
-- bytes counter retains previous value
s_bytes_c_reinit <= '0';
s_bytes_c_incr <= '0';
-- JC_TCK counter counting
s_tck_c_reinit <= '0';
s_tck_c_incr <= '1';
--------------------------------------
else
-- bytes counter
s_bytes_c_reinit <= '1';
s_bytes_c_incr <= '0';
-- JC_TCK counter reinitialization
s_tck_c_reinit <= '1';
s_tck_c_incr <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Number of TMS and TDI bits retreival --
---------------------------------------------------------------------------------------------------
Bits_Number_Retreival: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_bytes_c_d1 <= (others => '0');
s_frame_bits_msb <= (others => '0');
s_frame_bits_lsb <= (others => '0');
else
s_bytes_c_d1 <= s_bytes_c;
if s_bytes_c_d1 = 0 then
s_frame_bits_msb <= jc_mem_data_i;
end if;
if s_bytes_c_d1 = 1 then
s_frame_bits_lsb <= jc_mem_data_i;
end if;
end if;
end if;
end process;
s_frame_bits <= unsigned(s_frame_bits_msb) & unsigned (s_frame_bits_lsb);
---------------------------------------------------------------------------------------------------
-- TMS and TDI player --
---------------------------------------------------------------------------------------------------
JC_TMS_TDI_output: process (s_tck, nfip_rst_i)
begin
if nfip_rst_i = '1' then -- asynchronous reset
jc_tms_o <= '0';
jc_tdi_o <= '0';
elsif falling_edge (s_tck) then
if s_tck_c < (s_tck_period) then -- 1st JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(7);
jc_tdi_o <= jc_mem_data_i(6);
elsif s_tck_c < (s_tck_period sll 1) then -- 2nd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(5);
jc_tdi_o <= jc_mem_data_i(4);
elsif s_tck_c < ((s_tck_period sll 1)+s_tck_period) then -- 3rd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(3);
jc_tdi_o <= jc_mem_data_i(2);
else
jc_tms_o <= jc_mem_data_i(1); -- 4th JC_TMS/ JC_TDI pair
jc_tdi_o <= jc_mem_data_i(0);
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------
-- TDO sampler --
---------------------------------------------------------------------------------------------------
JC_TDO_sampling: process (s_tck)
begin
if rising_edge (s_tck) then
if s_idle= '1' then
jc_tdo_byte_o <= (others => '0');
else
jc_tdo_byte_o <= "0000000" & jc_tdo_i;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_model_constr_decoder.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_model_constr_decoder.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_model_constr_decoder --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_model_constr_decoder.vhd
--
-- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
-- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1
......@@ -36,32 +22,48 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- S_ID1 10
-- Vcc 11
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
-- Date 21/01/2011
--
--
-- Version v0.03
--
--
-- Depends on WF_reset_unit
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 11/09/2009 v0.01 PAS First version
-- -> 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1
-- "for" loop replaced with signals concatenation;
-- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up
-- -> 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed;
-- counter unit instantiated
-- -> 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3)
--
-- 11/09/2009 v0.01 PAS First version
-- 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1
-- "for" loop replaced with signals concatenation;
-- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up
-- 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed;
-- counter unit instantiated
-- 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3)
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......
wf_package.vhd
View file @ e91158c9
......@@ -4,53 +4,55 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_package.vhd |
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------------------------------
-- --
-- WF_package --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_package.vhd
--
-- Description Definitions of constants, types, entities, functions
--
--
-- Author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 11/01/2011
--
--
-- Version v0.04
--
--
-- Depends on
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed)
-- -> 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of
-- std_logic_vector (9 downto 0) to simplify calculations; cleaning-up
-- -> 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
-- added DualClkRam
-- -> 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics
-- added Ctrl bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG
-- 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed)
-- 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of
-- std_logic_vector (9 downto 0) to simplify calculations; cleaning-up
-- 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
-- added DualClkRam
-- 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics
-- added Ctrl bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
......@@ -67,6 +69,15 @@ package WF_package is
constant c_DEGLITCH_THRESHOLD : natural := 4;
---------------------------------------------------------------------------------------------------
-- Constant regarding the frame structure --
---------------------------------------------------------------------------------------------------
constant c_MAX_FRAME_BYTES : natural := 130; -- maximum number of bytes in a frame after the
-- FSS (counting starts from 0!)
---------------------------------------------------------------------------------------------------
-- Constants regarding the CRC calculation --
---------------------------------------------------------------------------------------------------
......@@ -119,6 +130,20 @@ package WF_package is
---------------------------------------------------------------------------------------------------
-- Constant regarding the JTAG controller --
---------------------------------------------------------------------------------------------------
constant c_MAX_FRAME_BITS : natural := 976; -- maximum number of TMS/ TDI bits that can be sent in
-- one frame : 122 bytes * 8 bits
constant c_JC_TCK_DIV : unsigned (3 downto 0) := "1000"; -- JC_TCK is created by a frequency
-- division of the 40 MHz uclk.
-- c_JC_TCK_div = 8 gives a JC_TCK of 5 MHz
constant c_FOUR_JC_TCK_C_LGTH : integer := 5; -- length of a counter
-- counting 4 JC_TCK periods
---------------------------------------------------------------------------------------------------
-- Constant regarding the Model & Constructor decoding --
---------------------------------------------------------------------------------------------------
......@@ -387,12 +412,6 @@ package WF_package is
crc_wrong_p_o : out std_logic;
fss_crc_fes_ok_p_o : out std_logic;
fss_received_p_o : out std_logic;
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
rx_osc_rst_o : out std_logic);
-----------------------------------------------------------------
end component WF_rx_deserializer;
......@@ -479,7 +498,7 @@ package WF_package is
---------------------------------------------------------------------------------------------------
component WF_jtag_player is
component WF_jtag_controller is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
......@@ -493,7 +512,7 @@ package WF_package is
jc_tdo_byte_o : out std_logic_vector (7 downto 0);
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0));
-----------------------------------------------------------------
end component WF_jtag_player;
end component WF_jtag_controller;
......@@ -510,12 +529,6 @@ package WF_package is
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
rx_crc_wrong_p_o : out std_logic );
-----------------------------------------------------------------
end component WF_fd_receiver;
......
wf_prod_bytes_retriever.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_prod_bytes_retriever.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_bytes_retriever --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_prod_bytes_retriever.vhd
--
-- Description After an ID_DAT frame requesting for a variable to be produced, the unit provides
-- to the WF_tx_serializer unit one by one, all the bytes of data needed for the
......@@ -66,39 +52,55 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 04/01/2011
--
--
-- Version v0.05
--
--
-- Depends on WF_reset_unit
-- WF_wb_controller
-- WF_engine_control
-- WF_prod_permit
-- WF_status_bytes_gen
-- WF_model_constr_dec
--
--
---------------------------------------------------------------------------------------------------
----------------
-- Last changes
-- -> 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames
-- signal s_wb_we includes the wb_stb_r_edge_p_i
-- cleaner structure
-- -> 06/2010 v0.03 EG signal s_mem_byte was not in sensitivity list in v0.01! by adding it
-- changes were essential in the timing of the tx (WF_osc, WF_tx,
-- WF_engine_control and the configuration of the memory needed changes)
-- -> 11/2010 v0.04 EG for simplification, new unit Slone_Data_Sampler created
-- -> 4/1/2011 v0.05 EG unit renamed from WF_prod_bytes_to_tx to WF_prod_bytes_retriever;
-- input byte_being_sent_p_i added, so that the reseting of status bytes
-- does not pass from the engine; clening-up+commenting
-- -> 2/2011 v0.051 EG WF_prod_bytes_from_dati unit removed.
--
--
-- 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames
-- signal s_wb_we includes the wb_stb_r_edge_p_i
-- cleaner structure
-- 06/2010 v0.03 EG signal s_mem_byte was not in sensitivity list in v0.01! by adding it
-- changes were essential in the timing of the tx (WF_osc, WF_tx,
-- WF_engine_control and the configuration of the memory needed changes)
-- 11/2010 v0.04 EG for simplification, new unit Slone_Data_Sampler created
-- 4/1/2011 v0.05 EG unit renamed from WF_prod_bytes_to_tx to WF_prod_bytes_retriever;
-- input byte_being_sent_p_i added, so that the reseting of status bytes
-- does not pass from the engine; clening-up+commenting
-- 2/2011 v0.051 EG WF_prod_bytes_from_dati unit removed.
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......@@ -159,7 +161,7 @@ entity WF_prod_bytes_retriever is
constr_id_dec_i : in std_logic_vector (7 downto 0); -- decoded constructor id settings
model_id_dec_i : in std_logic_vector (7 downto 0); -- decoded model id settings
-- Signals from the WF_jtag_player unit
-- Signals from the WF_jtag_controller unit
jc_tdo_byte_i : in std_logic_vector (7 downto 0); -- 8 last JC_TDO bits
-- OUTPUTS
......@@ -442,7 +444,7 @@ begin
-- MPS byte to the WF_tx_serializer.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The other byte comes from the JATG_player
-- The other byte comes from the JATG_controller
else
byte_o <= jc_tdo_byte_i;
rst_status_bytes_p_o <= '0';
......
wf_prod_data_lgth_calc.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_prod_data_lgth_calc.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_data_lgth_calc --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_prod_data_lgth_calc.vhd
--
-- Description Calculation of the number of bytes, after the FSS and before the FCS, that have
-- to be transferred when a variable is produced (var_pres, var_identif, var_3, var_jc3).
......@@ -49,31 +35,44 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- |-----P3_LGTH-----|
--
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 09/12/2010
--
--
-- Version v0.02
--
--
-- Depends on WF_engine_control
--
--
----------------
-- Last changes
-- 12/2010 v0.02 EG code cleaned-up+commented
---------------------------------------------------------------------------------------------------
--
---------------------------------------------------------------------------------------------------
--
-- Last changes
-- -> 12/2010 v0.02 EG code cleaned-up+commented
--
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_prod_data_lgth_calc
--=================================================================================================
......@@ -96,7 +95,6 @@ entity WF_prod_data_lgth_calc is
-- OUTPUT
-- Signal to the WF_engine_control and WF_production units
prod_data_lgth_o : out std_logic_vector (7 downto 0)
);
end entity WF_prod_data_lgth_calc;
......@@ -181,7 +179,7 @@ begin
when var_jc3 =>
-- data length calculation regardless of the operational mode, the P3_LGTH and the NOSTAT
-- 1 byte of data from the JTAG_player
-- 1 byte of data from the JTAG_controller
-- to these there should be added: 1 byte Control
-- 1 byte PDU_TYPE
-- 1 byte Length
......
wf_prod_permit.vhd
View file @ e91158c9
......@@ -4,53 +4,54 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_prod_permit.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_permit --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_prod_permit.vhd
--
-- Description Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY,
-- according to the variable (var_i) that is being treated.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 14/1/2011
--
--
-- Version v0.01
--
--
-- Depends on WF_engine_control
-- WF_reset_unit
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 1/2011 v0.01 EG First version
--
-- 1/2011 v0.01 EG First version
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......
wf_production.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_production.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_production --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_production.vhd
--
-- Description The unit groups the main actions that regard data production.
-- It instantiates the units:
......@@ -73,31 +59,46 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- which of the instantiated units needs it.
--
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 11/01/2011
--
--
-- Version v0.02
--
--
-- Depends on WF_reset_unit
-- WF_consumption
-- WF_engine_control
-- WF_wb_controller
-- WF_model_constr_decoder
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 2/2011 v0.02 EG WF_serializer removed from this unit
--
-- 2/2011 v0.02 EG WF_serializer removed from this unit
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......@@ -194,7 +195,7 @@ entity WF_production is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_jtag_player unit
-- Signals from the WF_jtag_controller unit
jc_tdo_byte_i : in std_logic_vector (7 downto 0);
......
wf_reset_unit.vhd
View file @ e91158c9
......@@ -4,28 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_reset_unit.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_reset_unit --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_reset_unit.vhd
--
-- Description The unit is responsible for the generation of the:
--
......@@ -112,25 +97,13 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- and one for resets coming from a var_rst.
--
--
--
--
--
-- Authors Erik van der Bij (Erik.van.der.Bij@cern.ch)
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 21/01/2011
--
--
-- Version v0.03
--
--
-- Depends on WF_cons_bytes_processor
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- 07/2009 v0.01 EB First version
-- 08/2010 v0.02 EG checking of bytes1 and 2 of reset var added
......@@ -139,9 +112,34 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- treated in the wf_cons_outcome; 2 state machines created; clean-up
-- PoR also for internal WISHBONE resets
-- 02/2011 v0.031 EG state nfip_off_fd_off added
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......
wf_rx_deglitcher.vhd
View file @ e91158c9
......@@ -4,54 +4,56 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_rx_deglitcher.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_deglitcher --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_rx_deglitcher.vhd
--
-- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD.
-- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 14/02/2011
--
--
-- Date 14/02/2011
-- Version v0.03
--
--
-- Depends on WF_reset_unit
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content
-- -> 23/08/2010 v0.02 EG code cleaned-up+commented
-- -> 14/02/2011 v0.03 EG complete change, no dependency on osc;
-- fd_rxd deglitched right at reception
--
-- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content
-- 23/08/2010 v0.02 EG code cleaned-up+commented
-- 14/02/2011 v0.03 EG complete change, no dependency on osc;
-- fd_rxd deglitched right at reception
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......
wf_rx_deserializer.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_rx_deserializer.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_deserializer --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_rx_deserializer.vhd
--
-- Description De-serialization of the "nanoFIP FIELDRIVE" input signal FD_RXD and construction
-- of bytes of data to be provided to:
......@@ -63,58 +49,71 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- sample_bit_p : ^ ^ (this sampling will give the 0 and the 1)
--
--
-- Reminder:
--
-- Consumed RP_DAT frame structure :
-- Reminder of the consumed RP_DAT frame structure:
-- _______ _______ ______ _______ ______ ________________ _______ ___________ _______
-- |__PRE__|__FSD__|_Ctrl_||__PDU__|_LGTH_|_..ApplicData.._|__MPS__||____FCS____|__FES__|
--
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 15/02/2011
--
--
-- Version v0.05
--
--
-- Depends on WF_reset_unit
-- WF_rx_osc
-- WF_rx_deglitcher
-- WF_engine_control
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 09/2009 v0.01 PAS First version
-- -> 10/2010 v0.02 EG state switch_to_deglitched added;
-- output signal rx_osc_rst_o added; signals renamed;
-- state machine rewritten (moore style);
-- units WF_rx_manch_code_check and Incoming_Bits_Index created;
-- each manch bit of FES checked (bf was just each bit, so any D5 was FES)
-- code cleaned-up + commented.
-- -> 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES;
-- like this we confirm that the CRC_ok_p arrived just before the FES,
-- and any 2 bytes that could by chanche be seen as CRC, are neglected.
-- FSM data_field_byte state: redundant code removed:
-- "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle"
-- code(more!)cleaned-up
-- -> 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if
-- bytes with size different than 8 have preceeded.
-- crc_wrong_p_o replaced the crc_wrong_p_o.
-- -> 02/2011 v0.05 EG changed crc pulse transfer; removed switch to deglitch state
-- s_fes_detected removed and s_byte_ready_p_d1; if bytes arrive with
-- bits not x8, the fss_crc_fes_ok_p_o stays 0 (bc of s_byte_ready_p_d1)
-- and the crc_wrong_p_o is asserted (bc of s_sample_manch_bit_p_d1);
-- unit reset during production;
-- check for code vilations completely removed!
--
-- 09/2009 v0.01 PAS First version
-- 10/2010 v0.02 EG state switch_to_deglitched added;
-- output signal rx_osc_rst_o added; signals renamed;
-- state machine rewritten (moore style);
-- units WF_rx_manch_code_check and Incoming_Bits_Index created;
-- each manch bit of FES checked (bf was just each bit, so any D5 was FES)
-- code cleaned-up + commented.
-- 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES;
-- like this we confirm that the CRC_ok_p arrived just before the FES,
-- and any 2 bytes that could by chanche be seen as CRC, are neglected.
-- FSM data_field_byte state: redundant code removed:
-- "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle"
-- code(more!)cleaned-up
-- 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if
-- bytes with size different than 8 have preceeded.
-- crc_wrong_p_o replaced the crc_wrong_p_o.
-- 02/2011 v0.05 EG changed crc pulse transfer; removed switch to deglitch state
-- s_fes_detected removed and s_byte_ready_p_d1; if bytes arrive with
-- bits not x8, the fss_crc_fes_ok_p_o stays 0 (bc of s_byte_ready_p_d1)
-- and the crc_wrong_p_o is asserted (bc of s_sample_manch_bit_p_d1);
-- unit reset during production;
-- check for code vilations completely removed!
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......@@ -163,17 +162,9 @@ entity WF_rx_deserializer is
-- Signal to the WF_engine_control unit
fss_received_p_o : out std_logic; -- pulse upon reception of a correct FSS (ID/RP)
TP14 : out std_logic;
TP15 : out std_logic;
TP16 : out std_logic;
TP39 : out std_logic;
-- Signal to the WF_rx_osc unit
rx_osc_rst_o : out std_logic -- resets the clk recovery procedure
);
);
end entity WF_rx_deserializer;
......@@ -652,10 +643,6 @@ begin
-- with number of bits not multiple of 8, but with correct FES, can be detected.
crc_wrong_p_o <= s_fes_detected and s_sample_manch_bit_p_d1 and (not s_CRC_ok_p_d);
TP14 <= fd_rxd_i;
TP15 <= s_CRC_ok_p_d;
TP16 <= s_sample_manch_bit_p_d1;
TP39 <= s_byte_ready_p_d1;
end architecture rtl;
--=================================================================================================
......
wf_rx_osc.vhd
View file @ e91158c9
......@@ -4,26 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_rx_osc.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_osc --
-- --
---------------------------------------------------------------------------------------------------
-- File WF_rx_osc.vhd
--
-- Description Generation of the clock signals needed for the FIELDRIVE reception
--
......@@ -39,36 +26,51 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- may not result in an edge (eg. a 0 followed by a 0 will give an edge _|-|_|-,
-- but a 0 followed by a 1 will not _|--|_ ).
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 14/02/2011
--
--
-- Version v0.04
--
--
-- Depends on WF_reset_unit
-- WF_deglitcher
-- WF_rx_deserializer
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 08/2009 v0.01 PS Entity Ports added, start of architecture content
-- -> 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned;
-- rx clk generation depends on edge detection;code cleanedup+commented
-- rst_rx_osc signal clearified
-- -> 12/2010 v0.03 EG code cleaned-up
-- -> 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments
-- -> 02/2011 v0.04 EG 2 units WF_rx_osc and WF_tx_osc; process replaced by WF_incr_counter
-- check for code violations removed completely
--
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content
-- 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned;
-- rx clk generation depends on edge detection;code cleanedup+commented
-- rst_rx_osc signal clearified
-- 12/2010 v0.03 EG code cleaned-up
-- 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments
-- 02/2011 v0.04 EG 2 units WF_rx_osc and WF_tx_osc; process replaced by WF_incr_counter
-- check for code violations removed completely
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......@@ -108,7 +110,6 @@ entity WF_rx_osc is
rx_adjac_bits_window_o : out std_logic -- time window where a transition between adjacent
-- bits is expected
);
end entity WF_rx_osc;
......
wf_status_bytes_gen.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_status_bytes_gen.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_status_bytes_gen --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_status_bytes_gen.vhd
--
-- Description Generation of the nanoFIP status and MPS status bytes.
-- The unit is also responsible for outputting the "nanoFIP User Interface,
......@@ -37,14 +23,15 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- o the "nanoFIP User Interface, NON_WISHBONE" inputs (VAR_ACC) and outputs
-- (VAR_RDY), for the bits 2 and 3.
--
-- For the MPS byte, in memory mode, the refreshment and significance bits are set to
-- 1 if the user has updated the produced variable var3 since its last transmission;
-- the signal "nanoFIP User Interface, NON_WISHBONE" input VAR3_ACC, is used for this.
-- In stand-alone mode the refreshment and the significance are set to 1.
-- Also, regardless of the mode, for the consumed variable jc_var3 the refreshment
-- and significance are set to 1.
--
-- For the refreshment and significance bits of the MPS status, the signal
-- "nanoFIP User Interface, NON_WISHBONE" input VAR3_ACC is used.
--
-- The MPS status byte and the bits 0 to 5 of the nanoFIP status byte are reset after
-- having been sent or after a nanoFIP internal reset. The bits 6 and 7 of the nanoFIP
-- status byte are only reset after a nanoFIP internal reset.
--
-- The MPS and the nanoFIP status byte are reset after having been sent or after a
-- nanoFIP internal reset.
--
-- Reminder:
-- ______________________ __________ ____________________________________________
......@@ -82,39 +69,56 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- | 4-7 | | 000 |
-- |__________________|_____________ |______________|
--
-- The refreshment and significance are set to 1 if the user has updated
-- the produced variable since the last transmission of the variable.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 10/01/2011
--
--
-- Version v0.03
--
--
-- Date 06/2011
-- Version v0.04
-- Depends on WF_reset_unit
-- WF_consumption
-- WF_prod_bytes_retriever
-- WF_prod_permit
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 07/07/2009 v0.01 PA First version
-- -> 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status
-- errors few cycles after var_rdy deactivation
-- -> 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_p_i
-- for nanoFIP status bit 4; var_i input not needed as the signals
-- nfip_status_r_fcser_p_i and nfip_status_r_tler_p_i check the var
--
-- 07/07/2009 v0.01 PA First version
-- 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status
-- errors few cycles after var_rdy deactivation
-- 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_p_i
-- for nanoFIP status bit 4; var_i input not needed as the signals
-- nfip_status_r_fcser_p_i and nfip_status_r_tler_p_i check the var
-- 06/2011 v0.04 EG all bits of nanoFIP status byte are reset upon rst_status_bytes_p_i
-- var_i added for the jtag_var1 treatment;
-- r_fcser, r_tler_o considered only for a cons variable (bf a wrong
-- crc on an id-dat could give r_fcser)
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_status_bytes_gen
......@@ -255,13 +259,12 @@ begin
---------------------------------------------------------------------------------------------------
-- Combinatorial process MPS_byte_Creation: Creation of the MPS byte
-- (nanoFIP functional specification, Table 2)
-- Combinatorial process MPS_byte_Generation: Creation of the MPS byte (Table 2, functional specs)
MPS_byte_Creation: process (slone_i, s_refreshment, var_i)
MPS_byte_Generation: process (slone_i, s_refreshment, var_i)
begin
if slone_i = '1' or var_i = var_jc3 then
begin -- var_jc3, regardless of the mode, has signif. & refresh. set to 1
if slone_i = '1' or var_i = var_jc3 then -- stand-alone mode has signif. & refresh. set to 1
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= '1';
mps_status_byte_o (1) <= '0';
......@@ -280,10 +283,10 @@ begin
---------------------------------------------------------------------------------------------------
-- nanoFIP status byte --
---------------------------------------------------------------------------------------------------
-- Synchronous process Status_byte_Formation: Formation of the nanoFIP status byte
-- (nanoFIP functional specification, Table 8)
-- Synchronous process nFIP_status_byte_Generation: Creation of the nanoFIP status byte (Table 8,
-- functional specs)
nFIP_status_byte_generation: process (uclk_i)
nFIP_status_byte_Generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
......@@ -294,8 +297,8 @@ begin
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reinitialization after the transmission of a produced variable
if rst_status_bytes_p_i = '1' then -- bits 0 to 5 reinitialised ------------------------------------------
s_nFIP_status_byte(7 downto 0) <= (others => '0'); -- after having been delivered
if rst_status_bytes_p_i = '1' then -- bits 0 to 5 reinitialised
s_nFIP_status_byte <= (others => '0'); -- after having been delivered
-- bits 6 and 7 are only reset
-- when nanoFIP is reset
else
......@@ -336,14 +339,14 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler
if (nfip_status_r_tler_p_i = '1') then
--r_tler -- PDU_TYPE or length error on a consumed var
if (nfip_status_r_tler_p_i = '1' and ((var_i = var_1) or (var_i = var_2) or (var_i = var_jc1) or (var_i = var_rst))) then
s_nFIP_status_byte(c_R_TLER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser
if (nfip_status_r_fcser_p_i = '1') then--and ((var_i = var_1) or (var_i = var_2) or (var_i = var_jc1) or (var_i = var_rst))) then
--r_fcser -- CRC or bit number error on a consumed var
if (nfip_status_r_fcser_p_i = '1' and ((var_i = var_1) or (var_i = var_2) or (var_i = var_jc1) or (var_i = var_rst))) then
s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1';
end if;
......@@ -373,7 +376,7 @@ begin
s_var1_rdy_c_reinit <= var1_rdy_i or nfip_rst_i;
s_var1_rdy_c_incr <= '1' when s_var1_rdy_c < "1111" else '0';
s_var1_rdy_extended <= '1' when var1_rdy_i= '1' or s_var1_rdy_c_incr = '1' else '0';
s_var1_rdy_extended <= '1' when var1_rdy_i= '1' or s_var1_rdy_c_incr = '1' else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR2_RDY: WF_incr_counter
......@@ -389,7 +392,7 @@ begin
s_var2_rdy_c_reinit <= var2_rdy_i or nfip_rst_i;
s_var2_rdy_c_incr <= '1' when s_var2_rdy_c < "1111" else '0';
s_var2_rdy_extended <= '1' when var2_rdy_i= '1' or s_var2_rdy_c_incr = '1' else '0';
s_var2_rdy_extended <= '1' when var2_rdy_i= '1' or s_var2_rdy_c_incr = '1' else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR3_RDY: WF_incr_counter
......@@ -405,7 +408,7 @@ begin
s_var3_rdy_c_reinit <= var3_rdy_i or nfip_rst_i;
s_var3_rdy_c_incr <= '1' when s_var3_rdy_c < "1111" else '0';
s_var3_rdy_extended <= '1' when VAR3_RDY_i= '1' or s_var3_rdy_c_incr = '1' else '0';
s_var3_rdy_extended <= '1' when VAR3_RDY_i= '1' or s_var3_rdy_c_incr = '1' else '0';
......
wf_tx_osc.vhd
View file @ e91158c9
......@@ -4,26 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_tx_osc.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx_osc --
-- --
---------------------------------------------------------------------------------------------------
-- File WF_tx_osc.vhd
--
-- Description Generation of the clock signals needed for the FIELDRIVE transmission
--
......@@ -37,35 +24,48 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- tx_sched_p_buff(1) : 0 1 0 0 0 1 0 0
-- tx_sched_p_buff(0) : 1 0 0 0 1 0 0 0
--
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 14/02/2011
--
--
-- Date 14/02/2011
-- Version v0.04
--
--
-- Depends on WF_reset_unit
-- WF_engine_control
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 08/2009 v0.01 PS Entity Ports added, start of architecture content
-- -> 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned;
-- c_TX_SCHED_BUFF_LGTH got 1 bit more
-- -> 12/2010 v0.03 EG code cleaned-up
-- -> 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_osc_rst_p_i
--
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content
-- 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned;
-- c_TX_SCHED_BUFF_LGTH got 1 bit more
-- 12/2010 v0.03 EG code cleaned-up
-- 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_osc_rst_p_i
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_tx_osc
--=================================================================================================
......@@ -93,7 +93,6 @@ entity WF_tx_osc is
-- buffer of pulses used for the scheduling
-- of the actions of the WF_tx_serializer
);
end entity WF_tx_osc;
......
wf_tx_serializer.vhd
View file @ e91158c9
......@@ -4,27 +4,13 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_tx_serializer.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx_serializer --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_tx_serializer.vhd
--
-- Description The unit is generating the nanoFIP FIELDRIVE outputs FD_TXD and FD_TXENA. It is
-- retreiving bytes of data from:
......@@ -41,47 +27,60 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- be transmitted, the WF_engine_control asserts the last_byte_p_i which signals the
-- unit to proceed with the transmission of the CRC bytes and the FES.
--
--
-- Reminder:
--
-- Produced RP_DAT frame structure :
-- Reminder of the Produced RP_DAT frame structure :
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
-- |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
--
-- |------------- Bytes from the WF_production -------------|
--
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 21/01/2011
--
--
-- Version v0.04
--
-- Depends on WF_engine_control
-- WF_production
-- WF_tx_osc
-- WF_reset_unit
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> v0.02 2009 PAS Entity Ports added, start of architecture content
-- -> v0.03 07/2010 EG timing changes; tx_sched_p_buff_i got 1 more bit
-- briefly byte_index_i needed to arrive 1 clock tick earlier
-- renamed from tx to tx_serializer;
-- stop_transmission state added for the synch of txena
-- -> v0.04 01/2011 EG sync_to_txck state added to start always with the bits 1,2,3 of the
-- clock buffer available(tx_start_p_i may arrive at any time)
-- tx_completed_p_o signal added
--
-- v0.02 2009 PAS Entity Ports added, start of architecture content
-- v0.03 07/2010 EG timing changes; tx_sched_p_buff_i got 1 more bit
-- briefly byte_index_i needed to arrive 1 clock tick earlier
-- renamed from tx to tx_serializer;
-- stop_transmission state added for the synch of txena
-- v0.04 01/2011 EG sync_to_txck state added to start always with the bits 1,2,3 of the
-- clock buffer available(tx_start_p_i may arrive at any time)
-- tx_completed_p_o signal added
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_tx_serializer
......
wf_wb_controller.vhd
View file @ e91158c9
......@@ -4,52 +4,53 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- File WF_wb_controller.vhd |
---------------------------------------------------------------------------------------------------
-- Standard library
library IEEE;
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific packages
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
-- --
-- WF_wb_controller --
-- --
---------------------------------------------------------------------------------------------------
--
-- File WF_wb_controller.vhd
--
-- Description The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to
-- the user's STBs.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
-- Date 21/01/2011
--
--
-- Version v0.01
--
--
-- Depends on WF_production
--
--
---------------------------------------------------------------------------------------------------
--
----------------
-- Last changes
-- -> 21/01/2011 v0.011 EG changed registering
--
-- 21/01/2011 v0.011 EG changed registering
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
......
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