Review12042010
Design review of PCB layout of the NanoFIP Test Board
12 May 2010
PCB layout of 29 April 2010. All documentation of the verified version
at link
Present
Matthieu Cattin (BE/CO), Javier Serrano (BE/CO), Gonzalo Peñacoba (TE/CRG), Erik van der Bij (BE/CO)
General description of the design.
The company HLP has made the PCB layout for the design and made the pdfs of the different layers available for review.
PCB layout
Important*
- The DAT_I and DAT_O connectors have no Gnd or Vcc pins. Without these it will not be easy to set values or read them. Add Gnd and Vcc pins so that the board can be easier used for testing and simple applications (needs 2 pins additional per connector).
- Add Gnd and Vcc test points on the board
- The GND an PWR planes use split planes. On the adjacent layers many signals are crossing the split, which causes EMC and signal quality problems. Suggest to add 2 layers for the different supplies to have less splits. Also verify that no signal lines are crossing the splits (return current should not need to cross from one domain to the other).
- Decoupling capacitors: there is a long line from the via to the
decoupling capacitors (e.g page TOP). This will introduce an
inductor and make that fast currents cannot be delivered.
- Put the vias directly next to the decoupling capacitors.
- Give each decoupling capacitor its own via for accessing Gnd and Vcc.
- Shorten the line length between capacitor and IC power/Gnd pins.
- Do not share vias for different pins.
- There are many long lines that seem to connect to Gnd or a Pwr. It seems that they share a single via (e.g. pins 1 of P5, P6, P9, P11) or P7, P8, P10, P12). See if they can have their own vias, reducing line length.
Minor*
- Silkscreen: add text "CERN NanoFIP test board"
- Scaling: all pages are marked "Echelle 1:2" while they are on different sizes (notably the ones with 2 layers on one page).
Conclusions
This has been a very useful review that revealed several issues that will make the design more robust and that will improve its documentation. The type of issues found are typical for designs of this complexity. The changes will be implemented before the PCB will be produced. We thank all people involved in the review.
- Erik van der Bij - 12 May 2010