Review25032010
Design review of NanoFIP Test Board
25 March 2010
Schematics of 19 March 2010. Schematics and other documentation of the
verified version at link
Present
Pablo Alvarez (BE/CO), Matthieu Cattin (BE/CO), Julien Palluel (BE/CO), Erik van der Bij (BE/CO)
General description of the design.
The company HLP has written specifications and made the schematics for the NanoFIP test board. This review verified the documentation and notably the schematics before the PCB layout will start at HLP.
Comments by Pablo
Comments on schematics
- The fielddrive filter is designed for 1Mb/s. I think it should be designed for the 2.5Mb/s rate
- Does the diode bridge protection correspond to any of the examples in the fieldrive documentation?
- Do we need U2? (Buffer between fielddrive and actel)
- I would like a switch on slone and rate
- Jtag lines on main cpld not connected properly (tms, tdi, tdo)
- It is simpler to put one JTAG connector per fpga
- Increase the intensity rate from 1A to 2A or 3A for the nanofip 3V3 and 1V5 power supplies.
Comments by Erik
Banc de test NanoFIP, Specification Generale
Important*
- Page 10: it seems that the LEDs and jumpers are directly on the
Wishbone interface.
- This is not possible as they are driven by the FPGA too
- Even if the direct I/O from the NanoFIP is meant, I don't see these back in the schematics (page 4 schematics: there is a test connector, but there is no ground or Vcc to be able to make a plugin card for it).
- The speed of the WorldFIP interface is not defined.
- I guess we'll test at the highest speed now, but it should be clear what should be done to make slower speeds.
Minor*
- It is not defined what WorldFIP master will be used to test, nor
what software is used there.
- Will this be part of the software specification?
- Page 2: Glossaire. VHDL stands for "Very High Speed Integrated Circuit Hardware Description Language".
- Page 9: it's not needed (or really possible, I think) to have independent temperature regulation.
Carte de test NanoFIP, Specifications techniques detaillees
Important*
- Page 11 Calculation of dissipation needed for 60 degrees increase is not clear. This may be very dependent on the size and layers of the PCB, cooling by airflow and so. Anyway currently with 1W there is no margin. Suggest to increase to 2W or even higher to leave a margin.
Minor*
- Page 6: output "recopie FIP" wasn't asked for (not in spec generale), but may come in handy anyway.
- The total current of both supplies (3V3, 1V5) to the NanoFIP is measured, but not seperately. As there are no inputs on the ADC left, this is probably good enough (4 ADC inputs: Temp 2x, I NanoFIP, I Fieldrive).
Schemas
- Not the same FPGA is used as the NanoFIP
- having the same FPGA helps in ordering, connectivity, etc.
- see recommendation No.7 in 1016-01-1 00-PRJ-B-005 -Document QR.xls
Conclusions
This has been a very useful review that revealed several serious mistakes and signalled other issues that will make the design more robust and that will improve its documentation. The changes will be implemented before finalising the PCB layout. We thank all people involved in the review.
- Erik van der Bij - 25 March 2010