Review25032010
Design review of NanoFIP Test Board
25 March 2010
Schematics of 19 March 2010. Schematics and other documentation of the
verified version at link
Present
Pablo Alvarez (BE/CO), Matthieu Cattin (BE/CO), Eva Gousiou (TE/CRG), Julien Palluel (BE/CO), Gonzalo Penacoba (TE/CRG), Erik van der Bij (BE/CO)
General description of the design.
The company HLP has written specifications and made the schematics for the NanoFIP test board. This review verified the documentation and notably the schematics before the PCB layout will start at HLP. It was noted that the documentation was very complete and clear.
Banc de test NanoFIP, Specification Generale
Important*
- Page 10: it seems that the LEDs and jumpers are directly on the
Wishbone interface.
- This is not possible as they are driven by the FPGA too
- Even if the direct I/O from the NanoFIP is meant, I don't see these back in the schematics (page 4 schematics: there is a test connector, but there is no ground or Vcc to be able to make a plugin card for it).
- In fact there no LEDs in the schematics.
- Page 10: the loopback is shown, but it is not clear if this is implemented on the actual card (e.g. the RS-485 comes from the FPGA and not from the NanoFIP).
- The speed of the WorldFIP interface is not defined.
- I guess we'll test at the highest speed now, but it should be clear what should be done to make slower speeds.
Minor*
- It is not defined what WorldFIP master will be used to test, nor
what software is used there. How would one implement things like
send frame, check data at a cycle rate of 10 ms.
- Will this be part of the software specification?
- Page 2: Glossaire. VHDL stands for "Very High Speed Integrated Circuit Hardware Description Language".
- Page 9: it's not needed (or really possible, I think as the power planes will transfer the heat effectively) to have independent temperature regulation.
Carte de test NanoFIP, Specifications techniques detaillees
Important*
- Page 11: Calculation of dissipation needed for 60 degrees increase is not clear. This may be very dependent on the size and layers of the PCB, cooling by airflow and so. Anyway currently with 1W there is no margin. Suggest to increase much higher to leave a margin. Suggest some prototyping with a small PCB (how can just 1W heat up such a large board by 60 degrees, anyway?)
- Page 13: the used FPGA is not the same as the NanoFIP. But it has
the same number of pins.
- having the same FPGA helps in ordering, connectivity, etc.
- see recommendation No.7 in 1016-01-1 00-PRJ-B-005 -Document QR.xls
- Page 16: assumes that 9 Volt arrives at input. But it will be much
lower
- See page 6, Banc de Test - spec generale: "compte tenu des pertes" will have 9V before 50 meters of cable (and much less at input of card).
- Page 24: Good idea to have the address settable by jumper. But "les sorties doivent etre en tri-state afin de ne pas generer de court circuit si un jumper est positionnee". The device cannot know if a jumper is inserted and therefore outputs can blow up. If you implement the outputs to behave like open collector, it always works. Suggestions: "va et vient switch" that switches between the jumper settings or FPGA output.
Minor or observations*
- Page 6: output "recopie FIP" wasn't asked for (not in spec generale), but may come in handy anyway.
- The total current of both supplies (3V3, 1V5) to the NanoFIP is measured, but not seperately. As there are no inputs on the ADC left, this is probably good enough (4 ADC inputs: Temp 2x, I NanoFIP, I Fieldrive).
- Page 27: "I2C EEPROM: configuration par defaut de la carte".
- It is not clear what configuration is in there. The FPGA (VHDL) configuration itself is stored in the Actel's own internal FLASH memory.
Schema Carte Adaptation
- Define the maximum Vin. It's specified now as 9V, but much more may be needed if the cable is long or too resistive.
Schema Carte Principale
Important*
- Jtag lines on main FPGA not connected properly (tms, tdi, tdo).
- It is simpler to put one JTAG connector per fpga.
- Not the same FPGA is used as the NanoFIP .
- having the same FPGA helps in ordering, connectivity, etc.
- see recommendation No.7 in 1016-01-1 00-PRJ-B-005 -Document QR.xls
- Page 12 of main schematics: GCLK and GCLRN are inverted.
- see also if a dedicated global clock pin can be used for the clock input.
- Increase the intensity rate from 1A to 3A for the nanofip 3V3 and 1V5 power supplies. The reason is that under radiation the current consumption may increase by a factor 3, while the device still will function.
- Need to adapt the range of the ADC of the current measurements as the current may be a factor three higher than typical.
- The latchup protection circuit should take into account that under radiation the current may be a factor three highter than typical.
- How to configure the used speed. The fielddrive filter is designed for 1Mb/s. I think it should be designed for the 2.5Mb/s rate. Could it be configurable like on the FIPADUC/FIPDIAG?
- Does the diode bridge protection correspond to any of the examples in the fieldrive documentation?
- Page 2: the WorldFIP connector is connected differently than FIPDIAG (pins 1 and 3 are now used, while they were unconnected).
- Page 2: Originally it was asked to be able to use other drivers than the FielDrive. Nothing is foreseen for this, no possibility even to make a plug-in card. See if this is possible by adding some connector.
- Suggest to add another ADC to measure the supply voltages (additional check to see that nothing changed there under radiation or that current limiting is active). Spare inputs may come in handy too.
- Page 13: the multiplexers can be replaced by four banks of jumpers (of which per bit only 1 of 4 is inserted). Removes problem if radiation (although low) may upset these multiplexers.
- Page 14: remove the RST input from the oscillator. It should always be running.
- There no LEDs in the schematics despite that they are described in the specification.
Minor or observations*
- Level conversion between FielDrive and NanoFIP. Now with IC. Could it work with a resistor as divider?
- Would like a switch on slone and rate.
- Page 5: JP4 header symbol: make it look like the physical one (2 rows of 5 pins).
- Page 11: typo: aorties -> sorties.
- Page 11: not clear whe all the pull-downs are needed.
- Page 14: why are there seperate clocks for the two FPGAs (FPGA: 24
MHz and NanoFIP: 40 MHz).
- Indeed the Wishbone bus can be asynchronous to the 40MHz, so this tests this nicely. But foresee to route the 40MHz clock to the FPGA too with a jumper or resistor (in case of problems and we like to run or test all synchronously).
- There is no parts list showing order numbers and package types.
Conclusions
This has been a very useful review that revealed several issues that will make the design more robust and that will improve its documentation. The type of issues found are typical for designs of this complexity. The changes will be implemented before the PCB layout will start. We thank all people involved in the review.
- Erik van der Bij - 26 March 2010