WP5 Write new nanoFIP VHDL code
Description
The work package 5 includes
- writing of technical specifications - based on the functional specification written as part of WP3
- writing new compatible MicroFIP VHDL with zero use of Alstom code
- implementing techniques for single event upset robustness
- Triple redundancy
- Scrubbing of memory
- FielDrive incoming glitch detection and handling
Pablo Alvarez and Evangelia Gousiou (BE/CO/HT) are responsible for the
nanoFIP code development.
Gonzalo Penacoba (TE/CRG/) is responsible for the simulation testing
development.
The deliverable of the work package 2 is
* Fully documented SEU robust VHDL code
** Compatible to orginal MicroFIP so that existing documentation, experience and software can be used in CERN’s applications
** Update: only partial compatibility required (see WP3)
The estimated duration is
- Twenty-six manweeks
Outcome
Timeline
Date | Status |
---|---|
30-06-2009 | Start of WP5. |
10-07-2009 | Initial high-level design and templates made available in SVN. |
30-07-2009 | Decided with Javier to make a quick-and-dirty prototype that is not rad-tol. This to allow other work packages to advance |
and to demonstrate the understanding of WorldFIP. Current resources don't allow to make at this time a radiation tolerant | |
version and a redesign will be needed to accomplish radiation tolerance. Pablo will be the lead designer. | |
13-11-2009 | All modules written. Needs additional time for finalization, simulation and debugging. |
06-04-2010 | Complete, independent, test bench being written by G. Penacoba. |
01-06-2010 | Eva Gousiou working full time on nanoFIP project (development, debug, documentation). |
13-10-2010 | Code working on nanoFIP test board. Continuing to test, code is not yet stable. |
Useful documentation
E.Gousiou, E.Van der Bij, June 2011