WP6. VHDL Testbench creation and simulation of NanoFIP
Description
The work package 6 includes
- writing VHDL testbenches that allow to test the nanoFIP
- FielDrive emulator (needed for MicroFIP stand-alone mode)
- Processor bus emulator (needed for MicroFIP in microcontrolled mode)
The deliverables are
- FielDrive emulator with file I/O and verification of data
- Processor bus emulator with file I/O and verification of data
- Complete set of PASS/FAIL test suites
Gonzalo Penacoba (TE/CRG/CI) is independently developing the Test Bench.
The estimated duration is
- Twelve manweeks
Outcome
Timeline
Date | Status |
---|---|
01-02-2010 | Gonzalo Fernandez Penacoba will create the testbench. |
29-06-2009 | Start of WP6. |
08-06-2010 | Simulations running, but not yet fully working. |
16-06-2010 | Simulation day with aim to get basic functionality working (Eva, Pablo, Gonzalo). |
15-04-2011 | Stable testbench used to validate design before first radiation test. |
Useful documentation
E.Gousiou, E.Van der Bij, June 2011