pax_global_header 0000666 0000000 0000000 00000000064 14574545710 0014526 g ustar 00root root 0000000 0000000 52 comment=7b3abf92979dfd14bcad792d3bb31dbd51332e07
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/ 0000775 0000000 0000000 00000000000 14574545710 0025111 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/.gitmodules 0000664 0000000 0000000 00000000525 14574545710 0027270 0 ustar 00root root 0000000 0000000 # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
[submodule "vme-bridge"]
path = dependencies/vme-bridge
url = https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/vme-bridge.git
[submodule "general-cores"]
path = dependencies/general-cores
url = https://ohwr.org/project/general-cores.git
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/.reuse/ 0000775 0000000 0000000 00000000000 14574545710 0026312 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/.reuse/dep5 0000664 0000000 0000000 00000002170 14574545710 0027072 0 ustar 00root root 0000000 0000000 Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
Upstream-Name: VME SBC A25 PCIe-VME Bridge Firmware
Upstream-Contact:
Source: https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge
Files: *.exe *.dll *.hex */bin2ihex */genDediProg */fpga_addheader
Copyright: 2016
License: GPL-3.0-or-later
Files: hdl/16z091-01_src/Source/CycV/x1/CycVTransReconf.txt
hdl/16z091-01_src/Source/CycV/x1/PCIeHardIPCycV.txt
hdl/16z091-01_src/Source/CycV/x2/CycVTransReconf.txt
hdl/16z091-01_src/Source/CycV/x2/PCIeHardIPCycV.txt
hdl/16z091-01_src/Source/CycV/x4/CycVTransReconf.txt
hdl/16z091-01_src/Source/CycV/x4/PCIeHardIPCycV.txt
hdl/16z091-01_src/Source/alt_reconf/alt_reconf.txt
hdl/16z091-01_src/Source/x1/Hard_IP_x1.txt
hdl/16z091-01_src/Source/x4/Hard_IP_x4.txt
hdl/16z126-01_src/Source/z126_01_pasmi/z126_01_pasmi_m25p32.txt
hdl/16z126-01_src/Source/z126_01_ru/z126_01_ru_cycloneiv.txt
hdl/top/pll_pcie/pll_pcie.txt
hdl/top/chameleon_V2.xls
hdl/top/chameleon_V2.bak
Copyright: 2016
License: CERN-OHL-S-2.0+
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/LICENSES/ 0000775 0000000 0000000 00000000000 14574545710 0026316 5 ustar 00root root 0000000 0000000 CC-BY-SA-4.0.txt 0000664 0000000 0000000 00000043707 14574545710 0030410 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/LICENSES Creative Commons Attribution-ShareAlike 4.0 International
Creative Commons Corporation (“Creative Commons”) is not a law firm and does not provide legal services or legal advice. Distribution of Creative Commons public licenses does not create a lawyer-client or other relationship. Creative Commons makes its licenses and related information available on an “as-is” basis. Creative Commons gives no warranties regarding its licenses, any material licensed under their terms and conditions, or any related information. Creative Commons disclaims all liability for damages resulting from their use to the fullest extent possible.
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Considerations for licensors: Our public licenses are intended for use by those authorized to give the public permission to use material in ways otherwise restricted by copyright and certain other rights. Our licenses are irrevocable. Licensors should read and understand the terms and conditions of the license they choose before applying it. Licensors should also secure all rights necessary before applying our licenses so that the public can reuse the material as expected. Licensors should clearly mark any material not subject to the license. This includes other CC-licensed material, or material used under an exception or limitation to copyright. More considerations for licensors.
Considerations for the public: By using one of our public licenses, a licensor grants the public permission to use the licensed material under specified terms and conditions. If the licensor’s permission is not necessary for any reason–for example, because of any applicable exception or limitation to copyright–then that use is not regulated by the license. Our licenses grant only permissions under copyright and certain other rights that a licensor has authority to grant. Use of the licensed material may still be restricted for other reasons, including because others have copyright or other rights in the material. A licensor may make special requests, such as asking that all changes be marked or described.
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Creative Commons Attribution-ShareAlike 4.0 International Public License
By exercising the Licensed Rights (defined below), You accept and agree to be bound by the terms and conditions of this Creative Commons Attribution-ShareAlike 4.0 International Public License ("Public License"). To the extent this Public License may be interpreted as a contract, You are granted the Licensed Rights in consideration of Your acceptance of these terms and conditions, and the Licensor grants You such rights in consideration of benefits the Licensor receives from making the Licensed Material available under these terms and conditions.
Section 1 – Definitions.
a. Adapted Material means material subject to Copyright and Similar Rights that is derived from or based upon the Licensed Material and in which the Licensed Material is translated, altered, arranged, transformed, or otherwise modified in a manner requiring permission under the Copyright and Similar Rights held by the Licensor. For purposes of this Public License, where the Licensed Material is a musical work, performance, or sound recording, Adapted Material is always produced where the Licensed Material is synched in timed relation with a moving image.
b. Adapter's License means the license You apply to Your Copyright and Similar Rights in Your contributions to Adapted Material in accordance with the terms and conditions of this Public License.
c. BY-SA Compatible License means a license listed at creativecommons.org/compatiblelicenses, approved by Creative Commons as essentially the equivalent of this Public License.
d. Copyright and Similar Rights means copyright and/or similar rights closely related to copyright including, without limitation, performance, broadcast, sound recording, and Sui Generis Database Rights, without regard to how the rights are labeled or categorized. For purposes of this Public License, the rights specified in Section 2(b)(1)-(2) are not Copyright and Similar Rights.
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g. License Elements means the license attributes listed in the name of a Creative Commons Public License. The License Elements of this Public License are Attribution and ShareAlike.
h. Licensed Material means the artistic or literary work, database, or other material to which the Licensor applied this Public License.
i. Licensed Rights means the rights granted to You subject to the terms and conditions of this Public License, which are limited to all Copyright and Similar Rights that apply to Your use of the Licensed Material and that the Licensor has authority to license.
j. Licensor means the individual(s) or entity(ies) granting rights under this Public License.
k. Share means to provide material to the public by any means or process that requires permission under the Licensed Rights, such as reproduction, public display, public performance, distribution, dissemination, communication, or importation, and to make material available to the public including in ways that members of the public may access the material from a place and at a time individually chosen by them.
l. Sui Generis Database Rights means rights other than copyright resulting from Directive 96/9/EC of the European Parliament and of the Council of 11 March 1996 on the legal protection of databases, as amended and/or succeeded, as well as other essentially equivalent rights anywhere in the world.
m. You means the individual or entity exercising the Licensed Rights under this Public License. Your has a corresponding meaning.
Section 2 – Scope.
a. License grant.
1. Subject to the terms and conditions of this Public License, the Licensor hereby grants You a worldwide, royalty-free, non-sublicensable, non-exclusive, irrevocable license to exercise the Licensed Rights in the Licensed Material to:
A. reproduce and Share the Licensed Material, in whole or in part; and
B. produce, reproduce, and Share Adapted Material.
2. Exceptions and Limitations. For the avoidance of doubt, where Exceptions and Limitations apply to Your use, this Public License does not apply, and You do not need to comply with its terms and conditions.
3. Term. The term of this Public License is specified in Section 6(a).
4. Media and formats; technical modifications allowed. The Licensor authorizes You to exercise the Licensed Rights in all media and formats whether now known or hereafter created, and to make technical modifications necessary to do so. The Licensor waives and/or agrees not to assert any right or authority to forbid You from making technical modifications necessary to exercise the Licensed Rights, including technical modifications necessary to circumvent Effective Technological Measures. For purposes of this Public License, simply making modifications authorized by this Section 2(a)(4) never produces Adapted Material.
5. Downstream recipients.
A. Offer from the Licensor – Licensed Material. Every recipient of the Licensed Material automatically receives an offer from the Licensor to exercise the Licensed Rights under the terms and conditions of this Public License.
B. Additional offer from the Licensor – Adapted Material. Every recipient of Adapted Material from You automatically receives an offer from the Licensor to exercise the Licensed Rights in the Adapted Material under the conditions of the Adapter’s License You apply.
C. No downstream restrictions. You may not offer or impose any additional or different terms or conditions on, or apply any Effective Technological Measures to, the Licensed Material if doing so restricts exercise of the Licensed Rights by any recipient of the Licensed Material.
6. No endorsement. Nothing in this Public License constitutes or may be construed as permission to assert or imply that You are, or that Your use of the Licensed Material is, connected with, or sponsored, endorsed, or granted official status by, the Licensor or others designated to receive attribution as provided in Section 3(a)(1)(A)(i).
b. Other rights.
1. Moral rights, such as the right of integrity, are not licensed under this Public License, nor are publicity, privacy, and/or other similar personality rights; however, to the extent possible, the Licensor waives and/or agrees not to assert any such rights held by the Licensor to the limited extent necessary to allow You to exercise the Licensed Rights, but not otherwise.
2. Patent and trademark rights are not licensed under this Public License.
3. To the extent possible, the Licensor waives any right to collect royalties from You for the exercise of the Licensed Rights, whether directly or through a collecting society under any voluntary or waivable statutory or compulsory licensing scheme. In all other cases the Licensor expressly reserves any right to collect such royalties.
Section 3 – License Conditions.
Your exercise of the Licensed Rights is expressly made subject to the following conditions.
a. Attribution.
1. If You Share the Licensed Material (including in modified form), You must:
A. retain the following if it is supplied by the Licensor with the Licensed Material:
i. identification of the creator(s) of the Licensed Material and any others designated to receive attribution, in any reasonable manner requested by the Licensor (including by pseudonym if designated);
ii. a copyright notice;
iii. a notice that refers to this Public License;
iv. a notice that refers to the disclaimer of warranties;
v. a URI or hyperlink to the Licensed Material to the extent reasonably practicable;
B. indicate if You modified the Licensed Material and retain an indication of any previous modifications; and
C. indicate the Licensed Material is licensed under this Public License, and include the text of, or the URI or hyperlink to, this Public License.
2. You may satisfy the conditions in Section 3(a)(1) in any reasonable manner based on the medium, means, and context in which You Share the Licensed Material. For example, it may be reasonable to satisfy the conditions by providing a URI or hyperlink to a resource that includes the required information.
3. If requested by the Licensor, You must remove any of the information required by Section 3(a)(1)(A) to the extent reasonably practicable.
b. ShareAlike.In addition to the conditions in Section 3(a), if You Share Adapted Material You produce, the following conditions also apply.
1. The Adapter’s License You apply must be a Creative Commons license with the same License Elements, this version or later, or a BY-SA Compatible License.
2. You must include the text of, or the URI or hyperlink to, the Adapter's License You apply. You may satisfy this condition in any reasonable manner based on the medium, means, and context in which You Share Adapted Material.
3. You may not offer or impose any additional or different terms or conditions on, or apply any Effective Technological Measures to, Adapted Material that restrict exercise of the rights granted under the Adapter's License You apply.
Section 4 – Sui Generis Database Rights.
Where the Licensed Rights include Sui Generis Database Rights that apply to Your use of the Licensed Material:
a. for the avoidance of doubt, Section 2(a)(1) grants You the right to extract, reuse, reproduce, and Share all or a substantial portion of the contents of the database;
b. if You include all or a substantial portion of the database contents in a database in which You have Sui Generis Database Rights, then the database in which You have Sui Generis Database Rights (but not its individual contents) is Adapted Material, including for purposes of Section 3(b); and
c. You must comply with the conditions in Section 3(a) if You Share all or a substantial portion of the contents of the database.
For the avoidance of doubt, this Section 4 supplements and does not replace Your obligations under this Public License where the Licensed Rights include other Copyright and Similar Rights.
Section 5 – Disclaimer of Warranties and Limitation of Liability.
a. Unless otherwise separately undertaken by the Licensor, to the extent possible, the Licensor offers the Licensed Material as-is and as-available, and makes no representations or warranties of any kind concerning the Licensed Material, whether express, implied, statutory, or other. This includes, without limitation, warranties of title, merchantability, fitness for a particular purpose, non-infringement, absence of latent or other defects, accuracy, or the presence or absence of errors, whether or not known or discoverable. Where disclaimers of warranties are not allowed in full or in part, this disclaimer may not apply to You.
b. To the extent possible, in no event will the Licensor be liable to You on any legal theory (including, without limitation, negligence) or otherwise for any direct, special, indirect, incidental, consequential, punitive, exemplary, or other losses, costs, expenses, or damages arising out of this Public License or use of the Licensed Material, even if the Licensor has been advised of the possibility of such losses, costs, expenses, or damages. Where a limitation of liability is not allowed in full or in part, this limitation may not apply to You.
c. The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
Section 6 – Term and Termination.
a. This Public License applies for the term of the Copyright and Similar Rights licensed here. However, if You fail to comply with this Public License, then Your rights under this Public License terminate automatically.
b. Where Your right to use the Licensed Material has terminated under Section 6(a), it reinstates:
1. automatically as of the date the violation is cured, provided it is cured within 30 days of Your discovery of the violation; or
2. upon express reinstatement by the Licensor.
c. For the avoidance of doubt, this Section 6(b) does not affect any right the Licensor may have to seek remedies for Your violations of this Public License.
d. For the avoidance of doubt, the Licensor may also offer the Licensed Material under separate terms or conditions or stop distributing the Licensed Material at any time; however, doing so will not terminate this Public License.
e. Sections 1, 5, 6, 7, and 8 survive termination of this Public License.
Section 7 – Other Terms and Conditions.
a. The Licensor shall not be bound by any additional or different terms or conditions communicated by You unless expressly agreed.
b. Any arrangements, understandings, or agreements regarding the Licensed Material not stated herein are separate from and independent of the terms and conditions of this Public License.
Section 8 – Interpretation.
a. For the avoidance of doubt, this Public License does not, and shall not be interpreted to, reduce, limit, restrict, or impose conditions on any use of the Licensed Material that could lawfully be made without permission under this Public License.
b. To the extent possible, if any provision of this Public License is deemed unenforceable, it shall be automatically reformed to the minimum extent necessary to make it enforceable. If the provision cannot be reformed, it shall be severed from this Public License without affecting the enforceability of the remaining terms and conditions.
c. No term or condition of this Public License will be waived and no failure to comply consented to unless expressly agreed to by the Licensor.
d. Nothing in this Public License constitutes or may be interpreted as a limitation upon, or waiver of, any privileges and immunities that apply to the Licensor or You, including from the legal processes of any jurisdiction or authority.
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Creative Commons may be contacted at creativecommons.org.
CERN-OHL-S-2.0.txt 0000664 0000000 0000000 00000032153 14574545710 0030650 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/LICENSES CERN Open Hardware Licence Version 2 - Strongly Reciprocal
Preamble
CERN has developed this licence to promote collaboration among
hardware designers and to provide a legal tool which supports the
freedom to use, study, modify, share and distribute hardware designs
and products based on those designs. Version 2 of the CERN Open
Hardware Licence comes in three variants: CERN-OHL-P (permissive); and
two reciprocal licences: CERN-OHL-W (weakly reciprocal) and this
licence, CERN-OHL-S (strongly reciprocal).
The CERN-OHL-S is copyright CERN 2020. Anyone is welcome to use it, in
unmodified form only.
Use of this Licence does not imply any endorsement by CERN of any
Licensor or their designs nor does it imply any involvement by CERN in
their development.
1 Definitions
1.1 'Licence' means this CERN-OHL-S.
1.2 'Compatible Licence' means
a) any earlier version of the CERN Open Hardware licence, or
b) any version of the CERN-OHL-S, or
c) any licence which permits You to treat the Source to which
it applies as licensed under CERN-OHL-S provided that on
Conveyance of any such Source, or any associated Product You
treat the Source in question as being licensed under
CERN-OHL-S.
1.3 'Source' means information such as design materials or digital
code which can be applied to Make or test a Product or to
prepare a Product for use, Conveyance or sale, regardless of its
medium or how it is expressed. It may include Notices.
1.4 'Covered Source' means Source that is explicitly made available
under this Licence.
1.5 'Product' means any device, component, work or physical object,
whether in finished or intermediate form, arising from the use,
application or processing of Covered Source.
1.6 'Make' means to create or configure something, whether by
manufacture, assembly, compiling, loading or applying Covered
Source or another Product or otherwise.
1.7 'Available Component' means any part, sub-assembly, library or
code which:
a) is licensed to You as Complete Source under a Compatible
Licence; or
b) is available, at the time a Product or the Source containing
it is first Conveyed, to You and any other prospective
licensees
i) as a physical part with sufficient rights and
information (including any configuration and
programming files and information about its
characteristics and interfaces) to enable it either to
be Made itself, or to be sourced and used to Make the
Product; or
ii) as part of the normal distribution of a tool used to
design or Make the Product.
1.8 'Complete Source' means the set of all Source necessary to Make
a Product, in the preferred form for making modifications,
including necessary installation and interfacing information
both for the Product, and for any included Available Components.
If the format is proprietary, it must also be made available in
a format (if the proprietary tool can create it) which is
viewable with a tool available to potential licensees and
licensed under a licence approved by the Free Software
Foundation or the Open Source Initiative. Complete Source need
not include the Source of any Available Component, provided that
You include in the Complete Source sufficient information to
enable a recipient to Make or source and use the Available
Component to Make the Product.
1.9 'Source Location' means a location where a Licensor has placed
Covered Source, and which that Licensor reasonably believes will
remain easily accessible for at least three years for anyone to
obtain a digital copy.
1.10 'Notice' means copyright, acknowledgement and trademark notices,
Source Location references, modification notices (subsection
3.3(b)) and all notices that refer to this Licence and to the
disclaimer of warranties that are included in the Covered
Source.
1.11 'Licensee' or 'You' means any person exercising rights under
this Licence.
1.12 'Licensor' means a natural or legal person who creates or
modifies Covered Source. A person may be a Licensee and a
Licensor at the same time.
1.13 'Convey' means to communicate to the public or distribute.
2 Applicability
2.1 This Licence governs the use, copying, modification, Conveying
of Covered Source and Products, and the Making of Products. By
exercising any right granted under this Licence, You irrevocably
accept these terms and conditions.
2.2 This Licence is granted by the Licensor directly to You, and
shall apply worldwide and without limitation in time.
2.3 You shall not attempt to restrict by contract or otherwise the
rights granted under this Licence to other Licensees.
2.4 This Licence is not intended to restrict fair use, fair dealing,
or any other similar right.
3 Copying, modifying and Conveying Covered Source
3.1 You may copy and Convey verbatim copies of Covered Source, in
any medium, provided You retain all Notices.
3.2 You may modify Covered Source, other than Notices, provided that
You irrevocably undertake to make that modified Covered Source
available from a Source Location should You Convey a Product in
circumstances where the recipient does not otherwise receive a
copy of the modified Covered Source. In each case subsection 3.3
shall apply.
You may only delete Notices if they are no longer applicable to
the corresponding Covered Source as modified by You and You may
add additional Notices applicable to Your modifications.
Including Covered Source in a larger work is modifying the
Covered Source, and the larger work becomes modified Covered
Source.
3.3 You may Convey modified Covered Source (with the effect that You
shall also become a Licensor) provided that You:
a) retain Notices as required in subsection 3.2;
b) add a Notice to the modified Covered Source stating that You
have modified it, with the date and brief description of how
You have modified it;
c) add a Source Location Notice for the modified Covered Source
if You Convey in circumstances where the recipient does not
otherwise receive a copy of the modified Covered Source; and
d) license the modified Covered Source under the terms and
conditions of this Licence (or, as set out in subsection
8.3, a later version, if permitted by the licence of the
original Covered Source). Such modified Covered Source must
be licensed as a whole, but excluding Available Components
contained in it, which remain licensed under their own
applicable licences.
4 Making and Conveying Products
You may Make Products, and/or Convey them, provided that You either
provide each recipient with a copy of the Complete Source or ensure
that each recipient is notified of the Source Location of the Complete
Source. That Complete Source is Covered Source, and You must
accordingly satisfy Your obligations set out in subsection 3.3. If
specified in a Notice, the Product must visibly and securely display
the Source Location on it or its packaging or documentation in the
manner specified in that Notice.
5 Research and Development
You may Convey Covered Source, modified Covered Source or Products to
a legal entity carrying out development, testing or quality assurance
work on Your behalf provided that the work is performed on terms which
prevent the entity from both using the Source or Products for its own
internal purposes and Conveying the Source or Products or any
modifications to them to any person other than You. Any modifications
made by the entity shall be deemed to be made by You pursuant to
subsection 3.2.
6 DISCLAIMER AND LIABILITY
6.1 DISCLAIMER OF WARRANTY -- The Covered Source and any Products
are provided 'as is' and any express or implied warranties,
including, but not limited to, implied warranties of
merchantability, of satisfactory quality, non-infringement of
third party rights, and fitness for a particular purpose or use
are disclaimed in respect of any Source or Product to the
maximum extent permitted by law. The Licensor makes no
representation that any Source or Product does not or will not
infringe any patent, copyright, trade secret or other
proprietary right. The entire risk as to the use, quality, and
performance of any Source or Product shall be with You and not
the Licensor. This disclaimer of warranty is an essential part
of this Licence and a condition for the grant of any rights
granted under this Licence.
6.2 EXCLUSION AND LIMITATION OF LIABILITY -- The Licensor shall, to
the maximum extent permitted by law, have no liability for
direct, indirect, special, incidental, consequential, exemplary,
punitive or other damages of any character including, without
limitation, procurement of substitute goods or services, loss of
use, data or profits, or business interruption, however caused
and on any theory of contract, warranty, tort (including
negligence), product liability or otherwise, arising in any way
in relation to the Covered Source, modified Covered Source
and/or the Making or Conveyance of a Product, even if advised of
the possibility of such damages, and You shall hold the
Licensor(s) free and harmless from any liability, costs,
damages, fees and expenses, including claims by third parties,
in relation to such use.
7 Patents
7.1 Subject to the terms and conditions of this Licence, each
Licensor hereby grants to You a perpetual, worldwide,
non-exclusive, no-charge, royalty-free, irrevocable (except as
stated in subsections 7.2 and 8.4) patent license to Make, have
Made, use, offer to sell, sell, import, and otherwise transfer
the Covered Source and Products, where such licence applies only
to those patent claims licensable by such Licensor that are
necessarily infringed by exercising rights under the Covered
Source as Conveyed by that Licensor.
7.2 If You institute patent litigation against any entity (including
a cross-claim or counterclaim in a lawsuit) alleging that the
Covered Source or a Product constitutes direct or contributory
patent infringement, or You seek any declaration that a patent
licensed to You under this Licence is invalid or unenforceable
then any rights granted to You under this Licence shall
terminate as of the date such process is initiated.
8 General
8.1 If any provisions of this Licence are or subsequently become
invalid or unenforceable for any reason, the remaining
provisions shall remain effective.
8.2 You shall not use any of the name (including acronyms and
abbreviations), image, or logo by which the Licensor or CERN is
known, except where needed to comply with section 3, or where
the use is otherwise allowed by law. Any such permitted use
shall be factual and shall not be made so as to suggest any kind
of endorsement or implication of involvement by the Licensor or
its personnel.
8.3 CERN may publish updated versions and variants of this Licence
which it considers to be in the spirit of this version, but may
differ in detail to address new problems or concerns. New
versions will be published with a unique version number and a
variant identifier specifying the variant. If the Licensor has
specified that a given variant applies to the Covered Source
without specifying a version, You may treat that Covered Source
as being released under any version of the CERN-OHL with that
variant. If no variant is specified, the Covered Source shall be
treated as being released under CERN-OHL-S. The Licensor may
also specify that the Covered Source is subject to a specific
version of the CERN-OHL or any later version in which case You
may apply this or any later version of CERN-OHL with the same
variant identifier published by CERN.
8.4 This Licence shall terminate with immediate effect if You fail
to comply with any of its terms and conditions.
8.5 However, if You cease all breaches of this Licence, then Your
Licence from any Licensor is reinstated unless such Licensor has
terminated this Licence by giving You, while You remain in
breach, a notice specifying the breach and requiring You to cure
it within 30 days, and You have failed to come into compliance
in all material respects by the end of the 30 day period. Should
You repeat the breach after receipt of a cure notice and
subsequent reinstatement, this Licence will terminate
immediately and permanently. Section 6 shall continue to apply
after any termination.
8.6 This Licence shall not be enforceable except by a Licensor
acting as such, and third party beneficiary rights are
specifically excluded.
GPL-3.0-or-later.txt 0000664 0000000 0000000 00000103562 14574545710 0031452 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/LICENSES GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright © 2007 Free Software Foundation, Inc.
Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
Preamble
The GNU General Public License is a free, copyleft license for software and other kinds of works.
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END OF TERMS AND CONDITIONS
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Copyright (C)
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vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/README.md 0000664 0000000 0000000 00000011336 14574545710 0026374 0 ustar 00root root 0000000 0000000
MEN A25 SBC PCIe-VME Bridge Gateware
====================================
This projects contains files required to build the PCIe to VME bridge gateware
for the MEN A25 VME SBC.
How to generate the FPGA bitstream
----------------------------------
1. Fetch all git submodules with ``git submodule update --init``.
2. Make sure you have [HDLmake](https://hdlmake.readthedocs.io) version
**greater** than 3.3 (it should include at least commit ``3ac2e4e``, if unsure
go for latest commit on the master branch).
3. Make sure you have Altera Quartus 16.0 installed, along with support for the
Cyclone IV GX FPGA family.
4. Enter the ``hdl/syn`` folder and run ``hdlmake`` (make sure that Altera
Quartus binaries are in your system path beforehand).
5. At this point you can either simply run ``make`` to build the project and
generate the FPGA bitstream, or ``make project`` to only generate the Altera
Quartus project files (``A25_top.qsf`` and ``A25_top.qpf``) which you can
then open in the Quartus GUI and continue the build process in there.
6. Either way, if the process is successful, new files with name
``16A025-00_MM_mm`` will be generated in ``hdl/syn/fpga_files``. You should
**only** use those files for programming the FPGA. Please note that the
``hdl/syn/A25_top.bin`` is **not** the right file, it will lead to
a programmed FPGA with a missing bitstream header.
How to set a new FPGA revision
------------------------------
The process inherited from MEN is based on a tool called Chameleon, which
generates an Intel hex file with the contents of the ROM that will be later
accessible through Wishbone. This ROM contains version information, addresses of
peripherals, etc.
When you need to bump the FPGA revision, please follow these steps:
1. You first need to compile the Chameleon tool (if not already done). To do
this, go to ``software/tools/16t001-00_src/Source`` and run ``create.sh``
(``create_exe.bat`` on Windows). This will build the binary and install it
under ``software/tools/16t001-00_bin/Bin`` (ignored by git). The tool is a
Perl-based compiled script so you will need a number of Perl-related packages
installed to be able to build it. The exact details are OS-dependent. As an
indication, on Archlinux the following packages were required (tested in
August 2023):
+ perl-par-packer
+ perl-getopt-mixed (AUR)
+ perl-xml-sax-expat-incremental (AUR)
+ perl-spreadsheet-parseexcel (AUR)
+ perl-spreadsheet-writeexcel (AUR)
2. Edit ``hdl/top/chameleon_V2.xls`` in order to set new revision (Page
"Content", minor revision in C8, major revision in C7) and close xls.
3. call ``hdl/top/cham2.sh`` (or ``cham2.bat`` on Windows) for hex file generation.
4. Edit ``hdl/syn/scripts/gen_programming_files.tcl`` and change programming
file name to new revision in variable PROJECT_RELEASE_NAM "16A025-00_MM_mm".
5. All set, proceed with building the project and producing the FPGA bitstream.
Flashing using ht-flasher
-------------------------
The bitstreams are stored in a M25P32 flash (4MB). Although the
bitstream image is slightly less than 1MB, the system is supposed to
contain only 2 images.
At offset 0, the factory image is stored in the raw format (the .rbf,
without any header). At power-up, the fpga will automatically load
this image. This is the recue image and it shouldn't be reflashed in
operation. The bitstream will automatically load the application
image unless an error happened before (like invalid application
image).
At offset 0x200000 (2MB), the application image is stored with an
header (256B). By default, this is the bitstream used.
Using ht-flasher (and we assume the pci slot is 03:00), you can check
which image is loaded:
```
> ht-flasher -a mena25 -d 03:00 -i
control: 00000000
data: ffffffff
board status: 00000001
image: application
boot-addr: 00200100
flash id: 00000015 (15=M25P32 - 4MB)
```
You can flash the application bitstream using the `-w` option.
You can reconfigure the FPGA using the `-b` option. But you then need
to rescan the pci device.
You can display the FPGA header using the `-H` option. This is useful
to display the version and date:
```
> sudo ht-flasher -a mena25 -d 03:00 -o 0x200000 -H
magic at 0x00300000: 52d4268e
filename: './A25_top ', fpga: 'EP4CGX30 '
size: 841044
date: 2023-12-13 17:16
board type: '16A025-00 '
```
In case of invalid bitstream, the FPGA will fallback to the factory bitstream:
```
>sudo ht-flasher -a mena25 -d 03:00 -i
control: 00000000
data: ffffffff
board status: 00000022
image: fallback after error
boot-addr: 00000000
flash id: 00000015 (15=M25P32 - 4MB)
```
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/dependencies/ 0000775 0000000 0000000 00000000000 14574545710 0027537 5 ustar 00root root 0000000 0000000 general-cores/ 0000775 0000000 0000000 00000000000 14574545710 0032206 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/dependencies vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/dependencies/vme-bridge/0000775 0000000 0000000 00000000000 14574545710 0031560 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/ 0000775 0000000 0000000 00000000000 14574545710 0025660 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src/ 0000775 0000000 0000000 00000000000 14574545710 0027604 5 ustar 00root root 0000000 0000000 Manifest.py 0000664 0000000 0000000 00000000207 14574545710 0031644 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
files = [
"Source/fpga_pkg_2.vhd",
]
Source/ 0000775 0000000 0000000 00000000000 14574545710 0030765 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src examples/ 0000775 0000000 0000000 00000000000 14574545710 0032603 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src/Source fpga_pkg_2_16zxxx.vhd 0000664 0000000 0000000 00000005101 14574545710 0036552 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src/Source/examples -- SPDX-FileCopyrightText: 2008, MEN Mikro Elektronik Nuremberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : fpga_pkg_2 example for IP-Core top file
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2_16zxxx.vhd
-- Author : Florian Wombacher
-- Email : florian.wombacher@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2008-04-01
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
-- fpga_pkg_2_16zxxx.vhd
-- - one_device.vhd
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: fpga_pkg_2_16zxxx.vhd,v $
-- Revision 1.2 2009/02/17 11:37:40 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:56 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/24 16:39:57 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/22 14:19:16 FWombacher
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY fpga_pkg_2_16zxxx IS
GENERIC (
FPGA_FAMILY : family_type := CYCLONE
);
PORT(
dummy : OUT std_logic
);
END ENTITY;
ARCHITECTURE fpga_pkg_2_16zxxx_arch OF fpga_pkg_2_16zxxx IS
CONSTANT SUPPORTED_DEVICES : supported_family_type := (CYCLONE);
COMPONENT one_device
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : OUT std_logic
);
END COMPONENT;
BEGIN
-- coverage off
ASSERT NOT NO_VALID_DEVICE(supported_device => SUPPORTED_DEVICES, device => FPGA_FAMILY) REPORT "No valid DEVICE!" SEVERITY failure;
-- coverage on
the_one_device : one_device
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy
);
END ARCHITECTURE fpga_pkg_2_16zxxx_arch;
fpga_pkg_2_16zyyy.vhd 0000664 0000000 0000000 00000005166 14574545710 0036570 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src/Source/examples -- SPDX-FileCopyrightText: 2008, MEN Mikro Elektronik Nuremberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : fpga_pkg_2 example for IP-Core top file
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2_16zyyy.vhd
-- Author : Florian Wombacher
-- Email : florian.wombacher@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2008-04-01
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
-- fpga_pkg_2_16zyyy.vhd
-- - many_devices.vhd
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: fpga_pkg_2_16zyyy.vhd,v $
-- Revision 1.2 2009/02/17 11:37:42 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:57 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/24 16:39:58 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/22 14:19:16 FWombacher
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY fpga_pkg_2_16zyyy IS
GENERIC (
FPGA_FAMILY : family_type := CYCLONE
);
PORT(
dummy : IN std_logic
);
END ENTITY;
ARCHITECTURE fpga_pkg_2_16zyyy_arch OF fpga_pkg_2_16zyyy IS
CONSTANT SUPPORTED_DEVICES : supported_family_types := (CYCLONE, CYCLONE2, A3P, ARRIA_GX);
COMPONENT many_devices
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : IN std_logic
);
END COMPONENT;
BEGIN
-- coverage off
ASSERT NOT NO_VALID_DEVICE(SUPPORTED_DEVICES => SUPPORTED_DEVICES, device => FPGA_FAMILY) REPORT "No valid DEVICE!" SEVERITY failure;
-- coverage on
the_many_devices : many_devices
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy
);
END ARCHITECTURE fpga_pkg_2_16zyyy_arch;
fpga_pkg_2_top_example.vhd 0000664 0000000 0000000 00000005550 14574545710 0037707 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src/Source/examples -- SPDX-FileCopyrightText: 2008, MEN Mikro Elektronik Nuremberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : fpga_pkg_2 example for top file
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2_top.vhd
-- Author : Florian Wombacher
-- Email : florian.wombacher@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2008-04-01
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
-- fpga_pkg_2_top.vhd
-- - fpga_pkg_2_16zxxx.vhd
-- - - one_device.vhd
-- - fpga_pkg_2_16zyyy.vhd
-- - - many_devices.vhd
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: fpga_pkg_2_top_example.vhd,v $
-- Revision 1.2 2009/02/17 11:37:37 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:55 FWombacher
-- Initial Revision
--
-- Revision 1.2 2008/10/24 16:39:55 FWombacher
-- more deatiled exampels
--
-- Revision 1.1 2008/10/22 14:19:16 FWombacher
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY fpga_pkg_2_top IS
PORT(
dummy_o : OUT std_logic;
dummy_i : IN std_logic
);
END ENTITY;
ARCHITECTURE fpga_pkg_2_top_arch OF fpga_pkg_2_top IS
CONSTANT FPGA_FAMILY : family_type := CYCLONE;
COMPONENT fpga_pkg_2_16zxxx
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : OUT std_logic
);
END COMPONENT;
COMPONENT fpga_pkg_2_16zyyy
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : IN std_logic
);
END COMPONENT;
BEGIN
the_one_device : fpga_pkg_2_16zxxx
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy_o
);
the_fpga_pkg_2_16zyyy : fpga_pkg_2_16zyyy
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy_i
);
END ARCHITECTURE fpga_pkg_2_top_arch;
many_devices.vhd 0000664 0000000 0000000 00000005334 14574545710 0035761 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src/Source/examples -- SPDX-FileCopyrightText: 2008, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : fpga_pkg_2 example for many devices
-- Project :
---------------------------------------------------------------
-- File : manny_devices.vhd
-- Author : Florian Wombacher
-- Email : Florian.Wombacher@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 08/10/17
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
-- exampel for fpga_pkg_2 usage
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: many_devices.vhd,v $
-- Revision 1.3 2008/11/21 15:16:58 FWombacher
-- changed name of the fpga_pkg to allow use together with local version
--
-- Revision 1.2 2008/10/24 16:40:00 FWombacher
-- more deatiled exampels
--
-- Revision 1.1 2008/10/22 14:19:18 FWombacher
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY many_devices IS
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : IN std_logic
);
END many_devices;
ARCHITECTURE many_devices_arch OF many_devices IS
COMPONENT cyclone_implementation
PORT
(
dummy : IN std_logic
);
END COMPONENT;
COMPONENT cyclone2_implementation
PORT
(
dummy : IN std_logic
);
END COMPONENT;
COMPONENT a3p_implementation
PORT
(
dummy : IN std_logic
);
END COMPONENT;
COMPONENT arria_gx_implementation
PORT
(
dummy : IN std_logic
);
END COMPONENT;
BEGIN
gen_cyc : IF (FPGA_FAMILY = CYCLONE) GENERATE
the_cyclone_implementation : cyclone_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
gen_cyc2 : IF (FPGA_FAMILY = CYCLONE2) GENERATE
the_cyclone2_implementation : cyclone2_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
gen_a3p : IF (FPGA_FAMILY = A3P) GENERATE
the_a3p_implementation : a3p_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
gen_ariagx : IF (FPGA_FAMILY = ARRIA_GX) GENERATE
the_arria_gx_implementation : arria_gx_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
END many_devices_arch;
one_device.vhd 0000664 0000000 0000000 00000003703 14574545710 0035411 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src/Source/examples -- SPDX-FileCopyrightText: 2008, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : fpga_pkg_2 example for one device
-- Project :
---------------------------------------------------------------
-- File : one_device.vhd
-- Author : Florian Wombacher
-- Email : Florian.Wombacher@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 08/10/17
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
-- exampel for fpga_pkg_2 usage
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: one_device.vhd,v $
-- Revision 1.3 2008/11/21 15:17:01 FWombacher
-- changed name of the fpga_pkg to allow use together with local version
--
-- Revision 1.2 2008/10/24 16:40:02 FWombacher
-- more deatiled exampels
--
-- Revision 1.1 2008/10/22 14:19:19 FWombacher
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY one_device IS
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : OUT std_logic
);
END one_device;
ARCHITECTURE one_device_arch OF one_device IS
COMPONENT cyclone_implementation
PORT
(
dummy : OUT std_logic
);
END COMPONENT;
BEGIN
gen_cyc : IF (FPGA_FAMILY = CYCLONE) GENERATE
the_cyclone_implementation : cyclone_implementation
PORT MAP (
dummy => dummy
);
END GENERATE;
END one_device_arch;
fpga_pkg_2.vhd 0000664 0000000 0000000 00000016321 14574545710 0033472 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z000-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Package for FPGA family type
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 24/10/06
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--! \desid
--! \archid
--! \desbody
---------------------------------------------------------------
--!\hierarchy
--!\endofhierarchy
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.8 $
--
-- $Log: fpga_pkg_2.vhd,v $
-- Revision 1.8 2014/11/19 10:10:34 FLenhardt
-- R: No support for device family "Cyclone V"
-- M: Added device family CYCLONE5 to family_type
--
-- Revision 1.7 2014/06/03 11:34:30 CSchwark
-- R: no support for device family SmartFusion2
-- M: added device family SF2 to family_type
--
-- Revision 1.6 2013/02/11 14:33:42 FLenhardt
-- * added CYCLONE4E
-- * added FUNCTION altera_device_family
--
-- Revision 1.5 2012/10/24 09:04:32 MMiehling
-- added ARRIA2_GX, ARRIA2_GZ
--
-- Revision 1.4 2010/12/22 14:22:27 TWickleder
-- added CYCLONE4
--
-- Revision 1.3 2010/05/05 10:27:55 TWickleder
-- added FUNCTION get_fsrev and conv_chr_to_int
--
-- Revision 1.2 2009/02/17 11:37:35 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:54 FWombacher
-- Initial Revision
--
-- Revision 1.2 2008/10/24 16:39:53 FWombacher
-- added comments
--
-- Revision 1.1 2008/10/22 14:19:15 FWombacher
-- Initial Revision
--
-- Revision 1.2 2007/12/12 14:04:48 mernst
-- Added Cyclone III device to FPGA_PKG
--
-- Revision 1.1 2006/11/27 14:15:26 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
PACKAGE fpga_pkg_2 IS
TYPE family_type IS (NONE, CYCLONE, CYCLONE2, CYCLONE3, CYCLONE4, CYCLONE4E, CYCLONE5, FLEX, ACEX, A3P, ARRIA_GX, ARRIA2_GX, ARRIA2_GZ, SF2);
TYPE supported_family_types IS array (natural range <>) OF family_type; -- for more than one supported devices
SUBTYPE supported_family_type IS family_type; -- for exactly one supported device
FUNCTION altera_device_family(FPGA_FAMILY : IN family_type) RETURN string;
-- CONSTANT fpga_family : family_type := CYCLONE3;
FUNCTION no_valid_device(
supported_devices : IN supported_family_types;
device : IN family_type )
RETURN boolean;
FUNCTION no_valid_device(
supported_device : IN supported_family_type;
device : IN family_type )
RETURN boolean;
FUNCTION get_fsrev(fsrev_str : IN string) RETURN std_logic_vector;
FUNCTION conv_chr_to_int(char : IN character) RETURN integer;
END fpga_pkg_2;
PACKAGE BODY fpga_pkg_2 IS
FUNCTION altera_device_family(FPGA_FAMILY : IN family_type) RETURN string IS
BEGIN
IF FPGA_FAMILY = CYCLONE THEN
RETURN "Cyclone";
ELSIF FPGA_FAMILY = CYCLONE2 THEN
RETURN "Cyclone II";
ELSIF FPGA_FAMILY = CYCLONE3 THEN
RETURN "Cyclone III";
ELSIF FPGA_FAMILY = CYCLONE4E THEN
RETURN "Cyclone IV E";
ELSIF FPGA_FAMILY = CYCLONE4 THEN
RETURN "Cyclone IV GX";
ELSIF FPGA_FAMILY = CYCLONE5 THEN
RETURN "Cyclone V";
ELSIF FPGA_FAMILY = ARRIA_GX THEN
RETURN "Arria GX";
ELSIF FPGA_FAMILY = ARRIA2_GX THEN
RETURN "Arria II GX";
ELSIF FPGA_FAMILY = ARRIA2_GZ THEN
RETURN "Arria II GZ";
--ELSIF FPGA_FAMILY = THEN
-- RETURN "";
ELSE
ASSERT FALSE REPORT "UNSUPPORTED ALTERA DEVICE" SEVERITY FAILURE;
RETURN "";
END IF;
END altera_device_family;
FUNCTION no_valid_device(
supported_devices : IN supported_family_types;
device : IN family_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
FOR i IN supported_devices'range LOOP
IF(device = supported_devices(i)) THEN
no_valid := FALSE;
ELSE
no_valid := no_valid;
END IF;
END LOOP;
RETURN no_valid;
END no_valid_device;
FUNCTION no_valid_device(
supported_device : IN supported_family_type;
device : IN family_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
IF(device = supported_device) THEN
no_valid := FALSE;
ELSE
no_valid := TRUE;
END IF;
RETURN no_valid;
END no_valid_device;
FUNCTION get_fsrev(fsrev_str : IN string) RETURN std_logic_vector IS
VARIABLE minor_no : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
VARIABLE major_no : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
VARIABLE scan_str : string(7 DOWNTO 1) := " ";
VARIABLE maj_str : string(3 DOWNTO 1) := " ";
VARIABLE min_str : string(3 DOWNTO 1) := " ";
VARIABLE fsrev_found : boolean := FALSE;
VARIABLE next_is_rev : boolean := FALSE;
VARIABLE major_found : boolean := FALSE;
VARIABLE minor_found : boolean := FALSE;
BEGIN
FOR i IN fsrev_str'range LOOP
scan_str := scan_str(6 DOWNTO 1) & fsrev_str(i); --shift string in
IF(scan_str = "%FSREV ") THEN fsrev_found := TRUE;
ELSIF(fsrev_found AND NOT next_is_rev) THEN
IF(scan_str(1) = ' ') THEN next_is_rev := TRUE; END IF;
ELSIF(next_is_rev AND NOT major_found) THEN
IF(scan_str(1) = '.') THEN major_found := TRUE; ELSE maj_str := maj_str(2 DOWNTO 1) & scan_str(1); END IF;
ELSIF(major_found AND NOT minor_found) THEN
IF(scan_str(1) = ' ') THEN minor_found := TRUE; ELSE min_str := min_str(2 DOWNTO 1) & scan_str(1); END IF;
ELSIF(minor_found) THEN exit;
END IF;
END LOOP;
minor_no := conv_std_logic_vector(100*conv_chr_to_int(min_str(3))+10*conv_chr_to_int(min_str(2))+conv_chr_to_int(min_str(1)),8);
major_no := conv_std_logic_vector(100*conv_chr_to_int(maj_str(3))+10*conv_chr_to_int(maj_str(2))+conv_chr_to_int(maj_str(1)),8);
RETURN (major_no&minor_no);
END get_fsrev;
FUNCTION conv_chr_to_int(char : IN character) RETURN integer IS
VARIABLE num : integer := 0;
BEGIN
CASE char IS
WHEN '0' => num := 0;
WHEN '1' => num := 1;
WHEN '2' => num := 2;
WHEN '3' => num := 3;
WHEN '4' => num := 4;
WHEN '5' => num := 5;
WHEN '6' => num := 6;
WHEN '7' => num := 7;
WHEN '8' => num := 8;
WHEN '9' => num := 9;
WHEN OTHERS => num := 0;
END CASE;
RETURN num;
END conv_chr_to_int;
END;
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z024-01_src/ 0000775 0000000 0000000 00000000000 14574545710 0027613 5 ustar 00root root 0000000 0000000 Manifest.py 0000664 0000000 0000000 00000000273 14574545710 0031656 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z024-01_src # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
files = [
"Source/iram_av.vhd",
"Source/iram_dp_wb.vhd",
"Source/iram_wb.vhd",
]
Source/ 0000775 0000000 0000000 00000000000 14574545710 0030774 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z024-01_src iram_av.vhd 0000664 0000000 0000000 00000011140 14574545710 0033112 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z024-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Internal RAM with Avalon I/F
-- Project : 16z024-01
---------------------------------------------------------------
-- File : iram_av.vhd
-- Author : Ferdinand Lenhardt
-- Email : Ferdinand.Lenhardt@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 30/05/05
---------------------------------------------------------------
-- Simulator : ModelSim-Altera 5.8e
-- Synthesis : Quartus II 4.2 SP1
---------------------------------------------------------------
-- Description :
--
-- This is a wrapper for "Internal RAM with Wishbone I/F".
-- For ACEX this module can be used only as a ROM.
---------------------------------------------------------------
-- Hierarchy:
--
-- iram_av
-- iram_wb
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.7 $
--
-- $Log: iram_av.vhd,v $
-- Revision 1.7 2009/01/27 14:30:15 FLenhardt
-- Added support for fpga_pkg_2
--
-- Revision 1.6 2007/11/21 13:46:03 FLenhardt
-- Added a commentary to generic USEDW_WIDTH
--
-- Revision 1.5 2006/02/27 16:49:41 TWickleder
-- Changed the handling of the generic read_only to use it in both interfaces
--
-- Revision 1.4 2005/10/19 14:24:18 flenhardt
-- Workaround for SOPC Builder bug regarding a generic of type BOOLEAN
--
-- Revision 1.3 2005/10/19 13:17:04 flenhardt
-- Added generic READ_ONLY
--
-- Revision 1.2 2005/06/28 09:13:47 flenhardt
-- Workaround for SOPC Builder bug regarding generics
--
-- Revision 1.1 2005/05/30 09:43:03 flenhardt
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.ALL;
ENTITY iram_av IS
GENERIC
(
fpga_family: family_type := CYCLONE; -- ACEX,CYCLONE,CYCLONE2,CYCLONE3,ARRIA_GX
read_only: natural := 0; -- 0=R/W, 1=R/O
usedw_width: positive := 6; -- 2**(usedw_width + 2) bytes
location: string := "iram.hex" -- string shall be empty if no HEX file
);
PORT
(
clk : IN std_logic; -- Wishbone clock
reset : IN std_logic; -- global async high active reset
-- Avalon signals
av_chipselect : IN std_logic; -- chip select
av_byteenable : IN std_logic_vector(3 DOWNTO 0); -- byte enable
av_write : IN std_logic; -- write enable
av_writedata : IN std_logic_vector(31 DOWNTO 0); -- write data
av_read : IN std_logic; -- read enable
av_readdata : OUT std_logic_vector(31 DOWNTO 0); -- read data
av_address : IN std_logic_vector((usedw_width + 1) DOWNTO 2);
av_waitrequest : OUT std_logic -- delay access
);
END iram_av;
ARCHITECTURE iram_av_arch OF iram_av IS
COMPONENT iram_wb
GENERIC
(
FPGA_FAMILY: family_type;
read_only: natural;
USEDW_WIDTH: positive;
LOCATION: string
);
PORT
(
clk : IN std_logic; -- Wishbone clock
rst : IN std_logic; -- global async high active reset
-- Wishbone signals
stb_i : IN std_logic; -- request
cyc_i : IN std_logic; -- chip select
ack_o : OUT std_logic; -- acknowledge
we_i : IN std_logic; -- write=1 read=0
sel_i : IN std_logic_vector(3 DOWNTO 0); -- byte enables
adr_i : IN std_logic_vector((usedw_width + 1) DOWNTO 2);
dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END COMPONENT;
SIGNAL wb_stb_i : std_logic;
SIGNAL wb_we_i : std_logic;
SIGNAL wb_ack_o : std_logic;
BEGIN
ram: iram_wb
GENERIC MAP
(
FPGA_FAMILY => FPGA_FAMILY,
read_only => read_only,
usedw_width => usedw_width,
location => location
)
PORT MAP
(
clk => clk,
rst => reset,
stb_i => wb_stb_i,
cyc_i => av_chipselect,
ack_o => wb_ack_o,
we_i => wb_we_i,
sel_i => av_byteenable,
adr_i => av_address,
dat_i => av_writedata,
dat_o => av_readdata
);
wb_stb_i <= av_write OR av_read;
wb_we_i <= av_write;
-- wait request only when stb_i and cyc_i active and no ackowledge yet.
av_waitrequest <= NOT(wb_ack_o) WHEN (av_chipselect='1' AND wb_stb_i='1') ELSE
'1';
END iram_av_arch;
iram_dp_wb.vhd 0000664 0000000 0000000 00000017463 14574545710 0033615 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z024-01_src/Source -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Dual Ported IRAM with Wishbone Interface
-- Project : -
---------------------------------------------------------------
-- File : iram_dp_wb.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 28/11/05
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: iram_dp_wb.vhd,v $
-- Revision 1.3 2007/11/21 13:46:06 FLenhardt
-- Added ERR output to Wishbone interfaces
--
-- Revision 1.2 2006/01/04 15:57:18 mmiehling
-- added generic usedw_width
--
-- Revision 1.1 2005/12/15 15:38:42 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library altera_mf;
use altera_mf.altera_mf_components.all;
ENTITY iram_dp_wb IS
GENERIC
(
USEDW_WIDTH : positive := 6; -- width of address vector (6 = one M4K)
SAME_CLK : boolean:= TRUE -- true: sl0_clk = sl1_clk; false: sl0_clk /= sl1_clk
);
PORT
(
rst : IN std_logic; -- global async high active reset
-- Wishbone Bus #0
sl0_clk : IN std_logic; -- Wishbone Bus #0 Clock
sl0_stb : IN std_logic; -- request
sl0_cyc : IN std_logic; -- chip select
sl0_ack : OUT std_logic; -- acknowledge
sl0_err : OUT std_logic; -- error
sl0_we : IN std_logic; -- write=1 read=0
sl0_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
sl0_adr : IN std_logic_vector(31 DOWNTO 0);
sl0_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
sl0_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
-- Wishbone Bus #0
sl1_clk : IN std_logic; -- Wishbone Bus #0 Clock
sl1_stb : IN std_logic; -- request
sl1_cyc : IN std_logic; -- chip select
sl1_ack : OUT std_logic; -- acknowledge
sl1_err : OUT std_logic; -- error
sl1_we : IN std_logic; -- write=1 read=0
sl1_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
sl1_adr : IN std_logic_vector(31 DOWNTO 0);
sl1_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
sl1_dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END iram_dp_wb;
ARCHITECTURE iram_dp_wb_arch OF iram_dp_wb IS
SIGNAL sl0_loc_be : std_logic_vector(3 DOWNTO 0);
SIGNAL sl0_ack_o_int : std_logic;
SIGNAL sl0_clk_int : std_logic;
SIGNAL sl0_write : std_logic;
SIGNAL sl1_loc_be : std_logic_vector(3 DOWNTO 0);
SIGNAL sl1_ack_o_int : std_logic;
SIGNAL sl1_clk_int : std_logic;
SIGNAL sl1_write : std_logic;
BEGIN
-------------------------------------------------------------------------------------------
-- WB #0 Interface
sl0_ack <= sl0_ack_o_int;
sl0_err <= '0';
sl0_write <= '1' WHEN sl0_ack_o_int = '1' AND sl0_we = '1' ELSE '0';
sl0: PROCESS(rst, sl0_clk_int)
BEGIN
IF(rst = '1') THEN
sl0_loc_be <= (OTHERS => '0');
sl0_ack_o_int <= '0';
ELSIF(sl0_clk_int'EVENT AND sl0_clk_int = '1') THEN
IF((sl0_stb = '1' AND sl0_cyc = '1') AND sl0_ack_o_int = '0') THEN
IF(sl0_we = '1') THEN
sl0_loc_be <= sl0_sel;
ELSE
sl0_loc_be <= (OTHERS => '0');
END IF;
sl0_ack_o_int <= '1';
ELSE
sl0_loc_be <= (OTHERS => '0');
sl0_ack_o_int <= '0';
END IF;
END IF;
END PROCESS sl0;
-------------------------------------------------------------------------------------------
-- WB #1 Interface
sl1_ack <= sl1_ack_o_int;
sl1_err <= '0';
sl1_write <= '1' WHEN sl1_ack_o_int = '1' AND sl1_we = '1' ELSE '0';
sl1: PROCESS(rst, sl1_clk_int)
BEGIN
IF(rst = '1') THEN
sl1_loc_be <= (OTHERS => '0');
sl1_ack_o_int <= '0';
ELSIF(sl1_clk_int'EVENT AND sl1_clk_int = '1') THEN
IF((sl1_stb = '1' AND sl1_cyc = '1') AND sl1_ack_o_int = '0') THEN
IF(sl1_we = '1') THEN
sl1_loc_be <= sl1_sel;
ELSE
sl1_loc_be <= (OTHERS => '0');
END IF;
sl1_ack_o_int <= '1';
ELSE
sl1_loc_be <= (OTHERS => '0');
sl1_ack_o_int <= '0';
END IF;
END IF;
END PROCESS sl1;
-------------------------------------------------------------------------------------------
gen_2clk: IF NOT SAME_CLK GENERATE
sl0_clk_int <= sl0_clk;
sl1_clk_int <= sl1_clk;
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
operation_mode => "BIDIR_DUAL_PORT",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
width_b => 32,
widthad_b => USEDW_WIDTH,
numwords_b => 2**USEDW_WIDTH,
lpm_type => "altsyncram",
width_byteena_a => 4,
width_byteena_b => 4,
byte_size => 8,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
outdata_reg_b => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
byteena_aclr_a => "NONE",
indata_reg_b => "CLOCK1",
address_reg_b => "CLOCK1",
wrcontrol_wraddress_reg_b => "CLOCK1",
indata_aclr_b => "NONE",
wrcontrol_aclr_b => "NONE",
address_aclr_b => "NONE",
byteena_reg_b => "CLOCK1",
byteena_aclr_b => "NONE",
outdata_aclr_b => "NONE",
power_up_uninitialized => "FALSE",
init_file => "iram.hex"
)
PORT MAP (
clock0 => sl0_clk,
wren_a => sl0_write,
byteena_a => sl0_loc_be,
address_a => sl0_adr(USEDW_WIDTH+1 DOWNTO 2),
data_a => sl0_dat_i,
q_a => sl0_dat_o,
clock1 => sl1_clk,
wren_b => sl1_write,
byteena_b => sl1_loc_be,
address_b => sl1_adr(USEDW_WIDTH+1 DOWNTO 2),
data_b => sl1_dat_i,
q_b => sl1_dat_o);
END GENERATE gen_2clk;
gen_1clk: IF SAME_CLK GENERATE
sl0_clk_int <= sl0_clk;
sl1_clk_int <= sl0_clk;
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
ram_block_type => "M4K",
operation_mode => "BIDIR_DUAL_PORT",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
width_b => 32,
widthad_b => USEDW_WIDTH,
numwords_b => 2**USEDW_WIDTH,
lpm_type => "altsyncram",
width_byteena_a => 4,
width_byteena_b => 4,
byte_size => 8,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
outdata_reg_b => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
byteena_aclr_a => "NONE",
indata_reg_b => "CLOCK0",
address_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
indata_aclr_b => "NONE",
wrcontrol_aclr_b => "NONE",
address_aclr_b => "NONE",
byteena_reg_b => "CLOCK0",
byteena_aclr_b => "NONE",
outdata_aclr_b => "NONE",
read_during_write_mode_mixed_ports => "OLD_DATA",
power_up_uninitialized => "FALSE",
init_file => "iram.hex")
PORT MAP (
clock0 => sl0_clk,
wren_a => sl0_write,
byteena_a => sl0_loc_be,
address_a => sl0_adr(USEDW_WIDTH+1 DOWNTO 2),
data_a => sl0_dat_i,
q_a => sl0_dat_o,
wren_b => sl1_write,
byteena_b => sl1_loc_be,
address_b => sl1_adr(USEDW_WIDTH+1 DOWNTO 2),
data_b => sl1_dat_i,
q_b => sl1_dat_o);
END GENERATE gen_1clk;
END iram_dp_wb_arch;
iram_wb.vhd 0000664 0000000 0000000 00000016736 14574545710 0033134 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z024-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Internal RAM with Wishbone I/F
-- Project : 16z024-01
---------------------------------------------------------------
-- File : iram_wb.vhd
-- Author : Ferdinand Lenhardt
-- Email : Ferdinand.Lenhardt@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/05/05
---------------------------------------------------------------
-- Simulator : ModelSim-Altera 5.8e
-- Synthesis : Quartus II 4.2 SP1
---------------------------------------------------------------
-- Description :
--
-- This module includes an arbitrary number of FPGA block RAMs.
-- A HEX (Intel-Format) file can be used to initialize the RAM.
-- For ACEX this module can be used only as a ROM.
---------------------------------------------------------------
-- Hierarchy:
--
-- iram_wb
-- lpm_ram_dq
-- altsyncram
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.8 $
--
-- $Log: iram_wb.vhd,v $
-- Revision 1.8 2017/05/10 Greg Daniluk
-- Generalized to instantiate altsyncram (for Cyclone, Cyclone2, Cyclone3,
-- Cyclone4, Cyclone 5, Arria GX) and lpm_ram_dq (for Acex).
--
-- Revision 1.7 2014/11/20 14:45:22 AGeissler
-- R1: Missing Cyclone V support
-- M1: Added Cyclone V support
--
-- Revision 1.6 2010/12/17 17:04:48 FWombacher
-- Added Cyclone IV RAM instance
--
-- Revision 1.5 2009/01/27 14:30:13 FLenhardt
-- Added support for fpga_pkg_2 (ACEX,ARRIA_GX,CYCLONE2,CYCLONE3)
--
-- Revision 1.4 2007/11/21 13:46:01 FLenhardt
-- Added a commentary to generic USEDW_WIDTH
-- Added ERR output to Wishbone interface
--
-- Revision 1.3 2006/02/27 16:49:39 TWickleder
-- Added read_only as generic to disable the we signal
--
-- Revision 1.2 2005/11/28 15:05:45 mmiehling
-- bug fix: (stb_i AND cyc_i) = '1' => (stb_i = '1' AND cyc_i = '1')
--
-- Revision 1.1 2005/05/30 09:43:02 flenhardt
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.ALL;
library lpm;
use lpm.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
ENTITY iram_wb IS
GENERIC
(
FPGA_FAMILY: family_type := CYCLONE; -- ACEX,CYCLONE,CYCLONE2,CYCLONE3,CYCLONE4,CYCLONE5,ARRIA_GX
read_only: natural := 0; -- 0=R/W, 1=R/O
USEDW_WIDTH: positive := 6; -- 2**(USEDW_WIDTH + 2) bytes
LOCATION: string := "iram.hex" -- string shall be empty if no HEX file
);
PORT
(
clk : IN std_logic; -- Wishbone clock
rst : IN std_logic; -- global async high active reset
-- Wishbone signals
stb_i : IN std_logic; -- request
cyc_i : IN std_logic; -- chip select
ack_o : OUT std_logic; -- acknowledge
err_o : OUT std_logic; -- error
we_i : IN std_logic; -- write=1 read=0
sel_i : IN std_logic_vector(3 DOWNTO 0); -- byte enables
adr_i : IN std_logic_vector((USEDW_WIDTH + 1) DOWNTO 2);
dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END iram_wb;
ARCHITECTURE iram_wb_arch OF iram_wb IS
CONSTANT SUPPORTED_DEVICES : supported_family_types := (ACEX,CYCLONE,CYCLONE2,CYCLONE3,CYCLONE4,CYCLONE5,ARRIA_GX);
COMPONENT lpm_ram_dq
GENERIC (
lpm_address_control : STRING;
lpm_file : STRING;
lpm_indata : STRING;
lpm_outdata : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthad : NATURAL);
PORT (
address : IN STD_LOGIC_VECTOR ((USEDW_WIDTH - 1) DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
we : IN STD_LOGIC);
END COMPONENT;
SIGNAL ack_o_int: std_logic;
SIGNAL we_int: std_logic;
SIGNAL sel_int: std_logic_vector(3 DOWNTO 0);
SIGNAL dat_int: std_logic_vector(31 DOWNTO 0);
BEGIN
gen_we: IF read_only = 0 GENERATE
we_control: PROCESS(rst, clk)
BEGIN
IF(rst = '1') THEN
we_int <= '0';
ELSIF(clk'EVENT AND clk = '1') THEN
IF((stb_i = '1' AND cyc_i = '1') AND ack_o_int = '0') THEN
we_int <= we_i;
ELSE
we_int <= '0';
END IF;
END IF;
END PROCESS we_control;
sel_int <= sel_i;
dat_int <= dat_i;
END GENERATE;
dis_we: IF read_only = 1 GENERATE
we_int <= '0';
dat_int <= (OTHERS => '0');
END GENERATE;
dis_sel: IF(read_only = 1 AND FPGA_FAMILY /= ACEX) GENERATE
sel_int <= (OTHERS => '0');
END GENERATE dis_sel;
gen_acex: IF(FPGA_FAMILY = ACEX) GENERATE
gen_acex_rom: IF(read_only = 1) GENERATE
lpm_ram_dq_component : lpm_ram_dq
GENERIC MAP (
lpm_address_control => "REGISTERED",
lpm_file => LOCATION,
lpm_indata => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_type => "LPM_RAM_DQ",
lpm_width => 32,
lpm_widthad => USEDW_WIDTH)
PORT MAP (
address => adr_i,
inclock => clk,
data => dat_int,
we => we_int,
q => dat_o);
END GENERATE gen_acex_rom;
ASSERT(read_only = 1) REPORT "IRAM: Read only for ACEX!" SEVERITY failure;
END GENERATE gen_acex;
gen_cyc: IF(FPGA_FAMILY = CYCLONE) GENERATE
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
operation_mode => "SINGLE_PORT",
outdata_reg_a => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
outdata_aclr_a => "NONE",
width_byteena_a => 4,
byte_size => 8,
byteena_aclr_a => "NONE",
init_file => LOCATION,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram")
PORT MAP (
wren_a => we_int,
clock0 => clk,
byteena_a => sel_int,
address_a => adr_i,
data_a => dat_int,
q_a => dat_o);
END GENERATE gen_cyc;
gen_cyclones: if(FPGA_FAMILY=CYCLONE2 or FPGA_FAMILY=CYCLONE3 or
FPGA_FAMILY=CYCLONE4 or FPGA_FAMILY=CYCLONE5 or FPGA_FAMILY=ARRIA_GX) generate
altsyncram_component : altsyncram
GENERIC MAP (
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => LOCATION,
intended_device_family => altera_device_family(FPGA_FAMILY),
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**USEDW_WIDTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
widthad_a => USEDW_WIDTH,
width_a => 32,
width_byteena_a => 4
)
PORT MAP (
wren_a => we_int,
clock0 => clk,
byteena_a => sel_int,
address_a => adr_i,
data_a => dat_int,
q_a => dat_o);
end generate;
ASSERT NOT NO_VALID_DEVICE(supported_devices => SUPPORTED_DEVICES, device => FPGA_FAMILY) REPORT "IRAM: No valid DEVICE!" SEVERITY failure;
control_logic: PROCESS(rst, clk)
BEGIN
IF(rst = '1') THEN
ack_o_int <= '0';
ELSIF(clk'EVENT AND clk = '1') THEN
IF((stb_i = '1' AND cyc_i = '1') AND ack_o_int = '0') THEN
ack_o_int <= '1';
ELSE
ack_o_int <= '0';
END IF;
END IF;
END PROCESS control_logic;
ack_o <= ack_o_int;
err_o <= '0';
END iram_wb_arch;
Synthesis/ 0000775 0000000 0000000 00000000000 14574545710 0031525 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z024-01_src constraints_16z024-01.tcl 0000664 0000000 0000000 00000001350 14574545710 0035743 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z024-01_src/Synthesis # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
# files to be included
set_global_assignment -name VHDL_FILE "../16z024-01_src/Source/iram_acex.vhd"
set_global_assignment -name VHDL_FILE "../16z024-01_src/Source/iram.vhd"
set_global_assignment -name VHDL_FILE "../16z024-01_src/Source/iram_arriagx.vhd"
set_global_assignment -name VHDL_FILE "../16z024-01_src/Source/iram_cyc2.vhd"
set_global_assignment -name VHDL_FILE "../16z024-01_src/Source/iram_cyc3.vhd"
set_global_assignment -name VHDL_FILE "../16z024-01_src/Source/iram_cyc4.vhd"
set_global_assignment -name VHDL_FILE "../16z024-01_src/Source/iram_wb.vhd"
set_global_assignment -name VHDL_FILE "../16z024-01_src/Source/iram_av.vhd"
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/ 0000775 0000000 0000000 00000000000 14574545710 0027617 5 ustar 00root root 0000000 0000000 Manifest.py 0000664 0000000 0000000 00000001322 14574545710 0031656 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
files = [
"Source/error.vhd",
"Source/generic_dcfifo_mixedw.vhd",
"Source/init.vhd",
"Source/interrupt_core.vhd",
"Source/interrupt_wb.vhd",
"Source/ip_16z091_01_top.vhd",
"Source/ip_16z091_01.vhd",
"Source/pcie_msi.vhd",
"Source/rx_ctrl.vhd",
"Source/rx_get_data.vhd",
"Source/rx_len_cntr.vhd",
"Source/rx_module.vhd",
"Source/src_utils_pkg.vhd",
"Source/tx_compl_timeout.vhd",
"Source/tx_ctrl.vhd",
"Source/tx_module.vhd",
"Source/tx_put_data.vhd",
"Source/z091_01_wb_master.vhd",
"Source/z091_01_wb_slave.vhd",
"Synthesis/z91_01_tmg_con.sdc",
]
README.rst 0000664 0000000 0000000 00000046056 14574545710 0031242 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src .. SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
..
.. SPDX-License-Identifier: CC-BY-SA-4.0+
16z091-01 IP core, Wishbone to PCIe bridge
==========================================
General description
-------------------
This IP core implements a Wishbone to PCIe bridge. The Wishbone interface is
32bit, the PCIe side allows x1, x2 and x4 configurations. Details concerning the
architecture of this IP core can be found in
inStep -> _MAIN -> 16Z091-/16Z091-01/Specifications/work/16Z091-01_IcArchSpec.doc
Integration advice
------------------
+------------------+
| Generic settings |
+------------------+
Some of the generics remain constant for all MEN devices. Thus their default value should be used:
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
Other generics can be adapted to the special needs of each top level design:
generics with restricted values:
--------------------------------
SIMULATION : std_logic := '0';
possible values:
=1 := simulation
=0 := synthesis
FPGA_FAMILY : family_type := NONE;
possible values: CYCLONE4, CYCLONE5
USE_LANES : std_logic_vector(2 downto 0) := "001";
possible values:
="001" := 1 lane
="010" := 2 lanes
="100" := 4 lanes
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
possible values according to FPGA_overview.xls
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000010000"; -- 16DW = 64Byte
typical values:
="0000010000" := 16DW = 64Byte
="0000100000" := 32DW = 128Byte
generics with any value within given range:
-------------------------------------------
IRQ_WIDTH : integer range 32 downto 1 := 1;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
BAR management - define how many BARs are used, if they are memory or I/O mapped and which size they have.
The minimum address range requested is 128 bytes.
Settings for BAR_MASK:
31 downto 7 := base address, configure the desired size with '0'
6 downto 4 := RESERVED
3 := prefetchable, set to '1' if prefetchable, otherwise '0'
2 downto 1 := type, must be "00" to denote 32bit encoder
0 := memory space indicator, =0 for memory, =1 for I/O
Examples:
BAR_MASK_x <= x"FFFFF000" => default setting for unused BARs
BAR_MASK_x <= x"FFF00000" => Size of BAR is 1MB, memory mapped
BAR_MASK_x <= x"FFFC0001" => Size of BAR is 256kB, IO mapped
BAR_MASK_x <= x"FF800008" => Size of BAR is 8MB, memory mapped, prefechable
BAR_MASK_x <= x"FFFFF000" => Size of BAR is 4kB, memory mapped, smallest size for memory mapping
BAR_MASK_x <= x"FFFFFF01" => Size of BAR is 256B, memory mapped, largest size of IO mapping
BAR_MASK_x <= x"FFFFFFFD" => Size of BAR is 4B, memory mapped, smallest size of IO mapping
NR_OF_BARS_USED : natural range 6 downto 1 := 5;
BAR_MASK_0 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_1 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_2 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_3 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_4 : std_logic_vector(31 downto 0) := x"FF000001";
BAR_MASK_5 : std_logic_vector(31 downto 0) := x"FF000001";
ROM_MASK : std_logic_vector(31 downto 0) := x"FFFF0000";
Manage internal FIFO widths for RX and TX FIFOs:
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10; -- RX FIFO
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5; -- TX FIFO for header information
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10; -- TX FIFO for user data
generic for debugging:
----------------------
GP_DEBUG_PORT_WIDTH : positive := 1
+-------------------+
| Cyclone V support |
+-------------------+
Cyclone V support is added to the 16z091-01 top file using a new architecture. Therefore you specify it
using configurations just as described above.
Example:
configuration ip_16z091_01_top_cfg of ip_16z091_01_top is
--for ip_16z091_01_top_arch <-- use this for Cyclone IV
for ip_16z091_01_top_cycv_arch <-- use this for Cyclone V
for ip_16z091_01_comp : ip_16z091_01
use configuration work.ip_16z091_01_cfg;
end for;
end for;
end configuration ip_16z091_01_top_cfg;
+------------+
| Simulation |
+------------+
* add fpga_pkg_2:
../../16z000-/Source/fpga_pkg_2.vhd
* first of all add the special simulation sources for the hard IP to your compile script:
for Cyclone IV add
../Source/x1/Simulation/altpcie_rs_serdes.vhd \
../Source/x1/Simulation/altpcie_pll_100_250.vhd \
../Source/x1/Simulation/altpcie_pll_125_250.vhd \
../Source/x1/Simulation/Hard_IP_x1_core.vho
for Cyclone V add
vlog -work work \
../Source/CycV/altpcie_cv_hip_ast_hwtcl.v \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altpcie_rs_serdes.v \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altpcie_rs_serdes.v \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altpcie_rs_hip.v \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altpcie_rs_hip.v \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altpcie_av_hip_128bit_atom.v \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altpcie_av_hip_128bit_atom.v \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altpcie_av_hip_ast_hwtcl.v \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altpcie_av_hip_ast_hwtcl.v \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altera_xcvr_functions.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altera_xcvr_functions.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/sv_reconfig_bundle_to_xcvr.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/sv_reconfig_bundle_to_ip.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/sv_reconfig_bundle_merger.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/sv_reconfig_bundle_to_xcvr.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/sv_reconfig_bundle_to_ip.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/sv_reconfig_bundle_merger.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_h.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_avmm_csr.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_tx_pma_ch.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_tx_pma.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_rx_pma.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_pma.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_pcs_ch.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_pcs.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_avmm.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_native.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_plls.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_data_adapter.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_reconfig_bundle_to_basic.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_reconfig_bundle_to_xcvr.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_h.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_avmm_csr.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_tx_pma_ch.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_tx_pma.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_rx_pma.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_pma.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_pcs_ch.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_pcs.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_avmm.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_native.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_plls.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_data_adapter.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_reconfig_bundle_to_basic.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_reconfig_bundle_to_xcvr.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_8g_rx_pcs_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_8g_tx_pcs_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_common_pcs_pma_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_common_pld_pcs_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_pipe_gen1_2_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_rx_pcs_pma_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_rx_pld_pcs_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_tx_pcs_pma_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_hssi_tx_pld_pcs_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_8g_rx_pcs_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_8g_tx_pcs_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_common_pcs_pma_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_common_pld_pcs_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_pipe_gen1_2_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_rx_pcs_pma_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_rx_pld_pcs_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_tx_pcs_pma_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_hssi_tx_pld_pcs_interface_rbc.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_reset_ctrl_lego.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_reset_ctrl_tgx_cdrauto.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_resync.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_reset_ctrl_lego.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_reset_ctrl_tgx_cdrauto.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_resync.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_common_h.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_common.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_pcs8g_h.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_pcs8g.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_csr_selector.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/alt_xcvr_mgmt2dec.sv \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/altera_wait_generate.v \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_common_h.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_common.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_pcs8g_h.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_pcs8g.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_csr_selector.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/alt_xcvr_mgmt2dec.sv \
../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/altera_wait_generate.v \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_emsip_adapter.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/av_xcvr_pipe_native_hip.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_emsip_adapter.sv \
-sv ../Source/CycV/PCIeHardIPCycV_sim/altera_pcie_cv_hip_ast/mentor/av_xcvr_pipe_native_hip.sv
vcom -work work ../Source/CycV/PCIeHardIPCycV.vhd
#------------------------------------
# compile files for reconfig module
#------------------------------------
vcom -work work ../Source/CycV/CycVTransReconf.vhd
* below the special files add all 16z091-01 sources to your compile script according to
the following list:
../Source/src_utils_pkg.vhd \
../Source/alt_reconf.vhd \
../Source/rx_fifo.vhd \
../Source/tx_data_fifo.vhd \
../Source/tx_header_fifo.vhd \
../Source/err_fifo.vhd \
../Source/rx_len_cntr.vhd \
../Source/rx_get_data.vhd \
../Source/rx_ctrl.vhd \
../Source/rx_module.vhd \
../Source/z091_01_wb_master.vhd \
../Source/error.vhd \
../Source/tx_put_data.vhd \
../Source/tx_compl_timeout.vhd \
../Source/tx_ctrl.vhd \
../Source/tx_module.vhd \
../Source/init.vhd \
../Source/z091_01_wb_slave.vhd \
../Source/interrupt_core.vhd \
../Source/interrupt_wb.vhd \
../Source/ip_16z091_01.vhd \
../Source/z091_01_wb_adr_dec.vhd \ <-- change this line to your top-level source folder and your version of the z091_01_wb_adr_dec
../Source/x1/Hard_IP_x1_serdes.vhd \
../Source/x1/Hard_IP_x1.vhd \
../Source/ip_16z091_01_top.vhd
+-----------+
| Synthesis |
+-----------+
* add the package files to your *.qsf file:
set_global_assignment -name VHDL_FILE "../../16z000-/Source/fpga_pkg_2.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/src_utils_pkg.vhd"
* add special Veriolog files that are needed for the hard IP:
for Cyclone IV add
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/alt_reconf.vhd"
set_global_assignment -name VERILOG_FILE "../../../../16/16z091-01/Source/x1/ip_compiler_for_pci_express-library/pciexp_dcram.v"
set_global_assignment -name VERILOG_FILE "../../../../16/16z091-01/Source/x1/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v"
set_global_assignment -name VERILOG_FILE "../../../../16/16z091-01/Source/x1/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v"
for Cyclone V add (as well described in z091_01_syn_con_cyc5.tcl)
set_global_assignment -name VHDL_FILE "../../../16z091-01/Source/CycV/PCIeHardIPCycV.vhd" -library PCIeHardIPCycV
set_global_assignment -name VHDL_FILE "../../../16z091-01/Source/CycV/CycVTransReconf.vhd" -library CycVTransReconf
set_global_assignment -name QIP_FILE "../../../16z091-01/Source/CycV/PCIeHardIPCycV.qip"
set_global_assignment -name QIP_FILE "../../../16z091-01/Source/CycV/CycVTransReconf.qip"
* add the 16z091-01 source files to your *.qsf file:
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/x1/Hard_IP_x1_serdes.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/x1/Hard_IP_x1_core.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/x1/Hard_IP_x1.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/z091_01_wb_adr_dec.vhd" <-- change this line to your top-level
source folder and your version of the
z091_01_wb_adr_dec
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/z091_01_wb_slave.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/z091_01_wb_master.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_put_data.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_header_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_data_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_compl_timeout.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/tx_module.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_len_cntr.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_get_data.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/rx_module.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/interrupt_wb.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/interrupt_core.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/init.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/err_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/error.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/ip_16z091_01.vhd"
set_global_assignment -name VHDL_FILE "../../../../16/16z091-01/Source/ip_16z091_01_top.vhd"
* add the 16z091-01 timing constraints to your *.sdc file:
for Cyclone IV add
set_global_assignment -name SDC_FILE z91_01_tmg_con.sdc
for Cyclone V add
set_global_assignment -name SDC_FILE z91_01_tmg_con_cyc5.sdc
=> files are located in /16z091-01/Synthesis
Source/ 0000775 0000000 0000000 00000000000 14574545710 0031000 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src CycV/ 0000775 0000000 0000000 00000000000 14574545710 0031644 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source x1/ 0000775 0000000 0000000 00000000000 14574545710 0032174 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV .gitignore 0000664 0000000 0000000 00000000200 14574545710 0034154 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x1 # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!*.txt
!cycv_x1.tcl
CycVTransReconf.txt 0000664 0000000 0000000 00000002172 14574545710 0035750 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x1 -- megafunction wizard: %Transceiver Reconfiguration Controller v16.0%
-- GENERATION: XML
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PCIeHardIPCycV.txt 0000664 0000000 0000000 00000075335 14574545710 0035347 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x1 -- megafunction wizard: %Cyclone V Hard IP for PCI Express v16.0%
-- GENERATION: XML
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cycv_x1.tcl 0000664 0000000 0000000 00000000223 14574545710 0034251 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x1 # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
qmegawiz { CycVTransReconf PCIeHardIPCycV }
x2/ 0000775 0000000 0000000 00000000000 14574545710 0032175 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV .gitignore 0000664 0000000 0000000 00000000200 14574545710 0034155 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x2 # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!*.txt
!cycv_x2.tcl
CycVTransReconf.txt 0000664 0000000 0000000 00000002172 14574545710 0035751 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x2 -- megafunction wizard: %Transceiver Reconfiguration Controller v16.0%
-- GENERATION: XML
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PCIeHardIPCycV.txt 0000664 0000000 0000000 00000075335 14574545710 0035350 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x2 -- megafunction wizard: %Cyclone V Hard IP for PCI Express v16.0%
-- GENERATION: XML
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cycv_x2.tcl 0000664 0000000 0000000 00000000223 14574545710 0034253 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x2 # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
qmegawiz { CycVTransReconf PCIeHardIPCycV }
x4/ 0000775 0000000 0000000 00000000000 14574545710 0032177 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV .gitignore 0000664 0000000 0000000 00000000200 14574545710 0034157 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x4 # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!*.txt
!cycv_x4.tcl
CycVTransReconf.txt 0000664 0000000 0000000 00000002172 14574545710 0035753 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x4 -- megafunction wizard: %Transceiver Reconfiguration Controller v16.0%
-- GENERATION: XML
-- Retrieval info:
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PCIeHardIPCycV.txt 0000664 0000000 0000000 00000075335 14574545710 0035352 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x4 -- megafunction wizard: %Cyclone V Hard IP for PCI Express v16.0%
-- GENERATION: XML
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cycv_x4.tcl 0000664 0000000 0000000 00000000223 14574545710 0034257 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/CycV/x4 # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
qmegawiz { CycVTransReconf PCIeHardIPCycV }
alt_reconf/ 0000775 0000000 0000000 00000000000 14574545710 0033114 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source .gitignore 0000664 0000000 0000000 00000000207 14574545710 0035103 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/alt_reconf # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!*.txt
!gen_alt_reconf.tcl
alt_reconf.txt 0000664 0000000 0000000 00000004234 14574545710 0035774 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/alt_reconf -- megafunction wizard: %ALTGX_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt_c3gxb_reconfig
-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: PMA NUMERIC "1"
-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: CONSTANT: BASE_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
-- Retrieval info: CONSTANT: ENABLE_CHL_ADDR_FOR_ANALOG_CTRL STRING "TRUE"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
-- Retrieval info: CONSTANT: READ_BASE_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "5"
-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 INPUT NODEFVAL "reconfig_fromgxb[4..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 5 0 reconfig_fromgxb 0 0 5 0
-- Retrieval info: CONNECT: @reconfig_mode_sel 0 0 3 0 GND 0 0 3 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_reconf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_reconf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_reconf.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_reconf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_reconf_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
gen_alt_reconf.tcl 0000664 0000000 0000000 00000000177 14574545710 0036572 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/alt_reconf # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
qmegawiz { alt_reconf }
error.vhd 0000664 0000000 0000000 00000022102 14574545710 0032631 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Error Module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : error.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- errors on RxModule, TxModule or hard IP core are collected here and passed
-- to Wishbone modules through a FIFO
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- * error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity error is
port(
clk : in std_logic;
rst : in std_logic;
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Rx Module
rx_tag_id : in std_logic_vector(7 downto 0);
rx_ecrc_err : in std_logic;
rx_type_fmt_err : in std_logic_vector(1 downto 0);
-- Tx Module
tx_compl_abort : in std_logic;
tx_timeout : in std_logic;
-- Interrupt
wb_num_err : in std_logic;
-- Wishbone
error_ecrc_err : out std_logic;
error_timeout : out std_logic;
error_tag_id : out std_logic_vector(7 downto 0);
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- IP Core
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic
);
end entity error;
-- ****************************************************************************
architecture error_arch of error is
-- internal signals -----------------------------------------------------------
signal err_fifo_clr : std_logic;
signal err_fifo_wr_enable : std_logic;
signal err_fifo_in : std_logic_vector(15 downto 0);
-- uncomment next line when increasing FIFO depth
-- signal err_fifo_full : std_logic;
signal err_fifo_rd_enable : std_logic;
signal err_fifo_out : std_logic_vector(15 downto 0);
signal err_fifo_empty : std_logic;
signal get_value : std_logic;
signal wb_num_err_q : std_logic;
signal wb_num_err_qq : std_logic;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
signal ip_error_in : std_logic_vector(14 downto 0);
signal ip_error_last : std_logic_vector(14 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-- instantiate components -----------------------------------------------------
err_fifo_comp: entity work.generic_async_fifo
generic map (
g_data_width => 16,
g_size => 8,
g_show_ahead => False,
g_with_rd_empty => True,
g_with_rd_full => False,
g_with_rd_almost_empty => False,
g_with_rd_almost_full => False,
g_with_rd_count => False,
g_with_wr_empty => False,
g_with_wr_full => False,
g_with_wr_almost_empty => False,
g_with_wr_almost_full => False,
g_with_wr_count => False,
g_almost_empty_threshold => 1,
g_almost_full_threshold => 1,
g_memory_implementation_hint => open
)
port map (
rst_n_i => err_fifo_clr,
clk_wr_i => clk,
d_i => err_fifo_in,
we_i => err_fifo_wr_enable,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => open,
clk_rd_i => wb_clk,
q_o => err_fifo_out,
rd_i => err_fifo_rd_enable,
rd_empty_o => err_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open
);
-------------------------------------------------------------------------------
fifo_wr : process(clk, rst)
begin
if(rst = '1') then
err_fifo_wr_enable <= '0';
err_fifo_in <= (others => '0');
err_fifo_clr <= '1';
ip_error_last <= (others => '0');
elsif(clk'event and clk = '1') then
err_fifo_clr <= '0';
-- store errors if new error occred
if(ip_error_last /= ip_error_in) then
err_fifo_wr_enable <= '1';
err_fifo_in <= '0' & ip_error_in;
ip_error_last <= ip_error_in;
end if;
-- reset signals
if(err_fifo_wr_enable = '1') then
err_fifo_wr_enable <= '0';
err_fifo_in <= (others => '0');
end if;
end if;
end process fifo_wr;
-------------------------------------------------------------------------------
fifo_rd : process(wb_clk, wb_rst)
begin
if(wb_rst = '1') then
error_timeout <= '0';
error_r2c0 <= '0';
error_rpl <= '0';
error_cor_ext_rpl <= '0';
error_cor_ext_rcv <= (others => '0');
error_ecrc_err <= '0';
error_tag_id <= (others => '0');
error_msi_num <= '0';
err_fifo_rd_enable <= '0';
get_value <= '0';
wb_num_err_q <= '0';
wb_num_err_qq <= '0';
elsif(wb_clk'event and wb_clk = '1') then
-- sample wb_num_err because this is synchronous to clk
wb_num_err_q <= wb_num_err;
wb_num_err_qq <= wb_num_err_q;
-- read values as soon as they appear
if(err_fifo_empty = '0') then
err_fifo_rd_enable <= '1';
end if;
-- reset enable an start analysis of value read from FIFO
if(err_fifo_rd_enable = '1') then
err_fifo_rd_enable <= '0';
get_value <= '1';
end if;
-- propagate error signals to outer environment
if(get_value = '1') then
get_value <= '0';
error_timeout <= err_fifo_out(14);
error_r2c0 <= err_fifo_out(13);
error_rpl <= err_fifo_out(12);
error_cor_ext_rpl <= err_fifo_out(11);
error_cor_ext_rcv <= err_fifo_out(10 downto 9);
error_ecrc_err <= err_fifo_out(8);
error_tag_id <= err_fifo_out(7 downto 0);
else
error_timeout <= '0';
error_r2c0 <= '0';
error_rpl <= '0';
error_cor_ext_rpl <= '0';
error_cor_ext_rcv <= (others => '0');
error_ecrc_err <= '0';
error_tag_id <= (others => '0');
end if;
-- propagate error signals to outer environment
error_msi_num <= wb_num_err_qq;
end if;
end process fifo_rd;
-------------------------------------------------------------------------------
-- capture occuring errors
ip_error_in(14) <= '1' when tx_timeout = '1' else '0';
ip_error_in(13) <= '1' when r2c_err0 = '1' else '0';
ip_error_in(12) <= '1' when derr_rpl = '1' else '0';
ip_error_in(11) <= '1' when derr_cor_ext_rpl = '1' else '0';
ip_error_in(10 downto 9) <= derr_cor_ext_rcv when derr_cor_ext_rcv /= "00" else "00";
ip_error_in(8) <= '1' when rx_ecrc_err = '1' else '0';
ip_error_in(7 downto 0) <= rx_tag_id when rx_ecrc_err = '1' else (others => '0');
cpl_err(6) <= '0';
cpl_err(5) <= '0' when rst = '1' else
'1' when rx_type_fmt_err = "01" else
'0';
cpl_err(4) <= '0' when rst = '1' else
'1' when rx_type_fmt_err = "10" else
'0';
cpl_err(3) <= '0';
cpl_err(2) <= '0' when rst = '1' else
'1' when tx_compl_abort = '1' else
'0';
cpl_err(1 downto 0) <= (others => '0');
cpl_pending <= '0';
-------------------------------------------------------------------------------
end architecture error_arch;
generic_dcfifo_mixedw.vhd 0000664 0000000 0000000 00000004270 14574545710 0036011 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2017, CERN
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Generic Altera Fifo
-- Project : PCIe-to-VME bridge
--------------------------------------------------------------------------------
-- File : generic_dcfifo_mixedw.vhd
-- Author : Grzegorz Daniluk
-- Email : grzegorz.daniluk@cern.ch
-- Organization: CERN
-- Created : 17/05/2017
--------------------------------------------------------------------------------
-- Description :
-- Generic, parametrized mixed width fifo based on Altera dcfifo.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity generic_dcfifo_mixedw is
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end generic_dcfifo_mixedw;
architecture syn of generic_dcfifo_mixedw is
signal rst_n_a : std_logic;
begin
rst_n_a <= not aclr;
inst_fifo: entity work.generic_async_fifo_mixedw
generic map (
g_wr_width => g_data_width,
g_rd_width => g_q_width,
g_size => g_fifo_depth,
g_show_ahead => g_showahead = "ON",
g_memory_implementation_hint => open
)
port map (
rst_n_a_i => rst_n_a,
clk_wr_i => wrclk,
d_i => data,
we_i => wrreq,
wr_full_o => wrfull,
wr_count_o => wrusedw,
clk_rd_i => rdclk,
q_o => q,
rd_i => rdreq,
rd_empty_o => rdempty,
rd_count_o => open
);
end syn;
init.vhd 0000664 0000000 0000000 00000016363 14574545710 0032457 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : init module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : init.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 13.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- this module collects information from the config space provided by the hard
-- IP core and presents it to the 16z091-01 design
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- * init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity init is
port(
core_clk : in std_logic; -- synchronous to core_clk from hard IP core
clk : in std_logic;
rst : in std_logic;
-- IP core
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
-- interrupt module
cfg_msicsr : out std_logic_vector(15 downto 0);
-- Tx Module
bus_dev_func : out std_logic_vector(15 downto 0);
max_read : out std_logic_vector(2 downto 0);
max_payload : out std_logic_vector(2 downto 0)
);
end entity init;
-- ****************************************************************************
architecture init_arch of init is
-- internal signals -----------------------------------------------------------
signal data : std_logic_vector(15 downto 0);
signal data_q : std_logic_vector(15 downto 0);
signal data_qq : std_logic_vector(15 downto 0);
signal ctl_max : std_logic;
signal ctl_bus : std_logic;
signal ctl_msi : std_logic;
signal ctl_max_q : std_logic;
signal ctl_max_qq : std_logic;
signal ctl_max_qqq : std_logic;
signal ctl_bus_q : std_logic;
signal ctl_bus_qq : std_logic;
signal ctl_bus_qqq : std_logic;
signal ctl_msi_q : std_logic;
signal ctl_msi_qq : std_logic;
signal ctl_msi_qqq : std_logic;
signal sample : std_logic;
signal get_sample : std_logic;
signal tl_cfg_ctl_wr_q : std_logic;
-------------------------------------------------------------------------------
begin
cfg_get_info : process(rst, core_clk)
begin
if(rst = '1') then
data <= (others => '0');
ctl_max <= '0';
ctl_bus <= '0';
sample <= '0';
tl_cfg_ctl_wr_q <= '0';
elsif(core_clk'event and core_clk = '1') then
tl_cfg_ctl_wr_q <= tl_cfg_ctl_wr;
-- Sample the interesting values when tl_cfg_ctl_wr toggles.
if(((tl_cfg_ctl_wr = '1' and tl_cfg_ctl_wr_q = '0') or (tl_cfg_ctl_wr = '0' and tl_cfg_ctl_wr_q = '1'))
and (tl_cfg_add = x"0" or tl_cfg_add = x"D" or tl_cfg_add = x"F") ) then
sample <= '1';
elsif(sample = '1') then
sample <= '0';
end if;
-- store values due to appropriate tl_cfg cycle represented by tl_cfg_add
-- if(tl_cfg_add = x"0") then
if(tl_cfg_add = x"0" and sample = '1') then
ctl_max <= '1';
data <= tl_cfg_ctl(31 downto 16);
elsif(tl_cfg_add /= x"0") then
ctl_max <= '0';
end if;
-- if(tl_cfg_add = x"D") then
if(tl_cfg_add = x"D" and sample = '1') then
ctl_msi <= '1';
data <= tl_cfg_ctl(15 downto 0);
elsif(tl_cfg_add /= x"D") then
ctl_msi <= '0';
end if;
-- if(tl_cfg_add = x"F") then
if(tl_cfg_add = x"F" and sample = '1') then
ctl_bus <= '1';
data <= tl_cfg_ctl(15 downto 0);
elsif(tl_cfg_add /= x"F") then
ctl_bus <= '0';
end if;
end if;
end process cfg_get_info;
-------------------------------------------------------------------------------
cfg_put_info : process(rst, clk)
begin
if(rst = '1') then
bus_dev_func <= (others => '0');
max_read <= (others => '0');
max_payload <= (others => '0');
cfg_msicsr <= (others => '0');
data_q <= (others => '0');
data_qq <= (others => '0');
ctl_max_q <= '0';
ctl_max_qq <= '0';
ctl_max_qqq <= '0';
ctl_bus_q <= '0';
ctl_bus_qq <= '0';
ctl_bus_qqq <= '0';
ctl_msi_q <= '0';
ctl_msi_qq <= '0';
ctl_msi_qqq <= '0';
get_sample <= '0';
elsif(clk'event and clk = '1') then
data_q <= data;
data_qq <= data_q;
ctl_max_q <= ctl_max;
ctl_max_qq <= ctl_max_q;
ctl_max_qqq <= ctl_max_qq;
ctl_bus_q <= ctl_bus;
ctl_bus_qq <= ctl_bus_q;
ctl_bus_qqq <= ctl_bus_qq;
ctl_msi_q <= ctl_msi;
ctl_msi_qq <= ctl_msi_q;
ctl_msi_qqq <= ctl_msi_qq;
if((ctl_max_qq = '1' and ctl_max_qqq = '0') or (ctl_bus_qq = '1' and ctl_bus_qqq = '0') or (ctl_msi_qq = '1' and ctl_msi_qqq = '0')
) then
get_sample <= '1';
elsif(get_sample = '1') then
get_sample <= '0';
end if;
-- propagate stored values to the other clock domain modules
if(ctl_max_qq = '1' and get_sample = '1') then
max_payload <= data_qq(7 downto 5);
max_read <= data_qq(14 downto 12);
end if;
-- hard IP stores bus and device number but for PCIe packets, the function number must be included
-- thus shift function number = 000 into signal
if(ctl_bus_qq = '1' and get_sample = '1') then
bus_dev_func <= data_qq(12 downto 0) & "000";
end if;
if(ctl_msi_qq = '1' and get_sample = '1') then
cfg_msicsr <= data_qq(15 downto 0);
end if;
end if;
end process cfg_put_info;
-------------------------------------------------------------------------------
end architecture init_arch;
interrupt_core.vhd 0000664 0000000 0000000 00000021726 14574545710 0034557 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Module for interrupt generation, synchronized to clk
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : interrupt_core.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 15.03.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- This module will generate both INTA and MSI messages. It will start in INTA
-- mode and then determine if it is allowed to send MSI interrupts by reading
-- the config space. If MSI are allowed, the corresponding number of allocated
-- requests will be shown.
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- * interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity interrupt_core is
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
-- interrupt_wb
wb_pwr_en : in std_logic;
wb_num_int : in std_logic_vector(4 downto 0);
wb_inter : in std_logic;
ack_ok : in std_logic;
inter_ack : out std_logic;
num_allowed : out std_logic_vector(5 downto 0);
-- init
cfg_msicsr : in std_logic_vector(15 downto 0);
-- error
wb_num_err : out std_logic
);
end entity interrupt_core;
-- ****************************************************************************
architecture interrupt_core_arch of interrupt_core is
-- internal signals -----------------------------------------------------------
signal msi_allowed_int : std_logic;
signal msi_allowed_num : std_logic_vector(5 downto 0);
signal ack_int : std_logic;
-- registers for synchronization:
signal cfg_msicsr_q : std_logic_vector(15 downto 0);
signal cfg_msicsr_qq : std_logic_vector(15 downto 0);
signal wb_pwr_en_q : std_logic;
signal wb_pwr_en_qq : std_logic;
signal wb_num_int_q : std_logic_vector(4 downto 0);
signal wb_num_int_qq : std_logic_vector(4 downto 0);
signal wb_inter_q : std_logic;
signal wb_inter_qq : std_logic;
signal wb_inter_qqq : std_logic;
signal ack_ok_q : std_logic;
signal ack_ok_qq : std_logic;
-------------------------------------------------------------------------------
begin
num_allowed <= msi_allowed_num;
-- register all input signals
reg_val : process(rst, clk)
begin
if(rst = '1') then
cfg_msicsr_q <= (others => '0');
cfg_msicsr_qq <= (others => '0');
wb_pwr_en_q <= '0';
wb_pwr_en_qq <= '0';
wb_num_int_q <= (others => '0');
wb_num_int_qq <= (others => '0');
wb_inter_q <= '0';
wb_inter_qq <= '0';
wb_inter_qqq <= '0';
ack_ok_q <= '0';
ack_ok_qq <= '0';
elsif(clk'event and clk = '1') then
cfg_msicsr_q <= cfg_msicsr;
cfg_msicsr_qq <= cfg_msicsr_q;
wb_pwr_en_q <= wb_pwr_en;
wb_pwr_en_qq <= wb_pwr_en_q;
wb_num_int_q <= wb_num_int;
wb_num_int_qq <= wb_num_int_q;
wb_inter_q <= wb_inter;
wb_inter_qq <= wb_inter_q;
wb_inter_qqq <= wb_inter_qq;
ack_ok_q <= ack_ok;
ack_ok_qq <= ack_ok_q;
end if;
end process reg_val;
-- fixed value for traffic class
app_msi_tc <= (others => '0');
-------------------------------------------------------------------------------
config : process(rst, cfg_msicsr_qq)
begin
if(rst = '1') then
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
else
-- set number of allowed vectors according to cfg register settings
if(cfg_msicsr_qq(0) = '0') then -- MSI not allowed
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
else
case cfg_msicsr_qq(6 downto 4) is
when "000" =>
msi_allowed_num <= "000001";
msi_allowed_int <= '1';
when "001" =>
msi_allowed_num <= "000010";
msi_allowed_int <= '1';
when "010" =>
msi_allowed_num <= "000100";
msi_allowed_int <= '1';
when "011" =>
msi_allowed_num <= "001000";
msi_allowed_int <= '1';
when "100" =>
msi_allowed_num <= "010000";
msi_allowed_int <= '1';
when "101" =>
msi_allowed_num <= "100000";
msi_allowed_int <= '1';
-- the following two encodings are specified as reserved by the PCIe base specification and should not be used. Thus they
-- should not be covered because these statements will never occur.
-- coverage off
when "110" =>
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
when "111" =>
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
when others =>
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
-- coverage on
end case;
end if;
end if;
end process config;
-------------------------------------------------------------------------------
calc : process(rst, clk)
begin
if(rst = '1') then
app_int_sts <= '0';
app_msi_req <= '0';
app_msi_num <= (others => '0');
pex_msi_num <= (others => '0');
inter_ack <= '0';
wb_num_err <= '0';
ack_int <= '0';
elsif(clk'event and clk = '1') then
-- pass acknowledge to interrupt_wb module
-- if app_int_ack is asserted on the next clock
-- cycle after Deassert_INTA is set then this
-- fails because ack_int is released too late
if(app_int_ack = '1' or app_msi_ack = '1') then
inter_ack <= '1';
elsif(ack_ok_qq = '1') then
inter_ack <= '0';
end if;
if(app_int_ack = '1' or app_msi_ack = '1') then
ack_int <= '1';
elsif(wb_inter_qqq = '0') then
ack_int <= '0';
end if;
-- is MSI is acknowledged, reset requesting signals
if(app_msi_ack = '1') then
app_msi_num <= (others => '0');
pex_msi_num <= (others => '0');
end if;
if(wb_inter_qqq = '1' and msi_allowed_int = '0') then
app_int_sts <= '1';
elsif(wb_inter_qqq = '0' and msi_allowed_int = '0') then
app_int_sts <= '0';
elsif(wb_inter_qqq = '1' and msi_allowed_int = '1' and app_msi_ack = '0' and ack_int = '0') then
app_msi_req <= '1';
elsif(wb_inter_qqq = '1' and msi_allowed_int = '1' and app_msi_ack = '1') then
app_msi_req <= '0';
end if;
-- set vector number according to wb_pwr_en_qq
if(wb_pwr_en_qq = '1' and msi_allowed_int = '1') then
pex_msi_num <= wb_num_int_qq;
elsif(wb_pwr_en_qq = '0' and msi_allowed_int = '1') then
app_msi_num <= wb_num_int_qq;
end if;
-- set num_error if input vector number exceeds maximum allowed, if msi_allowed_num(5) = '1' then the maximum is allocated
-- thus a check is not necessary
if(wb_inter_qqq = '1' and msi_allowed_int = '1' and msi_allowed_num(5) = '0' and wb_num_int_qq >= msi_allowed_num(4 downto 0)) then
wb_num_err <= '1';
else
wb_num_err <= '0';
end if;
end if;
end process calc;
-------------------------------------------------------------------------------
end architecture interrupt_core_arch;
interrupt_wb.vhd 0000664 0000000 0000000 00000011342 14574545710 0034230 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Module for interrupt generation, synchonized to wb_clk
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : interrupt_wb.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 15.03.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- This module will generate both INTA and MSI messages. It will start in INTA
-- mode and then determine if it is allowed to send MSI interrupts by reading
-- the config space. If MSI are allowed, the corresponding number of allocated
-- requests will be shown.
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- * interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity interrupt_wb is
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- interrupt_core
inter_ack : in std_logic;
num_allowed : in std_logic_vector(5 downto 0);
wb_pwr_en : out std_logic;
wb_num_int : out std_logic_vector(4 downto 0);
wb_inter : out std_logic;
ack_ok : out std_logic;
-- Wishbone
wb_int : in std_logic;
wb_pwr_enable : in std_logic; -- =1 if wb_int_num should be for power management, else
-- for normal interrupt
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0) -- =0 if MSI not allowed, else: nbr. of allocated signals
);
end entity interrupt_wb;
-- ****************************************************************************
architecture interrupt_wb_arch of interrupt_wb is
-- internal signals -----------------------------------------------------------
signal inter_ack_qqq : std_logic;
-- registers for synchronization:
signal inter_ack_q : std_logic;
signal inter_ack_qq : std_logic;
signal num_allowed_q : std_logic_vector(5 downto 0);
signal num_allowed_qq : std_logic_vector(5 downto 0);
-------------------------------------------------------------------------------
begin
set_val : process(wb_rst,wb_clk)
begin
if(wb_rst = '1') then
inter_ack_q <= '0';
inter_ack_qq <= '0';
num_allowed_q <= (others => '0');
num_allowed_qq <= (others => '0');
wb_pwr_en <= '0';
wb_num_int <= (others => '0');
wb_inter <= '0';
wb_int_ack <= '0';
wb_int_num_allowed <= (others => '0');
ack_ok <= '0';
inter_ack_qqq <= '0';
elsif(wb_clk'event and wb_clk = '1') then
-- register all inputs that need to be registered on rising edge of wb_clk
inter_ack_q <= inter_ack;
inter_ack_qq <= inter_ack_q;
inter_ack_qqq <= inter_ack_qq;
num_allowed_q <= num_allowed;
num_allowed_qq <= num_allowed_q;
wb_pwr_en <= wb_pwr_enable;
wb_num_int <= wb_int_num;
wb_inter <= wb_int;
wb_int_num_allowed <= num_allowed_qq;
ack_ok <= inter_ack_qq;
-- assert interrupt acknowledge when rising_edge(inter_ack_qq) occured
if(inter_ack_qq = '1' and inter_ack_qqq = '0') then
wb_int_ack <= '1';
else
wb_int_ack <= '0';
end if;
end if;
end process set_val;
-------------------------------------------------------------------------------
end architecture interrupt_wb_arch;
ip_16z091_01.vhd 0000664 0000000 0000000 00000054332 14574545710 0033354 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : 16z091-01 module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 22.11.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- combines modules to build the 16z091-01 module
--------------------------------------------------------------------------------
-- Hierarchy :
-- * ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fpga_pkg_2.all;
entity ip_16z091_01 is
generic(
FPGA_FAMILY : family_type := NONE;
READY_LATENCY : natural := 2; -- only specify values between 0 and 2
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001"; -- = 1017 DW;
-- set this value to "1111111111" - (READY_LATENCY + 1)
WBM_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011"; -- = 1019 DW
WBM_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111"; -- = 1015 DW
WBS_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100"; -- = 1020 DW, one place spare for put_stuffing
WBS_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111"; -- = 1015 DW
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
RX_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(RX_LPM_WIDTHU-1) < RX_FIFO_DEPTH <= 2^(RX_LPM_WIDTHU)
RX_LPM_WIDTHU : natural := 10;
TX_HEADER_FIFO_DEPTH : natural := 32; -- valid values are: 2^(TX_HEADER_LPM_WIDTHU-1) < TX_HEADER_FIFO_DEPTH <= 2^(TX_HEADER_LPM_WIDTHU)
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(TX_DATA_LPM_WIDTHU-1) < TX_DATA_FIFO_DEPTH <= 2^(TX_DATA_LPM_WIDTHU)
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
wb_rst : in std_logic;
-- IP Core
core_clk : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_bar_o : out std_logic_vector(6 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
wb_int : in std_logic;
wb_pwr_enable : in std_logic;
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end entity ip_16z091_01;
architecture ip_16z091_01_arch of ip_16z091_01 is
-- functions ------------------------------------------------------------------
function convert_family(
fpga_family_in : family_type
) return string is
begin
case fpga_family_in is
when CYCLONE4 => return "Cyclone IV GX";
when CYCLONE5 => return "Cyclone V";
when ARRIA2_GX => return "Arria II GX";
when others =>
assert false report "undefined family_type in function convert_family in rx_module.vhd" severity failure;
return "none";
end case;
end function convert_family;
-- constants ------------------------------------------------------------------
constant DEVICE_FAMILY_INT : string := convert_family(FPGA_FAMILY);
-- internal signals -----------------------------------------------------------
-- rx_module:
signal rx_fifo_wr_out_int : std_logic_vector(31 downto 0);
signal rx_fifo_wr_empty_int : std_logic;
signal rx_fifo_wr_rd_enable_int : std_logic;
signal rx_fifo_c_rd_enable_int : std_logic;
signal rx_fifo_c_empty_int : std_logic;
signal rx_fifo_c_out_int : std_logic_vector(31 downto 0);
signal tag_nbr_int : std_logic_vector(7 downto 0);
signal rx_tag_rcvd_int : std_logic;
signal ecrc_err_int : std_logic;
signal type_fmt_err_int : std_logic_vector(1 downto 0);
-- tx_module:
signal tx_fifo_c_head_clr_int : std_logic;
signal tx_fifo_c_data_clr_int : std_logic;
signal tx_fifo_c_head_full_int : std_logic;
signal tx_fifo_c_data_full_int : std_logic;
signal tx_fifo_c_data_usedw_int : std_logic_vector(9 downto 0);
signal tx_fifo_c_head_enable_int : std_logic;
signal tx_fifo_c_data_enable_int : std_logic;
signal tx_fifo_c_head_in_int : std_logic_vector(31 downto 0);
signal tx_fifo_c_data_in_int : std_logic_vector(31 downto 0);
signal bus_dev_func_int : std_logic_vector(15 downto 0);
signal max_read_int : std_logic_vector(2 downto 0);
signal max_payload_int : std_logic_vector(2 downto 0);
signal tx_fifo_wr_head_clr_int : std_logic;
signal tx_fifo_wr_head_enable_int : std_logic;
signal tx_fifo_wr_head_in_int : std_logic_vector(31 downto 0);
signal tx_fifo_wr_head_full_int : std_logic;
signal tx_fifo_w_data_clr_int : std_logic;
signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_in_int : std_logic_vector(31 downto 0);
signal tx_fifo_w_data_full_int : std_logic;
signal tx_fifo_w_data_usedw_int : std_logic_vector(9 downto 0);
signal tx_fifo_wr_head_usedw_int : std_logic_vector(6 downto 0);
-- error:
signal ecrc_err_wb_int : std_logic;
signal tag_id_wb_int : std_logic_vector(7 downto 0);
signal tx_timeout_int : std_logic;
signal timeout_wb_int : std_logic;
signal wb_num_err_int : std_logic;
signal tx_compl_abort_int : std_logic;
-- interrupt
signal cfg_msicsr_int : std_logic_vector(15 downto 0);
signal wb_pwr_en_int : std_logic;
signal wb_num_int_int : std_logic_vector(4 downto 0);
signal wb_inter_int : std_logic;
signal inter_ack_int : std_logic;
signal num_allowed_int : std_logic_vector(5 downto 0);
signal ack_ok_int : std_logic;
-------------------------------------------------------------------------------
begin
-- instanciate components --------------------------------------------------
rx_module_comp : entity work.rx_module
generic map(
DEVICE_FAMILY => DEVICE_FAMILY_INT,
READY_LATENCY => READY_LATENCY,
FIFO_MAX_USEDW => FIFO_MAX_USEDW,
RX_FIFO_DEPTH => RX_FIFO_DEPTH,
RX_LPM_WIDTHU => RX_LPM_WIDTHU
)
port map(
clk => clk,
wb_clk => wb_clk,
rst => rst,
-- IP Core
rx_st_data0 => rx_st_data0,
rx_st_err0 => rx_st_err0,
rx_st_valid0 => rx_st_valid0,
rx_st_sop0 => rx_st_sop0,
rx_st_eop0 => rx_st_eop0,
rx_st_be0 => rx_st_be0,
rx_st_bardec0 => rx_st_bardec0,
rx_st_mask0 => rx_st_mask0,
rx_st_ready0 => rx_st_ready0,
-- FIFO
rx_fifo_c_rd_enable => rx_fifo_c_rd_enable_int,
rx_fifo_wr_rd_enable => rx_fifo_wr_rd_enable_int,
rx_fifo_c_empty => rx_fifo_c_empty_int,
rx_fifo_wr_empty => rx_fifo_wr_empty_int,
rx_fifo_c_out => rx_fifo_c_out_int,
rx_fifo_wr_out => rx_fifo_wr_out_int,
-- Tx Module
rx_tag_nbr => tag_nbr_int,
rx_tag_rcvd => rx_tag_rcvd_int,
-- error
rx_type_fmt_err => type_fmt_err_int,
rx_ecrc_err => ecrc_err_int,
-- debug port
rx_debug_out => rx_debug_out
);
wb_master_comp : entity work.z091_01_wb_master
generic map(
SUSPEND_FIFO_ACCESS => WBM_SUSPEND_FIFO_ACCESS,
RESUME_FIFO_ACCESS => WBM_RESUME_FIFO_ACCESS
)
port map(
wb_clk => wb_clk,
wb_rst => wb_rst,
-- Rx Module
rx_fifo_wr_out => rx_fifo_wr_out_int,
rx_fifo_wr_empty => rx_fifo_wr_empty_int,
rx_fifo_wr_rd_enable => rx_fifo_wr_rd_enable_int,
-- Tx Module
tx_fifo_c_head_full => tx_fifo_c_head_full_int,
tx_fifo_c_data_full => tx_fifo_c_data_full_int,
tx_fifo_c_data_usedw => tx_fifo_c_data_usedw_int,
tx_fifo_c_head_enable => tx_fifo_c_head_enable_int,
tx_fifo_c_data_enable => tx_fifo_c_data_enable_int,
tx_fifo_c_head_in => tx_fifo_c_head_in_int,
tx_fifo_c_data_in => tx_fifo_c_data_in_int,
tx_fifo_c_data_clr => tx_fifo_c_data_clr_int,
tx_fifo_c_head_clr => tx_fifo_c_head_clr_int,
-- Wishbone
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
wbm_cyc_bar_o => wbm_cyc_bar_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
-- error
ecrc_err_in => ecrc_err_wb_int,
err_tag_id => tag_id_wb_int,
ecrc_err_out => open
);
error_comp : entity work.error
port map(
clk => clk,
rst => rst,
wb_clk => wb_clk,
wb_rst => wb_rst,
-- RxModule
rx_tag_id => tag_nbr_int,
rx_ecrc_err => ecrc_err_int,
rx_type_fmt_err => type_fmt_err_int,
-- TxModule
tx_compl_abort => tx_compl_abort_int,
tx_timeout => tx_timeout_int,
-- Interrupt
wb_num_err => wb_num_err_int,
-- Wishbone
error_ecrc_err => ecrc_err_wb_int,
error_timeout => timeout_wb_int,
error_tag_id => tag_id_wb_int,
error_cor_ext_rcv => error_cor_ext_rcv,
error_cor_ext_rpl => error_cor_ext_rpl,
error_rpl => error_rpl,
error_r2c0 => error_r2c0,
error_msi_num => error_msi_num,
-- IP Core
derr_cor_ext_rcv => derr_cor_ext_rcv,
derr_cor_ext_rpl => derr_cor_ext_rpl,
derr_rpl => derr_rpl,
r2c_err0 => r2c_err0,
cpl_err => cpl_err,
cpl_pending => cpl_pending
);
tx_module_comp : entity work.tx_module
generic map(
DEVICE_FAMILY => DEVICE_FAMILY_INT,
TX_HEADER_FIFO_DEPTH => TX_HEADER_FIFO_DEPTH,
TX_HEADER_LPM_WIDTHU => TX_HEADER_LPM_WIDTHU,
TX_DATA_FIFO_DEPTH => TX_DATA_FIFO_DEPTH,
TX_DATA_LPM_WIDTHU => TX_DATA_LPM_WIDTHU
)
port map(
clk => clk,
rst => rst,
wb_clk => wb_clk,
wb_rst => wb_rst,
clk_500 => clk_500,
-- IP Core
tx_st_ready0 => tx_st_ready0,
tx_fifo_full0 => tx_fifo_full0,
tx_fifo_empty0 => tx_fifo_empty0,
tx_fifo_rdptr0 => tx_fifo_rdptr0,
tx_fifo_wrptr0 => tx_fifo_wrptr0,
pme_to_sr => pme_to_sr,
tx_st_err0 => tx_st_err0,
tx_st_valid0 => tx_st_valid0,
tx_st_sop0 => tx_st_sop0,
tx_st_eop0 => tx_st_eop0,
tx_st_data0 => tx_st_data0,
pme_to_cr => pme_to_cr,
-- Wishbone Master
tx_fifo_c_data_clr => tx_fifo_c_data_clr_int,
tx_fifo_c_head_clr => tx_fifo_c_head_clr_int,
tx_fifo_c_head_enable => tx_fifo_c_head_enable_int,
tx_fifo_c_data_enable => tx_fifo_c_data_enable_int,
tx_fifo_c_head_in => tx_fifo_c_head_in_int,
tx_fifo_c_data_in => tx_fifo_c_data_in_int,
tx_fifo_c_head_full => tx_fifo_c_head_full_int,
tx_fifo_c_data_full => tx_fifo_c_data_full_int,
tx_fifo_c_data_usedw => tx_fifo_c_data_usedw_int,
-- Wishbone Slave
tx_fifo_wr_head_clr => tx_fifo_wr_head_clr_int,
tx_fifo_wr_head_enable => tx_fifo_wr_head_enable_int,
tx_fifo_wr_head_in => tx_fifo_wr_head_in_int,
tx_fifo_wr_head_full => tx_fifo_wr_head_full_int,
tx_fifo_w_data_clr => tx_fifo_w_data_clr_int,
tx_fifo_w_data_enable => tx_fifo_w_data_enable_int,
tx_fifo_w_data_in => tx_fifo_w_data_in_int,
tx_fifo_w_data_full => tx_fifo_w_data_full_int,
tx_fifo_w_data_usedw => tx_fifo_w_data_usedw_int,
tx_fifo_wr_head_usedw => tx_fifo_wr_head_usedw_int,
-- Rx Module
rx_tag_nbr => tag_nbr_int,
rx_tag_rcvd => rx_tag_rcvd_int,
-- init
bus_dev_func => bus_dev_func_int,
-- max_read => max_read_int,
max_payload => max_payload_int,
-- error
tx_compl_abort => tx_compl_abort_int,
tx_timeout => tx_timeout_int
);
init_comp : entity work.init
port map(
core_clk => core_clk, -- synchronous to core_clk from hard IP core
clk => clk,
rst => rst,
-- IP core
tl_cfg_add => tl_cfg_add,
tl_cfg_ctl => tl_cfg_ctl,
tl_cfg_ctl_wr => tl_cfg_ctl_wr,
tl_cfg_sts => tl_cfg_sts,
tl_cfg_sts_wr => tl_cfg_sts_wr,
-- interrupt module
cfg_msicsr => cfg_msicsr_int,
-- Tx Module
bus_dev_func => bus_dev_func_int,
max_read => max_read_int,
max_payload => max_payload_int
);
wb_slave_comp : entity work.z091_01_wb_slave
generic map(
PCIE_REQUEST_LENGTH => PCIE_REQUEST_LENGTH, -- 32DW = 128Byte
SUSPEND_FIFO_ACCESS => WBS_SUSPEND_FIFO_ACCESS, -- = 1020 DW, one place spare for put_stuffing
RESUME_FIFO_ACCESS => WBS_RESUME_FIFO_ACCESS -- = 1015 DW
)
port map(
wb_clk => wb_clk,
wb_rst => wb_rst,
-- Wishbone
wbs_cyc => wbs_cyc,
wbs_stb => wbs_stb,
wbs_we => wbs_we,
wbs_sel => wbs_sel,
wbs_adr => wbs_adr,
wbs_dat_i => wbs_dat_i,
wbs_cti => wbs_cti,
wbs_tga => wbs_tga,
wbs_ack => wbs_ack,
wbs_err => wbs_err,
wbs_dat_o => wbs_dat_o,
-- Rx Module (completion)
rx_fifo_c_empty => rx_fifo_c_empty_int,
rx_fifo_c_out => rx_fifo_c_out_int,
rx_fifo_c_rd_enable => rx_fifo_c_rd_enable_int,
-- Tx Module
tx_fifo_wr_head_full => tx_fifo_wr_head_full_int,
tx_fifo_wr_head_usedw => tx_fifo_wr_head_usedw_int,
tx_fifo_wr_head_clr => tx_fifo_wr_head_clr_int,
tx_fifo_wr_head_enable => tx_fifo_wr_head_enable_int,
tx_fifo_wr_head_in => tx_fifo_wr_head_in_int,
tx_fifo_w_data_full => tx_fifo_w_data_full_int,
tx_fifo_w_data_usedw => tx_fifo_w_data_usedw_int,
tx_fifo_w_data_clr => tx_fifo_w_data_clr_int,
tx_fifo_w_data_enable => tx_fifo_w_data_enable_int,
tx_fifo_w_data_in => tx_fifo_w_data_in_int,
max_read => max_read_int,
-- error
error_ecrc_err => ecrc_err_wb_int,
error_timeout => timeout_wb_int
);
interrupt_core_comp : entity work.interrupt_core
port map(
clk => clk,
rst => rst,
-- IP Core
app_int_ack => app_int_ack,
app_msi_ack => app_msi_ack,
app_int_sts => app_int_sts,
app_msi_req => app_msi_req,
app_msi_tc => app_msi_tc,
app_msi_num => app_msi_num,
pex_msi_num => pex_msi_num,
-- interrupt_wb
wb_pwr_en => wb_pwr_en_int,
wb_num_int => wb_num_int_int,
wb_inter => wb_inter_int,
ack_ok => ack_ok_int,
inter_ack => inter_ack_int,
num_allowed => num_allowed_int,
-- init
cfg_msicsr => cfg_msicsr_int,
-- error
wb_num_err => wb_num_err_int
);
interrupt_wb_comp : entity work.interrupt_wb
port map(
wb_clk => wb_clk,
wb_rst => wb_rst,
-- interrupt_core
inter_ack => inter_ack_int,
num_allowed => num_allowed_int,
wb_pwr_en => wb_pwr_en_int,
wb_num_int => wb_num_int_int,
wb_inter => wb_inter_int,
ack_ok => ack_ok_int,
-- Wishbone
wb_int => wb_int,
wb_pwr_enable => wb_pwr_enable,
wb_int_num => wb_int_num,
wb_int_ack => wb_int_ack,
wb_int_num_allowed => wb_int_num_allowed
);
-------------------------------------------------------------------------------
error_timeout <= timeout_wb_int;
-------------------------------------------------------------------------------
end architecture ip_16z091_01_arch;
ip_16z091_01_top.vhd 0000664 0000000 0000000 00000121513 14574545710 0034232 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : top level module for 16z091-01 design
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : ip_16z091_01_top
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 23.02.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a
-- Synthesis : Quartus II 10.0
--------------------------------------------------------------------------------
-- Description :
-- Toplevel module that combines the 16z091-01 IP core with the Altera hard
-- makro PCIe IP core
--------------------------------------------------------------------------------
-- Hierarchy :
-- * ip_16z091_01_top_core
-- ip_16z091_01
-- Hard_IP
-- z091_01_wb_adr_dec
-- pcie_msi
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.fpga_pkg_2.all;
entity ip_16z091_01_top is
generic(
SIMULATION : std_logic := '0'; -- =1 simulation,=0 synthesis
FPGA_FAMILY : family_type := NONE;
IRQ_WIDTH : integer range 32 downto 1 := 1;
-- only use one of the following 3:
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000010000"; -- 16DW = 64Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10
);
port(
-- Hard IP ports:
clk_50 : in std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
clk_125 : in std_logic; -- 125 MHz clock for fixed_clk, CycloneIV only
ref_clk : in std_logic; -- 100 MHz reference clock
clk_500 : in std_logic; -- 500 Hz clock
ext_rst_n : in std_logic; -- for CycloneV this MUST be connected to
-- nPERSTL0 for top left HardIP
-- nPERSTL1 for bottom left Hard IP <- use this one first (recommended by Altera)
rx_0 : in std_logic;
rx_1 : in std_logic;
rx_2 : in std_logic;
rx_3 : in std_logic;
tx_0 : out std_logic;
tx_1 : out std_logic;
tx_2 : out std_logic;
tx_3 : out std_logic;
-- Wishbone ports:
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_bar_o : out std_logic_vector(6 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
irq_req_i : in std_logic_vector(IRQ_WIDTH -1 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
link_train_active : out std_logic
);
end entity ip_16z091_01_top;
-- ****************************************************************************
-- +----------------------------------------------------------------------------
-- | Architecture for Cyclone IV
-- +----------------------------------------------------------------------------
architecture ip_16z091_01_top_arch of ip_16z091_01_top is
constant MAX_ADDR_VAL : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- := 2^32 - 1
constant SUPPORTED_DEVICES : supported_family_types := (CYCLONE4, ARRIA2_GX);
-- internal signals -----------------------------------------------------------
signal rst_int : std_logic;
signal core_clk_int : std_logic;
signal crst_int : std_logic;
signal srst_int : std_logic;
signal npor_int : std_logic;
signal rx_st_data0_int : std_logic_vector(63 downto 0);
signal rx_st_err0_int : std_logic;
signal rx_st_valid0_int : std_logic;
signal rx_st_sop0_int : std_logic;
signal rx_st_eop0_int : std_logic;
signal rx_st_be0_int : std_logic_vector(7 downto 0);
signal rx_st_bardec0_int : std_logic_vector(7 downto 0);
signal tx_st_ready0_int : std_logic;
signal tx_fifo_full0_int : std_logic;
signal tx_fifo_empty0_int : std_logic;
signal tx_fifo_rdptr0_int : std_logic_vector(3 downto 0);
signal tx_fifo_wrptr0_int : std_logic_vector(3 downto 0);
signal pme_to_sr_int : std_logic;
signal tl_cfg_add_int : std_logic_vector(3 downto 0);
signal tl_cfg_ctl_int : std_logic_vector(31 downto 0);
signal tl_cfg_ctl_wr_int : std_logic;
signal tl_cfg_sts_int : std_logic_vector(52 downto 0);
signal tl_cfg_sts_wr_int : std_logic;
signal app_int_ack_int : std_logic;
signal app_msi_ack_int : std_logic;
signal rx_st_mask0_int : std_logic;
signal rx_st_ready0_int : std_logic;
signal tx_st_err0_int : std_logic;
signal tx_st_valid0_int : std_logic;
signal tx_st_sop0_int : std_logic;
signal tx_st_eop0_int : std_logic;
signal tx_st_data0_int : std_logic_vector(63 downto 0);
signal pme_to_cr_int : std_logic;
signal app_int_sts_int : std_logic;
signal app_msi_req_int : std_logic;
signal app_msi_tc_int : std_logic_vector(2 downto 0);
signal app_msi_num_int : std_logic_vector(4 downto 0);
signal pex_msi_num_int : std_logic_vector(4 downto 0);
signal derr_cor_ext_rcv_int : std_logic_vector(1 downto 0) := "00";
signal derr_cor_ext_rpl_int : std_logic;
signal derr_rpl_int : std_logic;
signal r2c_err0_int : std_logic;
signal cpl_err_int : std_logic_vector(6 downto 0);
signal cpl_pending_int : std_logic;
--signal int_bar_hit : std_logic_vector(6 downto 0);
--signal wbm_adr_int : std_logic_vector(31 downto 0);
signal reconfig_fromgxb_int : std_logic_vector (4 downto 0);
signal reconfig_togxb_int : std_logic_vector (3 downto 0);
SIGNAL reconf_busy : std_logic;
signal pll_powerdown_int : std_logic;
signal l2_exit : std_logic;
signal hotrst_exit : std_logic;
signal dlup_exit : std_logic;
signal rst_cwh : std_logic;
signal rst_cwh_cnt : std_logic_vector (1 downto 0);
signal test_in_int : std_logic_vector(39 downto 0);
signal pipe_mode_int : std_logic;
-- signals to connect pcie_msi
signal int_wb_int : std_logic;
signal int_wb_pwr_enable : std_logic;
signal int_wb_int_num : std_logic_vector(4 downto 0);
signal int_wb_int_ack : std_logic;
signal int_wb_int_num_allowed : std_logic_vector(5 downto 0);
signal int_ltssm : std_logic_vector(4 downto 0);
-------------------------------------------------------------------------------
component hard_ip_x1
port (
-- inputs:
signal app_int_sts : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal app_msi_req : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC;
signal crst : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal lmi_wren : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pclk_in : IN STD_LOGIC;
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pm_event : IN STD_LOGIC;
signal pme_to_cr : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal rx_st_ready0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
-- outputs:
signal app_clk : OUT STD_LOGIC;
signal app_int_ack : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal core_clk_out : OUT STD_LOGIC;
signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
signal derr_cor_ext_rpl : OUT STD_LOGIC;
signal derr_rpl : OUT STD_LOGIC;
signal dlup_exit : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal l2_exit : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal lmi_ack : OUT STD_LOGIC;
signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal r2c_err0 : OUT STD_LOGIC;
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal rx_st_err0 : OUT STD_LOGIC;
signal rx_st_sop0 : OUT STD_LOGIC;
signal rx_st_valid0 : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_out0 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC
);
end component;
COMPONENT Hard_IP_x4 is
port (
-- inputs:
signal app_int_sts : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal app_msi_req : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC;
signal crst : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal lmi_wren : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pclk_in : IN STD_LOGIC;
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pm_event : IN STD_LOGIC;
signal pme_to_cr : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rx_in1 : IN STD_LOGIC;
signal rx_in2 : IN STD_LOGIC;
signal rx_in3 : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal rx_st_ready0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata1_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata2_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata3_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxdatak1_ext : IN STD_LOGIC;
signal rxdatak2_ext : IN STD_LOGIC;
signal rxdatak3_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxelecidle1_ext : IN STD_LOGIC;
signal rxelecidle2_ext : IN STD_LOGIC;
signal rxelecidle3_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus1_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus2_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus3_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal rxvalid1_ext : IN STD_LOGIC;
signal rxvalid2_ext : IN STD_LOGIC;
signal rxvalid3_ext : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
-- outputs:
signal app_int_ack : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal core_clk_out : OUT STD_LOGIC;
signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
signal derr_cor_ext_rpl : OUT STD_LOGIC;
signal derr_rpl : OUT STD_LOGIC;
signal dlup_exit : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal l2_exit : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal lmi_ack : OUT STD_LOGIC;
signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal r2c_err0 : OUT STD_LOGIC;
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal rx_st_err0 : OUT STD_LOGIC;
signal rx_st_sop0 : OUT STD_LOGIC;
signal rx_st_valid0 : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal rxpolarity1_ext : OUT STD_LOGIC;
signal rxpolarity2_ext : OUT STD_LOGIC;
signal rxpolarity3_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_out0 : OUT STD_LOGIC;
signal tx_out1 : OUT STD_LOGIC;
signal tx_out2 : OUT STD_LOGIC;
signal tx_out3 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txcompl1_ext : OUT STD_LOGIC;
signal txcompl2_ext : OUT STD_LOGIC;
signal txcompl3_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata1_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata2_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata3_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdatak1_ext : OUT STD_LOGIC;
signal txdatak2_ext : OUT STD_LOGIC;
signal txdatak3_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC;
signal txelecidle1_ext : OUT STD_LOGIC;
signal txelecidle2_ext : OUT STD_LOGIC;
signal txelecidle3_ext : OUT STD_LOGIC
);
end COMPONENT Hard_IP_x4;
component alt_reconf
port(
reconfig_clk : in std_logic;
reconfig_fromgxb : in std_logic_vector (4 downto 0);
busy : out std_logic;
reconfig_togxb : out std_logic_vector (3 downto 0)
);
end component;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
component pcie_msi
generic (
WIDTH : integer range 32 downto 1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
irq_req_i : in std_logic_vector(WIDTH -1 downto 0);
wb_int_o : out std_logic;
wb_pwr_enable_o : out std_logic;
wb_int_num_o : OUT std_logic_vector(4 downto 0);
wb_int_ack_i : in std_logic;
wb_int_num_allowed_i : in std_logic_vector(5 downto 0)
);
end component;
-------------------------------------------------------------------------------
begin
-- coverage off
assert not no_valid_device(supported_devices => SUPPORTED_DEVICES, device => FPGA_FAMILY) report "16z091-01: no valid FPGA device selected" severity failure;
-- coverage on
--wbm_cyc_o <= wbm_cyc_o_int;
npor_int <= ext_rst_n and '1';
pll_powerdown_int <= not npor_int;
----------------------------------
-- assign debug port if ltssm is
-- in link training mode
----------------------------------
link_train_active <= '0' when int_ltssm = "01111" else
'1';
-------------------------------------------------
-- work around for Altera receiver detect issue
-------------------------------------------------
pipe_mode_int <= '0'; -- use serial mode
test_in_int(39 downto 4) <= (others => '0');
test_in_int(3) <= not pipe_mode_int;
test_in_int(2 downto 1) <= (others => '0');
--------------------------------------------
-- speed up initialization for simulation:
--------------------------------------------
test_in_int(0) <= SIMULATION;
-- instanciate components
ip_16z091_01_comp : entity work.ip_16z091_01
generic map(
FPGA_FAMILY => FPGA_FAMILY,
READY_LATENCY => 2,
FIFO_MAX_USEDW => conv_std_logic_vector((2**RX_LPM_WIDTHU - 8),10),
WBM_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 5),10),
WBM_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
WBS_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 4),10),
WBS_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
PCIE_REQUEST_LENGTH => PCIE_REQUEST_LENGTH,
RX_FIFO_DEPTH => 2**RX_LPM_WIDTHU,
RX_LPM_WIDTHU => RX_LPM_WIDTHU,
TX_HEADER_FIFO_DEPTH => 2**TX_HEADER_LPM_WIDTHU,
TX_HEADER_LPM_WIDTHU => TX_HEADER_LPM_WIDTHU,
TX_DATA_FIFO_DEPTH => 2**TX_DATA_LPM_WIDTHU,
TX_DATA_LPM_WIDTHU => TX_DATA_LPM_WIDTHU
)
port map(
clk => core_clk_int,
rst => rst_int,
clk_500 => clk_500,
wb_clk => wb_clk,
wb_rst => wb_rst,
-- IP Core
core_clk => core_clk_int,
rx_st_data0 => rx_st_data0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_valid0 => rx_st_valid0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_bardec0 => rx_st_bardec0_int,
tx_st_ready0 => tx_st_ready0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
pme_to_sr => pme_to_sr_int,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_valid0 => tx_st_valid0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_data0 => tx_st_data0_int,
pme_to_cr => pme_to_cr_int,
app_int_sts => app_int_sts_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
app_msi_num => app_msi_num_int,
pex_msi_num => pex_msi_num_int,
derr_cor_ext_rcv => derr_cor_ext_rcv_int,
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
r2c_err0 => r2c_err0_int,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
-- Wishbone master
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
wbm_cyc_bar_o => wbm_cyc_bar_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
-- Wishbone slave
wbs_cyc => wbs_cyc,
wbs_stb => wbs_stb,
wbs_we => wbs_we,
wbs_sel => wbs_sel,
wbs_adr => wbs_adr,
wbs_dat_i => wbs_dat_i,
wbs_cti => wbs_cti,
wbs_tga => wbs_tga,
wbs_ack => wbs_ack,
wbs_err => wbs_err,
wbs_dat_o => wbs_dat_o,
-- interrupt
wb_int => int_wb_int,
wb_pwr_enable => int_wb_pwr_enable,
wb_int_num => int_wb_int_num,
wb_int_ack => int_wb_int_ack,
wb_int_num_allowed => int_wb_int_num_allowed,
-- error
error_timeout => error_timeout,
error_cor_ext_rcv => error_cor_ext_rcv,
error_cor_ext_rpl => error_cor_ext_rpl,
error_rpl => error_rpl,
error_r2c0 => error_r2c0,
error_msi_num => error_msi_num,
-- debug port
rx_debug_out => open
);
gen_x4: if USE_LANES = "100" generate
Hard_IP_x4_comp : entity work.Hard_IP_x4
port map(
-- inputs:
app_int_sts => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
busy_altgxb_reconfig => reconf_busy,
cal_blk_clk => clk_50,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
crst => crst_int,
fixedclk_serdes => clk_125,
gxb_powerdown => '0',
hpg_ctrler => (others => '0'),
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
npor => npor_int,
pclk_in => core_clk_int,
pex_msi_num => pex_msi_num_int,
phystatus_ext => '0',
pipe_mode => pipe_mode_int,
pld_clk => core_clk_int,
pll_powerdown => '0',
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_clk => clk_50,
reconfig_togxb => reconfig_togxb_int,
refclk => ref_clk,
rx_in0 => rx_0,
rx_in1 => rx_1,
rx_in2 => rx_2,
rx_in3 => rx_3,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
rxdata0_ext => (others => '0'),
rxdata1_ext => (others => '0'),
rxdata2_ext => (others => '0'),
rxdata3_ext => (others => '0'),
rxdatak0_ext => '0',
rxdatak1_ext => '0',
rxdatak2_ext => '0',
rxdatak3_ext => '0',
rxelecidle0_ext => '0',
rxelecidle1_ext => '0',
rxelecidle2_ext => '0',
rxelecidle3_ext => '0',
rxstatus0_ext => (others => '0'),
rxstatus1_ext => (others => '0'),
rxstatus2_ext => (others => '0'),
rxstatus3_ext => (others => '0'),
rxvalid0_ext => '0',
rxvalid1_ext => '0',
rxvalid2_ext => '0',
rxvalid3_ext => '0',
srst => srst_int,
test_in => (others => '0'),
tx_st_data0 => tx_st_data0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_valid0 => tx_st_valid0_int,
-- outputs:
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
clk250_out => open,
clk500_out => open,
core_clk_out => core_clk_int,
derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
dlup_exit => dlup_exit,
hotrst_exit => hotrst_exit,
ko_cpl_spc_vc0 => open,
l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
ltssm => int_ltssm,
pme_to_sr => pme_to_sr_int,
powerdown_ext => open,
r2c_err0 => r2c_err0_int,
rate_ext => open,
rc_pll_locked => open,
reconfig_fromgxb => reconfig_fromgxb_int,
reset_status => open,
rx_fifo_empty0 => open,
rx_fifo_full0 => open,
rx_st_bardec0 => rx_st_bardec0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_data0 => rx_st_data0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_valid0 => rx_st_valid0_int,
rxpolarity0_ext => open,
rxpolarity1_ext => open,
rxpolarity2_ext => open,
rxpolarity3_ext => open,
suc_spd_neg => open,
test_out => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred0 => open,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
tx_out0 => tx_0,
tx_out1 => tx_1,
tx_out2 => tx_2,
tx_out3 => tx_3,
tx_st_ready0 => tx_st_ready0_int,
txcompl0_ext => open,
txcompl1_ext => open,
txcompl2_ext => open,
txcompl3_ext => open,
txdata0_ext => open,
txdata1_ext => open,
txdata2_ext => open,
txdata3_ext => open,
txdatak0_ext => open,
txdatak1_ext => open,
txdatak2_ext => open,
txdatak3_ext => open,
txdetectrx_ext => open,
txelecidle0_ext => open,
txelecidle1_ext => open,
txelecidle2_ext => open,
txelecidle3_ext => open
);
end generate gen_x4;
gen_x1: if USE_LANES = "001" generate
Hard_IP_x1_comp : Hard_IP_x1
port map(
app_int_sts => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
busy_altgxb_reconfig => reconf_busy,
cal_blk_clk => clk_50,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
crst => crst_int,
fixedclk_serdes => clk_125,
gxb_powerdown => '0',
hpg_ctrler => (others => '0'),
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
npor => npor_int,
pclk_in => core_clk_int,
pex_msi_num => pex_msi_num_int,
phystatus_ext => '0',
pipe_mode => pipe_mode_int,
pld_clk => core_clk_int,
pll_powerdown => pll_powerdown_int,
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_clk => clk_50,
reconfig_togxb => reconfig_togxb_int,
refclk => ref_clk,
rx_in0 => rx_0,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
rxdata0_ext => (others => '0'),
rxdatak0_ext => '0',
rxelecidle0_ext => '0',
rxstatus0_ext => (others => '0'),
rxvalid0_ext => '0',
srst => srst_int,
test_in => test_in_int,
tx_st_data0 => tx_st_data0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_valid0 => tx_st_valid0_int,
-- outputs:
app_clk => open,
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
clk250_out => open,
clk500_out => open,
core_clk_out => core_clk_int,
derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
dlup_exit => dlup_exit,
hotrst_exit => hotrst_exit,
ko_cpl_spc_vc0 => open,
l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
ltssm => int_ltssm,
pme_to_sr => pme_to_sr_int,
powerdown_ext => open,
r2c_err0 => r2c_err0_int,
rate_ext => open,
rc_pll_locked => open,
rc_rx_digitalreset => open,
reconfig_fromgxb => reconfig_fromgxb_int,
reset_status => open,
rx_fifo_empty0 => open,
rx_fifo_full0 => open,
rx_st_bardec0 => rx_st_bardec0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_data0 => rx_st_data0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_valid0 => rx_st_valid0_int,
rxpolarity0_ext => open,
suc_spd_neg => open,
test_out => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred0 => open,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
tx_out0 => tx_0,
tx_st_ready0 => tx_st_ready0_int,
txcompl0_ext => open,
txdata0_ext => open,
txdatak0_ext => open,
txdetectrx_ext => open,
txelecidle0_ext => open
);
tx_1 <= '1';
tx_2 <= '1';
tx_3 <= '1';
end generate gen_x1;
alt_reconf_comp : alt_reconf
port map(
reconfig_clk => clk_50,
reconfig_fromgxb => reconfig_fromgxb_int,
busy => reconf_busy,
reconfig_togxb => reconfig_togxb_int
);
gen_srst_crst_for_cold_warm_hot: process(rst_int,core_clk_int)
begin
if(rst_int = '1') then -- deactivate rst_cwh during ext_rst
rst_cwh <= '0';
rst_cwh_cnt <= (others => '0');
elsif(core_clk_int'event and core_clk_int = '1') then
if(l2_exit = '0' or hotrst_exit = '0' or dlup_exit = '0') then -- start reset
rst_cwh_cnt <= (others => '1');
elsif(rst_cwh_cnt > 0) then -- count condition
rst_cwh_cnt <= rst_cwh_cnt - 1;
else -- stop condition
rst_cwh_cnt <= (others => '0');
end if;
if(rst_cwh_cnt = 0) then -- reset if cnt > 0
rst_cwh <= '0';
else
rst_cwh <= '1';
end if;
end if;
end process;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
pcie_msi_i0 : pcie_msi
generic map(
WIDTH => IRQ_WIDTH
)
port map(
clk_i => wb_clk,
rst_i => wb_rst,
irq_req_i => irq_req_i,
wb_int_o => int_wb_int,
wb_pwr_enable_o => int_wb_pwr_enable,
wb_int_num_o => int_wb_int_num,
wb_int_ack_i => int_wb_int_ack,
wb_int_num_allowed_i => int_wb_int_num_allowed
);
-------------------------------------------------------------------------------
-- port assignement
--wbm_adr <= wbm_adr_int;
-- reset and clock logic
rst_int <= not ext_rst_n;
crst_int <= rst_int or rst_cwh;
srst_int <= rst_int or rst_cwh;
-------------------------------------------------------------------------------
end architecture ip_16z091_01_top_arch;
pcie_msi.vhd 0000664 0000000 0000000 00000034543 14574545710 0033304 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Interrupt request logic for processing MSI
-- Project :
--------------------------------------------------------------------------------
-- File : pcie_msi.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 28/02/12
--------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
--
-- Interrupt request handler for processing legacy and MSI on
-- PCIe Altera.
-- Each interrupt request signal of the toplevel should be
-- connected to the irq_req vector. The generic WIDTH controls
-- the max size, which should be identical or less than the
-- setting in the PCIe core.
-- If wb_int_num_allowed is smaller than the WIDTH of the irq_req
-- vector, legacy interrupts are selected. This is also when
-- the SW does not enable the MSI capability (wb_int_num_allowed=0).
-- Else if wb_int_num_allowed greater or equal the WIDTH of the
-- irq_req vector, MSI is selected.
-- MSI:
-- The handler triggers the PCIe core interface each time if a
-- rising edge was detected on either bit of the irq_req vector
-- (interrupt request got active). This will trigger the PCIe
-- to send a MSI packet to the CPU, with a vector number equal to
-- the bit number of the irq_req vector. Only the rising edge will
-- trigger the MSI.
-- legacy Interrupts:
-- If one of the bit of irq_req gets active, the PCIe core will be
-- triggered to send a INTA_asserted message. If another bit gets
-- active, no further messages will be sent. If all bit return to
-- inactive (irq_req = 0), a INTA_deassert message will be sent.
--
-- SuR: added wb interrupt number wrap according to maximum
-- number of enabled MSI vectors; corrected state machine
-- behavior
--------------------------------------------------------------------------------
-- Hierarchy:
-- ip_16z091_01_top_core
-- ip_16z091_01
-- Hard_IP
-- z091_01_wb_adr_dec
-- * pcie_msi-
--
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pcie_msi is
generic (
WIDTH : integer range 32 downto 1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
irq_req_i : in std_logic_vector(WIDTH -1 downto 0);
wb_int_o : out std_logic;
wb_pwr_enable_o : out std_logic;
wb_int_num_o : out std_logic_vector(4 downto 0);
wb_int_ack_i : in std_logic;
wb_int_num_allowed_i : in std_logic_vector(5 downto 0)
);
end pcie_msi;
architecture pcie_msi_arch of pcie_msi is
-- +---------------------------------------------------------------------------
-- | constants
-- +---------------------------------------------------------------------------
constant ZERO_5B : std_logic_vector(4 downto 0) := (others => '0');
constant ZERO_6B : std_logic_vector(5 downto 0) := (others => '0');
constant ZERO_32B : std_logic_vector(31 downto 0) := (others => '0');
-- +---------------------------------------------------------------------------
-- | internal signals
-- +---------------------------------------------------------------------------
type msi_states is (IDLE, REQUEST_MSI, REQUEST_INTA, WAIT_ON_DEASSERT_INTA, DEASSERT_INTA, WAITONEND);
signal msi_state : msi_states;
signal irq_req_q : std_logic_vector(WIDTH -1 downto 0);
signal irq_req_qq : std_logic_vector(WIDTH -1 downto 0);
signal irq_req_qqq : std_logic_vector(WIDTH -1 downto 0);
signal irq : std_logic_vector(31 downto 0);
signal clr_irq : std_logic_vector(WIDTH -1 downto 0);
signal wb_num : std_logic_vector(4 downto 0);
signal irq_type : std_logic; -- when 1: msi is selected
signal wb_num_q : std_logic_vector(4 downto 0);
signal wb_num_conv_q : std_logic_vector(4 downto 0);
signal wb_num_conv : std_logic_vector(4 downto 0);
signal int_max_msi_nbr : std_logic_vector(4 downto 0);
begin
wb_pwr_enable_o <= '0';
irq_type <= '1' when to_integer(unsigned(wb_int_num_allowed_i)) > 0 else '0';
------------------------------
-- calculate int_max_msi_nbr
------------------------------
int_max_msi_nbr <= (others => '0') when wb_int_num_allowed_i = ZERO_6B else
(others => '1') when wb_int_num_allowed_i = "100000" else
std_logic_vector(to_unsigned(to_integer(unsigned(wb_int_num_allowed_i)),5));
------------------------------------
-- provide fixed irq vector number
-- for every irq request
------------------------------------
wb_num <= "00000" when irq(0) = '1' else
"00001" when irq(1) = '1' else
"00010" when irq(2) = '1' else
"00011" when irq(3) = '1' else
"00100" when irq(4) = '1' else
"00101" when irq(5) = '1' else
"00110" when irq(6) = '1' else
"00111" when irq(7) = '1' else
"01000" when irq(8) = '1' else
"01001" when irq(9) = '1' else
"01010" when irq(10) = '1' else
"01011" when irq(11) = '1' else
"01100" when irq(12) = '1' else
"01101" when irq(13) = '1' else
"01110" when irq(14) = '1' else
"01111" when irq(15) = '1' else
"10000" when irq(16) = '1' else
"10001" when irq(17) = '1' else
"10010" when irq(18) = '1' else
"10011" when irq(19) = '1' else
"10100" WHEN irq(20) = '1' ELSE
"10101" WHEN irq(21) = '1' ELSE
"10110" WHEN irq(22) = '1' ELSE
"10111" WHEN irq(23) = '1' ELSE
"11000" WHEN irq(24) = '1' ELSE
"11001" WHEN irq(25) = '1' ELSE
"11010" WHEN irq(26) = '1' ELSE
"11011" WHEN irq(27) = '1' ELSE
"11100" WHEN irq(28) = '1' ELSE
"11101" WHEN irq(29) = '1' ELSE
"11110" WHEN irq(30) = '1' ELSE
"11111" WHEN irq(31) = '1' ELSE
"00000";
-- set vector number to interrupt pin number
wb_int_num_o <= wb_num_conv_q;
-------------------------------------------
-- if less MSI vectors are assigned than
-- were requested wrap the vector numbers
-------------------------------------------
wb_num_conv <= (others => '0') when (wb_int_num_allowed_i = ZERO_6B or
irq = ZERO_32B or wb_num = ZERO_5B) else
std_logic_vector(unsigned(wb_num) mod unsigned(int_max_msi_nbr));
process (clk_i, rst_i)
begin
if rst_i = '1' then
wb_int_o <= '0';
wb_num_q <= (others => '0');
irq_req_q <= (others => '0');
irq_req_qq <= (others => '0');
irq_req_qqq <= (others => '0');
irq <= (others => '0');
clr_irq <= (others => '0');
msi_state <= IDLE;
wb_num_conv_q <= (others => '0');
elsif clk_i'event and clk_i = '1' then
irq_req_q <= irq_req_i;
irq_req_qq <= irq_req_q;
irq_req_qqq <= irq_req_qq;
for i in 0 to WIDTH-1 loop
if irq_req_qq(i) = '1' and irq_req_qqq(i) = '0' then
irq(i) <= '1';
elsif clr_irq(i) = '1' then
irq(i) <= '0';
end if;
end loop;
if WIDTH < 32 then
irq(31 downto WIDTH) <= (others => '0');
end if;
case msi_state is
-- wait until interrupt request is pending
when IDLE =>
if irq /= 0 and irq_type = '1' then -- send msi
wb_num_q <= wb_num; -- store number of interrupt at start of processing in order
-- not to get confused if another irq gets active
wb_num_conv_q <= wb_num_conv; -- set vector number to interrupt pin number
wb_int_o <= '1'; -- indicate interrupt request to pcie core
clr_irq <= (others => '0');
msi_state <= REQUEST_MSI;
elsif irq /= 0 and irq_type = '0' then -- send legacy
wb_num_q <= wb_num; -- store number of interrupt at start of processing in order
-- not to get confused if another irq gets active
wb_num_conv_q <= (others => '0'); -- unused for inta
wb_int_o <= '1'; -- indicate interrupt request to pcie core
clr_irq <= (others => '0');
msi_state <= REQUEST_INTA;
else
wb_num_q <= (others => '0');
wb_num_conv_q <= (others => '0');
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= IDLE;
end if;
-- wait until interrupt request was processed by pcie
when REQUEST_MSI =>
if wb_int_ack_i = '1' then
wb_num_q <= (others => '0'); -- clear
wb_num_conv_q <= wb_num_conv_q;
wb_int_o <= '0'; -- clear interrupt request
clr_irq <= (others => '0');
clr_irq(conv_integer(wb_num_q)) <= '1'; -- clear processed interrupt request
msi_state <= WAITONEND;
else
wb_num_q <= wb_num_q;
wb_num_conv_q <= wb_num_conv_q;
wb_int_o <= '1';
clr_irq <= (others => '0');
msi_state <= REQUEST_MSI;
end if;
-------------------------------------
-- wait until inta message was sent
-------------------------------------
when REQUEST_INTA =>
if wb_int_ack_i = '1' then
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '1';
clr_irq <= (others => '0');
msi_state <= WAIT_ON_DEASSERT_INTA;
else
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '1';
clr_irq <= (others => '0');
msi_state <= REQUEST_INTA;
end if;
----------------------------------
-- send deassert inta message if
-- processed irq is deasserted
----------------------------------
when WAIT_ON_DEASSERT_INTA =>
if irq_req_qq(to_integer(unsigned(wb_num_q))) = '0' then
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0'); -- unused for inta
wb_int_o <= '0'; -- indicate interrupt deassert to pcie core
clr_irq <= (others => '0');
clr_irq(to_integer(unsigned(wb_num_q))) <= '1'; -- clear processed interrupt request
msi_state <= DEASSERT_INTA;
else
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '1';
clr_irq <= (others => '0');
msi_state <= WAIT_ON_DEASSERT_INTA;
end if;
-----------------------------
-- wait until deassert inta
-- message was sent
-----------------------------
when DEASSERT_INTA =>
if wb_int_ack_i = '1' then -- deassertion was sent
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '0'; -- clear interrupt request
--clr_irq(to_integer(unsigned(wb_num_q))) <= '1'; -- clear processed interrupt request
clr_irq <= (others => '0');
msi_state <= WAITONEND;
else
wb_num_q <= wb_num_q;
wb_num_conv_q <= (others => '0');
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= DEASSERT_INTA;
end if;
-- wait until handshake has ended in order to be prepared for next interrupt
when WAITONEND =>
if wb_int_ack_i = '0' then -- handshake has ended
wb_num_q <= (others => '0'); -- clear
wb_num_conv_q <= (others => '0');
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= IDLE;
else
wb_num_q <= (others => '0'); -- clear
wb_num_conv_q <= wb_num_conv_q;
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= WAITONEND;
end if;
-- coverage_off
when others =>
wb_num_q <= (others => '0');
wb_num_conv_q <= (others => '0');
wb_int_o <= '0';
clr_irq <= (others => '0');
msi_state <= IDLE;
-- coverage_on
end case;
end if;
end process;
end pcie_msi_arch;
rx_ctrl.vhd 0000664 0000000 0000000 00000041335 14574545710 0033166 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : RX control state machine
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-24
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- RX path state machine for Avalon ST and FIFO control
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- * rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.src_utils_pkg.all;
entity rx_ctrl is
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- Hard IP
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
tlp_type_i : in std_logic_vector(4 downto 0);
tlp_fmt_i : in std_logic_vector(2 downto 0);
-- RX FIFO
rx_fifo_c_enable_o : out std_logic;
rx_fifo_wr_enable_o : out std_logic;
-- rx_sig_manage
fifo_action_done_o : out std_logic;
-- rx_get_data
len_cntr_val_i : in std_logic_vector(9 downto 0)
);
end entity rx_ctrl;
architecture rx_ctrl_arch of rx_ctrl is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
type fsm_state is (WAITING, IDLE, WRRD, CPL, ECRC_ERROR, LOAD_CNTR, FALSE_PACKET);
signal state : fsm_state;
signal int_fifo_c_en : std_logic;
signal int_fifo_wr_en : std_logic;
signal int_len2fifo_wr : std_logic_vector(9 downto 0);
signal int_len2fifo_c : std_logic_vector(9 downto 0);
signal int_enable_c_cntr : std_logic;
signal int_enable_wr_cntr : std_logic;
signal int_load_c_cntr : std_logic;
signal int_load_wr_cntr : std_logic;
signal int_c_wr : std_logic;
signal int_sop : std_logic;
signal int_false_packet : std_logic;
signal int_rxstvalid0_q : std_logic;
signal int_rxstsop0_q : std_logic;
signal int_rxsteop0_q : std_logic;
signal int_rxsteop0_qq : std_logic;
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
rx_fifo_c_enable_o <= int_fifo_c_en;
rx_fifo_wr_enable_o <= int_fifo_wr_en;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
reg_proc : process(rst_i, clk_i)
begin
if rst_i = '1' then
int_c_wr <= '0';
int_sop <= '0';
int_false_packet <= '0';
int_rxstvalid0_q <= '0';
int_rxstsop0_q <= '0';
int_rxsteop0_q <= '0';
int_rxsteop0_qq <= '0';
elsif clk_i'event and clk_i = '1' then
int_rxstvalid0_q <= rx_st_valid0;
int_rxstsop0_q <= rx_st_sop0;
int_rxsteop0_q <= rx_st_eop0;
int_rxsteop0_qq <= int_rxsteop0_q;
if rx_st_valid0 = '1' and rx_st_sop0 = '1' then
int_sop <= '1';
elsif rx_st_valid0 = '1' and rx_st_eop0 = '1' then
int_sop <= '0';
else
int_sop <= int_sop;
end if;
if rx_st_valid0 = '1' and rx_st_sop0 = '1' then
if tlp_type_i = TYPE_IS_MEMORY or tlp_type_i = TYPE_IS_IO then
int_c_wr <= '1';
elsif tlp_type_i = TYPE_IS_CPL and tlp_fmt_i = FMT_IS_WRITE then
int_c_wr <= '0';
else
int_c_wr <= '0';
end if;
else
int_c_wr <= int_c_wr;
end if;
-----------------------------------------------------------
-- if the transfer is invalid set int_false_packet to '1'
-- invalid = all packet types except I/O wr/rd,
-- memory wr/rd or completion (not locked)
-----------------------------------------------------------
if rx_st_valid0 = '1' and rx_st_sop0 = '1' then
if (tlp_fmt_i = FMT_IS_READ and tlp_type_i = TYPE_IS_MEMORY) or
(tlp_fmt_i = FMT_IS_READ and tlp_type_i = TYPE_IS_IO) or
(tlp_fmt_i = FMT_IS_WRITE and tlp_type_i = TYPE_IS_MEMORY) or
(tlp_fmt_i = FMT_IS_WRITE and tlp_type_i = TYPE_IS_IO) or
(tlp_fmt_i = FMT_IS_WRITE and tlp_type_i = TYPE_IS_CPL) then
int_false_packet <= '0';
else
int_false_packet <= '1';
end if;
elsif rx_st_valid0 = '1' and rx_st_eop0 = '1' then
int_false_packet <= '0';
end if;
end if;
end process reg_proc;
------------------------------
-- state machine transitions
------------------------------
fsm_trans : process(rst_i, clk_i)
begin
if rst_i = '1' then
state <= IDLE;
elsif clk_i'event and clk_i = '1' then
case state is
when IDLE =>
------------------------------------------------------
-- go to LOAD_CNTR if a transfer after ECRC error is
-- not finished yet or a new, valid transfer starts
-- if the transfer is invalid go to FALSE_PACKET
-- invalid => int_false_packet = '1'
------------------------------------------------------
if int_rxstvalid0_q = '0' and int_sop = '1' then
state <= LOAD_CNTR;
elsif int_rxstvalid0_q = '1' and int_rxstsop0_q = '1' then
if int_false_packet = '1' then
state <= FALSE_PACKET;
else
state <= LOAD_CNTR;
end if;
else
state <= IDLE;
end if;
when LOAD_CNTR =>
--------------------------------------------
-- load counter values for length counters
--------------------------------------------
if int_rxstvalid0_q = '0' then
state <= WAITING;
elsif int_c_wr = '0' then
state <= CPL;
else
state <= WRRD;
end if;
when CPL =>
---------------------------------------------------------
-- transfer completion data to the completion FIFO
-- go to ECRC_ERROR if the transfer is terminated early
-- go to WAITING if rx_st_valid0 is deasserted
-- go to IDLE if all data is transferred
---------------------------------------------------------
if int_rxsteop0_qq = '1' and int_len2fifo_c > ONE_10B then
state <= ECRC_ERROR;
elsif int_len2fifo_c > ONE_10B and int_rxstvalid0_q = '0' then
state <= WAITING;
elsif int_rxstvalid0_q = '1' and int_rxstsop0_q = '1' then
state <= LOAD_CNTR;
elsif (int_len2fifo_c = ONE_10B and int_rxstvalid0_q = '0') or
(int_len2fifo_c = ZERO_10B and int_rxstvalid0_q = '0' and int_rxsteop0_qq = '1') then
state <= IDLE;
else
state <= CPL;
end if;
when WRRD =>
---------------------------------------------------------
-- transfer write or read data to the wr FIFO
-- go to ECRC_ERROR if the transfer is terminated early
-- go to WAITING if rx_st_valid0 is deasserted
-- go to IDLE if all data is transferred
---------------------------------------------------------
if int_rxsteop0_qq = '1' and int_len2fifo_wr > ONE_10B then
state <= ECRC_ERROR;
elsif int_len2fifo_wr > ONE_10B and int_rxstvalid0_q = '0' then
state <= WAITING;
elsif int_rxstvalid0_q = '1' and int_rxstsop0_q = '1' then
state <= LOAD_CNTR;
elsif (int_len2fifo_wr = ONE_10B and int_rxstvalid0_q = '0') or
(int_len2fifo_wr = ZERO_10B and int_rxstvalid0_q = '0' and int_rxsteop0_qq = '1') then
state <= IDLE;
else
state <= WRRD;
end if;
when WAITING =>
-------------------------------------------------
-- wait until hard IP is ready to transfer data
-------------------------------------------------
if int_rxstvalid0_q = '1' then
if int_c_wr = '1' then
state <= WRRD;
else
state <= CPL;
end if;
else
state <= WAITING;
end if;
when ECRC_ERROR =>
----------------------------------------------------
-- if an ECRC error occurs the transfer may be
-- terminated early
-- in that case store dummy data to the FIFO until
-- the original transfer length is achieved
-- then go to IDLE
----------------------------------------------------
if int_c_wr = '0' and int_len2fifo_c = ONE_10B then
state <= IDLE;
elsif int_c_wr = '1' and int_len2fifo_wr = ONE_10B then
state <= IDLE;
else
state <= ECRC_ERROR;
end if;
when FALSE_PACKET =>
---------------------------------------------------------------
-- some packet types, e.g. messages, are forwarded by the
-- hard IP although the 16z091-01 core does not process them
-- in this case acknowledge the transfer but don't store
-- anything to the FIFO
---------------------------------------------------------------
if int_rxstvalid0_q = '1' and int_rxsteop0_q = '1' then
state <= IDLE;
else
state <= FALSE_PACKET;
end if;
when others =>
state <= IDLE;
assert false report "undecoded state in process fsm_trans in rx_ctrl.vhd" severity error;
end case;
end if;
end process fsm_trans;
--------------------------
-- state machine outputs
--------------------------
fsm_out : process(state, int_c_wr, int_len2fifo_c, int_len2fifo_wr)
begin
case state is
when IDLE =>
fifo_action_done_o <= '0';
int_fifo_c_en <= '0';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
when LOAD_CNTR =>
fifo_action_done_o <= '0';
if int_c_wr = '0' then
int_load_c_cntr <= '1';
int_load_wr_cntr <= '0';
int_fifo_c_en <= '1';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '1';
int_enable_wr_cntr <= '0';
else
int_load_c_cntr <= '0';
int_load_wr_cntr <= '1';
int_fifo_c_en <= '0';
int_fifo_wr_en <= '1';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '1';
end if;
when CPL =>
int_fifo_c_en <= '1';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '1';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
if int_len2fifo_c = ONE_10B then
fifo_action_done_o <= '1';
else
fifo_action_done_o <= '0';
end if;
when WRRD =>
int_fifo_c_en <= '0';
int_fifo_wr_en <= '1';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '1';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
if int_len2fifo_wr = ONE_10B then
fifo_action_done_o <= '1';
else
fifo_action_done_o <= '0';
end if;
when WAITING =>
fifo_action_done_o <= '0';
int_fifo_c_en <= '0';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
when ECRC_ERROR =>
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
if int_c_wr = '0' then
int_fifo_c_en <= '1';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '1';
int_enable_wr_cntr <= '0';
else
int_fifo_c_en <= '0';
int_fifo_wr_en <= '1';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '1';
end if;
if int_len2fifo_c = ONE_10B or int_len2fifo_wr = ONE_10B then
fifo_action_done_o <= '1';
else
fifo_action_done_o <= '0';
end if;
when FALSE_PACKET =>
------------------------------------------
-- a false packet should be acknowledged
-- but not stored to the FIFO
------------------------------------------
fifo_action_done_o <= '0';
int_fifo_c_en <= '0';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
when others =>
int_fifo_c_en <= '0';
int_fifo_wr_en <= '0';
int_enable_c_cntr <= '0';
int_enable_wr_cntr <= '0';
int_load_c_cntr <= '0';
int_load_wr_cntr <= '0';
fifo_action_done_o <= '0';
assert false report "undecoded state in process fsm_trans in rx_ctrl.vhd" severity error;
end case;
end process fsm_out;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
c_len_cntr_comp : entity work.rx_len_cntr
port map(
clk_i => clk_i,
rst_i => rst_i,
-- rx_get_data
load_cntr_val_i => len_cntr_val_i,
-- rx_ctrl
load_cntr_i => int_load_c_cntr,
enable_cntr_i => int_enable_c_cntr,
len2fifo_o => int_len2fifo_c
);
wr_len_cntr_comp : entity work.rx_len_cntr
port map(
clk_i => clk_i,
rst_i => rst_i,
-- rx_get_data
load_cntr_val_i => len_cntr_val_i,
-- rx_ctrl
load_cntr_i => int_load_wr_cntr,
enable_cntr_i => int_enable_wr_cntr,
len2fifo_o => int_len2fifo_wr
);
-------------------------------------------------------------------------------
end architecture rx_ctrl_arch;
rx_get_data.vhd 0000664 0000000 0000000 00000045504 14574545710 0033774 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : RX data path
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_get_data.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-24
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- manages RX data path and provides information contained in rx_st_data0
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- * rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity rx_get_data is
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_valid0 : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_sop0 : in std_logic;
-- FIFO
rx_fifo_in_o : out std_logic_vector(63 downto 0);
-- tx_ctrl
tag_nbr_o : out std_logic_vector(7 downto 0);
tag_rcvd_o : out std_logic;
-- rx_ctrl
len_cntr_val_o : out std_logic_vector(9 downto 0);
-- error
type_fmt_err_o : out std_logic_vector(1 downto 0);
-- rx_sig_manage
sop_q_i : in std_logic
);
end entity rx_get_data;
architecture rx_get_data_arch of rx_get_data is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
signal int_cntr_val_temp : std_logic_vector(9 downto 0); -- internal length counter
signal int_len_is_odd : std_logic; -- =1 if length is odd else 0
signal int_c_wr : std_logic; -- =0 cpl, =1 write/read
signal int_is_read : std_logic; -- =1 if transfer is a read, else 0
signal int_aligned : std_logic; -- =1 if data is QWORD aligned else 0
signal int_tag_rcvd : std_logic; -- =1 if tag number for last of multiple
-- completions is received, else 0
-------------------------------------
-- signals to register port signals
-------------------------------------
signal int_rxstvalid0_q : std_logic;
signal int_rxstdata0_q : std_logic_vector(63 downto 0);
signal int_rxstsop0_q : std_logic;
signal int_sopqi_q : std_logic;
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
len_cntr_val_o <= int_cntr_val_temp;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
------------------------------------------
-- process to register necessary signals
------------------------------------------
reg_proc : process(rst_i, clk_i)
begin
if rst_i = '1' then
int_rxstvalid0_q <= '0';
int_rxstdata0_q <= (others => '0');
int_rxstsop0_q <= '0';
int_sopqi_q <= '0';
elsif clk_i'event and clk_i = '1' then
int_rxstvalid0_q <= rx_st_valid0;
int_rxstsop0_q <= rx_st_sop0;
int_sopqi_q <= sop_q_i;
if rx_st_valid0 = '1' then
int_rxstdata0_q <= rx_st_data0;
end if;
end if;
end process reg_proc;
main : process(rst_i, clk_i)
begin
if rst_i = '1' then
rx_fifo_in_o <= (others => '0');
tag_nbr_o <= (others => '0');
tag_rcvd_o <= '0';
type_fmt_err_o <= (others => '0');
int_c_wr <= '0';
int_is_read <= '0';
int_tag_rcvd <= '0';
int_cntr_val_temp <= (others => '0');
int_len_is_odd <= '0';
int_aligned <= '0';
elsif clk_i'event and clk_i = '1' then
------------------------------------------------------
-- tag_rcvd_o must be a registered version of
-- int_tag_rcvd because the tag nbr for completions
-- can be stored one clock cycle later than
-- for memory writes/reads
------------------------------------------------------
tag_rcvd_o <= int_tag_rcvd;
if rx_st_valid0 = '1' then
if rx_st_sop0 = '1' then
int_len_is_odd <= rx_st_data0(0);
int_aligned <= int_aligned;
if rx_st_data0(28 downto 24) = TYPE_IS_CPL then
int_c_wr <= '0';
-----------------------------------------
-- check if this is the last completion
-- byte count value must be the same or
-- less than length value *4
-----------------------------------------
if rx_st_data0(43 downto 32) <= rx_st_data0(9 downto 0) & "00" then
int_tag_rcvd <= '1';
else
int_tag_rcvd <= '0';
end if;
elsif (rx_st_data0(28 downto 24) = TYPE_IS_MEMORY or rx_st_data0(28 downto 24) = TYPE_IS_IO) then
int_c_wr <= '1';
tag_nbr_o <= rx_st_data0(47 downto 40);
end if;
if rx_st_data0(31 downto 29) = FMT_IS_READ then
int_is_read <= '1';
else
int_is_read <= '0';
end if;
---------------------------------------------
-- check if a type or format error occurred
-- if I/O length is ok
-- and if a completion error occurred
---------------------------------------------
case rx_st_data0(31 downto 24) is
when "00000000" | "01000000" => -- memory
type_fmt_err_o <= (others => '0');
when "00000010" | "01000010" => -- I/O
if(rx_st_data0(9 downto 0) > "0000000001") then -- I/O requests must have length = 1
type_fmt_err_o <= "01";
else
type_fmt_err_o <= (others => '0');
end if;
when "00001010" => -- completion, no data
type_fmt_err_o <= (others => '0');
when "01001010" => -- completion, data
type_fmt_err_o <= (others => '0');
when "00110000" | "00110001" | "00110010" | "00110011" | -- message
"00110100" | "00110101" | "00110110" | "00110111" |
"01110000" | "01110001" | "01110010" | "01110011" |
"01110100" | "01110101" | "01110110" | "01110111" =>
type_fmt_err_o <= (others => '0');
when "00100000" | "00000001" | "00100001" | "01001100" | -- non-posted
"01101100" | "01001101" | "01101101" | "01001110" |
"01101110" =>
type_fmt_err_o <= "01";
when "01100000" => --posted
type_fmt_err_o <= "10";
when others =>
type_fmt_err_o <= "11"; -- e.g. TLP prefix or TCfg
end case;
------------------------------------------------------------------
-- calculate the amount of 64bit packets that must be stored to
-- the FIFO:
-- -> read length is always 2
-- -> 2 packets for the header information
-- -> length value divided by 2 because it represents the amount
-- of 32bit packets
-- length = 0 represents 1024DW otherwise as specified by length
------------------------------------------------------------------
if rx_st_data0(31 downto 29) = FMT_IS_READ then
int_cntr_val_temp <= std_logic_vector(to_unsigned(2,10));
elsif rx_st_data0(9 downto 0) = ZERO_10B then
int_cntr_val_temp <= std_logic_vector(unsigned('1' & rx_st_data0(9 downto 1)) + to_unsigned(2,10));
else
int_cntr_val_temp <= std_logic_vector(unsigned('0' & rx_st_data0(9 downto 1)) + to_unsigned(2,10));
end if;
elsif sop_q_i = '1' then
-------------------------------------------
-- reset int_tag_rcvd value one clock cycle
-- after it was asserted
-------------------------------------------
int_tag_rcvd <= '0';
if int_c_wr = '0' then
tag_nbr_o <= rx_st_data0(15 downto 8);
end if;
if int_rxstdata0_q(2) = '0' then
int_aligned <= '1';
else
int_aligned <= '0';
end if;
----------------------------------------------------------------
-- set counter value to temp value +1 if length is odd and
-- data is aligned
-- otherwise set counter value to temp value
-- don't change counter for read transactions
----------------------------------------------------------------
if int_is_read = '0' and int_len_is_odd = '1' and rx_st_data0(2) = '0' then
int_cntr_val_temp <= std_logic_vector(unsigned(int_cntr_val_temp) + to_unsigned(1,10));
else
int_cntr_val_temp <= int_cntr_val_temp;
end if;
else
int_len_is_odd <= int_len_is_odd;
int_cntr_val_temp <= int_cntr_val_temp;
int_aligned <= int_aligned;
end if;
else
int_len_is_odd <= int_len_is_odd;
int_aligned <= int_aligned;
end if;
if int_rxstvalid0_q = '1' and int_rxstsop0_q = '1' then
int_aligned <= '0';
if int_rxstdata0_q(28 downto 24) = TYPE_IS_MEMORY or int_rxstdata0_q(28 downto 24) = TYPE_IS_IO then
-------------------------------------------------------------------------
-- data alignment in FIFO for writes or reads
-- h : header information stored to FIFO
-- d : data packet stored to FIFO
-- x : data at this position is invalid (can differ from 0)
--+---------+--------------+--------------+--------------+--------------+
--| | aligned | aligned | not aligned | not aligned |
--| | even length | odd length | even length | odd length |
--+---------+--------------+--------------+--------------+--------------+
--| RX FIFO | | | | | | | | | | | | |
--| 63 | | | | | | | | | | | | |
--| ... | h1 | x | d1 | h1 | x | x | h1 | d0 | x | h1 | d0 | d2 |
--| 32 | | | | | | | | | | | | |
--|---------|----|----|----|----|----|----|----|----|----|----|----|----|
--| 31 | | | | | | | | | | | | |
--| ... | h0 | h2 | d0 | h0 | h2 | d0 | h0 | h2 | d1 | h0 | h2 | d1 |
--| 0 | | | | | | | | | | | | |
--+---------+----+----+----+----+----+----+----+----+----+----+----+----+
-------------------------------------------
-- store header for write or read to FIFO
-------------------------------------------
rx_fifo_in_o(63 downto 54) <= (others => '0'); -- R
rx_fifo_in_o(53 downto 51) <= int_rxstdata0_q(18) & int_rxstdata0_q(13 downto 12); -- Attr
rx_fifo_in_o(50 downto 48) <= int_rxstdata0_q(22 downto 20); -- TC
rx_fifo_in_o(47 downto 32) <= int_rxstdata0_q(63 downto 48); -- requester ID
rx_fifo_in_o(31) <= int_rxstdata0_q(30); -- write flag
if int_rxstdata0_q(28 downto 24) = TYPE_IS_IO then
rx_fifo_in_o(30) <= '1'; -- I/O flag
else
rx_fifo_in_o(30) <= '0';
end if;
rx_fifo_in_o(29) <= '0'; -- R
---------------------------------------
-- decode and store which BAR was hit
---------------------------------------
case rx_st_bardec0 is
when "00000001" =>
rx_fifo_in_o(28 downto 26) <= "000"; -- BAR0 hit
when "00000010" =>
rx_fifo_in_o(28 downto 26) <= "001"; -- BAR1 hit
when "00000100" =>
rx_fifo_in_o(28 downto 26) <= "010"; -- BAR2 hit
when "00001000" =>
rx_fifo_in_o(28 downto 26) <= "011"; -- BAR3 hit
when "00010000" =>
rx_fifo_in_o(28 downto 26) <= "100"; -- BAR4 hit
when "00100000" =>
rx_fifo_in_o(28 downto 26) <= "101"; -- BAR5 hit
when "01000000" =>
rx_fifo_in_o(28 downto 26) <= "110"; -- expansion ROM hit
when others =>
rx_fifo_in_o(28 downto 26) <= "111"; -- no BAR hit / reserved
end case;
rx_fifo_in_o(25 downto 18) <= int_rxstdata0_q(47 downto 40); -- tag ID
rx_fifo_in_o(17 downto 14) <= int_rxstdata0_q(35 downto 32); -- first DW BE
rx_fifo_in_o(13 downto 10) <= int_rxstdata0_q(39 downto 36); -- last DW BE
rx_fifo_in_o(9 downto 0) <= int_rxstdata0_q(9 downto 0); -- length
elsif int_rxstdata0_q(28 downto 24) = TYPE_IS_CPL then
-------------------------------------------------------------------------
-- data alignment in FIFO for completions
-- h : header information stored to FIFO
-- d : data packet stored to FIFO
-- x : data at this position is invalid (can differ from 0)
--+---------+--------------+--------------+--------------+--------------+
--| | aligned | aligned | not aligned | not aligned |
--| | even length | odd length | even length | odd length |
--+---------+--------------+--------------+--------------+--------------+
--| RX FIFO | | | | | | | | | | | | |
--| 63 | | | | | | | | | | | | |
--| ... | x | x | d1 | x | x | x | x | d0 | x | x | d0 | d2 |
--| 32 | | | | | | | | | | | | |
--|---------|----|----|----|----|----|----|----|----|----|----|----|----|
--| 31 | | | | | | | | | | | | |
--| ... | h0 | x | d0 | h0 | x | d0 | h0 | x | d1 | h0 | x | d1 |
--| 0 | | | | | | | | | | | | |
--+---------+----+----+----+----+----+----+----+----+----+----+----+----+
----------------------------------------
-- store header for completion to FIFO
----------------------------------------
rx_fifo_in_o(63 downto 22) <= (others => '0'); -- R
rx_fifo_in_o(21 downto 10) <= int_rxstdata0_q(43 downto 32); -- byte count
rx_fifo_in_o(9 downto 0) <= int_rxstdata0_q(9 downto 0); -- length
end if;
elsif int_rxstvalid0_q = '1' and int_sopqi_q = '1' then
rx_fifo_in_o <= int_rxstdata0_q; -- address and D0 or R
elsif int_rxstvalid0_q = '1' then
rx_fifo_in_o <= int_rxstdata0_q;
end if;
end if;
end process main;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
-- NONE
-------------------------------------------------------------------------------
end architecture rx_get_data_arch;
rx_len_cntr.vhd 0000664 0000000 0000000 00000011450 14574545710 0034021 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : RX length counter
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_len_cntr.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-23
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- length counter to manage data stored to the RX FIFOs
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- * rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity rx_len_cntr is
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- rx_get_data
load_cntr_val_i : in std_logic_vector(9 downto 0);
-- rx_ctrl
load_cntr_i : in std_logic;
enable_cntr_i : in std_logic;
len2fifo_o : out std_logic_vector(9 downto 0)
);
end entity rx_len_cntr;
architecture rx_len_cntr_arch of rx_len_cntr is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
signal int_cntr_val : std_logic_vector(9 downto 0);
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
len2fifo_o <= int_cntr_val;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
cntr_proc : process(rst_i, clk_i)
begin
if rst_i = '1' then
int_cntr_val <= (others => '0');
elsif clk_i'event and clk_i = '1' then
-----------------------------------------------
-- load new value if load_cntr_i is asserted
-- subtract one if counter is already enabled
-----------------------------------------------
if load_cntr_i = '1' then
if enable_cntr_i = '0' then
int_cntr_val <= load_cntr_val_i;
else
int_cntr_val <= std_logic_vector(unsigned(load_cntr_val_i) - to_unsigned(1,10));
end if;
-----------------------------------------------------------
-- decrement counter as long as enable_cntr_i is set
-- but stop decrementing as soon as int_cntr_val is zero
-----------------------------------------------------------
else
if int_cntr_val > ZERO_10B and enable_cntr_i = '1' then
int_cntr_val <= std_logic_vector(unsigned(int_cntr_val) - to_unsigned(1,10));
elsif int_cntr_val > ZERO_10B and enable_cntr_i = '0' then
int_cntr_val <= int_cntr_val;
else
int_cntr_val <= (others => '0');
end if;
end if;
end if;
end process cntr_proc;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
-- NONE
-------------------------------------------------------------------------------
end architecture rx_len_cntr_arch;
rx_module.vhd 0000664 0000000 0000000 00000027105 14574545710 0033506 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : RX module v2
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_module.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-23
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- combines modules rx_get_data.vhd, rx_ctrl.vhd and 2 FIFO's
-- to calculate valid values for RX_FIFO_DEPTH refer to ug_fifo.pdf page 9
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- * rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity rx_module is
generic(
DEVICE_FAMILY : string := "unused";
READY_LATENCY : natural := 2; -- only specify values between 0 and 2
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001"; -- = 1017 DW;
-- set this value to "1111111111" - (READY_LATENCY + 1)
RX_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(RX_LPM_WIDTHU-1) < RX_FIFO_DEPTH <= 2^(RX_LPM_WIDTHU)
RX_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
rst : in std_logic;
-- IP Core
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
-- FIFO
rx_fifo_c_rd_enable : in std_logic;
rx_fifo_wr_rd_enable : in std_logic;
rx_fifo_c_empty : out std_logic;
rx_fifo_wr_empty : out std_logic;
rx_fifo_c_out : out std_logic_vector(31 downto 0);
rx_fifo_wr_out : out std_logic_vector(31 downto 0);
-- Tx Module
rx_tag_nbr : out std_logic_vector(7 downto 0);
rx_tag_rcvd : out std_logic;
-- error
rx_type_fmt_err : out std_logic_vector(1 downto 0);
rx_ecrc_err : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end entity rx_module;
architecture rx_module_arch of rx_module is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
-- rx_ctrl and rx_get_data connection signals
signal int_len_cntr_val : std_logic_vector(9 downto 0);
signal int_fifo_action_done : std_logic;
-- FIFO signals
signal int_c_wr_enable : std_logic;
signal int_c_wr_full : std_logic;
signal int_rx_fifo_c_usedw : unsigned(RX_LPM_WIDTHU downto 0);
signal int_wr_wr_enable : std_logic;
signal int_wr_wr_full : std_logic;
signal int_rx_fifo_wr_usedw : unsigned(RX_LPM_WIDTHU downto 0);
signal int_rx_fifo_data : std_logic_vector(63 downto 0);
-- signals for signal management process
signal int_ready : std_logic;
signal int_err : std_logic;
signal int_sop_q : std_logic;
signal int_tlp_type : std_logic_vector(4 downto 0);
signal int_tlp_fmt : std_logic_vector(2 downto 0);
-- define some aliases for easier handling
alias rx_data0_type is rx_st_data0(28 downto 24);
alias rx_data0_fmt is rx_st_data0(31 downto 29);
-- debug signals: none
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
rx_st_mask0 <= '0';
rx_st_ready0 <= int_ready;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
-- registers to remembe the type and fmt for the last received TLP
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
int_tlp_type <= (others=>'0');
elsif (rx_st_valid0 = '1' and rx_st_sop0 = '1') then
int_tlp_type <= rx_data0_type;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
int_tlp_fmt <= (others=>'0');
elsif (rx_st_valid0 = '1' and rx_st_sop0 = '1') then
int_tlp_fmt <= rx_data0_fmt;
end if;
end if;
end process;
rx_sig_manage : process(rst, clk)
begin
if rst = '1' then
int_ready <= '0';
int_err <= '0';
int_sop_q <= '0';
elsif clk'event and clk = '1' then
------------------------------
-- manage registered signals
------------------------------
int_sop_q <= rx_st_sop0;
--------------------------------------
-- signal ECRC error to error module
--------------------------------------
if rx_st_err0 = '1' and int_err = '0' then
rx_ecrc_err <= '1';
else
rx_ecrc_err <= '0';
end if;
-------------------------------------------------------
-- if an error state occured reset ready signal
-- until rx_ctrl has finished processing the error
-- if the FIFOs are not full assert ready
-- else deassert it until the FIFOs are not full
-------------------------------------------------------
if ((int_err = '1' or rx_st_err0 = '1') and rx_st_eop0 = '1' and rx_st_valid0 = '1') or
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw >= unsigned(FIFO_MAX_USEDW)) or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw >= unsigned(FIFO_MAX_USEDW)) then
int_ready <= '0';
elsif int_err = '0' and (
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw < unsigned(FIFO_MAX_USEDW) and int_c_wr_full = '0') or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw < unsigned(FIFO_MAX_USEDW) and int_wr_wr_full = '0')
) then
int_ready <= '1';
end if;
-----------------------------------------------------------------
-- reset error flag if rx_ctrl has finished working on the fifo
-- set error flag if error ocurs during transmission
-- otherwise keep error flag value
-----------------------------------------------------------------
if int_fifo_action_done = '1' then
int_err <= '0';
elsif rx_st_err0 = '1' and rx_st_valid0 = '1' then
int_err <= '1';
else
int_err <= int_err;
end if;
end if;
end process rx_sig_manage;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
rx_ctrl_comp : entity work.rx_ctrl
port map(
clk_i => clk,
rst_i => rst,
-- Hard IP
rx_st_err0 => rx_st_err0,
rx_st_valid0 => rx_st_valid0,
rx_st_sop0 => rx_st_sop0,
rx_st_eop0 => rx_st_eop0,
rx_st_be0 => rx_st_be0,
tlp_type_i => rx_data0_type,
tlp_fmt_i => rx_data0_fmt,
-- FIFO
rx_fifo_c_enable_o => int_c_wr_enable,
rx_fifo_wr_enable_o => int_wr_wr_enable,
-- rx_sig_manage
fifo_action_done_o => int_fifo_action_done,
-- rx_get_data
len_cntr_val_i => int_len_cntr_val
);
rx_get_data_comp : entity work.rx_get_data
port map(
clk_i => clk,
rst_i => rst,
-- Hard IP
rx_st_valid0 => rx_st_valid0,
rx_st_data0 => rx_st_data0,
rx_st_bardec0 => rx_st_bardec0,
rx_st_sop0 => rx_st_sop0,
-- FIFO
rx_fifo_in_o => int_rx_fifo_data,
-- tx_ctrl
tag_nbr_o => rx_tag_nbr,
tag_rcvd_o => rx_tag_rcvd,
-- rx_ctrl
len_cntr_val_o => int_len_cntr_val,
-- error
type_fmt_err_o => rx_type_fmt_err,
-- rx_sig_manage
sop_q_i => int_sop_q
);
-- Completion TLP
c_fifo_comp : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU+1,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "ON")
port map (
aclr => rst,
data => int_rx_fifo_data,
rdclk => wb_clk,
rdreq => rx_fifo_c_rd_enable,
wrclk => clk,
wrreq => int_c_wr_enable,
q => rx_fifo_c_out,
rdempty => rx_fifo_c_empty,
wrfull => int_c_wr_full,
unsigned(wrusedw) => int_rx_fifo_c_usedw);
-- MEM or IO TLP, read by wb master
wr_fifo_comp : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU+1,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "OFF")
port map (
aclr => rst,
data => int_rx_fifo_data,
rdclk => wb_clk,
rdreq => rx_fifo_wr_rd_enable,
wrclk => clk,
wrreq => int_wr_wr_enable,
q => rx_fifo_wr_out,
rdempty => rx_fifo_wr_empty,
wrfull => int_wr_wr_full,
unsigned(wrusedw) => int_rx_fifo_wr_usedw);
-------------------------
-- manage debug signals
-------------------------
rx_debug_out <= (others => '0');
-------------------------------------------------------------------------------
end architecture rx_module_arch;
src_utils_pkg.vhd 0000664 0000000 0000000 00000010243 14574545710 0034353 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Utilities package
-- Project :
--------------------------------------------------------------------------------
-- File : src_utils_pkg.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 02.06.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- utilities to foster source code programming
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package src_utils_pkg is
constant TYPE_IS_MEMORY : std_logic_vector(4 downto 0) := "00000";
constant TYPE_IS_IO : std_logic_vector(4 downto 0) := "00010";
constant TYPE_IS_CPL : std_logic_vector(4 downto 0) := "01010";
constant FMT_IS_READ : std_logic_vector(2 downto 0) := "000";
constant FMT_IS_WRITE : std_logic_vector(2 downto 0) := "010";
constant ZERO_02B : std_logic_vector(1 downto 0) := "00";
constant ZERO_03B : std_logic_vector(2 downto 0) := "000";
constant ZERO_04B : std_logic_vector(3 downto 0) := x"0";
constant ZERO_10B : std_logic_vector(9 downto 0) := "0000000000";
constant ZERO_11B : std_logic_vector(10 downto 0) := "00000000000";
constant ZERO_12B : std_logic_vector(11 downto 0) := x"000";
constant ZERO_20B : std_logic_vector(19 downto 0) := x"00000";
constant ONE_02B : std_logic_vector(1 downto 0) := "01";
constant ONE_03B : std_logic_vector(2 downto 0) := "001";
constant ONE_04B : std_logic_vector(3 downto 0) := x"1";
constant ONE_05B : std_logic_vector(4 downto 0) := "00001";
constant ONE_10B : std_logic_vector(9 downto 0) := "0000000001";
constant ONE_11B : std_logic_vector(10 downto 0) := "00000000001";
constant ONE_12B : std_logic_vector(11 downto 0) := x"001";
constant TWO_02B : std_logic_vector(1 downto 0) := "10";
constant TWO_03B : std_logic_vector(2 downto 0) := "010";
constant TWO_04B : std_logic_vector(3 downto 0) := x"2";
constant TWO_10B : std_logic_vector(9 downto 0) := "0000000010";
constant TWO_11B : std_logic_vector(10 downto 0) := "00000000010";
constant TWO_12B : std_logic_vector(11 downto 0) := x"002";
constant THREE_02B : std_logic_vector(1 downto 0) := "11";
constant THREE_03B : std_logic_vector(2 downto 0) := "011";
constant THREE_04B : std_logic_vector(3 downto 0) := x"3";
constant THREE_10B : std_logic_vector(9 downto 0) := "0000000011";
constant THREE_12B : std_logic_vector(11 downto 0) := x"003";
constant FOUR_03B : std_logic_vector(2 downto 0) := "100";
constant FOUR_04B : std_logic_vector(3 downto 0) := x"4";
constant FOUR_12B : std_logic_vector(11 downto 0) := x"004";
constant FOUR_32B : std_logic_vector(31 downto 0) := x"00000004";
constant FIVE_12B : std_logic_vector(11 downto 0) := x"005";
constant SIX_04B : std_logic_vector(3 downto 0) := x"6";
constant SIX_12B : std_logic_vector(11 downto 0) := x"006";
constant EIGHT_04B : std_logic_vector(3 downto 0) := x"8";
constant EIGHT_32B : std_logic_vector(31 downto 0) := x"00000008";
constant C_04B : std_logic_vector(3 downto 0) := x"C";
constant FULL_03B : std_logic_vector(2 downto 0) := "111";
constant FULL_10B : std_logic_vector(9 downto 0) := "1111111111";
constant X_400_11B : std_logic_vector(10 downto 0) := "10000000000";
end src_utils_pkg;
tx_compl_timeout.vhd 0000664 0000000 0000000 00000065041 14574545710 0035104 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : tx_compl_timeout
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_compl_timeout.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 07.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- this module controls the tag ID timeout timer, the maximum number of tags
-- is limited to 32
-- at present counters are only started for read requests and reset when the
-- appropriate completion is received
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- * tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx_compl_timeout is
generic(
CLOCK_TIME : time := 8 ns; -- clock cycle time
TIMEOUT_TIME : integer := 25 -- timeout for one tag ID
);
port(
clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
-- tx_ctrl
tag_nbr_in : in std_logic_vector(4 downto 0);
start : in std_logic;
-- Rx Module
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- error
timeout : out std_logic
);
end entity tx_compl_timeout;
-- ****************************************************************************
architecture tx_compl_timeout_arch of tx_compl_timeout is
-- internal signals -----------------------------------------------------------
signal clk_500_q : std_logic;
signal clk_500_qq : std_logic;
signal clk_500_qqq : std_logic;
signal rise : std_logic;
signal timer_overview : std_logic_vector(31 downto 0);
-- initial values assigned due to Quartus II Synthesis critical warning
signal timer_0 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_1 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_2 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_3 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_4 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_5 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_6 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_7 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_8 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_9 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_10 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_11 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_12 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_13 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_14 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_15 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_16 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_17 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_18 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_19 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_20 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_21 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_22 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_23 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_24 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_25 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_26 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_27 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_28 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_29 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_30 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timer_31 : integer range 25 downto 0 := TIMEOUT_TIME;
signal timeout_int : std_logic;
-------------------------------------------------------------------------------
begin
-- sample clock that processes 50ms timeout counting
clk_500_q <= '0' when rst = '1' else
clk_500 when rising_edge(clk);
clk_500_qq <= '0' when rst = '1' else
clk_500_q when rising_edge(clk);
clk_500_qqq <= '0' when rst = '1' else
clk_500_qq when rising_edge(clk);
-------------------------------------------------------------------------------
count : process(clk, rst)
begin
if(rst = '1') then
-- ports:
timeout <= '0';
-- signals:
timer_overview <= (others => '0');
timer_0 <= TIMEOUT_TIME;
timer_1 <= TIMEOUT_TIME;
timer_2 <= TIMEOUT_TIME;
timer_3 <= TIMEOUT_TIME;
timer_4 <= TIMEOUT_TIME;
timer_5 <= TIMEOUT_TIME;
timer_6 <= TIMEOUT_TIME;
timer_7 <= TIMEOUT_TIME;
timer_8 <= TIMEOUT_TIME;
timer_9 <= TIMEOUT_TIME;
timer_10 <= TIMEOUT_TIME;
timer_11 <= TIMEOUT_TIME;
timer_12 <= TIMEOUT_TIME;
timer_13 <= TIMEOUT_TIME;
timer_14 <= TIMEOUT_TIME;
timer_15 <= TIMEOUT_TIME;
timer_16 <= TIMEOUT_TIME;
timer_17 <= TIMEOUT_TIME;
timer_18 <= TIMEOUT_TIME;
timer_19 <= TIMEOUT_TIME;
timer_20 <= TIMEOUT_TIME;
timer_21 <= TIMEOUT_TIME;
timer_22 <= TIMEOUT_TIME;
timer_23 <= TIMEOUT_TIME;
timer_24 <= TIMEOUT_TIME;
timer_25 <= TIMEOUT_TIME;
timer_26 <= TIMEOUT_TIME;
timer_27 <= TIMEOUT_TIME;
timer_28 <= TIMEOUT_TIME;
timer_29 <= TIMEOUT_TIME;
timer_30 <= TIMEOUT_TIME;
timer_31 <= TIMEOUT_TIME;
timeout_int <= '0';
rise <= '0';
elsif(clk'event and clk = '1') then
-- when rising edge on clk_500 then enable counting
if(clk_500_qq = '1' and clk_500_qqq = '0') then
rise <= '1';
else
rise <= '0';
end if;
-- state of counters (running or not) is administered using the internal register timer_overview
-- if a timer (diplayed by tag_nbr_in) is started, set equivalent bit in register
if(start = '1') then -- start timers
case tag_nbr_in is
when "00000" =>
timer_overview(0) <= '1';
when "00001" =>
timer_overview(1) <= '1';
when "00010" =>
timer_overview(2) <= '1';
when "00011" =>
timer_overview(3) <= '1';
when "00100" =>
timer_overview(4) <= '1';
when "00101" =>
timer_overview(5) <= '1';
when "00110" =>
timer_overview(6) <= '1';
when "00111" =>
timer_overview(7) <= '1';
when "01000" =>
timer_overview(8) <= '1';
when "01001" =>
timer_overview(9) <= '1';
when "01010" =>
timer_overview(10) <= '1';
when "01011" =>
timer_overview(11) <= '1';
when "01100" =>
timer_overview(12) <= '1';
when "01101" =>
timer_overview(13) <= '1';
when "01110" =>
timer_overview(14) <= '1';
when "01111" =>
timer_overview(15) <= '1';
when "10000" =>
timer_overview(16) <= '1';
when "10001" =>
timer_overview(17) <= '1';
when "10010" =>
timer_overview(18) <= '1';
when "10011" =>
timer_overview(19) <= '1';
when "10100" =>
timer_overview(20) <= '1';
when "10101" =>
timer_overview(21) <= '1';
when "10110" =>
timer_overview(22) <= '1';
when "10111" =>
timer_overview(23) <= '1';
when "11000" =>
timer_overview(24) <= '1';
when "11001" =>
timer_overview(25) <= '1';
when "11010" =>
timer_overview(26) <= '1';
when "11011" =>
timer_overview(27) <= '1';
when "11100" =>
timer_overview(28) <= '1';
when "11101" =>
timer_overview(29) <= '1';
when "11110" =>
timer_overview(30) <= '1';
when "11111" =>
timer_overview(31) <= '1';
-- coverage off
when others =>
-- synthesis translate_off
report "undecoded case in tag_nbr_in" severity error;
-- synthesis translate_on
-- coverage on
end case;
end if;
-- if a tag number is received from rx_module reset according bit in timer_overview register and thus deactivate
-- the timer
if(rx_tag_rcvd = '1') then -- clear timers
case rx_tag_nbr(4 downto 0) is
when "00000" =>
timer_overview(0) <= '0';
when "00001" =>
timer_overview(1) <= '0';
when "00010" =>
timer_overview(2) <= '0';
when "00011" =>
timer_overview(3) <= '0';
when "00100" =>
timer_overview(4) <= '0';
when "00101" =>
timer_overview(5) <= '0';
when "00110" =>
timer_overview(6) <= '0';
when "00111" =>
timer_overview(7) <= '0';
when "01000" =>
timer_overview(8) <= '0';
when "01001" =>
timer_overview(9) <= '0';
when "01010" =>
timer_overview(10) <= '0';
when "01011" =>
timer_overview(11) <= '0';
when "01100" =>
timer_overview(12) <= '0';
when "01101" =>
timer_overview(13) <= '0';
when "01110" =>
timer_overview(14) <= '0';
when "01111" =>
timer_overview(15) <= '0';
when "10000" =>
timer_overview(16) <= '0';
when "10001" =>
timer_overview(17) <= '0';
when "10010" =>
timer_overview(18) <= '0';
when "10011" =>
timer_overview(19) <= '0';
when "10100" =>
timer_overview(20) <= '0';
when "10101" =>
timer_overview(21) <= '0';
when "10110" =>
timer_overview(22) <= '0';
when "10111" =>
timer_overview(23) <= '0';
when "11000" =>
timer_overview(24) <= '0';
when "11001" =>
timer_overview(25) <= '0';
when "11010" =>
timer_overview(26) <= '0';
when "11011" =>
timer_overview(27) <= '0';
when "11100" =>
timer_overview(28) <= '0';
when "11101" =>
timer_overview(29) <= '0';
when "11110" =>
timer_overview(30) <= '0';
when "11111" =>
timer_overview(31) <= '0';
-- coverage off
when others =>
-- synthesis translate_off
report "undecoded case in rx_tag_nbr" severity warning;
-- synthesis translate_on
-- coverage on
end case;
end if;
-- if a timer is set and signal rise is asserted to propagate that enough time has passed
-- then decrement all active counters
-- if a counter has reached 0 assert signal timeout and reset timer_overview register
if(timer_overview(0) = '1' and rise = '1') then
if(timer_0 > 0) then
timer_0 <= timer_0 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(0) <= '0';
end if;
elsif(timer_overview(0) = '0') then
timer_0 <= TIMEOUT_TIME;
end if;
if(timer_overview(1) = '1' and rise = '1') then
if(timer_1 > 0) then
timer_1 <= timer_1 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(1) <= '0';
end if;
elsif(timer_overview(1) = '0') then
timer_1 <= TIMEOUT_TIME;
end if;
if(timer_overview(2) = '1' and rise = '1') then
if(timer_2 > 0) then
timer_2 <= timer_2 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(2) <= '0';
end if;
elsif(timer_overview(2) = '0') then
timer_2 <= TIMEOUT_TIME;
end if;
if(timer_overview(3) = '1' and rise = '1') then
if(timer_3 > 0) then
timer_3 <= timer_3 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(3) <= '0';
end if;
elsif(timer_overview(3) = '0') then
timer_3 <= TIMEOUT_TIME;
end if;
if(timer_overview(4) = '1' and rise = '1') then
if(timer_4 > 0) then
timer_4 <= timer_4 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(4) <= '0';
end if;
elsif(timer_overview(4) = '0') then
timer_4 <= TIMEOUT_TIME;
end if;
if(timer_overview(5) = '1' and rise = '1') then
if(timer_5 > 0) then
timer_5 <= timer_5 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(5) <= '0';
end if;
elsif(timer_overview(5) = '0') then
timer_5 <= TIMEOUT_TIME;
end if;
if(timer_overview(6) = '1' and rise = '1') then
if(timer_6 > 0) then
timer_6 <= timer_6 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(6) <= '0';
end if;
elsif(timer_overview(6) = '0') then
timer_6 <= TIMEOUT_TIME;
end if;
if(timer_overview(7) = '1' and rise = '1') then
if(timer_7 > 0) then
timer_7 <= timer_7 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(7) <= '0';
end if;
elsif(timer_overview(7) = '0') then
timer_7 <= TIMEOUT_TIME;
end if;
if(timer_overview(8) = '1' and rise = '1') then
if(timer_8 > 0) then
timer_8 <= timer_8 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(8) <= '0';
end if;
elsif(timer_overview(8) = '0') then
timer_8 <= TIMEOUT_TIME;
end if;
if(timer_overview(9) = '1' and rise = '1') then
if(timer_9 > 0) then
timer_9 <= timer_9 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(9) <= '0';
end if;
elsif(timer_overview(9) = '0') then
timer_9 <= TIMEOUT_TIME;
end if;
if(timer_overview(10) = '1' and rise = '1') then
if(timer_10 > 0) then
timer_10 <= timer_10 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(10) <= '0';
end if;
elsif(timer_overview(10) = '0') then
timer_10 <= TIMEOUT_TIME;
end if;
if(timer_overview(11) = '1' and rise = '1') then
if(timer_11 > 0) then
timer_11 <= timer_11 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(11) <= '0';
end if;
elsif(timer_overview(11) = '0') then
timer_11 <= TIMEOUT_TIME;
end if;
if(timer_overview(12) = '1' and rise = '1') then
if(timer_12 > 0) then
timer_12 <= timer_12 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(12) <= '0';
end if;
elsif(timer_overview(12) = '0') then
timer_12 <= TIMEOUT_TIME;
end if;
if(timer_overview(13) = '1' and rise = '1') then
if(timer_13 > 0) then
timer_13 <= timer_13 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(13) <= '0';
end if;
elsif(timer_overview(13) = '0') then
timer_13 <= TIMEOUT_TIME;
end if;
if(timer_overview(14) = '1' and rise = '1') then
if(timer_14 > 0) then
timer_14 <= timer_14 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(14) <= '0';
end if;
elsif(timer_overview(14) = '0') then
timer_14 <= TIMEOUT_TIME;
end if;
if(timer_overview(15) = '1' and rise = '1') then
if(timer_15 > 0) then
timer_15 <= timer_15 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(15) <= '0';
end if;
elsif(timer_overview(15) = '0') then
timer_15 <= TIMEOUT_TIME;
end if;
if(timer_overview(16) = '1' and rise = '1') then
if(timer_16 > 0) then
timer_16 <= timer_16 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(16) <= '0';
end if;
elsif(timer_overview(16) = '0') then
timer_16 <= TIMEOUT_TIME;
end if;
if(timer_overview(17) = '1' and rise = '1') then
if(timer_17 > 0) then
timer_17 <= timer_17 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(17) <= '0';
end if;
elsif(timer_overview(17) = '0') then
timer_17 <= TIMEOUT_TIME;
end if;
if(timer_overview(18) = '1' and rise = '1') then
if(timer_18 > 0) then
timer_18 <= timer_18 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(18) <= '0';
end if;
elsif(timer_overview(18) = '0') then
timer_18 <= TIMEOUT_TIME;
end if;
if(timer_overview(19) = '1' and rise = '1') then
if(timer_19 > 0) then
timer_19 <= timer_19 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(19) <= '0';
end if;
elsif(timer_overview(19) = '0') then
timer_19 <= TIMEOUT_TIME;
end if;
if(timer_overview(20) = '1' and rise = '1') then
if(timer_20 > 0) then
timer_20 <= timer_20 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(20) <= '0';
end if;
elsif(timer_overview(20) = '0') then
timer_20 <= TIMEOUT_TIME;
end if;
if(timer_overview(21) = '1' and rise = '1') then
if(timer_21 > 0) then
timer_21 <= timer_21 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(21) <= '0';
end if;
elsif(timer_overview(21) = '0') then
timer_21 <= TIMEOUT_TIME;
end if;
if(timer_overview(22) = '1' and rise = '1') then
if(timer_22 > 0) then
timer_22 <= timer_22 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(22) <= '0';
end if;
elsif(timer_overview(22) = '0') then
timer_22 <= TIMEOUT_TIME;
end if;
if(timer_overview(23) = '1' and rise = '1') then
if(timer_23 > 0) then
timer_23 <= timer_23 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(23) <= '0';
end if;
elsif(timer_overview(23) = '0') then
timer_23 <= TIMEOUT_TIME;
end if;
if(timer_overview(24) = '1' and rise = '1') then
if(timer_24 > 0) then
timer_24 <= timer_24 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(24) <= '0';
end if;
elsif(timer_overview(24) = '0') then
timer_24 <= TIMEOUT_TIME;
end if;
if(timer_overview(25) = '1' and rise = '1') then
if(timer_25 > 0) then
timer_25 <= timer_25 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(25) <= '0';
end if;
elsif(timer_overview(25) = '0') then
timer_25 <= TIMEOUT_TIME;
end if;
if(timer_overview(26) = '1' and rise = '1') then
if(timer_26 > 0) then
timer_26 <= timer_26 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(26) <= '0';
end if;
elsif(timer_overview(26) = '0') then
timer_26 <= TIMEOUT_TIME;
end if;
if(timer_overview(27) = '1' and rise = '1') then
if(timer_27 > 0) then
timer_27 <= timer_27 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(27) <= '0';
end if;
elsif(timer_overview(27) = '0') then
timer_27 <= TIMEOUT_TIME;
end if;
if(timer_overview(28) = '1' and rise = '1') then
if(timer_28 > 0) then
timer_28 <= timer_28 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(28) <= '0';
end if;
elsif(timer_overview(28) = '0') then
timer_28 <= TIMEOUT_TIME;
end if;
if(timer_overview(29) = '1' and rise = '1') then
if(timer_29 > 0) then
timer_29 <= timer_29 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(29) <= '0';
end if;
elsif(timer_overview(29) = '0') then
timer_29 <= TIMEOUT_TIME;
end if;
if(timer_overview(30) = '1' and rise = '1') then
if(timer_30 > 0) then
timer_30 <= timer_30 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(30) <= '0';
end if;
elsif(timer_overview(30) = '0') then
timer_30 <= TIMEOUT_TIME;
end if;
if(timer_overview(31) = '1' and rise = '1') then
if(timer_31 > 0) then
timer_31 <= timer_31 - 1;
else
timeout <= '1';
timeout_int <= '1';
timer_overview(31) <= '0';
end if;
elsif(timer_overview(31) = '0') then
timer_31 <= TIMEOUT_TIME;
end if;
if(timeout_int = '1') then
timeout <= '0';
timeout_int <= '0';
end if;
end if;
end process count;
-------------------------------------------------------------------------------
end architecture tx_compl_timeout_arch;
tx_ctrl.vhd 0000664 0000000 0000000 00000112060 14574545710 0033162 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : tx_ctrl
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 09.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- this module controls all actions within the TxModule, including power
-- messages and information given by the init module
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- * tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.src_utils_pkg.all;
entity tx_ctrl is
port(
clk : in std_logic;
rst : in std_logic;
-- IP core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
pme_to_cr : out std_logic;
-- FIFO
tx_c_head_empty : in std_logic;
tx_wr_head_empty : in std_logic;
tx_c_data_empty : in std_logic;
tx_wr_data_empty : in std_logic;
tx_c_head_enable : out std_logic;
tx_wr_head_enable : out std_logic;
tx_c_data_enable : out std_logic;
tx_wr_data_enable : out std_logic;
-- tx_put_data
aligned : in std_logic;
data_len : in std_logic_vector(9 downto 0);
wr_rd : in std_logic; -- 0: write, 1: read
posted : in std_logic; -- 0: non-posted, 1: posted
byte_count : in std_logic_vector(11 downto 0);
io_write : in std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : in std_logic_vector(31 downto 0);
tx_tag_nbr : out std_logic_vector(7 downto 0);
get_header : out std_logic;
get_next_header : out std_logic;
make_header : out std_logic;
data_enable : out std_logic;
c_wrrd : out std_logic; -- =0: completion, =1: write or read
completer_id : out std_logic_vector(15 downto 0);
own_id : out std_logic_vector(15 downto 0);
abort_compl : out std_logic;
send_len : out std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : out std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : out std_logic; -- =0: no loop, =1: loop
first_last_full : out std_logic_vector(1 downto 0); -- 00: unused, 01: first packet of payload_loop, 01: last
-- packet of payload_loop, 11: all enabled
-- tx_compl_timeout
start : out std_logic;
start_tag_nbr : out std_logic_vector(4 downto 0);
-- error
compl_abort : out std_logic;
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0)
);
end entity tx_ctrl;
-- ****************************************************************************
architecture tx_ctrl_arch of tx_ctrl is
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
PREP_HEADER, IDLE, PREP_TRANS, START_TRANS, TRANSMIT, PME_OFF, TAG_START, ABORT, IO_WR
);
signal state : fsm_state;
-------------------------------------------------------------------------------
-- constants ------------------------------------------------------------------
constant ADDR_INCR : std_logic_vector(31 downto 0) := x"00000008";
-------------------------------------------------------------------------------
-- internal signals -----------------------------------------------------------
signal data_from_fifo : std_logic_vector(10 downto 0);
signal desired_len : std_logic_vector(10 downto 0);
signal data_to_ava : std_logic_vector(11 downto 0);
signal ready_q : std_logic;
signal wait_clk : integer range 3 downto 0 := 0;
signal pme_off_int : std_logic;
signal c_wr_int : std_logic;
signal tag_nbr_cntr : std_logic_vector(4 downto 0);
signal data_enable_int : std_logic;
signal fifo_enable_int : std_logic;
signal own_id_int : std_logic_vector(15 downto 0);
signal abort_compl_int : std_logic;
signal max_payload_len : std_logic_vector(9 downto 0);
signal payload_loop_en : std_logic;
signal addr_int : std_logic_vector(31 downto 0);
signal addr_offset : std_logic_vector(31 downto 0);
signal eop_int : std_logic;
signal get_last_packet : std_logic;
signal tx_st_valid0_int : std_logic;
signal send_len_int : std_logic_vector(9 downto 0);
signal arbit_access : std_logic_vector(1 downto 0); -- 00: invalid, 01: cpl, 10: wr/rd
-------------------------------------------------------------------------------
begin
-- unused signal, set to zero
tx_st_err0 <= '0';
-- decode max_payload
with max_payload select
max_payload_len <= "0001000000" when "001",
"0010000000" when "010",
"0100000000" when "011",
"1000000000" when "100",
"0000000000" when "101",
"0000100000" when others;
data_enable <= data_enable_int;
c_wrrd <= c_wr_int;
abort_compl <= abort_compl_int;
tx_st_valid0 <= tx_st_valid0_int;
send_len <= send_len_int;
-------------------------------------------------------------------------------
fsm_trans : process(rst, clk)
begin
if(rst = '1') then
state <= IDLE;
elsif(clk'event and clk = '1') then
case state is
when IDLE =>
if(arbit_access /= "00") then
state <= PREP_TRANS;
elsif(pme_off_int = '1') then
state <= PME_OFF;
else
state <= IDLE;
end if;
when PREP_HEADER =>
if(wait_clk = 3) then
state <= START_TRANS;
else
state <= PREP_HEADER;
end if;
when PREP_TRANS =>
if(wait_clk = 1 and c_wr_int = '1') then
state <= PREP_HEADER;
elsif(wait_clk = 2 and c_wr_int = '0') then
state <= PREP_HEADER;
else
state <= PREP_TRANS;
end if;
when START_TRANS =>
if(ready_q = '1') then
state <= TRANSMIT;
else
state <= START_TRANS;
end if;
when TRANSMIT =>
if(io_write = '1') then
state <= IO_WR;
elsif(data_to_ava <= TWO_12B and c_wr_int = '1' and wr_rd = '1') then
state <= TAG_START;
elsif(data_to_ava <= TWO_12B and c_wr_int = '0' and abort_compl_int = '1') then
state <= ABORT;
-- no loop on completion as read requests with length > max_payload_len are rejected
-- if looped write is finished (payload_loop_en = 0) go to IDLE as well
elsif(ready_q = '1' and
(c_wr_int = '0' or (c_wr_int = '1' and wr_rd = '0' and payload_loop_en = '0')) and
((data_to_ava <= TWO_12B and ((aligned = '1' and send_len_int(0) = '0') or (aligned = '0' and send_len_int(0) = '1'))) or
(data_to_ava <= ONE_12B and ((aligned = '1' and send_len_int(0) = '1') or (aligned = '0' and send_len_int(0) = '0')))) ) then
state <= IDLE;
elsif(data_to_ava <= TWO_12B and c_wr_int = '1' and wr_rd = '0' and payload_loop_en = '1' and tx_st_valid0_int = '1') then
state <= PREP_HEADER;
else
state <= TRANSMIT;
end if;
when PME_OFF =>
state <= IDLE;
when TAG_START =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
elsif(payload_loop_en = '1') then
state <= PREP_HEADER;
else
state <= IDLE;
end if;
when ABORT =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
elsif(data_from_fifo <= TWO_11B) then
state <= IDLE;
else
state <= ABORT;
end if;
when IO_WR =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
else
state <= IDLE;
end if;
-- coverage off
when others =>
-- synthesis translate_off
report "undecoded state in ctrl_fsm" severity error;
-- synthesis translate_on
-- coverage on
end case;
end if;
end process fsm_trans;
-------------------------------------------------------------------------------
fsm_out : process(rst, clk)
begin
if(rst = '1') then
tx_st_valid0_int <= '0';
tx_st_sop0 <= '0';
tx_st_eop0 <= '0';
pme_to_cr <= '0';
tx_c_head_enable <= '0';
tx_wr_head_enable <= '0';
tx_c_data_enable <= '0';
tx_wr_data_enable <= '0';
tx_tag_nbr <= (others => '0');
get_header <= '0';
get_next_header <= '0';
make_header <= '0';
data_enable_int <= '0';
c_wr_int <= '0';
completer_id <= (others => '0');
own_id <= (others => '0');
abort_compl_int <= '0';
send_len_int <= (others => '0');
send_addr <= (others => '0');
payload_loop <= '0';
first_last_full <= (others => '0');
start <= '0';
start_tag_nbr <= (others => '0');
compl_abort <= '0';
data_from_fifo <= (others => '0');
desired_len <= (others => '0');
data_to_ava <= (others => '0');
ready_q <= '0';
wait_clk <= 0;
pme_off_int <= '0';
tag_nbr_cntr <= (others => '0');
fifo_enable_int <= '0';
own_id_int <= (others => '0');
payload_loop_en <= '0';
addr_int <= (others => '0');
addr_offset <= (others => '0');
eop_int <= '0';
get_last_packet <= '0';
arbit_access <= (others => '0');
elsif(clk'event and clk = '1') then
if(state = IDLE and tx_c_head_empty = '0') then
arbit_access <= "01";
elsif(state = IDLE and tx_wr_head_empty = '0') then
arbit_access <= "10";
elsif(state /= IDLE) then
arbit_access <= (others => '0');
end if;
if(state = TRANSMIT and tx_st_ready0 = '0' and data_from_fifo <= FOUR_12B and data_from_fifo > ZERO_12B and get_last_packet = '0') then
get_last_packet <= '1';
elsif(state = IDLE or (state = TRANSMIT and tx_st_ready0 = '1' and get_last_packet = '1')) then
get_last_packet <= '0';
end if;
if(state = TRANSMIT and data_to_ava >= THREE_12B and ready_q = '0') then
eop_int <= '1';
elsif(state = IDLE or state = PREP_HEADER or state = ABORT or state = TAG_START or state = IO_WR
or (state = TRANSMIT and tx_st_ready0 = '1' and ready_q = '1')
) then
eop_int <= '0';
end if;
-- release transfer when there is no more data to send
if(state = IDLE or state = PREP_HEADER or state = ABORT or state = IO_WR or state = TAG_START or
(state = TRANSMIT and ((data_to_ava <= TWO_12B and eop_int = '0') or ready_q = '0')) or
(state = START_TRANS and ready_q = '0')) then
tx_st_valid0_int <= '0';
-- assert tx_st_valid0 after correct ReadyLatency, in this case ReadyLatency = 2
elsif((state = START_TRANS and ready_q = '1') or (state = TRANSMIT and ready_q = '1')
) then
tx_st_valid0_int <= '1';
end if;
-- assert tx_st_sop0 after correct ReadyLatency, in this case ReadyLatency = 2
if(state = START_TRANS and ready_q = '1') then
tx_st_sop0 <= '1';
elsif((state = START_TRANS and ready_q = '0') or state = TRANSMIT) then
tx_st_sop0 <= '0';
end if;
if(state = IDLE or state = PREP_HEADER or state = TAG_START or state = ABORT or state = IO_WR or (state = TRANSMIT and
(data_to_ava > FOUR_12B or (data_to_ava <= TWO_12B and eop_int = '0')) and io_write = '0')) then
tx_st_eop0 <= '0';
-- set end of packet according to actual transfer length
elsif(state = TRANSMIT and ready_q = '1' and ((wr_rd = '1' and data_to_ava = THREE_12B) or
(data_to_ava = FOUR_12B and eop_int = '0' and ((aligned = '1' and send_len_int(0) = '0') or (aligned = '0' and send_len_int(0) = '1'))) or
(data_to_ava = THREE_12B and eop_int = '0' and ((aligned = '1' and send_len_int(0) = '1') or (aligned = '0' and send_len_int(0) = '0'))) or
io_write = '1' or (eop_int = '1' and data_to_ava <= TWO_12B) or (abort_compl_int = '1' and data_to_ava <= FOUR_12B))) then
tx_st_eop0 <= '1';
end if;
-- enable FIFO for corresponding type of transaction chosen before
if((state = IDLE and tx_c_head_empty = '0' and arbit_access = "01") or (state = PREP_TRANS and wait_clk = 1 and tx_c_head_empty = '0' and c_wr_int = '0')) then
tx_c_head_enable <= '1';
elsif(state = PREP_TRANS and (wait_clk /= 1 or tx_c_head_empty = '1' or c_wr_int = '1')) then
tx_c_head_enable <= '0';
end if;
-- enable FIFO for corresponding type of transaction chosen before
if(state = IDLE and tx_wr_head_empty = '0' and arbit_access = "10") then
tx_wr_head_enable <= '1';
-- enable correct header FIFO
elsif(state = PREP_TRANS and (wait_clk /= 1 or tx_c_head_empty = '1' or c_wr_int = '1')) then
tx_wr_head_enable <= '0';
end if;
-- enable appropriate FIFO
if((state = PREP_HEADER and wait_clk = 0 and c_wr_int = '0' and abort_compl_int = '0') or
(state = START_TRANS and tx_st_ready0 = '1' and c_wr_int = '0' and data_from_fifo > ZERO_11B and abort_compl_int = '0') or
(state = ABORT and data_from_fifo > TWO_11B) or
(state = TRANSMIT and tx_st_ready0 = '1' and c_wr_int = '0' and ((data_from_fifo > TWO_11B and data_to_ava > THREE_12B) or (get_last_packet = '1' and data_from_fifo > ZERO_12B)))
) then
tx_c_data_enable <= '1';
elsif((state = PREP_HEADER and wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or
(state = START_TRANS and c_wr_int = '0' and ((tx_st_ready0 = '0' and data_from_fifo = ONE_11B) or
(ready_q = '1' and data_from_fifo <= ONE_11B))) or
(state = TRANSMIT and ((data_from_fifo <= TWO_11B and c_wr_int = '0') or (tx_st_ready0 = '0'))) or -- reset FIFO enable when hard IP
-- core isn't able to receive data
(state = ABORT and data_from_fifo <= TWO_11B) -- disble data retrieval from FIFO due to end of transmission
) then
tx_c_data_enable <= '0';
end if;
if((state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and tx_st_ready0 = '1' and c_wr_int = '1' and wr_rd = '0' and data_from_fifo > ZERO_11B and fifo_enable_int = '0') or
(state = TRANSMIT and tx_st_ready0 = '1' and c_wr_int = '1' and wr_rd = '0' and ((data_from_fifo > TWO_11B and data_to_ava > THREE_12B) or (get_last_packet = '1' and data_from_fifo > ZERO_12B)))
) then
tx_wr_data_enable <= '1';
elsif((state = PREP_HEADER and wait_clk = 2 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and c_wr_int = '1' and ((fifo_enable_int = '1' and ((send_len_int(0) = '1' and data_from_fifo = ONE_11B) or
(send_len_int(0) = '0' and data_from_fifo = TWO_11B))) or (tx_st_ready0 = '0' and data_from_fifo = ONE_11B))) or
(state = TRANSMIT and ((data_from_fifo <= TWO_11B and c_wr_int = '1') or (tx_st_ready0 = '0'))) -- reset FIFO enable when hard IP
-- core isn't able to receive data
) then
tx_wr_data_enable <= '0';
end if;
-- calculate tag ID
if(state = PREP_HEADER and c_wr_int = '1' and (wr_rd = '1' or (wr_rd = '0' and posted = '0'))) then
tx_tag_nbr <= "000" & tag_nbr_cntr;
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and posted = '1') then
tx_tag_nbr <= "00100000";
end if;
-- tell tx_put_data module to process header information
if(state = PREP_TRANS and wait_clk = 0) then
get_header <= '1';
elsif(state = PREP_HEADER or (state = PREP_TRANS and wait_clk = 1)) then
get_header <= '0';
end if;
-- completion information is stored to the FIFO using more than one header packet, thus get next header too
if(state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0') then
get_next_header <= '1';
elsif(state = PREP_HEADER) then
get_next_header <= '0';
end if;
-- advise tx_put_data module to process header information and to route that onto Avalon ST data bus
if(state = PREP_HEADER and ((c_wr_int = '0' and wait_clk = 0) or (c_wr_int = '1' and wait_clk = 1))) then
make_header <= '1';
elsif(state = PREP_HEADER and ((c_wr_int = '0' and wait_clk = 1) or (c_wr_int = '1' and wait_clk = 2))) then
make_header <= '0';
end if;
if((state = IDLE or state = ABORT or (state = START_TRANS and ready_q = '0')) or
(state = TRANSMIT and (ready_q = '0' or data_to_ava <= ZERO_12B)) or
(state = PREP_HEADER and (wait_clk = 0 or (wait_clk = 2 and c_wr_int = '0') or (wait_clk = 3 and c_wr_int = '1')))
) then
data_enable_int <= '0';
elsif((state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0') or (wait_clk = 2 and c_wr_int = '1'))) or
(state = START_TRANS and ready_q = '1') or -- enable data processing when hard IP is ready to process data
(state = TRANSMIT and ready_q = '1' and data_to_ava > ZERO_12B) -- enable data processing as long as the data length counter isn't 0
) then
data_enable_int <= '1';
end if;
-- start transaction with priority on completions, don't change in any other state except IDLE
if(state = IDLE and arbit_access = "01") then
c_wr_int <= '0';
elsif(state = IDLE and arbit_access = "10") then
c_wr_int <= '1';
end if;
-- give actual own bus/dev/func number (=own_id_int) to tx_put_data module either for completion transmission
if(state = PREP_TRANS and c_wr_int = '0') then
completer_id <= own_id_int;
end if;
-- give actual own bus/dev/func number (=own_id_int) to tx_put_data module either for write/read transmission
if(state = PREP_TRANS and c_wr_int = '1') then
own_id <= own_id_int;
end if;
if(state = IDLE or state = ABORT) then
abort_compl_int <= '0';
-- if byte_count is greater than allowed (greater than max_payload) reject transmission, send completion without data
-- with completer abort status and signal error to error module which will signal error to hard IP by asserting cpl_err(2)
-- for 1 clock cycle
elsif(state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and tx_c_head_empty = '0' and ((data_len = ZERO_10B and
max_payload_len /= ZERO_10B) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
abort_compl_int <= '1';
end if;
if(state = IDLE) then
send_len_int <= (others => '0');
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0') or (state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and
wr_rd = '1')) then
send_len_int <= data_len;
-- store transmission length
elsif(state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and wr_rd = '0') then
send_len_int <= data_from_fifo(9 downto 0);
end if;
if(state = IDLE) then
send_addr <= (others => '0');
-- show right address to tx_put_data module
elsif(state = PREP_HEADER and wait_clk = 1) then
send_addr <= addr_int;
end if;
if(state = IDLE) then
payload_loop <= '0';
-- if packet length is greater than allowed payload size, set payload_loop_en = 1 and do internal loop until desired
-- packet length is sent using multiple TLPs; don't forget to adapt packet address after each loop
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
payload_loop <= '1';
end if;
if(state = IDLE) then
first_last_full <= (others => '0');
-- advise tx_put_data module how to process first/last byte enables
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
first_last_full <= "01";
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and wait_clk = 1 and desired_len <= data_from_fifo) then
first_last_full <= "10";
elsif(state = START_TRANS) then
first_last_full <= "11";
end if;
if(state = IDLE or state = ABORT) then
compl_abort <= '0';
-- assert completion abort indicator
elsif(state = TRANSMIT and data_to_ava <= TWO_12B and c_wr_int = '0' and abort_compl_int = '1') then
compl_abort <= '1';
end if;
-- calculate length counter for data that has to be taken from appropriate FIFO
if((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and data_len = ZERO_10B) or
(state = PREP_HEADER and wait_clk = 0 and data_len = ZERO_10B and ((desired_len /= ZERO_11B and c_wr_int = '0') or (desired_len = ZERO_11B and
(c_wr_int = '0' or (c_wr_int = '1' and data_len = max_payload_len)))))
) then
data_from_fifo <= '1' & data_len;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and data_len > ZERO_10B) or
(state = PREP_HEADER and wait_clk = 0 and data_len /= ZERO_10B and ((desired_len /= ZERO_11B and c_wr_int = '0') or (desired_len = ZERO_11B
and (c_wr_int = '0' or (c_wr_int = '1' and (max_payload_len = ZERO_10B or data_len <= max_payload_len))))))
) then
data_from_fifo <= '0' & data_len;
elsif(state = PREP_HEADER and wait_clk = 0 and c_wr_int = '1' and ((desired_len = ZERO_11B and ((data_len = ZERO_10B and data_len /= max_payload_len) or
(data_len /= ZERO_10B and data_len > max_payload_len))) or (desired_len /= ZERO_11B and ((desired_len = X_400_11B and
desired_len(9 downto 0) /= max_payload_len) or (desired_len < X_400_11B and desired_len(9 downto 0) > max_payload_len))))
)then
data_from_fifo <= '0' & max_payload_len;
elsif(state = PREP_HEADER and desired_len /= ZERO_11B and wait_clk = 0 and c_wr_int = '1' and desired_len = X_400_11B and desired_len(9 downto 0) = max_payload_len) then
data_from_fifo <= desired_len;
elsif(state = PREP_HEADER and desired_len /= ZERO_11B and wait_clk = 0 and c_wr_int = '1' and ((desired_len < X_400_11B and max_payload_len = ZERO_10B) or (desired_len < X_400_11B
and desired_len(9 downto 0) <= max_payload_len)))then
data_from_fifo <= '0' & desired_len(9 downto 0);
elsif((state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0' and data_from_fifo > ONE_11B) or
(wait_clk = 2 and c_wr_int = '1' and wr_rd = '0' and data_from_fifo > ONE_11B))) or
(fifo_enable_int = '1' and ((state = TRANSMIT and data_from_fifo > ONE_11B and abort_compl_int = '0') or (state = ABORT and abort_compl_int = '0') or (state = START_TRANS and data_from_fifo > ONE_11B)))
)then
data_from_fifo <= data_from_fifo - TWO_11B;
elsif((state = PREP_HEADER and data_from_fifo <= ONE_11B and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or
(wait_clk = 2 and c_wr_int = '1' and wr_rd = '0'))) or
(state = START_TRANS and fifo_enable_int = '1' and data_from_fifo = ONE_11B) or
(fifo_enable_int = '1' and state = TRANSMIT and data_from_fifo <= ONE_11B)
)then
data_from_fifo <= (others => '0');
end if;
-- as this is a loop, change desired_len only when entering this state for the very first time
-- on other entry times only subtract data_from_fifo value
-- new value for data_from_fifo is valid when wait_clk = 1
if(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and data_len = ZERO_10B) then
desired_len <= '1' & data_len;
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and data_len /= ZERO_10B) then
desired_len <= '0' & data_len;
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and wait_clk = 1 and desired_len >= data_from_fifo) then
desired_len <= desired_len - data_from_fifo;
elsif(state = PREP_HEADER and c_wr_int = '1' and (wr_rd = '1' or (wr_rd = '0' and wait_clk = 1 and desired_len < data_from_fifo))) then
desired_len <= (others => '0');
end if;
-- in actual design, completion data is returned using one completion only
-- reads that request more data than max_payload_size (max_read ignored by PCIe requester) are rejected thus use original data length here
-- check bit 2 for address alignment (=0: aligned, =1: not aligned) thus wait until addr_int is set (wait_clk = 1)
-- decrement length counters for amount of data taken from FIFO and amount of data sent to hard IP core
if((state = PREP_TRANS and wait_clk = 2 and ((c_wr_int = '0' and abort_compl_int = '1') or (c_wr_int = '1' and wr_rd = '1'))) or
(state = PREP_HEADER and ((c_wr_int = '1' and wait_clk = 1 and wr_rd = '1') or (abort_compl_int = '1' and wait_clk < 2)))) then
data_to_ava <= THREE_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '1' and data_len = ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '1' and data_len = ZERO_10B)) then
data_to_ava <= ("01" & data_len) + FOUR_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '0' and data_len = ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '0' and data_len = ZERO_10B)) then
data_to_ava <= ("01" & data_len) + THREE_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '1' and data_len /= ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '1' and data_len /= ZERO_10B)) then
data_to_ava <= ("00" & data_len) + FOUR_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '0' and data_len /= ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '0' and data_len /= ZERO_10B)) then
data_to_ava <= ("00" & data_len) + THREE_12B;
elsif(state = PREP_HEADER and c_wr_int = '1' and wait_clk = 1 and addr_int(2) = '0') then
data_to_ava <= ('0' & data_from_fifo) + FOUR_12B;
elsif(state = PREP_HEADER and c_wr_int = '1' and wait_clk = 1 and addr_int(2) = '1') then
data_to_ava <= ('0' & data_from_fifo) + THREE_12B;
elsif(state = TRANSMIT and data_to_ava > ONE_12B and tx_st_valid0_int = '1') then
data_to_ava <= data_to_ava - "10";
elsif((state = START_TRANS and data_enable_int = '1' and data_to_ava = 1) or (state = TRANSMIT and data_enable_int = '1' and data_to_ava <= ONE_12B)) then
data_to_ava <= (others => '0');
end if;
if(state = IDLE or state = PREP_HEADER or (tx_st_ready0 = '0' and (state = TRANSMIT or state = START_TRANS))) then
ready_q <= '0';
elsif(tx_st_ready0 = '1' and (state = TRANSMIT or state = START_TRANS)) then
ready_q <= '1';
end if;
-- use wait_clk to enable processing at the right point of time
if(state = IDLE or (state = PREP_TRANS and ((wait_clk = 2 and c_wr_int = '0') or (wait_clk = 1 and c_wr_int = '1'))) or
(state = PREP_HEADER and wait_clk = 3)) then
wait_clk <= 0;
elsif((state = PREP_TRANS and (c_wr_int = '1' or (c_wr_int = '0' and tx_c_head_empty = '0'))) or
(state = PREP_HEADER and wait_clk /= 3)) then
wait_clk <= wait_clk + 1;
end if;
-- if power off request occured, save it for later processing
if(pme_to_sr = '1' and (state = IDLE or state = PREP_TRANS or state = PREP_HEADER or state = START_TRANS or state = TRANSMIT
or state = TAG_START or state = ABORT)) then
pme_off_int <= '1';
elsif(state = PME_OFF or (state = IDLE and pme_to_sr = '0')) then
pme_off_int <= '0';
end if;
-- disable or enable data retrieval from FIFO
if(state = IDLE or
(state = ABORT and data_from_fifo <= 2) or
(state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or (wait_clk = 2 and c_wr_int = '1' and
wr_rd = '0'))) or
(state = START_TRANS and ((tx_st_ready0 = '0' and data_from_fifo = ONE_11B) or
(ready_q = '1' and c_wr_int = '0' and data_from_fifo <= 1) or
(c_wr_int = '1' and fifo_enable_int = '1' and ((data_len(0) = '1' and data_from_fifo = ONE_11B) or (data_len(0) = '0' and
data_from_fifo = TWO_11B))))) or
(state = TRANSMIT and (tx_st_ready0 = '0' or (data_from_fifo <= TWO_11B and get_last_packet = '0')))) then
fifo_enable_int <= '0';
elsif((state = START_TRANS and tx_st_ready0 = '1' and data_from_fifo > ZERO_11B and (c_wr_int = '1' or (c_wr_int = '0' and
abort_compl_int = '0'))) or (state = ABORT and data_from_fifo > TWO_11B) or
(state = PREP_HEADER and ((wait_clk = 0 and c_wr_int = '0' and abort_compl_int = '0') or (wait_clk = 1 and c_wr_int = '1' and
wr_rd = '0'))) or
(state = TRANSMIT and tx_st_ready0 = '1') ) then
fifo_enable_int <= '1';
end if;
-- if packet length is greater than allowed payload size, set payload_loop_en = 1 and do internal loop until desired
-- packet length is sent using multiple TLPs
-- don't forget to adapt packet address after each loop
if(state = IDLE or
(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and desired_len > 0 and wait_clk = 1 and desired_len <= data_from_fifo)) then
payload_loop_en <= '0';
elsif(state = PREP_HEADER and desired_len = 0 and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
payload_loop_en <= '1';
end if;
if(state = IDLE) then
addr_int <= (others => '0');
-- calculate internal address used if transaction must be split into more parts
elsif(state = PREP_HEADER and wait_clk = 0) then
addr_int <= orig_addr + addr_offset;
end if;
-- calculate address offset for internal address calculation
if(state = IDLE) then
addr_offset <= (others => '0');
elsif((state = PREP_HEADER and wait_clk = 2 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and fifo_enable_int = '1' and c_wr_int = '1') or
(state = TRANSMIT and fifo_enable_int = '1' and c_wr_int = '1' and data_from_fifo > ZERO_12B)) then
addr_offset <= addr_offset + ADDR_INCR;
end if;
case state is
when IDLE =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
own_id_int <= bus_dev_func;
when PREP_HEADER =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when PREP_TRANS =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when START_TRANS =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when TRANSMIT =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when PME_OFF =>
pme_to_cr <= '1';
start <= '0';
start_tag_nbr <= (others => '0');
when TAG_START =>
pme_to_cr <= '0';
start <= '1';
start_tag_nbr <= tag_nbr_cntr;
tag_nbr_cntr <= tag_nbr_cntr + '1';
when ABORT =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when others =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
end case;
end if;
end process fsm_out;
-------------------------------------------------------------------------------
end architecture tx_ctrl_arch;
tx_module.vhd 0000664 0000000 0000000 00000034450 14574545710 0033511 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Tx Module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_module.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 13.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- combines the modules tx_put_data, tx_compl_timeout and tx_ctrl
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- * tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tx_module is
generic(
DEVICE_FAMILY : string := "unused";
TX_HEADER_FIFO_DEPTH : natural := 32; -- valid values are: 2^(TX_HEADER_LPM_WIDTHU-1) < TX_HEADER_FIFO_DEPTH <= 2^(TX_HEADER_LPM_WIDTHU)
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(TX_DATA_LPM_WIDTHU-1) < TX_DATA_FIFO_DEPTH <= 2^(TX_DATA_LPM_WIDTHU)
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
rst : in std_logic;
wb_clk : in std_logic;
wb_rst : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
-- IP Core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
-- Rx Module
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- Wishbone Master
tx_fifo_c_data_clr : in std_logic;
tx_fifo_c_head_clr : in std_logic;
tx_fifo_c_head_enable : in std_logic;
tx_fifo_c_data_enable : in std_logic;
tx_fifo_c_head_in : in std_logic_vector(31 downto 0);
tx_fifo_c_data_in : in std_logic_vector(31 downto 0);
tx_fifo_c_head_full : out std_logic;
tx_fifo_c_data_full : out std_logic;
tx_fifo_c_data_usedw : out std_logic_vector(9 downto 0);
-- Wishbone Slave
tx_fifo_wr_head_clr : in std_logic;
tx_fifo_wr_head_enable : in std_logic;
tx_fifo_wr_head_in : in std_logic_vector(31 downto 0);
tx_fifo_w_data_clr : in std_logic;
tx_fifo_w_data_enable : in std_logic;
tx_fifo_w_data_in : in std_logic_vector(31 downto 0);
tx_fifo_wr_head_full : out std_logic;
tx_fifo_w_data_full : out std_logic;
tx_fifo_w_data_usedw : out std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : out std_logic_vector(6 downto 0);
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0);
-- error
tx_compl_abort : out std_logic;
tx_timeout : out std_logic
);
end entity tx_module;
-- ****************************************************************************
architecture tx_module_arch of tx_module is
-- internal signals -----------------------------------------------------------
signal aligned_int : std_logic;
signal data_len_int : std_logic_vector(9 downto 0);
signal wr_rd_int : std_logic; -- 0: write, 1: read
signal posted_int : std_logic; -- 0: non-posted, 1: posted
signal byte_count_int : std_logic_vector(11 downto 0);
signal orig_addr_int : std_logic_vector(31 downto 0);
signal tx_tag_nbr_int : std_logic_vector(7 downto 0);
signal get_header_int : std_logic;
signal make_header_int : std_logic;
signal data_enable_int : std_logic;
signal start_int : std_logic;
signal start_tag_nbr_int : std_logic_vector(4 downto 0);
signal c_wrrd_int : std_logic;
signal completer_id_int : std_logic_vector(15 downto 0);
signal own_id_int : std_logic_vector(15 downto 0);
signal get_next_header_int : std_logic;
signal abort_compl_int : std_logic;
signal send_len_int : std_logic_vector(9 downto 0);
signal send_addr_int : std_logic_vector(31 downto 0);
signal payload_loop_int : std_logic;
signal first_last_full_int : std_logic_vector(1 downto 0);
signal io_write_int : std_logic;
-- FIFO:
signal tx_fifo_c_head_empty_int : std_logic;
signal tx_fifo_c_head_enable_int : std_logic;
signal tx_fifo_c_head_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_c_data_empty_int : std_logic;
signal tx_fifo_c_data_enable_int : std_logic;
signal tx_fifo_c_data_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_wr_head_empty_int : std_logic;
signal tx_fifo_wr_head_enable_int : std_logic;
signal tx_fifo_wr_head_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_empty_int : std_logic;
signal tx_fifo_w_data_out_int : std_logic_vector(63 downto 0);
signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU+1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU+1 downto 0);
begin
-- instanciate components -----------------------------------------------------
tx_ctrl_comp : entity work.tx_ctrl
port map(
clk => clk,
rst => rst,
-- IP core
tx_st_ready0 => tx_st_ready0,
tx_fifo_full0 => tx_fifo_full0,
tx_fifo_empty0 => tx_fifo_empty0,
tx_fifo_rdptr0 => tx_fifo_rdptr0,
tx_fifo_wrptr0 => tx_fifo_wrptr0,
pme_to_sr => pme_to_sr,
tx_st_err0 => tx_st_err0,
tx_st_valid0 => tx_st_valid0,
tx_st_sop0 => tx_st_sop0,
tx_st_eop0 => tx_st_eop0,
pme_to_cr => pme_to_cr,
-- FIFO
tx_c_head_empty => tx_fifo_c_head_empty_int,
tx_wr_head_empty => tx_fifo_wr_head_empty_int,
tx_c_data_empty => tx_fifo_c_data_empty_int,
tx_wr_data_empty => tx_fifo_w_data_empty_int,
tx_c_head_enable => tx_fifo_c_head_enable_int,
tx_wr_head_enable => tx_fifo_wr_head_enable_int,
tx_c_data_enable => tx_fifo_c_data_enable_int,
tx_wr_data_enable => tx_fifo_w_data_enable_int,
-- tx_put_data
aligned => aligned_int,
data_len => data_len_int,
wr_rd => wr_rd_int, -- 0: write, 1: read
posted => posted_int, -- 0: non-posted, 1: posted
byte_count => byte_count_int,
io_write => io_write_int,
orig_addr => orig_addr_int,
tx_tag_nbr => tx_tag_nbr_int,
get_header => get_header_int,
get_next_header => get_next_header_int,
make_header => make_header_int,
data_enable => data_enable_int,
c_wrrd => c_wrrd_int,
completer_id => completer_id_int,
own_id => own_id_int,
abort_compl => abort_compl_int,
send_len => send_len_int,
send_addr => send_addr_int,
payload_loop => payload_loop_int,
first_last_full => first_last_full_int,
-- tx_compl_timeout
start => start_int,
start_tag_nbr => start_tag_nbr_int,
-- error
compl_abort => tx_compl_abort,
-- init
bus_dev_func => bus_dev_func,
max_payload => max_payload
);
tx_put_data_comp : entity work.tx_put_data
port map(
clk => clk,
rst => rst,
-- IP Core
tx_st_data0 => tx_st_data0,
-- FIFO
tx_c_head_out => tx_fifo_c_head_out_int,
tx_c_data_out => tx_fifo_c_data_out_int,
tx_wr_head_out => tx_fifo_wr_head_out_int,
tx_wr_data_out => tx_fifo_w_data_out_int,
-- tx_ctrl
data_enable => data_enable_int,
tag_nbr => tx_tag_nbr_int,
req_id => own_id_int,
completer_id => completer_id_int,
c_wrrd => c_wrrd_int,
get_header => get_header_int,
get_next_header => get_next_header_int,
make_header => make_header_int,
abort_compl => abort_compl_int,
send_len => send_len_int,
send_addr => send_addr_int,
payload_loop => payload_loop_int,
first_last_full => first_last_full_int,
data_length => data_len_int,
aligned => aligned_int,
wr_rd => wr_rd_int,
posted => posted_int,
byte_count => byte_count_int,
io_write => io_write_int,
orig_addr => orig_addr_int
);
tx_compl_timeout_comp : entity work.tx_compl_timeout
generic map(
CLOCK_TIME => 8 ns, -- clock cycle time
TIMEOUT_TIME => 25
)
port map(
clk => clk,
clk_500 => clk_500,
rst => rst,
-- tx_ctrl
tag_nbr_in => start_tag_nbr_int,
start => start_int,
-- RxModule
rx_tag_nbr => rx_tag_nbr,
rx_tag_rcvd => rx_tag_rcvd,
-- error
timeout => tx_timeout
);
------------------------------------------------
tx_c_header_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_c_head_clr,
data => tx_fifo_c_head_in,
rdclk => clk,
rdreq => tx_fifo_c_head_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_c_head_enable,
q => tx_fifo_c_head_out_int,
rdempty => tx_fifo_c_head_empty_int,
wrfull => tx_fifo_c_head_full,
wrusedw => open);
tx_wr_header_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_wr_head_clr,
data => tx_fifo_wr_head_in,
rdclk => clk,
rdreq => tx_fifo_wr_head_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_wr_head_enable,
q => tx_fifo_wr_head_out_int,
rdempty => tx_fifo_wr_head_empty_int,
wrfull => tx_fifo_wr_head_full,
wrusedw => tx_fifo_wr_head_usedw);
------------------------------------------------
tx_c_data_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_c_data_clr,
data => tx_fifo_c_data_in,
rdclk => clk,
rdreq => tx_fifo_c_data_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_c_data_enable,
q => tx_fifo_c_data_out_int,
rdempty => tx_fifo_c_data_empty_int,
wrfull => tx_fifo_c_data_full,
wrusedw => tx_wrusedw_c);
tx_w_data_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_w_data_clr,
data => tx_fifo_w_data_in,
rdclk => clk,
rdreq => tx_fifo_w_data_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_w_data_enable,
q => tx_fifo_w_data_out_int,
rdempty => tx_fifo_w_data_empty_int,
wrfull => tx_fifo_w_data_full,
wrusedw => tx_wrusedw_w);
-------------------------------------------------------------------------------
tx_fifo_c_data_usedw <= "0" & tx_wrusedw_c(8 downto 0);
tx_fifo_w_data_usedw <= "0" & tx_wrusedw_w(8 downto 0);
-------------------------------------------------------------------------------
end architecture tx_module_arch;
tx_put_data.vhd 0000664 0000000 0000000 00000042421 14574545710 0034022 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : tx_put_data
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_put_data.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 07.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- data handling module for tx path, controlled by tx_ctrl.vhd;
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- * tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx_put_data is
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
tx_st_data0 : out std_logic_vector(63 downto 0);
-- FIFO
tx_c_head_out : in std_logic_vector(63 downto 0);
tx_c_data_out : in std_logic_vector(63 downto 0);
tx_wr_head_out : in std_logic_vector(63 downto 0);
tx_wr_data_out : in std_logic_vector(63 downto 0);
-- tx_ctrl
data_enable : in std_logic;
tag_nbr : in std_logic_vector(7 downto 0);
req_id : in std_logic_vector(15 downto 0);
completer_id : in std_logic_vector(15 downto 0);
c_wrrd : in std_logic; -- 0: completion, 1: write/read
get_header : in std_logic;
get_next_header : in std_logic;
make_header : in std_logic;
abort_compl : in std_logic;
send_len : in std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : in std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : in std_logic; -- =0: no loop, =1: loop -> keep most header info
first_last_full : in std_logic_vector(1 downto 0); -- 00: unused, 01: first packet of payload_loop, 01: last
-- packet of payload_loop, 11: all enabled
data_length : out std_logic_vector(9 downto 0);
aligned : out std_logic;
wr_rd : out std_logic; -- 0: write, 1: read
posted : out std_logic; -- 0: non-posted, 1: posted
byte_count : out std_logic_vector(11 downto 0);
io_write : out std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : out std_logic_vector(31 downto 0)
);
end entity tx_put_data;
-- ****************************************************************************
architecture tx_put_data_arch of tx_put_data is
-- internal signals: ----------------------------------------------------------
signal aligned_int : std_logic;
signal data_in_q : std_logic_vector(63 downto 0);
signal data_q : std_logic_vector(63 downto 0);
signal data_qq : std_logic_vector(63 downto 0);
signal req_id_int : std_logic_vector(15 downto 0);
signal tag_id_int : std_logic_vector(7 downto 0);
signal lower_addr_int : std_logic_vector(6 downto 0);
signal first_DW_int : std_logic_vector(3 downto 0);
signal last_DW_int : std_logic_vector(3 downto 0);
signal wr_rd_int : std_logic; -- =0: wr, =1: rd
signal mem_io_int : std_logic; -- =0: mem, =1: I/O
signal io_write_int : std_logic;
-------------------------------------------------------------------------------
begin
io_write <= io_write_int;
data_path : process(rst, clk)
begin
if(rst = '1') then
-- ports:
tx_st_data0 <= (others => '0');
data_length <= (others => '0');
aligned <= '0';
wr_rd <= '0';
posted <= '0';
byte_count <= (others => '0');
orig_addr <= (others => '0');
-- signals:
aligned_int <= '0';
data_in_q <= (others => '0');
data_q <= (others => '0');
data_qq <= (others => '0');
req_id_int <= (others => '0');
tag_id_int <= (others => '0');
lower_addr_int <= (others => '0');
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
wr_rd_int <= '0';
mem_io_int <= '0';
io_write_int <= '0';
elsif(clk'event and clk = '1') then
-- capture data length from appropriate FIFO packet
if(get_header = '1' and c_wrrd = '0') then
data_length <= tx_c_head_out(9 downto 0);
elsif(get_header = '1' and c_wrrd = '1') then
data_length <= tx_wr_head_out(9 downto 0);
end if;
-- store alignment information for both completion and write/read transmissions
if(get_header = '1' and c_wrrd = '0') then
case tx_c_head_out(34) is
when '0' => -- check bit 2 of address for alignment
aligned_int <= '1' ;
aligned <= '1' ;
when others =>
aligned_int <= '0';
aligned <= '0';
end case;
elsif(get_header = '1' and c_wrrd = '1') then
case tx_wr_head_out(34) is
when '0' =>
aligned_int <= '1';
aligned <= '1';
when others =>
aligned_int <= '0';
aligned <= '0';
end case;
end if;
-- capture information if transmission is write or read
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(31) = '1') then
wr_rd <= '0';
wr_rd_int <= '0';
else
wr_rd <= '1';
wr_rd_int <= '1';
end if;
----------------------------------------------------------------------------------------
-- wr_rd is not reset if c_wrrd = 0 and if previous transfer is read it's stuck at '1'
-- which causes errors during transfer
-- thus added elsif
----------------------------------------------------------------------------------------
elsif get_header = '1' and c_wrrd = '0' then
wr_rd <= '0';
wr_rd_int <= '0';
end if;
-- define if transfer is posted or not
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(30) = '1') then -- posted
posted <= '1';
else -- non-posted
posted <= '0';
end if;
end if;
-- define wether transfer is of type memory or I/O
if(get_header = '1' and c_wrrd = '1') then
if(tx_wr_head_out(29) = '1') then
mem_io_int <= '0'; -- memory
else
mem_io_int <= '1'; -- I/O
end if;
end if;
-- store information on first/last byte enables
if(get_header = '1' and c_wrrd = '1') then
first_DW_int <= tx_wr_head_out(17 downto 14); -- first DW
last_DW_int <= tx_wr_head_out(13 downto 10); -- last DW
end if;
-- register header packet
if(get_header = '1' and c_wrrd = '0') then
data_in_q <= tx_c_head_out;
end if;
-- store requester ID
if(get_next_header = '1' and c_wrrd = '0') then
req_id_int <= tx_c_head_out(15 downto 0);
end if;
-- store tag ID
if(get_header = '1' and c_wrrd = '0') then
tag_id_int <= tx_c_head_out(25 downto 18);
end if;
-- store byte count
if(get_next_header = '1' and c_wrrd = '0') then
byte_count <= tx_c_head_out(27 downto 16);
end if;
-- store I/O write flag
if(get_next_header = '1' and c_wrrd = '0') then
io_write_int <= tx_c_head_out(28);
elsif c_wrrd = '1' then
io_write_int <= '0';
end if;
-- store original transfer address
if(get_header = '1' and c_wrrd = '0') then
orig_addr <= tx_c_head_out(63 downto 32);
elsif(get_header = '1' and c_wrrd = '1') then
orig_addr <= tx_wr_head_out(63 downto 32);
end if;
-- calculate lower address for completions
if(get_header = '1' and c_wrrd = '0') then
if(tx_c_head_out(17 downto 14) = "0000" or tx_c_head_out(14) = '1') then
lower_addr_int <= tx_c_head_out(38 downto 34) & "00"; -- calculate from first DW
elsif(tx_c_head_out(15 downto 14) = "10") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "01";
elsif(tx_c_head_out(16 downto 14) = "100") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "10";
elsif(tx_c_head_out(17 downto 14) = "1000") then
lower_addr_int <= tx_c_head_out(38 downto 34) & "11";
-- coverage off
else
-- synthesis translate_off
report "wrong encoding of tx_c_head_out(17 downto 14)" severity error;
-- synthesis translate_on
-- coverage on
end if;
end if;
-- assebmle packets for transmission
-- c_wrrd controls whether completion or write/read transfer is needed
-- R := reserved according to PCIe base specification, thus set to '0' here
if(make_header = '1' and c_wrrd = '0') then
if(abort_compl = '1' or io_write_int = '1') then
data_qq(31 downto 24) <= "00001010"; -- fmt & type -> completion without data
else
data_qq(31 downto 24) <= "01001010"; -- fmt & type -> completion with data
end if;
data_qq(23) <= '0'; -- R
data_qq(22 downto 20) <= data_in_q(28 downto 26); -- TC
data_qq(19) <= '0'; -- R
data_qq(18) <= data_in_q(31); -- Attr(2)
data_qq(17 downto 14) <= '0' & '0' & '0' & '0'; -- R & TH & TD & EP
data_qq(13 downto 12) <= data_in_q(30 downto 29); -- Attr(1:0)
data_qq(11 downto 10) <= "00"; -- AT
data_qq(9 downto 0) <= data_in_q(9 downto 0); -- length
data_qq(63 downto 48) <= completer_id;
if(abort_compl = '1') then
data_qq(47 downto 45) <= "100"; -- completion status = completer abort
else
data_qq(47 downto 45) <= "000"; -- completion status = successful completion
end if;
data_qq(44) <= '0'; -- bcm
data_qq(43 downto 32) <= tx_c_head_out(27 downto 16); -- byte count
data_q(63 downto 32) <= x"00000000";
data_q(31 downto 16) <= req_id_int; -- requester ID
data_q(15 downto 8) <= tag_id_int; -- tag ID
data_q(7 downto 0) <= '0' & lower_addr_int; -- R & lower address
elsif(make_header = '1' and c_wrrd = '1') then
if(mem_io_int = '0' and wr_rd_int = '0') then -- memory write
data_qq(31 downto 24) <= "01000000";
elsif(mem_io_int = '1' and wr_rd_int = '0') then -- I/O write
data_qq(31 downto 24) <= "01000010";
elsif(mem_io_int = '0' and wr_rd_int = '1') then -- memory read
data_qq(31 downto 24) <= "00000000";
else -- I/O read
data_qq(31 downto 24) <= "00000010";
end if;
-- R & TC(2:0) & R & Attr(2) & R & TH & TD & EP & Attr(1:0) & AT
data_qq(23 downto 10) <= '0' & "000" & '0' & '0' & '0' & '0' & '0' & '0' & "00" & "00";
data_qq(9 downto 0) <= send_len; -- length
data_qq(63 downto 48) <= req_id;
data_qq(47 downto 40) <= tag_nbr;
data_q(63 downto 32) <= x"00000000";
data_q(31 downto 0) <= send_addr; -- address
-- do payload loop, that means: one request was transmitted from Wishbone but the length is too big
-- thus split up in order to obey PCIe max_payload_size or max_read_size, which means
-- to send several packets with the same header info except address and length
-- CAUTION:
-- if the last packet to be sent has length =1 then last_DW must be =0
-- and the original setting for last_DW must be inserted for first_DW
if(payload_loop = '0') then
data_qq(39 downto 36) <= last_DW_int; -- last DW
data_qq(35 downto 32) <= first_DW_int; -- first DW
elsif(payload_loop = '1' and first_last_full = "01") then
data_qq(39 downto 36) <= x"F";
data_qq(35 downto 32) <= first_DW_int; -- first DW
elsif(payload_loop = '1' and first_last_full = "10") then
if send_len = "0000000001" then
data_qq(39 downto 36) <= x"0";
data_qq(35 downto 32) <= last_DW_int;
else
data_qq(39 downto 36) <= last_DW_int; -- last DW
data_qq(35 downto 32) <= x"F";
end if;
elsif(payload_loop = '1' and first_last_full = "11") then
data_qq(39 downto 36) <= x"F";
data_qq(35 downto 32) <= x"F";
end if;
end if;
-- manage registration of data retrieved from FIFO's
if(data_enable = '1' and aligned_int = '0' and c_wrrd = '0') then
data_q(31 downto 0) <= tx_c_data_out(63 downto 32);
data_qq <= tx_c_data_out(31 downto 0) & data_q(31 downto 0);
elsif(data_enable = '1' and aligned_int = '0' and c_wrrd = '1') then
data_q(31 downto 0) <= tx_wr_data_out(63 downto 32);
data_qq <= tx_wr_data_out(31 downto 0) & data_q(31 downto 0);
elsif(data_enable = '1' and aligned_int = '1' and c_wrrd = '0') then
data_q <= tx_c_data_out;
data_qq <= data_q;
elsif(data_enable = '1' and aligned_int = '1' and c_wrrd = '1') then
data_q <= tx_wr_data_out;
data_qq <= data_q;
end if;
-- output registered data to Avalon ST data bus
if(data_enable = '1') then
tx_st_data0 <= data_qq;
end if;
end if;
end process data_path;
-------------------------------------------------------------------------------
end architecture tx_put_data_arch;
x1/ 0000775 0000000 0000000 00000000000 14574545710 0031330 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source .gitignore 0000664 0000000 0000000 00000000173 14574545710 0033321 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/x1 # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!*.txt
!x1.tcl
Hard_IP_x1.txt 0000664 0000000 0000000 00000122206 14574545710 0033752 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/x1 -- megafunction wizard: %IP Compiler for PCI Express v16.0%
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x1.tcl 0000664 0000000 0000000 00000000177 14574545710 0032371 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/x1 # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
qmegawiz { Hard_IP_x1 }
x4/ 0000775 0000000 0000000 00000000000 14574545710 0031333 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source .gitignore 0000664 0000000 0000000 00000000173 14574545710 0033324 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/x4 # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!*.txt
!x4.tcl
Hard_IP_x4.txt 0000664 0000000 0000000 00000122215 14574545710 0033760 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/x4 -- megafunction wizard: %IP Compiler for PCI Express v16.0%
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x4.tcl 0000664 0000000 0000000 00000000177 14574545710 0032377 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source/x4 # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
qmegawiz { Hard_IP_x4 }
z091_01_wb_master.vhd 0000664 0000000 0000000 00000111056 14574545710 0034555 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : internal Wishbone master module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : wb_master.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 16.11.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- handles Wishbone accesses, writes data from rx_module and returns read
-- data to tx_module
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- * wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
library work;
use work.src_utils_pkg.all;
entity z091_01_wb_master is
generic(
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011"; -- = 1019 DW
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Rx Module
rx_fifo_wr_out : in std_logic_vector(31 downto 0);
rx_fifo_wr_empty : in std_logic;
rx_fifo_wr_rd_enable : out std_logic;
-- Tx Module
tx_fifo_c_head_full : in std_logic;
tx_fifo_c_data_full : in std_logic;
tx_fifo_c_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_c_head_enable : out std_logic;
tx_fifo_c_data_enable : out std_logic;
tx_fifo_c_head_in : out std_logic_vector(31 downto 0);
tx_fifo_c_data_in : out std_logic_vector(31 downto 0);
tx_fifo_c_data_clr : out std_logic;
tx_fifo_c_head_clr : out std_logic;
-- Wishbone
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_bar_o : out std_logic_vector(6 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic; -- wbm_tga(0)=1 if ECRC error occured
-- error
ecrc_err_in : in std_logic; -- input from error module
err_tag_id : in std_logic_vector(7 downto 0);
ecrc_err_out : out std_logic -- output of 16z091-01
);
end entity z091_01_wb_master;
-- ****************************************************************************
architecture z091_01_wb_master_arch of z091_01_wb_master is
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
PREPARE_FIFO, IDLE, GET_HEADER_0, GET_HEADER_1, GET_HEADER_2, GET_WR_DATA, START_TRANS,
TRANSMIT, WAIT_ON_FIFO, PUT_HEADER_0, PUT_HEADER_1, PUT_HEADER_2, GET_Z
);
signal state : fsm_state;
-------------------------------------------------------------------------------
-- constants ------------------------------------------------------------------
constant ADDR_INCR : std_logic_vector(13 downto 0) := "00000000000100"; -- address increment for burst access
-------------------------------------------------------------------------------
-- internal signals -----------------------------------------------------------
signal get_data : std_logic;
signal decode_header : std_logic_vector(1 downto 0); -- 00 = idle, 01 = H0, 10 = H1, 11 = H3
signal data_to_wb : std_logic;
signal data_to_fifo : std_logic;
signal listen_to_ack : std_logic;
signal write_header : std_logic_vector(1 downto 0); -- 00 = idle, 01 = H0, 10 = H1, 11 = H3
signal wr_en_int : std_logic; -- write flag, 0 = read, 1 = write
signal attr_int : std_logic_vector(2 downto 0);
signal tc_int : std_logic_vector(2 downto 0);
signal req_id_int : std_logic_vector(15 downto 0);
signal addr_int : std_logic_vector(31 downto 0);
signal tag_id_int : std_logic_vector(7 downto 0);
signal first_dw_int : std_logic_vector(3 downto 0);
signal last_dw_int : std_logic_vector(3 downto 0);
signal length_int : std_logic_vector(9 downto 0);
signal data_q : std_logic_vector(31 downto 0);
signal data_qq : std_logic_vector(31 downto 0);
signal cnt_len_wb : std_logic_vector(10 downto 0); -- count amount of data tranfered through wishbone
signal cnt_len_fifo : std_logic_vector(10 downto 0); -- count amount of data taken from fifo
signal addr_offset : std_logic_vector(13 downto 0);
signal wait_clk : integer range 2 downto 0 := 0;
signal q_to_wbm : std_logic_vector(1 downto 0);
signal wbm_ack_int : std_logic;
signal err_tag_id_int : std_logic_vector(7 downto 0);
signal byte_count_int : std_logic_vector(11 downto 0);
signal suspend : std_logic;
signal goto_start : std_logic;
signal bar_dec_int : std_logic_vector(6 downto 0); -- decode which BAR was hit, only one bit may be set at a time
signal aligned_int : std_logic;
signal transmission : std_logic;
signal io_wr_int : std_logic;
signal wb_bar_dec_int : std_logic_vector(6 downto 0);
signal wb_bar_dec_int_d : std_logic_vector(6 downto 0);
signal ecrc_err_int : std_logic;
-------------------------------------------------------------------------------
begin
wb_bar_dec_int <= bar_dec_int when (state = START_TRANS) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B
and tx_fifo_c_data_full = '0' and goto_start = '0') else
(OTHERS => '0') when (state = IDLE) or
(state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
state = GET_Z or state = PUT_HEADER_0
else
wb_bar_dec_int_d;
ecrc_err_int <= '0' when wb_rst = '1' else
'0' when state = TRANSMIT else
'1' when state /= TRANSMIT and ecrc_err_in = '1';
-------------------------------------------------------------------------------
fsm_trans : process(wb_rst, wb_clk)
begin
if(wb_rst = '1') then
state <= IDLE;
elsif(wb_clk'event and wb_clk = '1') then
case state is
when IDLE =>
if(rx_fifo_wr_empty = '0') then
state <= PREPARE_FIFO;
else
state <= IDLE;
end if;
when PREPARE_FIFO =>
state <= GET_HEADER_0;
when GET_HEADER_0 =>
state <= GET_HEADER_1;
when GET_HEADER_1 =>
state <= GET_HEADER_2;
when GET_HEADER_2 =>
if((tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1') and wr_en_int = '0') then
state <= WAIT_ON_FIFO;
elsif(rx_fifo_wr_out(2) = '0') then
------------------------
-- transfer is aligned
------------------------
state <= GET_Z;
elsif(rx_fifo_wr_out(2) = '1' and wr_en_int = '1') then
state <= GET_WR_DATA;
elsif(rx_fifo_wr_out(2) = '1' and wr_en_int = '0') then
state <= START_TRANS;
end if;
when GET_WR_DATA =>
if(length_int = ONE_10B or ((length_int > ONE_10B or length_int = ZERO_10B) and wait_clk = 1)) then
state <= START_TRANS;
else
state <= GET_WR_DATA;
end if;
when START_TRANS =>
if(cnt_len_wb > ZERO_11B) then
state <= TRANSMIT;
elsif(cnt_len_wb <= ZERO_11B and wbm_ack = '1' and wr_en_int = '1') then
state <= IDLE;
elsif(cnt_len_wb <= ZERO_11B and (wbm_ack = '1' or wr_en_int = '0')) then
state <= START_TRANS;
end if;
when TRANSMIT =>
if(wbm_ack = '1' and (wr_en_int = '0' or (io_wr_int = '1' and aligned_int = '0')) and ((tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B) or cnt_len_wb = ZERO_11B)) then
state <= PUT_HEADER_0;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and wr_en_int = '1' and ((addr_int(2) = '0' and length_int(0) = '0') or
(addr_int(2) = '1' and length_int(0) = '1'))) then
state <= IDLE;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and wr_en_int = '1' and ((addr_int(2) = '0' and length_int(0) = '1') or
(addr_int(2) = '1' and length_int(0) = '0') or (io_wr_int = '1' and aligned_int = '1'))) then
state <= GET_Z;
else
state <= TRANSMIT;
end if;
when WAIT_ON_FIFO =>
if(tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and tx_fifo_c_data_full = '0' and goto_start = '1') then
state <= START_TRANS;
elsif(tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and tx_fifo_c_data_full = '0' and goto_start = '0') then
state <= TRANSMIT;
else
state <= WAIT_ON_FIFO;
end if;
when PUT_HEADER_0 =>
state <= PUT_HEADER_1;
when PUT_HEADER_1 =>
if(wr_en_int = '0' or io_wr_int = '1') then
state <= PUT_HEADER_2;
else
state <= IDLE;
end if;
when PUT_HEADER_2 =>
if(wait_clk = 1 and suspend = '0') then
state <= IDLE;
elsif(suspend = '1') then
state <= WAIT_ON_FIFO;
else
state <= PUT_HEADER_2;
end if;
when GET_Z =>
if(io_wr_int = '1' and aligned_int = '1' and transmission = '0') then
state <= PUT_HEADER_0;
elsif(transmission = '1' and wr_en_int = '1') then
state <= GET_WR_DATA;
elsif(transmission = '1' and wr_en_int = '0') then
state <= START_TRANS;
else
state <= IDLE;
end if;
-- coverage off
when others =>
-- synthesis translate_off
report "reached unknown FSM state in process fsm_trans of z091_01_wb_master.vhd" severity error;
-- synthesis translate_on
state <= IDLE;
-- coverage on
end case;
end if;
end process fsm_trans;
-------------------------------------------------------------------------------
fsm_out : process(wb_rst, wb_clk)
begin
if(wb_rst = '1') then
rx_fifo_wr_rd_enable <= '0';
tx_fifo_c_head_enable <= '0';
tx_fifo_c_data_enable <= '0';
tx_fifo_c_data_clr <= '1';
tx_fifo_c_head_clr <= '1';
wbm_stb <= '0';
wbm_cyc_bar_o <= (others => '0');
wbm_we <= '0';
wbm_sel <= (others => '0');
wbm_adr <= (others => '0');
wbm_cti <= (others => '0');
wbm_tga <= '0';
ecrc_err_out <= '0';
get_data <= '0';
decode_header <= (others => '0');
data_to_wb <= '0';
data_to_fifo <= '0';
listen_to_ack <= '0';
write_header <= (others => '0');
cnt_len_wb <= (others => '0');
cnt_len_fifo <= (others => '0');
addr_offset <= (others => '0');
wait_clk <= 0;
q_to_wbm <= (others => '0');
wbm_ack_int <= '0';
err_tag_id_int <= x"FF"; -- init with a value greater than allowed 32 tags
byte_count_int <= (others => '0');
suspend <= '0';
goto_start <= '0';
aligned_int <= '0';
transmission <= '0';
elsif(wb_clk'event and wb_clk = '1') then
wb_bar_dec_int_d <= wb_bar_dec_int;
if(state = PREPARE_FIFO) then
transmission <= '1';
elsif(state = TRANSMIT) then
transmission <= '0';
end if;
-- determine data alignment which decides whether first packet after header2 is empty or contains first data packet
if(state = GET_HEADER_2 and rx_fifo_wr_out(2) = '0') then
aligned_int <= '1';
elsif(state = IDLE) then
aligned_int <= '0';
end if;
if((state = IDLE and rx_fifo_wr_empty = '1') or state = START_TRANS or state = WAIT_ON_FIFO or
(state = GET_Z and (transmission = '0' or wr_en_int = '0' or (wr_en_int = '1' and aligned_int = '1' and length_int = ONE_10B))) or
(state = GET_HEADER_2 and (wr_en_int = '0' or (wr_en_int = '1' and length_int = ONE_10B and rx_fifo_wr_out(2) = '1'))) or
(state = TRANSMIT and wbm_ack = '1' and cnt_len_fifo = ONE_11B) or
(state = GET_WR_DATA and ((length_int = TWO_10B and wait_clk = 0) or (length_int = THREE_10B and wait_clk = 1))) or
(state = TRANSMIT and wbm_ack = '0')
) then
rx_fifo_wr_rd_enable <= '0';
elsif((state = IDLE and rx_fifo_wr_empty = '0') or
(state = GET_Z and transmission = '1' and wr_en_int = '1') or
(state = TRANSMIT and wbm_ack = '1' and wr_en_int = '1' and ((cnt_len_wb = ZERO_11B and ((addr_int(2) = '0' and length_int(0) = '1') or
(addr_int(2) = '1' and length_int(0) = '0'))) or cnt_len_fifo > ONE_11B))) then
rx_fifo_wr_rd_enable <= '1';
end if;
if(state = IDLE or state = GET_Z or (state = WAIT_ON_FIFO and wait_clk = 1)) then
tx_fifo_c_head_enable <= '0';
elsif(state = PUT_HEADER_0) then
tx_fifo_c_head_enable <= '1';
end if;
if(state = IDLE or (state = PUT_HEADER_2 and length_int(0) = '1')) then
tx_fifo_c_data_enable <= '0';
elsif(state = TRANSMIT or state = PUT_HEADER_0 or (state = PUT_HEADER_1 and length_int(0) = '0') ) then
tx_fifo_c_data_enable <= wbm_ack_int;
end if;
if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
(state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ZERO_11B or (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and
cnt_len_wb /= ZERO_11B and wr_en_int = '0'))) ) then
wbm_stb <= '0';
elsif(state = START_TRANS or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0') ) then
wbm_stb <= '1';
end if;
--wbm_cyc never used before and now it is removed
--if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
-- (state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ZERO_11B or (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and
-- cnt_len_wb /= ZERO_11B and wr_en_int = '0'))) ) then
-- wbm_cyc <= '0';
--elsif(state = START_TRANS or
-- (state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
-- tx_fifo_c_data_full = '0' and goto_start = '0') ) then
-- wbm_cyc <= '1';
--end if;
if(state = IDLE or (cnt_len_wb = ZERO_11B and wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')))) then
wbm_we <= '0';
elsif(state = START_TRANS and wr_en_int = '1') then
wbm_we <= '1';
end if;
if(state = IDLE or (cnt_len_wb = ZERO_11B and wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')))) then
wbm_sel <= (others => '0');
elsif(state = START_TRANS) then
wbm_sel <= first_dw_int;
elsif(state = TRANSMIT and wbm_ack = '1' and cnt_len_wb > ONE_11B) then
wbm_sel <= x"F";
elsif(state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ONE_11B) then
wbm_sel <= last_dw_int;
end if;
----------------------------------------
-- manage Wishbone address
-- add addr_offset during transmission
----------------------------------------
if(state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) then
wbm_adr <= addr_int + addr_offset;
--else
--wbm_adr <= addr_int;
end if;
-- calculate address offset
if(state = IDLE) then
addr_offset <= (others => '0');
elsif(state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) then
addr_offset <= addr_offset + ADDR_INCR;
end if;
-- add wbm_cyc_o to be registered
if((state = START_TRANS and suspend = '0' and length_int /= ONE_10B) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb > ZERO_11B) ) then
wbm_cti <= "010";
wbm_cyc_bar_o <= wb_bar_dec_int;
elsif((state = START_TRANS and suspend = '0' and length_int = ONE_10B) or
(state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ONE_11B or (tx_fifo_c_data_usedw = SUSPEND_FIFO_ACCESS and
wr_en_int = '0'))) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb <= ZERO_11B) ) then
wbm_cti <= "111";
wbm_cyc_bar_o <= wb_bar_dec_int;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')) ) then
wbm_cti <= "000";
wbm_cyc_bar_o <= (OTHERS=>'0');
end if;
if(state = IDLE or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
wbm_tga <= '0';
elsif(state = START_TRANS and err_tag_id_int = tag_id_int) then
wbm_tga <= '1';
end if;
if(state = IDLE or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
ecrc_err_out <= '0';
elsif(state = START_TRANS and ecrc_err_int = '1' and err_tag_id_int = tag_id_int) then
ecrc_err_out <= '1';
end if;
if(state = IDLE or state = START_TRANS or (state = GET_HEADER_2 and wr_en_int = '0') or (state = GET_WR_DATA and length_int = ONE_10B) or
(state = TRANSMIT and ((wbm_ack = '0' or wr_en_int = '0' or cnt_len_wb = ZERO_11B) or (wbm_ack = '1' and cnt_len_wb = ZERO_11B))) ) then
get_data <= '0';
elsif((state = GET_HEADER_2 and rx_fifo_wr_out(2) = '1' and wr_en_int = '1') or (state = GET_WR_DATA and length_int /= ONE_10B) or
(state = TRANSMIT and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb > ZERO_11B) or
(state = GET_Z and aligned_int = '1' and wr_en_int = '1')
) then
get_data <= '1';
end if;
if(state = IDLE or state = GET_WR_DATA or state = START_TRANS or state = GET_HEADER_2) then
decode_header <= (others => '0');
elsif(state = PREPARE_FIFO) then
decode_header <= "01";
elsif(state = GET_HEADER_0) then
decode_header <= "10";
elsif(state = GET_HEADER_1) then
decode_header <= "11";
end if;
if(state = IDLE or state = START_TRANS or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
data_to_wb <= '0';
elsif(state = GET_WR_DATA and wr_en_int = '1' and (length_int = ONE_10B or wait_clk = 1)) then
data_to_wb <= '1';
end if;
if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B)) then
data_to_fifo <= '0';
elsif(wr_en_int = '0' and (state = START_TRANS or state = TRANSMIT)) then
data_to_fifo <= '1';
end if;
if(state = IDLE or
(wbm_ack = '1' and cnt_len_wb = ZERO_11B and ((state = START_TRANS and wr_en_int = '1') or state = TRANSMIT)) ) then
listen_to_ack <= '0';
elsif(state = START_TRANS and wr_en_int = '1') then
listen_to_ack <= '1';
end if;
if(state = IDLE) then
write_header <= (others => '0');
elsif(state = TRANSMIT and wbm_ack = '1' and (wr_en_int = '0' or io_wr_int = '1') and (cnt_len_wb = ZERO_11B or
(tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B)) ) then
write_header <= "01";
elsif(state = PUT_HEADER_0) then
write_header <= "10";
elsif(state = PUT_HEADER_1 and (wr_en_int = '0' or io_wr_int = '1')) then
write_header <= "11";
end if;
-- calculate length counters for Wishbone transactions and decrement when necessary
if(state = IDLE) then
cnt_len_wb <= (others => '0');
elsif(state = GET_HEADER_1 and length_int = ZERO_10B) then
cnt_len_wb <= '1' & length_int;
elsif(state = GET_HEADER_1 and length_int /= ZERO_10B) then
cnt_len_wb <= '0' & length_int;
elsif(cnt_len_wb > ZERO_11B and (state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) ) then
cnt_len_wb <= cnt_len_wb - ONE_11B;
end if;
-- calculate length counters for FIFO transactions and decrement when necessary
if(state = IDLE) then
cnt_len_fifo <= (others => '0');
elsif(state = GET_HEADER_1 and length_int = ZERO_10B) then
cnt_len_fifo <= '1' & length_int;
elsif(state = GET_HEADER_1 and length_int /= ZERO_10B) then
cnt_len_fifo <= '0' & length_int;
elsif(wr_en_int = '1' and cnt_len_fifo > ZERO_11B and (state = GET_WR_DATA or state = START_TRANS or
(state = TRANSMIT and wbm_ack = '1')) ) then
cnt_len_fifo <= cnt_len_fifo - ONE_11B;
end if;
if(state = IDLE or state = GET_HEADER_1 or state = PUT_HEADER_1 or (state = PUT_HEADER_2 and suspend = '1') or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0') ) then
wait_clk <= 0;
elsif(state = GET_WR_DATA or (state = WAIT_ON_FIFO and wait_clk < 1) or (state = PUT_HEADER_2 and suspend = '0')) then
wait_clk <= wait_clk + 1;
end if;
if(state = IDLE) then
q_to_wbm <= (others => '0');
elsif((state = GET_HEADER_1 and length_int = ONE_10B) or (state = TRANSMIT and wbm_ack = '1')) then
q_to_wbm <= "01";
elsif((state = GET_HEADER_1 and length_int /= ONE_10B) or (state = TRANSMIT and wbm_ack = '0')) then
q_to_wbm <= "10";
end if;
if(state = IDLE or (wbm_ack = '0' and wr_en_int = '0' and (state = TRANSMIT or state = PUT_HEADER_0 or state = PUT_HEADER_1))) then
wbm_ack_int <= '0';
elsif(wbm_ack = '1' and wr_en_int = '0' and (state = TRANSMIT or state = PUT_HEADER_0 or state = PUT_HEADER_1)) then
wbm_ack_int <= '1';
end if;
-- capture ecrc error
if(state = IDLE and ecrc_err_in = '0') then
err_tag_id_int <= (others => '0');
elsif(ecrc_err_in = '1' and (state = IDLE or state = GET_HEADER_0 or state = GET_HEADER_1 or state = GET_HEADER_2 or
state = GET_WR_DATA)) then
err_tag_id_int <= err_tag_id;
end if;
-- calculate byte count
-- correct byte count value according to first_dw_int value as defined in PCIe base specification in state PUT_HEADER_0
if(state = IDLE) then
byte_count_int <= (others => '0');
elsif(wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1' and cnt_len_wb = 0))) then
byte_count_int <= byte_count_int + FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and (first_dw_int = ZERO_04B or first_dw_int = EIGHT_04B or first_dw_int = FOUR_04B or first_dw_int = TWO_04B or first_dw_int = ONE_04B)) then
byte_count_int <= ONE_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and (first_dw_int = C_04B or first_dw_int = SIX_04B or first_dw_int = THREE_04B)) then
byte_count_int <= TWO_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and ((first_dw_int(3) = '1' and first_dw_int(1 downto 0) = TWO_02B) or (first_dw_int(3 downto 2) = ONE_02B and first_dw_int(0) = '1'))) then
byte_count_int <= THREE_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and first_dw_int(3) = '1' and first_dw_int(0) = '1') then
byte_count_int <= FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int(1 downto 0) = TWO_02B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - ONE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(1 downto 0) = TWO_02B and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - TWO_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int = ONE_04B) or (first_dw_int(1 downto 0) = ONE_02B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int = EIGHT_04B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - THREE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(1 downto 0) = TWO_02B and last_dw_int = ONE_04B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int = EIGHT_04B and last_dw_int(3 downto 2) = ONE_02B))) then
byte_count_int <= byte_count_int - FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int = EIGHT_04B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int = ONE_04B))) then
byte_count_int <= byte_count_int - FIVE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and first_dw_int = EIGHT_04B and last_dw_int = ONE_04B) then
byte_count_int <= byte_count_int - SIX_12B;
end if;
-- suspend all actions when FIFO is full until there is space in FIFO again
if(state = IDLE or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0')) then
suspend <= '0';
elsif((state = GET_HEADER_2 and (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1') and wr_en_int = '0') or
(state = TRANSMIT and wbm_ack = '1' and tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B and
wr_en_int = '0')) then
suspend <= '1';
end if;
if(state = IDLE or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '1')) then
goto_start <= '0';
elsif(state = GET_HEADER_2 and (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1')) then
goto_start <= '1';
end if;
if(state = IDLE) then
tx_fifo_c_data_clr <= '0';
tx_fifo_c_head_clr <= '0';
end if;
end if;
end process fsm_out;
-------------------------------------------------------------------------------
data_path : process(wb_clk, wb_rst)
begin
if(wb_rst = '1') then
-- ports:
tx_fifo_c_head_in <= (others => '0');
tx_fifo_c_data_in <= (others => '0');
wbm_dat_o <= (others => '0');
-- signals:
data_q <= (others => '0');
data_qq <= (others => '0');
wr_en_int <= '0';
attr_int <= (others => '0');
tc_int <= (others => '0');
req_id_int <= (others => '0');
addr_int <= (others => '0');
tag_id_int <= (others => '0');
first_dw_int <= (others => '0');
last_dw_int <= (others => '0');
length_int <= (others => '0');
bar_dec_int <= (others => '0');
io_wr_int <= '0';
elsif(wb_clk'event and wb_clk = '1') then
if(decode_header = "01") then
-- decode which BAR was hit
case rx_fifo_wr_out(28 downto 26) is
when "000" =>
bar_dec_int(0) <= '1';
bar_dec_int(6 downto 1) <= (others => '0');
when "001" =>
bar_dec_int(0) <= '0';
bar_dec_int(1) <= '1';
bar_dec_int(6 downto 2) <= (others => '0');
when "010" =>
bar_dec_int(1 downto 0) <= (others => '0');
bar_dec_int(2) <= '1';
bar_dec_int(6 downto 3) <= (others => '0');
when "011" =>
bar_dec_int(2 downto 0) <= (others => '0');
bar_dec_int(3) <= '1';
bar_dec_int(6 downto 4) <= (others => '0');
when "100" =>
bar_dec_int(3 downto 0) <= (others => '0');
bar_dec_int(4) <= '1';
bar_dec_int(6 downto 5) <= (others => '0');
when "101" =>
bar_dec_int(4 downto 0) <= (others => '0');
bar_dec_int(5) <= '1';
bar_dec_int(6) <= '0';
when "110" =>
bar_dec_int(5 downto 0) <= (others => '0');
bar_dec_int(6) <= '1';
-- coverage off
when others =>
bar_dec_int <= (0 => '1', others => '0');
-- synthesis translate_off
report "Error while decoding BAR" severity error;
-- synthesis translate_on
-- coverage on
end case;
-- split value of data bus into its components
wr_en_int <= rx_fifo_wr_out(31);
io_wr_int <= rx_fifo_wr_out(30) and rx_fifo_wr_out(31);
first_dw_int <= rx_fifo_wr_out(17 downto 14);
last_dw_int <= rx_fifo_wr_out(13 downto 10);
length_int <= rx_fifo_wr_out(9 downto 0);
tag_id_int <= rx_fifo_wr_out(25 downto 18);
elsif(decode_header = "10") then
attr_int <= rx_fifo_wr_out(21 downto 19);
tc_int <= rx_fifo_wr_out(18 downto 16);
req_id_int <= rx_fifo_wr_out(15 downto 0);
elsif(decode_header = "11") then
addr_int <= rx_fifo_wr_out;
end if;
-- manage data registering pipeline
if(get_data = '1' and wr_en_int = '1') then
data_q <= rx_fifo_wr_out;
data_qq <= data_q;
elsif(get_data = '1' and wr_en_int = '0') then
data_q <= wbm_dat_i;
end if;
-- route registered data signals to output port
if(listen_to_ack = '1' and wbm_ack = '1') then
case q_to_wbm is
when "01" =>
wbm_dat_o <= data_q;
when "10" =>
wbm_dat_o <= data_qq;
when "11" =>
-- coverage off
when others =>
-- synthesis translate_off
report "Reached undecoded state of signal q_to_wbm" severity error;
-- synthesis translate_on
-- coverage on
end case;
elsif(data_to_wb = '1') then
case q_to_wbm is
when "01" =>
wbm_dat_o <= data_q;
when "10" =>
wbm_dat_o <= data_qq;
when "11" =>
-- coverage off
when others =>
-- synthesis translate_off
report "Reached undecoded state of signal q_to_wbm" severity error;
-- synthesis translate_on
-- coverage on
end case;
elsif(data_to_fifo = '1') then
data_q <= wbm_dat_i;
tx_fifo_c_data_in <= data_q;
end if;
-- asseble tx data packet
if(write_header = "01") then
tx_fifo_c_head_in(31 downto 29) <= attr_int;
tx_fifo_c_head_in(28 downto 26) <= tc_int;
tx_fifo_c_head_in(25 downto 18) <= tag_id_int;
tx_fifo_c_head_in(17 downto 14) <= first_dw_int;
tx_fifo_c_head_in(13 downto 10) <= last_dw_int;
tx_fifo_c_head_in(9 downto 0) <= length_int;
elsif(write_header = "10") then
tx_fifo_c_head_in <= addr_int;
elsif(write_header = "11") then
tx_fifo_c_head_in(31 downto 29) <= (others => '0');
tx_fifo_c_head_in(28) <= io_wr_int;
if(io_wr_int = '1') then
tx_fifo_c_head_in(27 downto 16) <= "000000000100";
else
tx_fifo_c_head_in(27 downto 16) <= byte_count_int;
end if;
tx_fifo_c_head_in(15 downto 0) <= req_id_int;
else
tx_fifo_c_head_in <= (others => '0');
end if;
end if;
end process data_path;
-------------------------------------------------------------------------------
end architecture z091_01_wb_master_arch;
z091_01_wb_slave.vhd 0000664 0000000 0000000 00000174700 14574545710 0034401 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : new Wishbone Slave
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : wbs_new.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2015-03-10
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- Wishbone slave module to receive read and write requests from Wishbone
-- master and to return read data via completion
-- Due to different FIFO data port widths (32bit for WB, 64bit for RX & TX)
-- storing or deleting dummy packets is necessary on the WB side.
-- 1. RX storing 64bit wide -> delete 1 dummy packet on WB side
-- 2. store 1 dummy packet on WB side so that TX can read 64bit (otherwise
-- fifo_empty will not indicate 32bit contents to TX side)
-- CPLD := completion with data
-- CDC := clock domain crossing
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- * wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity z091_01_wb_slave is
generic(
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100"; -- = 1020 DW, one place spare for put_stuffing
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- Rx Module
rx_fifo_c_empty : in std_logic;
rx_fifo_c_out : in std_logic_vector(31 downto 0);
rx_fifo_c_rd_enable : out std_logic;
-- Tx Module
tx_fifo_wr_head_full : in std_logic;
tx_fifo_w_data_full : in std_logic;
tx_fifo_w_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : in std_logic_vector(6 downto 0);
tx_fifo_wr_head_clr : out std_logic;
tx_fifo_wr_head_enable : out std_logic;
tx_fifo_wr_head_in : out std_logic_vector(31 downto 0);
tx_fifo_w_data_clr : out std_logic;
tx_fifo_w_data_enable : out std_logic;
tx_fifo_w_data_in : out std_logic_vector(31 downto 0);
max_read : in std_logic_vector(2 downto 0);
-- error
error_ecrc_err : in std_logic;
error_timeout : in std_logic
);
end entity z091_01_wb_slave;
architecture z091_01_wb_slave_arch of z091_01_wb_slave is
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
WAIT_ON_FIFO, IDLE, HEADER_TO_FIFO, WR_TRANS, RD_TRANS, GET_RD_HEADER,
DROP_DATA
);
signal state : fsm_state;
-- internal signals -----------------------------------------------------------
signal tx_fifo_wr_head_en_int : std_logic; -- internal enable
signal cnt_len : std_logic_vector(9 downto 0); -- packet counter
signal cpl_return_len : std_logic_vector(9 downto 0); -- count amount of CPL data
signal put_header : std_logic; -- valid signal for put_h0_h1
signal put_h0_h1 : std_logic; -- qualify which kind of header to store
-- 0: put h0, 1: put h1
signal get_header : std_logic; -- get header info from CPLD
signal wbs_adr_int : std_logic_vector(31 downto 0); -- store wbs_adr
signal first_DW_int : std_logic_vector(3 downto 0); -- store first_DW byte enable
signal last_DW_int : std_logic_vector(3 downto 0); -- store last_DW byte enable
signal length_int : std_logic_vector(9 downto 0); -- store length returned with CPLD
signal max_read_len : std_logic_vector(9 downto 0); -- max read length for RD_TRANS
signal wr_req : std_logic; -- active while write request
signal rd_req : std_logic; -- active while read request
signal wr_burst : std_logic; -- active if burst write
signal rd_burst : std_logic; -- active if burst read
signal max_wr_len_reached : std_logic; -- break if cnt_len will wrap thus 1024DW were written to FIFO
signal multi_cpl : std_logic; -- asserted if read returned in multiple cycles
signal rd_trans_done : std_logic; -- store if WB transaction is finished
signal len_is_1024DW : std_logic; -- if asserted length is 1024
-- 1024DW is encoded as len=0 thus
-- needed to distinguish from reset value
signal compare_to_4k_len : std_logic; -- enable 4k honoring
signal to_4k_len : std_logic_vector(9 downto 0); -- DW counter which holds amount of DWs until next 4k boundary
signal requested_len : std_logic_vector(9 downto 0); -- save requested length for reads
signal act_read_size : std_logic_vector(9 downto 0); -- actual read size composed in IDLE state
-- registered signals
signal max_read_q : std_logic_vector(2 downto 0); -- used for CDC synchronization
signal max_read_qq : std_logic_vector(2 downto 0); -- used for CDC synchronization
signal put_header_q : std_logic;
signal get_header_q : std_logic; -- define 4 stages of header aquisition
signal get_header_qq : std_logic;
signal get_header_qqq : std_logic;
signal first_rd_cycle : std_logic; -- first cycle in RD_TRANS
signal wbs_tga_q : std_logic; -- registered copy of wbs_tga
-------------------------------------------------------------------------------
signal wbs_stb_d1 : std_logic;
signal tx_fifo_w_data_enable_int : std_logic;
signal dbg_resume_fifo_cmp : std_logic;
attribute noprune : boolean;
attribute noprune of dbg_resume_fifo_cmp : signal is true;
begin
tx_fifo_w_data_enable <= tx_fifo_w_data_enable_int;
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
----------------------------------------
-- assign static connections for ports
----------------------------------------
wbs_err <= error_ecrc_err or error_timeout;
tx_fifo_w_data_in <= wbs_dat_i;
wbs_dat_o <= rx_fifo_c_out;
-----------------------
-- decode max_read_qq
-----------------------
with max_read_qq select
max_read_len <= "0001000000" when "001",
"0010000000" when "010",
"0100000000" when "011",
"1000000000" when "100",
"0000000000" when "101",
"0000100000" when others;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
--------------------------------------------
-- register different signals using wb_clk
--------------------------------------------
reg_proc : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
tx_fifo_wr_head_enable <= '0';
max_read_q <= (others => '0');
max_read_qq <= (others => '0');
put_header_q <= '0';
get_header_q <= '0';
get_header_qq <= '0';
get_header_qqq <= '0';
first_rd_cycle <= '0';
wbs_tga_q <= '0';
wbs_stb_d1 <= '0';
elsif wb_clk'event and wb_clk = '1' then
tx_fifo_wr_head_enable <= tx_fifo_wr_head_en_int;
max_read_q <= max_read;
max_read_qq <= max_read_q;
put_header_q <= put_header;
get_header_q <= get_header;
get_header_qq <= get_header_q;
get_header_qqq <= get_header_qq;
first_rd_cycle <= get_header_qqq;
if state /= WAIT_ON_FIFO then
wbs_stb_d1 <= wbs_stb;
end if;
if state = HEADER_TO_FIFO then
wbs_tga_q <= wbs_tga;
end if;
end if;
end process reg_proc;
---------------------------
-- manage FSM transitions
---------------------------
fsm_transout : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
-- ports
tx_fifo_wr_head_clr <= '1';
tx_fifo_w_data_clr <= '1';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
-- internal signals
wbs_adr_int <= (others => '0');
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
elsif wb_clk'event and wb_clk = '1' then
----------DBG
if (tx_fifo_w_data_usedw > RESUME_FIFO_ACCESS) then
dbg_resume_fifo_cmp <= '1';
else
dbg_resume_fifo_cmp <= '0';
end if;
case state is
when IDLE =>
-- ports
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
-- internal signals
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
------------------------------
-- wait until active request
------------------------------
if wbs_cyc = '1' and (wbs_stb = '1' or wbs_stb_d1 = '1') then
wbs_adr_int <= wbs_adr;
first_DW_int <= wbs_sel;
----------------------------------------------------------------------------------------
-- calculate length to 4k boundary:
-- wbs_adr[12] denotes 4k boundary which is 0x1000
-- maximum transfer length is 1024DW = 1024 *4B = 4096B := 0x1000
-- => if wbs_adr[11:0] = 0b000 then all lenghts are ok
-- otherwise calculate length offset to next 4k boundary, use to_4k_len as DW counter
-- subtracting wbs_adr from the next 4k boundary results in a byte value
-- -> use 1024 instead of 4096 to calculated DW counter instead of byte counter
-- ! manage first_DW_be and last_DW_be accordingly
----------------------------------------------------------------------------------------
if wbs_adr(11 downto 0) = x"000" then
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
else
compare_to_4k_len <= '1';
to_4k_len <= std_logic_vector(to_unsigned((1024 - to_integer(unsigned(wbs_adr(11 downto 2)))), 10));
end if;
if wbs_we = '0' and wbs_cti = "010" then
rd_burst <= '1';
else
rd_burst <= '0';
end if;
-----------------------------------------------------------------------------------
-- if write request and TX data FIFO full or
-- read request and TX header FIFO full then
-- wait until FIFO is empty again
-- for both read and write requests the header FIFO must have at least 2 DW space
-- (here 3 for easier checking)
-----------------------------------------------------------------------------------
if (wbs_we = '1' and (tx_fifo_w_data_full = '1' or tx_fifo_w_data_usedw > RESUME_FIFO_ACCESS or
tx_fifo_wr_head_full = '1' or tx_fifo_wr_head_usedw(4 downto 2) = "111")) or
(wbs_we = '0' and (tx_fifo_wr_head_full = '1' or tx_fifo_wr_head_usedw(4 downto 2) = "111")) then
state <= WAIT_ON_FIFO;
elsif wbs_we = '1' and tx_fifo_w_data_full = '0' then
tx_fifo_w_data_enable_int <= '1';
wbs_ack <= '1';
wr_req <= '1';
state <= WR_TRANS;
elsif wbs_we = '0' and tx_fifo_wr_head_full = '0' then
tx_fifo_wr_head_en_int <= '1';
rd_req <= '1';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
else
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
end if;
when HEADER_TO_FIFO =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '1';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= '0';
put_header <= '1';
put_h0_h1 <= '1';
multi_cpl <= '0'; -- new read startet thus reset
first_DW_int <= first_DW_int;
last_DW_int <= last_DW_int;
cpl_return_len <= (others => '0'); -- requesting new packet thus clear cpl_return_len
rd_trans_done <= '0';
len_is_1024DW <= '0';
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
-- NOTE: this setting is not always true as this state can now be entered for wr_burst as
-- well but it has no influence on write bursts so it will remain unchanged
if wbs_cti = "010" then
rd_burst <= '1';
else
rd_burst <= '0';
end if;
----------------------------------------------------------
-- update address information for reads because multiple
-- read cycles without transition to IDLE are possible
----------------------------------------------------------
if put_header = '1' and put_header_q = '0' and rd_req = '1' then
wbs_adr_int <= wbs_adr;
else
wbs_adr_int <= wbs_adr_int;
end if;
------------------------------------------------------------------------------------
-- don't clear cnt_len for writes because this info must be stored to header first
------------------------------------------------------------------------------------
if wr_req = '1' then
cnt_len <= cnt_len;
else
-- cnt_len is not used for RD headers so it may be cleared here
cnt_len <= (others => '0');
end if;
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif put_h0_h1 = '1' then
tx_fifo_wr_head_en_int <= '0';
put_header <= '0';
put_h0_h1 <= '0';
----------------------------------------------------------------
-- 1. if max write length was reached split packet by writing
-- header and start new PCIe packet thus return to WR_TRANS
-- 2. for reads write request header first then go to RD_TRANS
-- for multiple returned CPLDs this state should not
-- be entered
-- 3. if neither write nor read request then FIFO was full
-- during start of WB transaction thus return to IDLE
----------------------------------------------------------------
if rd_req = '1' then
max_wr_len_reached <= '0';
state <= GET_RD_HEADER;
elsif wr_req = '1' and max_wr_len_reached = '1' then
max_wr_len_reached <= '0';
tx_fifo_w_data_enable_int <= '1';
wbs_ack <= '1';
first_DW_int <= x"F"; -- set value for next wr cycle
state <= WR_TRANS;
else
wr_req <= '0';
rd_req <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
rd_trans_done <= '0';
len_is_1024DW <= '0';
cpl_return_len <= (others => '0');
state <= IDLE;
end if;
else
state <= HEADER_TO_FIFO;
end if;
when RD_TRANS =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '0';
rd_burst <= rd_burst;
wr_burst <= '0';
max_wr_len_reached <= '0';
first_DW_int <= first_DW_int; -- unused for read requests
last_DW_int <= last_DW_int; -- unused for read requests
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
cpl_return_len <= cpl_return_len;
len_is_1024DW <= len_is_1024DW;
--------------------------------------------------------------------------------
-- there are several possible transitions:
-- 1. CPLD length is the same as PCIE_REQUEST_LENGTH
-- 1a. aligned address and even length => no action
-- 1b. aligned address and odd length => drop 1 dummy packet from RX FIFO
-- 1c. not aligned address and even length => drop 1 dummy packet from RX FIFO
-- 1d. not aligned address and odd length => no action
-- 2. CPLD length is smaller than PCIE_REQUEST_LENGTH (multiple CPLDs)
-- 2a. return to GET_RD_HEADER and wait for next packet
-- 2b. don't write a new header to TX header FIFO
-- 2c. manage address and length as described in 1.
-- 3. WBM finishes transfer while more data packets are in RX FIFO
-- 3a. drop data until PCIE_REQUEST_LENGTH is reached
-- 3b. remember that every split completion has its own header info included
--------------------------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif rx_fifo_c_empty = '1' and cnt_len < length_int then
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
state <= WAIT_ON_FIFO;
-------------------------
-- single read requests
-------------------------
elsif wbs_cti = ZERO_03B or (wbs_cti = FULL_03B and rd_burst = '0') then
-------------------------------------------------------------
-- aligned single requests always include a dummy packet
-- not aligned single requests never include a dummy packet
-- I/O completions are always aligned
-------------------------------------------------------------
wbs_ack <= '0';
rd_trans_done <= '1';
if wbs_tga_q = '0' and wbs_adr_int(2) = '1' then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
else
rx_fifo_c_rd_enable <= '1';
state <= DROP_DATA;
end if;
-----------------
-- end of burst
-----------------
elsif wbs_cti = FULL_03B and rd_burst = '1' then
wbs_ack <= '0';
rd_trans_done <= '1';
-------------------------------------------------------------------
-- requested length is reached and data is transferred completely
-- drop dummy packet for aligned & odd or !aligned & even
-------------------------------------------------------------------
if cpl_return_len = requested_len and cnt_len = length_int then
if (wbs_adr_int(2) = '0' and length_int(0) = '0') or
(wbs_adr_int(2) = '1' and length_int(0) = '1') then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
end if;
---------------------------------------------------------------------------
-- drop all outstanding CPLDs but capture header thus go to GET_RD_HEADER
-- from there we'll go to DROP_DATA again
---------------------------------------------------------------------------
elsif cpl_return_len < requested_len and cnt_len = length_int then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
---------------------------------
-- drop all outstanding packets
---------------------------------
else
state <= DROP_DATA;
end if;
-----------------------
-- burst still active
-----------------------
else
-----------------------------------------------------------------------------
-- when first_rd_cycle is asserted and cnt_len =0 this is a 1024DW transfer
-- -> remain in RD_TRANS
-- in case of PCIE_REQUEST_LENGTH = 1024 and full transfer then
-- cpl_return_len =0 and cpl_return_len = cnt_len would be true right
-- and we would transition to IDLE too early
-----------------------------------------------------------------------------
if first_rd_cycle = '1' and cnt_len = ZERO_10B then
state <= RD_TRANS;
elsif cnt_len = length_int and cpl_return_len = requested_len then
wbs_ack <= '0';
------------------------------------------
-- check if dummy packet must be removed
------------------------------------------
if (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
else
----------------------------------------------------------------------------------------
-- calculate length to 4k boundary:
-- wbs_adr[12] denotes 4k boundary which is 0x1000
-- maximum transfer length is 1024DW = 1024 *4B = 4096B := 0x1000
-- => if wbs_adr[11:0] = 0b000 then all lenghts are ok
-- otherwise calculate length offset to next 4k boundary, use to_4k_len as DW counter
-- subtracting wbs_adr from the next 4k boundary results in a byte value
-- -> use 1024 instead of 4096 to calculated DW counter instead of byte counter
-- ! manage first_DW_be and last_DW_be accordingly
-- wbs_adr is the last transferred address here so to_4k_len must be reduced by 4bytes
----------------------------------------------------------------------------------------
--if wbs_adr(11 downto 0) = x"000" then
if (unsigned(wbs_adr(11 downto 0)) + to_unsigned(4,12)) = x"000" then
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
else
compare_to_4k_len <= '1';
to_4k_len <= std_logic_vector(to_unsigned((1024 - to_integer(unsigned(wbs_adr(11 downto 2))) -1), 10));
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
elsif cnt_len = length_int and cpl_return_len < requested_len then
wbs_ack <= '0';
if (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
else
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
end if;
else
state <= RD_TRANS;
end if;
end if;
when WR_TRANS =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= wbs_stb;
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '1';
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '1';
rd_req <= '0';
multi_cpl <= '0';
if tx_fifo_w_data_enable_int = '1' then
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
end if;
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
wbs_adr_int <= wbs_adr_int;
first_DW_int <= first_DW_int;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
if (cnt_len = FULL_10B and tx_fifo_w_data_enable_int = '0') or
(cnt_len = std_logic_vector(unsigned(FULL_10B) - 1) and tx_fifo_w_data_enable_int = '1') then
max_wr_len_reached <= '1';
else
max_wr_len_reached <= '0';
end if;
-------------------------------------------------------------
-- stop transfer upon error timeout
-- if TX data FIFO is full suspend until space is available
-- cti = "000" and cti = "111" signal end of transfer thus
-- put header to FIFO
-- cti = "010" states ongoing burst thus stay here
-- if max wr length is reached put header to FIFO
-------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif tx_fifo_w_data_usedw >= SUSPEND_FIFO_ACCESS then
if (cnt_len(0) = '1' and tx_fifo_w_data_enable_int = '0') or
(cnt_len(0) = '0' and tx_fifo_w_data_enable_int = '1') then
-- cnt_len(0) = '0' because cnt is incremented one more time in this cycle
tx_fifo_w_data_enable_int <= '1';
else
tx_fifo_w_data_enable_int <= '0';
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
-- full FIFO and last packet of transfer could coincide and would not be covered here so use wbs_sel instead of 0xF
-- if cnt_len = 0x1 then last_DW_int must be 0x0 as single transfers only contain first_DW_int
if (cnt_len = ONE_10B and tx_fifo_w_data_enable_int = '0') or
(cnt_len = ZERO_10B and tx_fifo_w_data_enable_int = '1') then
last_DW_int <= x"0";
else
last_DW_int <= wbs_sel;
end if;
state <= HEADER_TO_FIFO;
elsif wbs_cti = "010" and wbs_cyc = '1' then
wr_burst <= '1';
if max_wr_len_reached = '1' or (compare_to_4k_len = '1' and cnt_len = to_4k_len) then
-- store dummy packet if to_4k_len is not even, max_wr_len_reached should result in even length
if (cnt_len(0) = '1' and tx_fifo_w_data_enable_int = '0') or
(cnt_len(0) = '0' and tx_fifo_w_data_enable_int = '1') then
-- cnt_len(0) = '0' because cnt is incremented one more time in this cycle
tx_fifo_w_data_enable_int <= '1';
else
tx_fifo_w_data_enable_int <= '0';
end if;
-- if cnt_len = 0x1 then last_DW_int must be 0x0 as single transfers only contain first_DW_int
if (cnt_len = ONE_10B and tx_fifo_w_data_enable_int = '0') or
(cnt_len = ZERO_10B and tx_fifo_w_data_enable_int = '1') then
last_DW_int <= x"0";
else
last_DW_int <= x"F";
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
else
state <= WR_TRANS;
end if;
else
wr_burst <= '0';
---------------------------------------------------------
-- odd lengths need one dummy packet so that 64bit side
-- can take the data from the FIFO
---------------------------------------------------------
if (cnt_len(0) = '1' and tx_fifo_w_data_enable_int = '0') or
(cnt_len(0) = '0' and tx_fifo_w_data_enable_int = '1') then
-- cnt_len(0) = '0' because cnt is incremented one more time in this cycle
tx_fifo_w_data_enable_int <= '1';
else
tx_fifo_w_data_enable_int <= '0';
end if;
----------------------------------------
-- for single writes last_DW must be 0
----------------------------------------
--TODO ITEM cti=111 is a valid equivalent for cti=000 for single!
-- idea: use signal which is set if cti=010 and which remains active (e.g. registered) to qualify cti=111 as either
-- single (extra signal=0) or burst (extra signal=1)
if (wbs_cti = "111" or wbs_cti = "010") and wr_burst = '1' and cnt_len /= ONE_10B then
last_DW_int <= wbs_sel;
else
last_DW_int <= (others => '0');
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
when WAIT_ON_FIFO =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= wr_burst;
max_wr_len_reached <= '0';
multi_cpl <= multi_cpl;
first_DW_int <= first_DW_int;
cnt_len <= cnt_len;
cpl_return_len <= cpl_return_len;
rd_trans_done <= rd_trans_done;
len_is_1024DW <= len_is_1024DW;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
---------------------------------------------------------
-- if wr_req and rd_req =0 then previous state was IDLE
-- else return to RD_TRANS or WR_TRANS respectively
---------------------------------------------------------
--------------------------------------------------------
-- for writes several FIFO states occur:
-- 1. from IDLE because TX data FIFO is full
-- wr_req is still 0 as this is set during WR_TRANS
-- 2. from WR_TRANS because data FIFO is full
-- this is managed by SUSPEND_FIFO_ACCESS and
-- RESUME_FIFO_ACCESS and wr_req = 1
--------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif wr_req = '1' and tx_fifo_w_data_full = '0' and tx_fifo_w_data_usedw <= RESUME_FIFO_ACCESS then
tx_fifo_w_data_enable_int <= '1';
wbs_ack <= '1';
state <= WR_TRANS;
------------------------------------------------------------------
-- for reads several FIFO states occur:
-- 1. from IDLE because TX header FIFO is full
-- rd_req is still 0 as this is set during HEADER_TO_FIFO
-- 2. from RD_TRANS because RX FIFO is empty
-- rd_req = 1
-- 2a. because PCIE_REQUEST_LENGTH is transferred
-- multi_cpl= 0
-- 2b. because root splits PCIE_REQUEST_LENGTH into several CPLD
-- multi_cpl= 1
-- 2c. because WBM requests more than PCIE_REQUEST_LENGTH
-- cnt_len = PCIE_REQUEST_LENGTH and wbs_cti /= 111
------------------------------------------------------------------
elsif rd_req = '1' and multi_cpl = '0' and tx_fifo_wr_head_full = '0' then
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
state <= RD_TRANS;
elsif rd_req = '1' and multi_cpl = '1' and rx_fifo_c_empty = '0' then
state <= GET_RD_HEADER;
elsif wr_req = '0' and rd_req = '0' and tx_fifo_w_data_full = '0' and tx_fifo_w_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_wr_head_full = '0' then
state <= IDLE;
else
state <= WAIT_ON_FIFO;
end if;
when GET_RD_HEADER =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
wbs_ack <= '0';
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '0';
rd_req <= '1';
wr_burst <= '0';
max_wr_len_reached <= '0';
first_DW_int <= first_DW_int;
cnt_len <= ONE_10B;
rd_trans_done <= rd_trans_done;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
------------------------------------------------------------------------
-- update internal address for multiple CPLDs to manage FIFO correctly
-- shifting length_int left by 2 is the same as *4
-- update wbs_adr_int on last valid cycle of length_int which is
-- before any header updates thus check for all get_headers=0
------------------------------------------------------------------------
if multi_cpl = '1' and rx_fifo_c_empty = '0' and get_header = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
wbs_adr_int <= std_logic_vector(unsigned(wbs_adr_int) + unsigned(length_int(7 downto 0) & "00"));
else
wbs_adr_int <= wbs_adr_int;
end if;
if rx_fifo_c_empty = '0' then
rx_fifo_c_rd_enable <= '1';
else
rx_fifo_c_rd_enable <= '0';
end if;
-----------------------------------------------------------------------------------
-- as multiple completions can occur add actual transfer length to cpl_return_len
-----------------------------------------------------------------------------------
if get_header = '1' then
cpl_return_len <= std_logic_vector(unsigned(cpl_return_len) + unsigned(length_int));
end if;
if get_header = '1' and get_header_q = '0' then
get_header <= '0';
elsif rx_fifo_c_empty = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
get_header <= '1';
end if;
------------------------------------------
-- capture if multiple CPLD will be send
-- relevant for bursts only
------------------------------------------
--if get_header_q = '1' and rd_burst = '1' and cpl_return_len < requested_len then
if get_header_q = '1' and rd_burst = '1' and (
(requested_len /= ZERO_10B and cpl_return_len < requested_len) or
(requested_len = ZERO_10B and cpl_return_len > requested_len)) then
multi_cpl <= '1';
end if;
--------------------------------------
-- 1024DW is encoded as length_int=0
-- decode to enable comparison with
-- cnt_len in RD_TRANS as cnt_len
-- has 0 as reset value
--------------------------------------
if get_header_q = '1' and length_int = ZERO_10B then
len_is_1024DW <= '1';
elsif get_header_q = '1' and length_int > ZERO_10B then
len_is_1024DW <= '0';
else
len_is_1024DW <= len_is_1024DW;
end if;
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
----------------------------------------------
-- WB transaction done but outstanding CPLDs
-- -> burst only
----------------------------------------------
elsif multi_cpl = '1' and rd_trans_done = '1' and ((wbs_adr_int(2) = '0' and get_header_qqq = '1') or (wbs_adr_int(2) = '1' and get_header_qq = '1')) then
state <= DROP_DATA;
------------------------------------------------------------
-- RX FIFO contains 4 header packets if address is aligned
-- else 3 header packets
-- I/O completions always return with lower address =0
-- thus they are always aligned!
------------------------------------------------------------
elsif (wbs_tga_q = '0' and ((wbs_adr_int(2) = '0' and get_header_qqq = '1') or (wbs_adr_int(2) = '1' and get_header_qq = '1'))) or
(wbs_tga_q = '1' and get_header_qqq = '1') then
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
state <= RD_TRANS;
else
state <= GET_RD_HEADER;
end if;
when DROP_DATA =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '0';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= wr_burst;
max_wr_len_reached <= '0';
multi_cpl <= multi_cpl;
first_DW_int <= first_DW_int;
last_DW_int <= last_DW_int;
cpl_return_len <= cpl_return_len;
rd_trans_done <= rd_trans_done;
len_is_1024DW <= len_is_1024DW;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
-----------------------------------------------------
-- remain in DROP_DATA and don't go to WAIT ON FIFO
-- if FIFO is not ready
-----------------------------------------------------
if rx_fifo_c_empty = '0' then
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
end if;
-------------------------------------------------------------------------------------
-- for I/O completions just drop one packet then go to IDLE
-- for single transmission return to IDLE when all data packets are taken from FIFO
-- for multiple CPLDs
-- 1. drop dummy data packet at the end of RD_TRANS before GET_RD_HEADER
-- 2. drop data packets because WB transaction is done including possible
-- dummy packet
-- as cnt_len now starts with 1 cnt_len can have the value cnt_len +1 = length_int
-- thus use >= for comparison
-------------------------------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable_int <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif wbs_tga_q = '1' then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
------------------------------
-- no dummy packet to remove
------------------------------
elsif cnt_len = length_int and (
(wbs_adr_int(2) = '0' and length_int(0) = '0') or
(wbs_adr_int(2) = '1' and length_int(0) = '1') ) then
if multi_cpl = '0' or (multi_cpl = '1' and cpl_return_len = requested_len) then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif multi_cpl = '1' and cpl_return_len < requested_len then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
else
state <= DROP_DATA;
end if;
---------------------------
-- dummy packet to remove
---------------------------
elsif cnt_len > length_int and (
(wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') ) then
if multi_cpl = '0' or (multi_cpl = '1' and cpl_return_len = requested_len) then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif multi_cpl = '1' and cpl_return_len < requested_len then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
else
state <= DROP_DATA;
end if;
-------------------------------------
-- length to remove not reached yet
-------------------------------------
else
state <= DROP_DATA;
end if;
-- coverage off
when others =>
-- synthesis translate_off
wbs_ack <= '0';
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
report "wrong state encoding in process fsm_transout of z091_01_wb_slave.vhd" severity error;
-- synthesis translate_on
-- coverage on
end case;
end if;
end process fsm_transout;
-------------------------------------------------------------------------------
wbs_data : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
requested_len <= (others => '0');
tx_fifo_wr_head_in <= (others => '0');
length_int <= (others => '0');
act_read_size <= (others => '0');
elsif wb_clk'event and wb_clk = '1' then
-------------------------------------------------------------------------------------
-- compose the actual maximum read size out of PCIE_REQUEST_LENGTH and max_read_len
-- CAUTION: max_read_len may not change during an ongoing burst!
-------------------------------------------------------------------------------------
if max_read_len = "0000000000" then
act_read_size <= PCIE_REQUEST_LENGTH;
elsif PCIE_REQUEST_LENGTH > max_read_len or PCIE_REQUEST_LENGTH = "0000000000" then
act_read_size <= max_read_len;
else
act_read_size <= PCIE_REQUEST_LENGTH;
end if;
-------------------------------------------------
-- assemble write request specific header parts
-------------------------------------------------
if(put_header = '1' and put_h0_h1 = '0' and wr_req = '1') then
requested_len <= (others => '0');
tx_fifo_wr_head_in(31) <= '1';
--------------------------------------------------
-- write request is done when header is composed
-- thus use registered copy of tga
--------------------------------------------------
if(wbs_tga = '0') then -- memory
tx_fifo_wr_head_in(30) <= '1';
tx_fifo_wr_head_in(29) <= '1';
else -- I/O
tx_fifo_wr_head_in(30) <= '0';
tx_fifo_wr_head_in(29) <= '0';
end if;
tx_fifo_wr_head_in(28 downto 18) <= "00000000000";
tx_fifo_wr_head_in(17 downto 14) <= first_DW_int;
tx_fifo_wr_head_in(13 downto 10) <= last_DW_int;
---------------------------------------------------------------------------------
tx_fifo_wr_head_in(9 downto 0) <= cnt_len;
------------------------------------------------
-- assemble read request specific header parts
------------------------------------------------
elsif(put_header = '1' and put_h0_h1 = '0' and rd_req = '1') then
tx_fifo_wr_head_in(31) <= '0';
tx_fifo_wr_head_in(30) <= '0';
if(wbs_tga = '0') then -- memory
tx_fifo_wr_head_in(29) <= '1';
else -- I/O
tx_fifo_wr_head_in(29) <= '0';
end if;
tx_fifo_wr_head_in(28 downto 18) <= "00000000000";
---------------------------------------
-- always request all bytes for reads
-- WBM will chose later
---------------------------------------
tx_fifo_wr_head_in(17 downto 14) <= x"F"; -- first_DW
---------------------------------------------------------------------------------------------------------------------------
-- if PCIE_REQUEST_LENGTH is max (=0), max_read_len is either =0 too then maximum size is allowed or max_read_len is /= 0
-- then max_read_len must be used -> using max_read_len for both cases is always correct
-- otherwise PCIE_REQUEST_LENGTH is only allowed if <= max_read_len
-- all values may not exceed to_4k_len if it has to be obeyed which is denoted by compare_to_4k_len
---------------------------------------------------------------------------------------------------------------------------
if wbs_cti = "000" or wbs_cti = "111" then
requested_len <= "0000000001";
tx_fifo_wr_head_in(9 downto 0) <= "0000000001";
--------------------------------
-- for single read last_DW =0!
--------------------------------
tx_fifo_wr_head_in(13 downto 10) <= x"0"; -- last_DW
else
tx_fifo_wr_head_in(13 downto 10) <= x"F"; -- last_DW
if compare_to_4k_len = '1' then
if act_read_size <= to_4k_len then
tx_fifo_wr_head_in(9 downto 0) <= act_read_size;
requested_len <= act_read_size;
else
requested_len <= to_4k_len;
tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
end if;
else
tx_fifo_wr_head_in(9 downto 0) <= act_read_size;
requested_len <= act_read_size;
end if;
--if compare_to_4k_len = '1' and to_4k_len /= "0000000000" then
-- if PCIE_REQUEST_LENGTH <= max_read_len and PCIE_REQUEST_LENGTH <= to_4k_len then
-- requested_len <= PCIE_REQUEST_LENGTH;
-- tx_fifo_wr_head_in(9 downto 0) <= PCIE_REQUEST_LENGTH;
-- elsif PCIE_REQUEST_LENGTH <= max_read_len and PCIE_REQUEST_LENGTH > to_4k_len then
-- requested_len <= to_4k_len;
-- tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
-- elsif PCIE_REQUEST_LENGTH > max_read_len and max_read_len > to_4k_len then
-- requested_len <= to_4k_len;
-- tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
-- else
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- end if;
--else
-- if(PCIE_REQUEST_LENGTH = "0000000000") then
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- elsif(PCIE_REQUEST_LENGTH <= max_read_len or max_read_len = "0000000000") then
-- requested_len <= PCIE_REQUEST_LENGTH;
-- tx_fifo_wr_head_in(9 downto 0) <= PCIE_REQUEST_LENGTH;
-- else
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- end if;
--end if;
end if;
------------------------------------------------------------------------------
-- length is for both read and write requests at the same position in header
------------------------------------------------------------------------------
elsif(put_header = '1' and put_h0_h1 = '1') then
requested_len <= requested_len;
tx_fifo_wr_head_in <= wbs_adr_int(31 downto 2) & "00";
end if;
-------------------------------------------
-- store length of this completion packet
-------------------------------------------
if state = GET_RD_HEADER and rx_fifo_c_empty = '0' and get_header = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
length_int <= rx_fifo_c_out(9 downto 0);
end if;
end if;
end process wbs_data;
end architecture z091_01_wb_slave_arch;
Synthesis/ 0000775 0000000 0000000 00000000000 14574545710 0031531 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src z91_01_syn_con.tcl 0000664 0000000 0000000 00000006746 14574545710 0034725 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Synthesis # SPDX-FileCopyrightText: 2011 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
#-------------------------------------------------------------------------------
# Title : synthesis settings for 16z091-01 on CycloneV
# Project :
#-------------------------------------------------------------------------------
# File : z91_01_syn_con.tcl
# Author : Thomas Wickleder
# Email : Thomas.Wickleder@men.de
# Organization: MEN Mikroelektronik Nuernberg GmbH
# Created : 19/04/11
#-------------------------------------------------------------------------------
# Simulator : -
# Synthesis : -
#-------------------------------------------------------------------------------
# Description :
# Created by Thomas Wickleder for G215,
# adapted by Susanne Reinfelder for 16z091-01
#-------------------------------------------------------------------------------
# Hierarchy :
# none
#-------------------------------------------------------------------------------
set_global_assignment -name VHDL_FILE "../16z000-00_src/Source/fpga_pkg_2.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/src_utils_pkg.vhd"
set_global_assignment -name VERILOG_FILE "../16z091-01_src/Source/x1/ip_compiler_for_pci_express-library/pciexp_dcram.v"
set_global_assignment -name VERILOG_FILE "../16z091-01_src/Source/x1/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v"
set_global_assignment -name VERILOG_FILE "../16z091-01_src/Source/x1/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/alt_reconf.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/x1/Hard_IP_x1_serdes.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/x1/Hard_IP_x1_core.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/x1/Hard_IP_x1.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/z091_01_wb_slave.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/z091_01_wb_master.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_put_data.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_header_fifo.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_data_fifo.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_compl_timeout.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_module.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_len_cntr.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_fifo.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_get_data.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_module.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/interrupt_wb.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/interrupt_core.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/init.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/err_fifo.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/error.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/ip_16z091_01.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/ip_16z091_01_top.vhd"
set_global_assignment -name VHDL_FILE ../Source/z091_01_wb_adr_dec.vhd
z91_01_syn_con_cyc5.tcl 0000664 0000000 0000000 00000006657 14574545710 0035651 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Synthesis # SPDX-FileCopyrightText: 2014 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
#-------------------------------------------------------------------------------
# Title : synthesis settings for 16z091-01 on CycloneV
# Project :
#-------------------------------------------------------------------------------
# File : z091_01_syn_con_cyc5.tcl
# Author : Susanne Reinfelder
# Email : susanne.reinfelder@men.de
# Organization: MEN Mikro Elektronik Nuremberg GmbH
# Created : 2014-12-03
#-------------------------------------------------------------------------------
# Simulator : -
# Synthesis : -
#-------------------------------------------------------------------------------
# Description :
# Includes all file references for CycloneV
#-------------------------------------------------------------------------------
# Hierarchy :
# none
#-------------------------------------------------------------------------------
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx
set_instance_assignment -name IO_STANDARD HCSL -to pcie_clk
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/CycV/PCIeHardIPCycV.vhd" -library PCIeHardIPCycV
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/CycV/CycVTransReconf.vhd" -library CycVTransReconf
set_global_assignment -name QIP_FILE "../16z091-01_src/Source/CycV/PCIeHardIPCycV.qip"
set_global_assignment -name QIP_FILE "../16z091-01_src/Source/CycV/CycVTransReconf.qip"
set_global_assignment -name VHDL_FILE "../16z000-00_src/Source/fpga_pkg_2.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/src_utils_pkg.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_fifo.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_data_fifo.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_header_fifo.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/err_fifo.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_len_cntr.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_get_data.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/rx_module.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/z091_01_wb_master.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/error.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_put_data.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_compl_timeout.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/tx_module.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/init.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/z091_01_wb_slave.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/interrupt_core.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/interrupt_wb.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/pcie_msi.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/ip_16z091_01.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/z091_01_wb_adr_dec.vhd"
set_global_assignment -name VHDL_FILE "../16z091-01_src/Source/ip_16z091_01_top.vhd"
z91_01_tmg_con.sdc 0000664 0000000 0000000 00000003410 14574545710 0034653 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Synthesis # SPDX-FileCopyrightText: 2011 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
#-------------------------------------------------------------------------------
# Title : 16z091-01 timing constraints
# Project : MAIN
#-------------------------------------------------------------------------------
# File : z91_01_tmg_con.sdc
# Author : Thomas Wickleder
# Email : Thomas.Wickleder@men.de
# Organization: MEN Mikro Elektronik Nuremberg GmbH
# Created : 2011-04-19
#-------------------------------------------------------------------------------
# Simulator :
#-------------------------------------------------------------------------------
# Description :
# Timing constraints for Cyclone IV. Created by Thomas Wickleder for G215,
# adapted by Susanne Reinfelder for 16z091-01.
#-------------------------------------------------------------------------------
# Hierarchy :
#-------------------------------------------------------------------------------
create_clock -name pcie_clk -period 10.000 -waveform {0.000 5.000} [get_ports {pcie_clk}]
create_clock -name pcie_sys_clk -period 8.000 -waveform {0 4} [get_nets {*altpcie_hip_pipen1b_inst|core_clk_out}] -add
set_false_path -from [get_clocks {pcie_sys_clk}] -to [get_clocks {clk_wb}]
set_false_path -from [get_clocks {clk_wb}] -to [get_clocks {pcie_sys_clk}]
set_false_path -from * -to [get_keepers {*~OBSERVABLEDPRIODISABLE*}]
set_false_path -from * -to [get_keepers {*~OBSERVABLEDPRIOLOAD*}]
set_false_path -from * -to [get_keepers {*~OBSERVABLERXANALOGRESET*}]
set_false_path -from * -to [get_keepers {*~OBSERVABLERXDIGITALRESET*}]
set_false_path -from * -to [get_keepers {*~OBSERVABLETXDIGITALRESET*}]
set_false_path -from * -to [get_keepers {*~OBSERVABLE_DIGITAL_RESET*}]
z91_01_tmg_con_cyc5.sdc 0000664 0000000 0000000 00000003375 14574545710 0035610 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z091-01_src/Synthesis # SPDX-FileCopyrightText: 2014 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
##------------------------------------------------------------------------------
## Title :
## Project :
#-------------------------------------------------------------------------------
# Title : sdc settings for 16z091-01 on CycloneV
# Project : MAIN
#-------------------------------------------------------------------------------
# File : z091_01_tmg_con_cyc5.sdc
# Author : Susanne Reinfelder
# Email : susanne.reinfelder@men.de
# Organization: MEN Mikro Elektronik Nuremberg GmbH
# Created : 2014-12-03
#-------------------------------------------------------------------------------
# Simulator :
#-------------------------------------------------------------------------------
# Description :
# Includes all timing constraints for CycloneV.
#-------------------------------------------------------------------------------
# Hierarchy :
# none
#-------------------------------------------------------------------------------
set_time_format -unit ns -decimal_places 3
#--------------------
# create PCIe clock
#--------------------
create_clock -name pcie_clk -period 10.000 -waveform {0.000 5.000} [get_ports {pcie_clk}]
#----------------------------------
# derive all PLL clocks in design
#----------------------------------
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
#-----------------------------------------------------------------
# pcie_clk and coreclkout from hard IP must be in the same group
#-----------------------------------------------------------------
set_clock_groups -exclusive -group {pcie_clk [get_clocks {ip_16z091_01_top_i0|*|coreclkout}]}
set_false_path -from pcie_rst_n -to *
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/ 0000775 0000000 0000000 00000000000 14574545710 0027605 5 ustar 00root root 0000000 0000000 Manifest.py 0000664 0000000 0000000 00000000547 14574545710 0031654 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
files = [
"Source/clk_trans_wb2wb.vhd",
"Source/fifo_d1.vhd",
"Source/switch_fab_1.vhd",
"Source/switch_fab_2.vhd",
"Source/switch_fab_3.vhd",
"Source/switch_fab_4.vhd",
"Source/wbmon64.vhd",
"Source/wbmon.vhd",
# "wb_pkg.vhd",
]
Source/ 0000775 0000000 0000000 00000000000 14574545710 0030766 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src clk_trans_wb2wb.vhd 0000664 0000000 0000000 00000025601 14574545710 0034560 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Adaption from clk a to clk b
-- Project : A15
---------------------------------------------------------------
-- File : clk_trans_wb2wb.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/03
---------------------------------------------------------------
-- Simulator : Modelsim 5.6
-- Synthesis : Leonardo/Quartus
---------------------------------------------------------------
-- Description :
--
-- This Module transforms the request and acknoledge signals to
-- connect to a a MHz internal bus. Also the data must be
-- transformed in order to fit into the a MHz clk domain.
-- The module supports posted and delayed writes:
-- POSTED_WR=true => acknowledge write access immediately
-- POSTED_WR=false => acknowledge write if access has finished on side b
---------------------------------------------------------------
-- Hierarchy:
--
-- sys_unit
-- clk_trans_wb2wb
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.7 $
--
-- $Log: clk_trans_wb2wb.vhd,v $
-- Revision 1.7 2015/09/08 17:23:00 AGeissler
-- R1: Missing reset for second clock domain
-- M1: Replaced rstn with rst_a and rst_b
--
-- Revision 1.6 2015/06/15 16:40:10 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Removed bte signals from clock trans
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.5 2012/09/07 09:59:14 MMiehling
-- added delayed write support by generic switch
--
-- Revision 1.4 2011/05/17 11:16:00 FLenhardt
-- R: Under certain conditions (e.g. when not all cycles of a Wishbone master
-- were connected to CLK_TRANS_WB2WB) a Wishbone access could happen to
-- stuck, because the clock transition was controlled only by the strobe
-- M: A Wishbone access is valid only when also at least one cycle is active
--
-- Revision 1.3 2010/03/12 13:00:27 mmiehling
-- added generic NBR_OF_CYC and NBR_OF_TGA in order to configure the bridge
--
-- Revision 1.2 2007/07/05 13:22:53 FLenhardt
-- Removed an unused signal (due to synthesis warnings)
--
-- Revision 1.1 2005/05/06 12:06:50 MMiehling
-- Initial Revision
--
-- Revision 1.2 2004/11/02 11:29:24 mmiehling
-- replaced full => full_a and full_b
--
-- Revision 1.1 2004/07/27 17:15:20 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY clk_trans_wb2wb IS
GENERIC (
POSTED_WR : boolean := TRUE;
NBR_OF_CYC : integer range 1 TO 100 := 1;
NBR_OF_TGA : integer range 1 TO 100 := 6
);
PORT (
-- a MHz domain
rst_a : IN std_logic;
clk_a : IN std_logic;
cyc_a : IN std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_a : IN std_logic; -- request signal from a MHz side
ack_a : OUT std_logic; -- adopted acknoledge signal to b MHz
err_a : OUT std_logic;
we_a : IN std_logic; -- '1' = write, '0' = read
tga_a : IN std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_a : IN std_logic_vector(2 DOWNTO 0); -- transfer type
adr_a : IN std_logic_vector(31 DOWNTO 0); -- adr from a MHz side
sel_a : IN std_logic_vector(3 DOWNTO 0); -- byte enables from a MHz side
dat_i_a : IN std_logic_vector(31 DOWNTO 0); -- data from a MHz side
dat_o_a : OUT std_logic_vector(31 DOWNTO 0); -- data from b MHz side to a MHz side
-- b MHz domain
rst_b : IN std_logic;
clk_b : IN std_logic;
cyc_b : OUT std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_b : OUT std_logic; -- request signal adopted to b MHz
ack_b : IN std_logic; -- acknoledge signal from internal bus
err_b : IN std_logic;
we_b : OUT std_logic; -- '1' = write, '0' = read
tga_b : OUT std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_b : OUT std_logic_vector(2 DOWNTO 0); -- transfer type
adr_b : OUT std_logic_vector(31 DOWNTO 0); -- adr from b MHz side
sel_b : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for b MHz side
dat_i_b : IN std_logic_vector(31 DOWNTO 0); -- data from b MHz side
dat_o_b : OUT std_logic_vector(31 DOWNTO 0) -- data from a MHz side to b MHz side
);
END clk_trans_wb2wb;
ARCHITECTURE clk_trans_wb2wb_arch OF clk_trans_wb2wb IS
COMPONENT fifo_d1
GENERIC (
width : IN integer );
PORT (
rst_a : IN std_logic;
clk_a : IN std_logic;
wr_a : IN std_logic;
data_a : IN std_logic_vector(width-1 DOWNTO 0);
full_a : OUT std_logic;
rst_b : IN std_logic;
clk_b : IN std_logic;
rd_b : IN std_logic;
data_b : OUT std_logic_vector(width-1 DOWNTO 0);
full_b : OUT std_logic
);
END COMPONENT;
TYPE ct_states IS (idle, waitstate, acknoledge);
SIGNAL ct_state : ct_states;
CONSTANT WR_FIFO_WIDTH : integer:= 69 + NBR_OF_CYC + NBR_OF_TGA; -- cyc + dat + adr + sel + we = 32+32+4+1 = 69
CONSTANT RD_FIFO_WIDTH : integer:= 32; -- dat = 32
SIGNAL ff1_rd : std_logic;
SIGNAL ff1_wr : std_logic;
SIGNAL ff1_full_a : std_logic;
SIGNAL ff1_full_b : std_logic;
SIGNAL ff2_rd : std_logic;
SIGNAL ff2_wr : std_logic;
SIGNAL ff2_full_b : std_logic;
SIGNAL stb_b_int : std_logic;
SIGNAL ff1_dat_a : std_logic_vector((WR_FIFO_WIDTH - 1) DOWNTO 0);
SIGNAL ff1_dat_b : std_logic_vector((WR_FIFO_WIDTH - 1) DOWNTO 0);
SIGNAL ack_a_int : std_logic;
BEGIN
ack_a <= ack_a_int;
stb_b <= stb_b_int;
err_a <= '0'; -- errors will not reported: error-access will never end!
ff1_dat_a <= tga_a & cyc_a & dat_i_a & adr_a & sel_a & we_a;
tga_b <= ff1_dat_b(68+NBR_OF_CYC+NBR_OF_TGA DOWNTO 69+NBR_OF_CYC);
cyc_b <= ff1_dat_b(68+NBR_OF_CYC DOWNTO 69) WHEN stb_b_int = '1' ELSE (OTHERS => '0');
dat_o_b <= ff1_dat_b(68 DOWNTO 37);
adr_b <= ff1_dat_b(36 DOWNTO 5);
sel_b <= ff1_dat_b(4 DOWNTO 1);
we_b <= ff1_dat_b(0);
cti_b <= (OTHERS => '0');
ff1 : fifo_d1
GENERIC MAP (
width => WR_FIFO_WIDTH
)
PORT MAP (
rst_a => rst_a,
clk_a => clk_a,
wr_a => ff1_wr,
data_a => ff1_dat_a,
full_a => ff1_full_a,
rst_b => rst_b,
clk_b => clk_b,
rd_b => ff1_rd,
data_b => ff1_dat_b,
full_b => ff1_full_b
);
ff2 : fifo_d1
GENERIC MAP (
width => RD_FIFO_WIDTH
)
PORT MAP (
rst_a => rst_b,
clk_a => clk_b,
wr_a => ff2_wr,
data_a => dat_i_b,
rst_b => rst_a,
clk_b => clk_a,
rd_b => ff2_rd,
data_b => dat_o_a,
full_b => ff2_full_b
);
ff1_wr <= '1' WHEN (ct_state = idle AND stb_a = '1' AND unsigned(cyc_a) /= 0 AND ff1_full_a = '0') ELSE '0';
ff2_rd <= '1' WHEN ff2_full_b = '1' ELSE '0'; -- read data from ff when available
proca : PROCESS (clk_a, rst_a)
BEGIN
IF rst_a = '1' THEN
ack_a_int <= '0';
ct_state <= idle;
ELSIF clk_a'EVENT AND clk_a = '1' THEN
CASE ct_state IS
WHEN idle =>
IF (ff1_wr = '1' AND we_a = '1') AND POSTED_WR THEN -- posted write
ct_state <= acknoledge;
ack_a_int <= '1';
ELSIF (ff1_wr = '1' AND we_a = '1') AND NOT POSTED_WR THEN -- delayed write
ct_state <= waitstate;
ack_a_int <= '0';
ELSIF (ff1_wr = '1' AND we_a = '0') THEN -- read
ct_state <= waitstate;
ack_a_int <= '0';
ELSE
ct_state <= idle;
ack_a_int <= '0';
END IF;
WHEN waitstate =>
IF ff2_full_b = '1' THEN
ct_state <= acknoledge;
ack_a_int <= '1';
ELSE
ct_state <= waitstate;
ack_a_int <= '0';
END IF;
WHEN acknoledge =>
ack_a_int <= '0';
ct_state <= idle;
WHEN OTHERS =>
ct_state <= idle;
ack_a_int <= '0';
END CASE;
END IF;
END PROCESS proca;
------------------------------------------------------------------
-- side b: stb_b is not dependent on we_a
------------------------------------------------------------------
-- for read and write equal:
ff1_rd <= '1' WHEN ((ack_b = '0' AND err_b = '0') AND ff1_full_b = '1' AND stb_b_int = '0') OR -- first data phase
((ack_b = '1' OR err_b = '1') AND ff1_full_b = '1' AND stb_b_int = '1') -- within a burst (not the last)
ELSE '0';
ff2_wr <= '1' WHEN stb_b_int = '1' AND (ack_b = '1' OR err_b = '1') AND (NOT POSTED_WR OR (ff1_dat_b(0) = '0' AND POSTED_WR)) ELSE '0'; -- store read-data
-- ack_b stb_b ff1_full stb_b(+1)
-- x 0 1 1
-- x 1 1 1
-- x 0 0 0
-- 1 1 0 0
-- 0 1 0 1
procb : PROCESS (clk_b, rst_b)
BEGIN
IF rst_b = '1' THEN
stb_b_int <= '0';
ELSIF clk_b'EVENT AND clk_b = '1' THEN
IF ff1_full_b = '1' THEN
IF stb_b_int = '0' THEN
stb_b_int <= '1'; -- start next data phase
ELSE
-- end of current data phase, start of next
stb_b_int <= '1'; -- or no end of current data phase
END IF;
ELSE
IF stb_b_int = '0' THEN -- no current access and no next access
stb_b_int <= '0';
ELSE
IF ack_b = '1' OR err_b = '1' THEN -- end of current data phase, no next
stb_b_int <= '0';
ELSE
stb_b_int <= '1'; -- no end of current data phase
END IF;
END IF;
END IF;
END IF;
END PROCESS procb;
END clk_trans_wb2wb_arch;
fifo_d1.vhd 0000664 0000000 0000000 00000007162 14574545710 0033006 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : FIFO with depth one word
-- Project :
---------------------------------------------------------------
-- File : fifo_d1.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 23/06/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- This module describes a fifo with depth one word.
-- No EAB-Block is required, just registers.
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: fifo_d1.vhd,v $
-- Revision 1.3 2015/09/08 17:22:58 AGeissler
-- R1: Missing reset for second clock domain
-- M1: Replaced rstn with rst_a and rst_b
--
-- Revision 1.2 2015/06/15 16:40:08 AGeissler
-- R1: Clearness
-- M1: Replaced tabs with spaces
--
-- Revision 1.1 2005/05/06 12:06:49 MMiehling
-- Initial Revision
--
-- Revision 1.2 2004/11/02 11:29:27 mmiehling
-- added regs for full/empty signals
--
-- Revision 1.1 2004/07/27 17:15:22 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fifo_d1 IS
GENERIC (
width : IN integer:=8
);
PORT (
rst_a : IN std_logic;
clk_a : IN std_logic;
wr_a : IN std_logic;
data_a : IN std_logic_vector(width-1 DOWNTO 0);
full_a : OUT std_logic;
rst_b : IN std_logic;
clk_b : IN std_logic;
rd_b : IN std_logic;
data_b : OUT std_logic_vector(width-1 DOWNTO 0);
full_b : OUT std_logic
);
END fifo_d1;
ARCHITECTURE fifo_d1_arch OF fifo_d1 IS
SIGNAL wr_ptr : std_logic;
SIGNAL rd_ptr : std_logic;
SIGNAL wr_ptr_b : std_logic;
SIGNAL rd_ptr_a : std_logic;
SIGNAL full_a_int : std_logic;
SIGNAL full_b_int : std_logic;
SIGNAL data_a_q : std_logic_vector(width-1 DOWNTO 0);
BEGIN
full_a_int <= '1' WHEN (wr_ptr = '1' AND rd_ptr_a = '0') OR (wr_ptr = '0' AND rd_ptr_a = '1') ELSE '0';
full_a <= full_a_int;
full_b_int <= '1' WHEN (wr_ptr_b = '1' AND rd_ptr = '0') OR (wr_ptr_b = '0' AND rd_ptr = '1') ELSE '0';
full_b <= full_b_int;
proca : PROCESS (clk_a, rst_a)
BEGIN
IF rst_a = '1' THEN
data_a_q <= (OTHERS => '0');
wr_ptr <= '0';
rd_ptr_a <= '0';
ELSIF clk_a'EVENT AND clk_a = '1' THEN
rd_ptr_a <= rd_ptr;
IF wr_a = '1' AND full_a_int = '0' THEN
data_a_q <= data_a;
wr_ptr <= NOT wr_ptr;
END IF;
END IF;
END PROCESS proca;
procb : PROCESS (clk_b, rst_b)
BEGIN
IF rst_b = '1' THEN
data_b <= (OTHERS => '0');
rd_ptr <= '0';
wr_ptr_b <= '0';
ELSIF clk_b'EVENT AND clk_b = '1' THEN
wr_ptr_b <= wr_ptr;
IF rd_b = '1' AND full_b_int = '1' THEN
data_b <= data_a_q;
rd_ptr <= NOT rd_ptr;
END IF;
END IF;
END PROCESS procb;
END fifo_d1_arch;
switch_fab_1.vhd 0000664 0000000 0000000 00000006551 14574545710 0034031 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------------
-- File : switch_fab_1.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 13/08/07
---------------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------------
-- Description :
--!\reqid
--!\upreqid
---------------------------------------------------------------------
--!\hierarchy
--!\endofhierarchy
---------------------------------------------------------------------
--
---------------------------------------------------------------------
-- History
---------------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: switch_fab_1.vhd,v $
-- Revision 1.4 2015/06/15 16:39:52 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.3 2009/07/29 14:05:11 FLenhardt
-- Fixed bug (WB slave strobe had been activated without addressing)
--
-- Revision 1.2 2007/08/13 17:04:22 FWombacher
-- fixed typos
--
-- Revision 1.1 2007/08/13 16:28:20 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_1 IS
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- wb-bus #0
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
-- wb-bus to slave
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_1;
ARCHITECTURE switch_fab_1_arch OF switch_fab_1 IS
SIGNAL wbi_slave_stb : std_logic;
BEGIN
wbi_slave_cyc <= cyc_0;
wbi_slave.stb <= wbi_slave_stb;
ack_0 <= wbo_slave.ack AND wbi_slave_stb;
err_0 <= wbo_slave.err AND wbi_slave_stb;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave_stb <= '0';
END IF;
END IF;
END PROCESS;
END switch_fab_1_arch;
switch_fab_2.vhd 0000664 0000000 0000000 00000030601 14574545710 0034023 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : switch_fab_2.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: switch_fab_2.vhd,v $
-- Revision 1.3 2015/06/15 16:39:54 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.2 2007/08/13 10:14:19 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.1 2004/08/13 15:16:05 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:48 mmiehling
-- Initial Revision
--
-- Revision 1.2 2004/07/27 17:06:19 mmiehling
-- multifunction added
--
-- Revision 1.1 2004/04/29 15:07:24 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_2 IS
GENERIC (
registered : IN boolean );
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_2;
ARCHITECTURE switch_fab_2_arch OF switch_fab_2 IS
SUBTYPE sw_states IS std_logic_vector(1 DOWNTO 0);
CONSTANT sw_0 : sw_states := "01";
CONSTANT sw_1 : sw_states := "10";
-- TYPE sw_states IS (sw_0, sw_1);
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL ack_0_int : std_logic;
SIGNAL ack_1_int : std_logic;
SIGNAL sel : std_logic_vector(1 DOWNTO 0);
SIGNAL wbi_slave_stb : std_logic;
BEGIN
without_q : IF NOT registered GENERATE
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
END GENERATE without_q;
---------------------------------------------------------------------
with_q : IF registered GENERATE
ack_0 <= ack_0_int;
ack_1 <= ack_1_int;
wbi_slave.stb <= wbi_slave_stb;
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_state <= sw_0;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF (wbo_slave.ack = '1' OR ack_0_int = '1') AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
sw_state <= sw_1;
wbi_slave_stb <= wbo_1.stb;
ELSE
sw_state <= sw_0;
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_state <= sw_1;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- single
wbi_slave_stb <= wbo_1.stb;
ELSIF (wbo_slave.ack = '1' OR ack_1_int = '1') AND wbo_1.cti /= "010" THEN -- burst
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= wbo_0.stb;
ELSE
sw_state <= sw_1;
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
sw_state <= sw_0;
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN sel <= "01";
ELSIF cyc_1 = '1' THEN sel <= "10";
ELSE sel <= "00";
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN sel <= "10";
ELSIF cyc_0 = '1' THEN sel <= "01";
ELSE sel <= "00";
END IF;
WHEN OTHERS => sel <= "00";
END CASE;
END PROCESS sw_fsm_sel;
data_sw : PROCESS( clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave.dat <= (OTHERS => '0');
wbi_slave.adr <= (OTHERS => '0');
wbi_slave.sel <= (OTHERS => '0');
wbi_slave.we <= '0';
wbi_slave_cyc <= '0';
ack_0_int <= '0';
err_0 <= '0';
ack_1_int <= '0';
err_1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
wbi_slave_cyc <= sel(0) OR sel(1);
IF sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_0_int <= '1';
ELSE
ack_0_int <= '0';
END IF;
IF sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_0 <= '1';
ELSE
err_0 <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_1_int <= '1';
ELSE
ack_1_int <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_1 <= '1';
ELSE
err_1 <= '0';
END IF;
CASE sel IS
WHEN "01" => wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
WHEN OTHERS => wbi_slave.dat <= wbo_1.dat;
wbi_slave.adr <= wbo_1.adr;
wbi_slave.sel <= wbo_1.sel;
wbi_slave.we <= wbo_1.we;
wbi_slave.cti <= wbo_1.cti;
wbi_slave.tga <= wbo_1.tga;
END CASE;
END IF;
END PROCESS data_sw;
END GENERATE with_q;
END switch_fab_2_arch;
switch_fab_3.vhd 0000664 0000000 0000000 00000042223 14574545710 0034027 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : switch_fab_3.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: switch_fab_3.vhd,v $
-- Revision 1.4 2015/06/15 16:39:57 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.3 2007/08/13 10:14:21 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.2 2007/04/04 13:15:15 smahveen
-- cyc_x handling in SW_2 corrected.
-- (FSM state will not change after WB Master-3 access wishbone slave in SW_2 state)
--
-- Revision 1.1 2004/08/13 15:16:06 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:49 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:06:21 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/04/29 15:07:24 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_3 IS
GENERIC (
registered : IN boolean );
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
cyc_2 : IN std_logic;
ack_2 : OUT std_logic;
err_2 : OUT std_logic;
wbo_2 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_3;
ARCHITECTURE switch_fab_3_arch OF switch_fab_3 IS
SUBTYPE sw_states IS std_logic_vector(1 DOWNTO 0);
CONSTANT sw_0 : sw_states := "01";
CONSTANT sw_1 : sw_states := "10";
CONSTANT sw_2 : sw_states := "11";
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL ack_0_int : std_logic;
SIGNAL ack_1_int : std_logic;
SIGNAL ack_2_int : std_logic;
SIGNAL sel : std_logic_vector(2 DOWNTO 0);
SIGNAL wbi_slave_stb : std_logic;
BEGIN
without_q : IF NOT registered GENERATE
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_2.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_2.stb;
ELSIF wbo_slave.ack = '1' AND wbo_2.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_2.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1, cyc_2)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_2;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat, wbo_2.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN sw_2 => wbi_slave.dat <= wbo_2.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr, wbo_2.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN sw_2 => wbi_slave.adr <= wbo_2.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel, wbo_2.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN sw_2 => wbi_slave.sel <= wbo_2.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we, wbo_2.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN sw_2 => wbi_slave.we <= wbo_2.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti, wbo_2.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN sw_2 => wbi_slave.cti <= wbo_2.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga, wbo_2.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN sw_2 => wbi_slave.tga <= wbo_2.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') OR (sw_state = sw_2 AND cyc_2 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.ack = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
END GENERATE without_q;
---------------------------------------------------------------------
with_q : IF registered GENERATE
ack_0 <= ack_0_int;
ack_1 <= ack_1_int;
ack_2 <= ack_2_int;
wbi_slave.stb <= wbi_slave_stb;
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_state <= sw_0;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF (wbo_slave.ack = '1' OR ack_0_int = '1') AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
sw_state <= sw_1;
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
sw_state <= sw_2;
wbi_slave_stb <= wbo_2.stb;
ELSE
sw_state <= sw_0;
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_state <= sw_1;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- single
wbi_slave_stb <= wbo_0.stb;
ELSIF (wbo_slave.ack = '1' OR ack_1_int = '1') AND wbo_1.cti /= "010" THEN -- burst
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_2 = '1' THEN
sw_state <= sw_2;
wbi_slave_stb <= wbo_2.stb;
ELSE
sw_state <= sw_1;
wbi_slave_stb <= '0';
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
sw_state <= sw_2;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_2.cti = "010" THEN -- single
wbi_slave_stb <= wbo_2.stb;
ELSIF (wbo_slave.ack = '1' OR ack_2_int = '1') AND wbo_2.cti /= "010" THEN -- burst
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_2.stb;
END IF;
ELSIF cyc_0 = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
sw_state <= sw_1;
wbi_slave_stb <= wbo_1.stb;
ELSE
sw_state <= sw_2;
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
sw_state <= sw_0;
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1, cyc_2)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN sel <= "001";
ELSIF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_2 = '1' THEN sel <= "100";
ELSE sel <= "000";
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_2 = '1' THEN sel <= "100";
ELSIF cyc_0 = '1' THEN sel <= "001";
ELSE sel <= "000";
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN sel <= "100";
ELSIF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_0 = '1' THEN sel <= "001";
ELSE sel <= "000";
END IF;
WHEN OTHERS => sel <= "000";
END CASE;
END PROCESS sw_fsm_sel;
data_sw : PROCESS( clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave.dat <= (OTHERS => '0');
wbi_slave.adr <= (OTHERS => '0');
wbi_slave.sel <= (OTHERS => '0');
wbi_slave.cti <= (OTHERS => '0');
wbi_slave.tga <= (OTHERS => '0');
wbi_slave.we <= '0';
wbi_slave_cyc <= '0';
ack_0_int <= '0';
err_0 <= '0';
ack_1_int <= '0';
err_1 <= '0';
ack_2_int <= '0';
err_2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
wbi_slave_cyc <= sel(0) OR sel(1) OR sel(2);
IF sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_0_int <= '1';
ELSE
ack_0_int <= '0';
END IF;
IF sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_0 <= '1';
ELSE
err_0 <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_1_int <= '1';
ELSE
ack_1_int <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_1 <= '1';
ELSE
err_1 <= '0';
END IF;
IF sw_state = sw_2 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_2_int <= '1';
ELSE
ack_2_int <= '0';
END IF;
IF sw_state = sw_2 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_2 <= '1';
ELSE
err_2 <= '0';
END IF;
CASE sel IS
WHEN "001" => wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
WHEN "010" => wbi_slave.dat <= wbo_1.dat;
wbi_slave.adr <= wbo_1.adr;
wbi_slave.sel <= wbo_1.sel;
wbi_slave.we <= wbo_1.we;
wbi_slave.cti <= wbo_1.cti;
wbi_slave.tga <= wbo_1.tga;
WHEN OTHERS => wbi_slave.dat <= wbo_2.dat;
wbi_slave.adr <= wbo_2.adr;
wbi_slave.sel <= wbo_2.sel;
wbi_slave.we <= wbo_2.we;
wbi_slave.cti <= wbo_2.cti;
wbi_slave.tga <= wbo_2.tga;
END CASE;
END IF;
END PROCESS data_sw;
END GENERATE with_q;
END switch_fab_3_arch;
switch_fab_4.vhd 0000664 0000000 0000000 00000030667 14574545710 0034041 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : switch_fab_4.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.6 $
--
-- $Log: switch_fab_4.vhd,v $
-- Revision 1.6 2015/06/15 16:39:59 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.5 2007/08/13 13:58:56 FWombacher
-- added intermediate for output wbi_slave_cyc
--
-- Revision 1.4 2007/08/13 10:14:24 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.3 2005/02/09 14:29:20 mmiehling
-- sw_2 and sw_3 does not work correct
--
-- Revision 1.2 2005/01/18 15:17:29 mmiehling
-- changed muxes to process structure
--
-- Revision 1.1 2004/08/13 15:16:07 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:51 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:06:23 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/04/29 15:07:24 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_4 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
cyc_2 : IN std_logic;
ack_2 : OUT std_logic;
err_2 : OUT std_logic;
wbo_2 : IN wbo_type;
cyc_3 : IN std_logic;
ack_3 : OUT std_logic;
err_3 : OUT std_logic;
wbo_3 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_4;
ARCHITECTURE switch_fab_4_arch OF switch_fab_4 IS
SUBTYPE sw_states IS std_logic_vector(2 DOWNTO 0);
CONSTANT sw_0 : sw_states := "001";
CONSTANT sw_1 : sw_states := "010";
CONSTANT sw_2 : sw_states := "011";
CONSTANT sw_3 : sw_states := "100";
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL ack_0_int : std_logic;
SIGNAL ack_1_int : std_logic;
SIGNAL ack_2_int : std_logic;
SIGNAL ack_3_int : std_logic;
SIGNAL wbi_slave_stb : std_logic;
SIGNAL wbi_slave_cyc_q : std_logic;
BEGIN
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSIF cyc_3 = '1' THEN
wbi_slave_stb <= wbo_3.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSIF cyc_3 = '1' THEN
wbi_slave_stb <= wbo_3.stb;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_2.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_2.stb;
ELSIF wbo_slave.ack = '1' AND wbo_2.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_2.stb;
END IF;
ELSIF cyc_3 = '1' THEN
wbi_slave_stb <= wbo_3.stb;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_3 =>
IF cyc_3 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_3.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_3.stb;
ELSIF wbo_slave.ack = '1' AND wbo_3.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_3.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1, cyc_2, cyc_3)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_3 = '1' THEN
sw_nxt_state <= sw_3;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_3 = '1' THEN
sw_nxt_state <= sw_3;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_3 = '1' THEN
sw_nxt_state <= sw_3;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_2;
END IF;
WHEN sw_3 =>
IF cyc_3 = '1' THEN
sw_nxt_state <= sw_3;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSE
sw_nxt_state <= sw_3;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat, wbo_2.dat, wbo_3.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN sw_2 => wbi_slave.dat <= wbo_2.dat;
WHEN sw_3 => wbi_slave.dat <= wbo_3.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr, wbo_2.adr, wbo_3.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN sw_2 => wbi_slave.adr <= wbo_2.adr;
WHEN sw_3 => wbi_slave.adr <= wbo_3.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel, wbo_2.sel, wbo_3.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN sw_2 => wbi_slave.sel <= wbo_2.sel;
WHEN sw_3 => wbi_slave.sel <= wbo_3.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we, wbo_2.we, wbo_3.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN sw_2 => wbi_slave.we <= wbo_2.we;
WHEN sw_3 => wbi_slave.we <= wbo_3.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti, wbo_2.cti, wbo_3.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN sw_2 => wbi_slave.cti <= wbo_2.cti;
WHEN sw_3 => wbi_slave.cti <= wbo_3.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga, wbo_2.tga, wbo_3.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN sw_2 => wbi_slave.tga <= wbo_2.tga;
WHEN sw_3 => wbi_slave.tga <= wbo_3.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc_q <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') OR (sw_state = sw_2 AND cyc_2 = '1') OR (sw_state = sw_3 AND cyc_3 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
ack_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.ack = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
ack_3 <= '1' WHEN sw_state = sw_3 AND wbo_slave.ack = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
err_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.err = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
err_3 <= '1' WHEN sw_state = sw_3 AND wbo_slave.err = '1' AND wbi_slave_cyc_q = '1' ELSE '0';
wbi_slave_cyc <= wbi_slave_cyc_q;
---------------------------------------------------------------------
END switch_fab_4_arch;
wb_pkg.vhd 0000664 0000000 0000000 00000214170 14574545710 0032747 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : system unit package
-- Project : Embedded System Module
---------------------------------------------------------------
-- File : wb_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 17/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Package for wishbone bus functions.
-- Consists of data mux for x chip selects.
-- Wishbone bus input and output type definition.
-- This package is used for wb_bus (busmaker).
--
-- Switch-fab naming convention is:
-- All signal names are based on the source of the signal
-- (wbo_slave = output singals of slave)
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.15 $
--
-- $Log: wb_pkg.vhd,v $
-- Revision 1.15 2015/06/15 16:40:01 AGeissler
-- R1: Clearness
-- M1: Replaced tabs with spaces
--
-- Revision 1.14 2014/03/11 13:51:10 AVieira
-- R: data_mux for 16 and 1-bit are not necessary; WB bte signal unused
-- M: data_mux for 16 and 1-bit removed; WB bte signal removed from wbi_type/wbo_type
--
-- Revision 1.13 2014/03/10 16:29:54 avieira
-- R: data muxes for unconstrained array data input not supported
-- M: added new data_mux implementations and unconstrained array times for 64/32/16 bits data
--
-- Revision 1.12 2014/02/28 10:27:01 avieira
-- R: 64-bit support missing
-- M: Added 64-bit types
--
-- Revision 1.11 2009/07/29 14:05:13 FLenhardt
-- Fixed bug in SWITCH_FAB (WB slave strobe had been activated without addressing)
--
-- Revision 1.10 2007/08/24 11:15:23 FLenhardt
-- Re-added procedure SWITCH_FAB for backward compatibility
--
-- Revision 1.9 2007/08/13 16:28:35 MMiehling
-- moved switch_fab to entity switch_fab_1
--
-- Revision 1.8 2007/08/13 13:58:58 FWombacher
-- fixed typos
--
-- Revision 1.7 2007/08/13 10:14:26 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.6 2006/05/18 16:14:32 twickleder
-- added data_mux for 23 slaves
--
-- Revision 1.5 2006/05/09 11:57:29 twickleder
-- added data_mux for 21 and 22 slaves
--
-- Revision 1.4 2006/02/24 16:09:39 TWickleder
-- Added DATA_MUX procedure with 20 data inputs
--
-- Revision 1.3 2006/02/17 13:54:20 flenhardt
-- Added DATA_MUX procedure with 19 data inputs
--
-- Revision 1.2 2005/12/13 13:48:56 flenhardt
-- Added DATA_MUX procedure with 18 data inputs
--
-- Revision 1.1 2004/08/13 15:16:09 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:52 mmiehling
-- Initial Revision
--
-- Revision 1.6 2004/07/27 17:06:24 mmiehling
-- multifunction added
--
-- Revision 1.4 2004/05/13 14:21:25 MMiehling
-- multifunction device
--
-- Revision 1.3 2004/04/29 15:07:22 MMiehling
-- removed switch_fab from pkg, now new entity
--
-- Revision 1.2 2004/04/27 09:37:42 MMiehling
-- now correct signal names and wb-types
--
-- Revision 1.3 2004/04/14 16:54:50 MMiehling
-- now correct switch_fab io's
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE wb_pkg IS
TYPE wbo_type IS record
stb : std_logic;
sel : std_logic_vector(3 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
END record;
TYPE wbi_type IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
END record;
TYPE wbo_type_64 IS record
stb : std_logic;
sel : std_logic_vector(7 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(63 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
END record;
TYPE wbi_type_64 IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(63 DOWNTO 0);
END record;
TYPE slv64_arr IS array (natural range <>) OF std_logic_vector(63 DOWNTO 0);
TYPE slv32_arr IS array (natural range <>) OF std_logic_vector(31 DOWNTO 0);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv64_arr;
SIGNAL data_out : OUT std_logic_vector(63 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv32_arr;
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_in_22 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) ;
END wb_pkg;
PACKAGE BODY wb_pkg IS
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv64_arr;
SIGNAL data_out : OUT std_logic_vector(63 DOWNTO 0)
) IS
BEGIN
FOR i IN 0 TO cyc'HIGH LOOP
IF cyc(i) = '1' THEN
data_out <= data_in(i);
END IF;
END LOOP;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv32_arr;
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
FOR i IN 0 TO cyc'HIGH LOOP
IF cyc(i) = '1' THEN
data_out <= data_in(i);
END IF;
END LOOP;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "01" => data_out <= data_in_0;
WHEN "10" => data_out <= data_in_1;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "001" => data_out <= data_in_0;
WHEN "010" => data_out <= data_in_1;
WHEN "100" => data_out <= data_in_2;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0001" => data_out <= data_in_0;
WHEN "0010" => data_out <= data_in_1;
WHEN "0100" => data_out <= data_in_2;
WHEN "1000" => data_out <= data_in_3;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00001" => data_out <= data_in_0;
WHEN "00010" => data_out <= data_in_1;
WHEN "00100" => data_out <= data_in_2;
WHEN "01000" => data_out <= data_in_3;
WHEN "10000" => data_out <= data_in_4;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000001" => data_out <= data_in_0;
WHEN "000010" => data_out <= data_in_1;
WHEN "000100" => data_out <= data_in_2;
WHEN "001000" => data_out <= data_in_3;
WHEN "010000" => data_out <= data_in_4;
WHEN "100000" => data_out <= data_in_5;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000001" => data_out <= data_in_0;
WHEN "0000010" => data_out <= data_in_1;
WHEN "0000100" => data_out <= data_in_2;
WHEN "0001000" => data_out <= data_in_3;
WHEN "0010000" => data_out <= data_in_4;
WHEN "0100000" => data_out <= data_in_5;
WHEN "1000000" => data_out <= data_in_6;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000001" => data_out <= data_in_0;
WHEN "00000010" => data_out <= data_in_1;
WHEN "00000100" => data_out <= data_in_2;
WHEN "00001000" => data_out <= data_in_3;
WHEN "00010000" => data_out <= data_in_4;
WHEN "00100000" => data_out <= data_in_5;
WHEN "01000000" => data_out <= data_in_6;
WHEN "10000000" => data_out <= data_in_7;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000001" => data_out <= data_in_0;
WHEN "000000010" => data_out <= data_in_1;
WHEN "000000100" => data_out <= data_in_2;
WHEN "000001000" => data_out <= data_in_3;
WHEN "000010000" => data_out <= data_in_4;
WHEN "000100000" => data_out <= data_in_5;
WHEN "001000000" => data_out <= data_in_6;
WHEN "010000000" => data_out <= data_in_7;
WHEN "100000000" => data_out <= data_in_8;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000001" => data_out <= data_in_0;
WHEN "0000000010" => data_out <= data_in_1;
WHEN "0000000100" => data_out <= data_in_2;
WHEN "0000001000" => data_out <= data_in_3;
WHEN "0000010000" => data_out <= data_in_4;
WHEN "0000100000" => data_out <= data_in_5;
WHEN "0001000000" => data_out <= data_in_6;
WHEN "0010000000" => data_out <= data_in_7;
WHEN "0100000000" => data_out <= data_in_8;
WHEN "1000000000" => data_out <= data_in_9;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000001" => data_out <= data_in_0;
WHEN "00000000010" => data_out <= data_in_1;
WHEN "00000000100" => data_out <= data_in_2;
WHEN "00000001000" => data_out <= data_in_3;
WHEN "00000010000" => data_out <= data_in_4;
WHEN "00000100000" => data_out <= data_in_5;
WHEN "00001000000" => data_out <= data_in_6;
WHEN "00010000000" => data_out <= data_in_7;
WHEN "00100000000" => data_out <= data_in_8;
WHEN "01000000000" => data_out <= data_in_9;
WHEN "10000000000" => data_out <= data_in_10;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000001" => data_out <= data_in_0;
WHEN "000000000010" => data_out <= data_in_1;
WHEN "000000000100" => data_out <= data_in_2;
WHEN "000000001000" => data_out <= data_in_3;
WHEN "000000010000" => data_out <= data_in_4;
WHEN "000000100000" => data_out <= data_in_5;
WHEN "000001000000" => data_out <= data_in_6;
WHEN "000010000000" => data_out <= data_in_7;
WHEN "000100000000" => data_out <= data_in_8;
WHEN "001000000000" => data_out <= data_in_9;
WHEN "010000000000" => data_out <= data_in_10;
WHEN "100000000000" => data_out <= data_in_11;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000001" => data_out <= data_in_0;
WHEN "0000000000010" => data_out <= data_in_1;
WHEN "0000000000100" => data_out <= data_in_2;
WHEN "0000000001000" => data_out <= data_in_3;
WHEN "0000000010000" => data_out <= data_in_4;
WHEN "0000000100000" => data_out <= data_in_5;
WHEN "0000001000000" => data_out <= data_in_6;
WHEN "0000010000000" => data_out <= data_in_7;
WHEN "0000100000000" => data_out <= data_in_8;
WHEN "0001000000000" => data_out <= data_in_9;
WHEN "0010000000000" => data_out <= data_in_10;
WHEN "0100000000000" => data_out <= data_in_11;
WHEN "1000000000000" => data_out <= data_in_12;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000001" => data_out <= data_in_0;
WHEN "00000000000010" => data_out <= data_in_1;
WHEN "00000000000100" => data_out <= data_in_2;
WHEN "00000000001000" => data_out <= data_in_3;
WHEN "00000000010000" => data_out <= data_in_4;
WHEN "00000000100000" => data_out <= data_in_5;
WHEN "00000001000000" => data_out <= data_in_6;
WHEN "00000010000000" => data_out <= data_in_7;
WHEN "00000100000000" => data_out <= data_in_8;
WHEN "00001000000000" => data_out <= data_in_9;
WHEN "00010000000000" => data_out <= data_in_10;
WHEN "00100000000000" => data_out <= data_in_11;
WHEN "01000000000000" => data_out <= data_in_12;
WHEN "10000000000000" => data_out <= data_in_13;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000001" => data_out <= data_in_0;
WHEN "000000000000010" => data_out <= data_in_1;
WHEN "000000000000100" => data_out <= data_in_2;
WHEN "000000000001000" => data_out <= data_in_3;
WHEN "000000000010000" => data_out <= data_in_4;
WHEN "000000000100000" => data_out <= data_in_5;
WHEN "000000001000000" => data_out <= data_in_6;
WHEN "000000010000000" => data_out <= data_in_7;
WHEN "000000100000000" => data_out <= data_in_8;
WHEN "000001000000000" => data_out <= data_in_9;
WHEN "000010000000000" => data_out <= data_in_10;
WHEN "000100000000000" => data_out <= data_in_11;
WHEN "001000000000000" => data_out <= data_in_12;
WHEN "010000000000000" => data_out <= data_in_13;
WHEN "100000000000000" => data_out <= data_in_14;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000001" => data_out <= data_in_0;
WHEN "0000000000000010" => data_out <= data_in_1;
WHEN "0000000000000100" => data_out <= data_in_2;
WHEN "0000000000001000" => data_out <= data_in_3;
WHEN "0000000000010000" => data_out <= data_in_4;
WHEN "0000000000100000" => data_out <= data_in_5;
WHEN "0000000001000000" => data_out <= data_in_6;
WHEN "0000000010000000" => data_out <= data_in_7;
WHEN "0000000100000000" => data_out <= data_in_8;
WHEN "0000001000000000" => data_out <= data_in_9;
WHEN "0000010000000000" => data_out <= data_in_10;
WHEN "0000100000000000" => data_out <= data_in_11;
WHEN "0001000000000000" => data_out <= data_in_12;
WHEN "0010000000000000" => data_out <= data_in_13;
WHEN "0100000000000000" => data_out <= data_in_14;
WHEN "1000000000000000" => data_out <= data_in_15;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000001" => data_out <= data_in_0;
WHEN "00000000000000010" => data_out <= data_in_1;
WHEN "00000000000000100" => data_out <= data_in_2;
WHEN "00000000000001000" => data_out <= data_in_3;
WHEN "00000000000010000" => data_out <= data_in_4;
WHEN "00000000000100000" => data_out <= data_in_5;
WHEN "00000000001000000" => data_out <= data_in_6;
WHEN "00000000010000000" => data_out <= data_in_7;
WHEN "00000000100000000" => data_out <= data_in_8;
WHEN "00000001000000000" => data_out <= data_in_9;
WHEN "00000010000000000" => data_out <= data_in_10;
WHEN "00000100000000000" => data_out <= data_in_11;
WHEN "00001000000000000" => data_out <= data_in_12;
WHEN "00010000000000000" => data_out <= data_in_13;
WHEN "00100000000000000" => data_out <= data_in_14;
WHEN "01000000000000000" => data_out <= data_in_15;
WHEN "10000000000000000" => data_out <= data_in_16;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000100" => data_out <= data_in_2;
WHEN "000000000000001000" => data_out <= data_in_3;
WHEN "000000000000010000" => data_out <= data_in_4;
WHEN "000000000000100000" => data_out <= data_in_5;
WHEN "000000000001000000" => data_out <= data_in_6;
WHEN "000000000010000000" => data_out <= data_in_7;
WHEN "000000000100000000" => data_out <= data_in_8;
WHEN "000000001000000000" => data_out <= data_in_9;
WHEN "000000010000000000" => data_out <= data_in_10;
WHEN "000000100000000000" => data_out <= data_in_11;
WHEN "000001000000000000" => data_out <= data_in_12;
WHEN "000010000000000000" => data_out <= data_in_13;
WHEN "000100000000000000" => data_out <= data_in_14;
WHEN "001000000000000000" => data_out <= data_in_15;
WHEN "010000000000000000" => data_out <= data_in_16;
WHEN "100000000000000000" => data_out <= data_in_17;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000100000" => data_out <= data_in_5;
WHEN "0000000000001000000" => data_out <= data_in_6;
WHEN "0000000000010000000" => data_out <= data_in_7;
WHEN "0000000000100000000" => data_out <= data_in_8;
WHEN "0000000001000000000" => data_out <= data_in_9;
WHEN "0000000010000000000" => data_out <= data_in_10;
WHEN "0000000100000000000" => data_out <= data_in_11;
WHEN "0000001000000000000" => data_out <= data_in_12;
WHEN "0000010000000000000" => data_out <= data_in_13;
WHEN "0000100000000000000" => data_out <= data_in_14;
WHEN "0001000000000000000" => data_out <= data_in_15;
WHEN "0010000000000000000" => data_out <= data_in_16;
WHEN "0100000000000000000" => data_out <= data_in_17;
WHEN "1000000000000000000" => data_out <= data_in_18;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000100000" => data_out <= data_in_5;
WHEN "00000000000001000000" => data_out <= data_in_6;
WHEN "00000000000010000000" => data_out <= data_in_7;
WHEN "00000000000100000000" => data_out <= data_in_8;
WHEN "00000000001000000000" => data_out <= data_in_9;
WHEN "00000000010000000000" => data_out <= data_in_10;
WHEN "00000000100000000000" => data_out <= data_in_11;
WHEN "00000001000000000000" => data_out <= data_in_12;
WHEN "00000010000000000000" => data_out <= data_in_13;
WHEN "00000100000000000000" => data_out <= data_in_14;
WHEN "00001000000000000000" => data_out <= data_in_15;
WHEN "00010000000000000000" => data_out <= data_in_16;
WHEN "00100000000000000000" => data_out <= data_in_17;
WHEN "01000000000000000000" => data_out <= data_in_18;
WHEN "10000000000000000000" => data_out <= data_in_19;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000000100" => data_out <= data_in_2;
WHEN "000000000000000001000" => data_out <= data_in_3;
WHEN "000000000000000010000" => data_out <= data_in_4;
WHEN "000000000000000100000" => data_out <= data_in_5;
WHEN "000000000000001000000" => data_out <= data_in_6;
WHEN "000000000000010000000" => data_out <= data_in_7;
WHEN "000000000000100000000" => data_out <= data_in_8;
WHEN "000000000001000000000" => data_out <= data_in_9;
WHEN "000000000010000000000" => data_out <= data_in_10;
WHEN "000000000100000000000" => data_out <= data_in_11;
WHEN "000000001000000000000" => data_out <= data_in_12;
WHEN "000000010000000000000" => data_out <= data_in_13;
WHEN "000000100000000000000" => data_out <= data_in_14;
WHEN "000001000000000000000" => data_out <= data_in_15;
WHEN "000010000000000000000" => data_out <= data_in_16;
WHEN "000100000000000000000" => data_out <= data_in_17;
WHEN "001000000000000000000" => data_out <= data_in_18;
WHEN "010000000000000000000" => data_out <= data_in_19;
WHEN "100000000000000000000" => data_out <= data_in_20;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000000100000" => data_out <= data_in_5;
WHEN "0000000000000001000000" => data_out <= data_in_6;
WHEN "0000000000000010000000" => data_out <= data_in_7;
WHEN "0000000000000100000000" => data_out <= data_in_8;
WHEN "0000000000001000000000" => data_out <= data_in_9;
WHEN "0000000000010000000000" => data_out <= data_in_10;
WHEN "0000000000100000000000" => data_out <= data_in_11;
WHEN "0000000001000000000000" => data_out <= data_in_12;
WHEN "0000000010000000000000" => data_out <= data_in_13;
WHEN "0000000100000000000000" => data_out <= data_in_14;
WHEN "0000001000000000000000" => data_out <= data_in_15;
WHEN "0000010000000000000000" => data_out <= data_in_16;
WHEN "0000100000000000000000" => data_out <= data_in_17;
WHEN "0001000000000000000000" => data_out <= data_in_18;
WHEN "0010000000000000000000" => data_out <= data_in_19;
WHEN "0100000000000000000000" => data_out <= data_in_20;
WHEN "1000000000000000000000" => data_out <= data_in_21;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_in_22 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000000100000" => data_out <= data_in_5;
WHEN "00000000000000001000000" => data_out <= data_in_6;
WHEN "00000000000000010000000" => data_out <= data_in_7;
WHEN "00000000000000100000000" => data_out <= data_in_8;
WHEN "00000000000001000000000" => data_out <= data_in_9;
WHEN "00000000000010000000000" => data_out <= data_in_10;
WHEN "00000000000100000000000" => data_out <= data_in_11;
WHEN "00000000001000000000000" => data_out <= data_in_12;
WHEN "00000000010000000000000" => data_out <= data_in_13;
WHEN "00000000100000000000000" => data_out <= data_in_14;
WHEN "00000001000000000000000" => data_out <= data_in_15;
WHEN "00000010000000000000000" => data_out <= data_in_16;
WHEN "00000100000000000000000" => data_out <= data_in_17;
WHEN "00001000000000000000000" => data_out <= data_in_18;
WHEN "00010000000000000000000" => data_out <= data_in_19;
WHEN "00100000000000000000000" => data_out <= data_in_20;
WHEN "01000000000000000000000" => data_out <= data_in_21;
WHEN "10000000000000000000000" => data_out <= data_in_22;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) IS
BEGIN
IF rst = '1' THEN
wbi_slave.stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave.stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave.stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave.stb <= '0';
ELSE
wbi_slave.stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave.stb <= '0';
END IF;
END IF;
wbi_slave_cyc <= cyc_0;
ack_0 <= wbo_slave.ack;
err_0 <= wbo_slave.err;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
END switch_fab;
END;
wbmon.vhd 0000664 0000000 0000000 00000054101 14574545710 0032614 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : wbmon.vhd
-- Author : Michael Ernst
-- Email :
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 21/09/04
---------------------------------------------------------------
-- Simulator : Modelsim Altera 5.8g
-- Synthesis : --
---------------------------------------------------------------
-- Description : This Wishbone Monitor asserts that all signals
-- and transaction on a wishbone bus are handled
-- correct. It outputs errors on std_out and the
-- rest into a file
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- Version| Author | Mod. Date | Changes Made:
-- v0.1 | Ernst | 21/09/04 | first code
--
-- $Revision: 1.8 $
--
-- $Log: wbmon.vhd,v $
-- Revision 1.8 2015/06/15 16:40:04 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Removed bte signals from wishbone monitor
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.7 2010/03/01 09:28:34 SKrieger
-- R: Evaluation of master outputs / slave inputs should be done when stb and cyc are both different from '0'.
-- M: Changed accordingly
--
-- Revision 1.6 2008/10/27 08:42:22 skrieger
-- R: The wrong address is displayed during an access (lower than 32 bit) to a not 32-bit-alligned address. Example: 8-bit access to address 0x00000001
-- is displayed as 8-bit access to address 0x00000000 but with the same data.
-- M: Changed data output that a 32-bit-alligned address will be output but with the correct data and with the corresponding select-lines.
--
-- Revision 1.5 2008/07/04 11:25:09 mernst
-- - Added enable signal for simulation (use signal_force to deactivate output temporarily)
-- - Data lines are only checked while they have to be valid now
--
-- Revision 1.4 2007/11/20 11:55:46 FWombacher
-- Cosmetics: Removed obsoltete address decoding
--
-- Revision 1.3 2005/09/15 08:18:17 flenhardt
-- Fixed bug in error indication
--
-- Revision 1.2 2005/04/29 08:23:05 MMiehling
-- added reset values
--
-- Revision 1.1 2005/02/07 13:09:30 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
--
--Errorcoding:
--
-- 0x00
-- Acknowledge without Strobe or cycle:
-- an Acknowledge was given by the module alltough the module was not
-- addressed with strobe or cycle
--
-- 0x01
-- Address changed during transaction!
-- The address changed during a normal cycle or within a burst cycle
-- Not if it happens in a burst cycle it only asserts inside a single
-- transaction of the burst, address increment is handled in error 0x09
--
-- 0x02
-- Data in of slave changed during transaction!
-- data in of the slave changed during a write cycle
--
-- 0x03
-- Select Bits changed during transaction!
--
-- 0x04
-- CTI changed during transaction!
--
-- 0x05
-- Burst with not allowed cti:
-- in the current wishbone specification only cti of 000,010,111 are defined
--
-- 0x07
-- WE changed during burst!
--
-- 0x08
-- SEL changed during burst!
--
-- 0x09
-- wrong address increment or address changed during burst cycle:
-- the address has to increment by 4 in burst mode
--
-- 0x0a
-- Missing End Of Burst:
-- the end of a burst has to be shown by setting cti to 111 in the last
-- burst cycle. This signal is missing here
--
-- 0x0b
-- We changed during transaction!
--
-- 0x0c
-- Sel changed during transaction!
--
-- 0x0d
-- Strobe went low without acknowledge:
-- no acknowledge was given by the module but strobe was reset to 0
--
-- 0x0e
-- U Z X in statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
USE std.textio.all;
USE ieee.std_logic_textio.all;
-- synthesis translate_on
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY wbmon IS
GENERIC(
wbname : string := "wbmon";
-- Output Settings
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic;
er : OUT std_logic;
co : OUT std_logic_vector(7 DOWNTO 0)
);
END wbmon;
ARCHITECTURE wbmon_arch OF wbmon IS
function to_string
(
constant val : in std_logic_vector
) return string is
constant reglen : INTEGER := val'LENGTH;
variable result_str : string(1 to reglen);
variable slv : std_logic_vector(1 to reglen) := val;
begin
for i in reglen downto 1 loop
case slv(i) is
when 'U' => result_str(i) := 'U';
when 'X' => result_str(i) := 'X';
when '0' => result_str(i) := '0';
when '1' => result_str(i) := '1';
when 'Z' => result_str(i) := 'Z';
when 'W' => result_str(i) := 'W';
when 'L' => result_str(i) := 'L';
when 'H' => result_str(i) := 'H';
when '-' => result_str(i) := '-';
when others => -- an unknown std_logic value was passed
assert false
report "to_string -- unknown std_logic_vector value"
severity error;
end case;
end loop;
return result_str;
end;
FUNCTION to_hstring
(
CONSTANT bitaccess : IN natural;
CONSTANT val : in std_logic_vector--(7 DOWNTO 0)
) RETURN string is
VARIABLE reglen : natural := 1;
VARIABLE result_str : string(1 to (bitaccess / 4));
VARIABLE slv : std_logic_vector(bitaccess-1 DOWNTO 0);-- := val;
VARIABLE temp : std_logic_vector(3 DOWNTO 0);
BEGIN
slv := val;
IF bitaccess = 8 THEN
reglen := 1;
ELSIF bitaccess = 16 THEN
reglen := 3;
ELSIF bitaccess = 32 THEN
reglen := 7;
ELSIF bitaccess = 64 THEN
reglen := 15;
ELSE
END IF;
FOR i in reglen DOWNTO 0 LOOP
temp := slv(i*4 + 3 DOWNTO (i *4));
CASE temp IS
WHEN "0000" => result_str(reglen + 1 - i) := '0';
WHEN "0001" => result_str(reglen + 1 - i) := '1';
WHEN "0010" => result_str(reglen + 1 - i) := '2';
WHEN "0011" => result_str(reglen + 1 - i) := '3';
WHEN "0100" => result_str(reglen + 1 - i) := '4';
WHEN "0101" => result_str(reglen + 1 - i) := '5';
WHEN "0110" => result_str(reglen + 1 - i) := '6';
WHEN "0111" => result_str(reglen + 1 - i) := '7';
WHEN "1000" => result_str(reglen + 1 - i) := '8';
WHEN "1001" => result_str(reglen + 1 - i) := '9';
WHEN "1010" => result_str(reglen + 1 - i) := 'A';
WHEN "1011" => result_str(reglen + 1 - i) := 'B';
WHEN "1100" => result_str(reglen + 1 - i) := 'C';
WHEN "1101" => result_str(reglen + 1 - i) := 'D';
WHEN "1110" => result_str(reglen + 1 - i) := 'E';
WHEN "1111" => result_str(reglen + 1 - i) := 'F';
WHEN others => result_str(reglen + 1 - i) := ' ';
-- an unknown std_logic value was passed
END CASE;
END LOOP;
RETURN result_str;
END;
FUNCTION data_out (bsel : std_logic_vector(3 downto 0); dat : std_logic_vector(31 downto 0)) RETURN string IS
variable byte0 : string(1 to 2);
variable byte1 : string(1 to 2);
variable byte2 : string(1 to 2);
variable byte3 : string(1 to 2);
BEGIN
if bsel(0) = '1' then
byte0 := to_hstring(8,dat( 7 downto 0));
else
byte0 := "XX";
end if;
if bsel(1) = '1' then
byte1 := to_hstring(8,dat(15 downto 8));
else
byte1 := "XX";
end if;
if bsel(2) = '1' then
byte2 := to_hstring(8,dat(23 downto 16));
else
byte2 := "XX";
end if;
if bsel(3) = '1' then
byte3 := to_hstring(8,dat(31 downto 24));
else
byte3 := "XX";
end if;
return (byte3 & byte2 & "_" & byte1 & byte0);
end data_out;
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
)
IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
IF NOT(condition) AND enable = '1' THEN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " 0x");
hwrite(wl, code);
WRITELINE(Output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
IF (sev = ERROR) THEN
e := '1';
c := code;
END IF;
END IF;
END;
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
addr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
) IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, addr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 4);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 8);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
END;
-- SIGNALS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Write_Mode
IS wbname & "_transcript.txt"; -- Write- File
-- synthesis translate_on
TYPE wb_state_type IS (IDLE, CYCLE, BURST);
SIGNAL wb_state : wb_state_type;
SIGNAL adr_s : std_logic_vector(31 DOWNTO 0);
SIGNAL sldat_i_s : std_logic_vector(31 DOWNTO 0);
SIGNAL we_s : std_logic;
SIGNAL cti_s : std_logic_vector(2 DOWNTO 0);
SIGNAL sel_s : std_logic_vector (3 DOWNTO 0);
SIGNAL cti_b : std_logic_vector(2 DOWNTO 0);
SIGNAL sldat_i_b : std_logic_vector(31 DOWNTO 0);
SIGNAL new_b : std_logic;
SIGNAL enable : std_logic;
BEGIN
enable <= '1';
-- synthesis translate_off
PROCESS(clk)
VARIABLE burststr : string (1 TO 5);
BEGIN
IF rising_edge(clk) THEN
IF (cti /= "000") THEN
burststr := "Burst";
ELSE
burststr := " ";
END IF;
IF (ack = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burststr, NOTE, adr, sldat_i, " --> OK");
ELSE
outp_cycle("Read Cycle " & burststr, NOTE, adr, sldat_o, " --> OK");
END IF;
END IF;
IF (err = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burststr, NOTE, adr, sldat_i, " --> ERROR");
ELSE
outp_cycle("Read Cycle " & burststr, NOTE, adr, sldat_o, " --> ERROR");
END IF;
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
-- Create Cycle start time
PROCESS(clk, rst)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF (rst = '1') THEN
sel_s <= (OTHERS => '0');
adr_s <= (OTHERS => '0');
sldat_i_s <= (OTHERS => '0');
sldat_i_b <= (OTHERS => '0');
we_s <= '0';
new_b <= '0';
e := '0';
c := (OTHERS => '0');
er <= '0';
co <= (OTHERS => '0');
cti_b <= (OTHERS => '0');
cti_s <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
CASE wb_state IS
WHEN IDLE =>
IF (stb = '1' AND cyc = '1') THEN
IF (cti = "111" OR cti = "000") THEN
-- Normal Cycle SAVE DATA
wb_state <= CYCLE;
cti_s <= cti;
adr_s <= adr;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "010") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' THEN
adr_s <= adr + 4;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSE
outp(e,c,"Unsupported CTI " & to_string(cti),x"05", enable , ERROR);
END IF;
IF ack = '1' THEN
IF cti /= "010" THEN
-- stay in idle if single cycle with acknowledge
wb_state <= IDLE;
END IF;
END IF;
ELSE
IF ack = '1' THEN
outp(e,c,"acknowledge without cycle and/or strobe",x"00", enable , ERROR);
END IF;
END IF;
WHEN BURST =>
IF (cti /= "010" AND cti /="111") THEN
-- ERROR missing End of burst
outp(e,c,"Missing end of burst", x"0a", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
-- CHECK SIGNALS which can change after ack
IF (new_b = '1') THEN
cti_b <= cti;
sldat_i_b <= sldat_i;
new_b <= '0';
ELSE
outp(e,c,"CTI changed during burst cycle ("&to_string(cti)&" sb "&to_string(cti_b)&")", x"04", enable , ERROR, cti = cti_b);
outp(e,c,"Master Data Out changed during burst cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_b)&")", x"02", enable , ERROR, sldat_i = sldat_i_b OR we = '0');
END IF;
IF (ack = '1' AND cti = "111") THEN
-- End of Burst
wb_state <= IDLE;
ELSIF (ack = '1') THEN
-- Addrress Increment on acknowledge
adr_s <= adr_s + 4;
new_b <= '1';
wb_state <= BURST;
END IF;
-- CHECK SIGNALS:
-- we has to stay the same throughout the burst
outp(e,c,"We changed during burst (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"07", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during burst (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"09", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during burst ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"08", enable , ERROR, sel = sel_s);
WHEN CYCLE =>
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge ", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (ack = '1') THEN
wb_state <= IDLE;
END IF;
-- we has to stay the same throughout the burst
outp(e,c,"We changed during cycle (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"0b", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during cycle (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"01", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during cycle ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"0c", enable , ERROR, sel = sel_s);
outp(e,c,"CTI changed during cycle ("&to_string(cti)&" sb "&to_string(cti_s)&")", x"04", enable , ERROR, cti = cti_s);
outp(e,c,"Master Data Out changed during cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_s)&")", x"02", enable , ERROR, sldat_i = sldat_i_s OR we = '0');
WHEN OTHERS =>
ASSERT FALSE REPORT "AHH OHHHHHHH" SEVERITY failure;
END CASE;
co <= c;
er <= e;
END IF;
END PROCESS;
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS( clk, rst, cyc, stb, we, ack, err, cti, adr, sldat_i, sldat_o, sel, enable)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF(NOT (NOW = 0 ps)) THEN
IF (rst = '0' OR rst = 'U') AND (cyc = 'U' OR cyc = 'Z' OR cyc = 'X') THEN
outp(e,c,"cyc is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (clk = 'U' OR clk = 'Z' OR clk = 'X') THEN
outp(e,c,"clk is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (stb = 'U' OR stb = 'Z' OR stb = 'X') THEN
outp(e,c,"stb is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (we = 'U' OR we = 'Z' OR we = 'X') AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"we is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (ack = 'U' OR ack = 'Z' OR ack = 'X') THEN
outp(e,c,"ack is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (err = 'U' OR err = 'Z' OR err = 'X') THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sel) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(cti) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"cti is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(adr) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"adr is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_i) AND cyc /= '0' AND stb = '1' THEN
outp(e,c,"data_in is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_o) AND ack /= '0' THEN
outp(e,c,"data_o is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
END wbmon_arch; wbmon64.vhd 0000664 0000000 0000000 00000060414 14574545710 0032772 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : wbmon64.vhd
-- Author : Michael Ernst
-- Email :
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 21/09/04
---------------------------------------------------------------
-- Simulator : Modelsim Altera 5.8g
-- Synthesis : --
---------------------------------------------------------------
-- Description : This Wishbone Monitor asserts that all signals
-- and transaction on a wishbone bus are handled
-- correct. It outputs errors on std_out and the
-- rest into a file
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- Version| Author | Mod. Date | Changes Made:
-- v0.1 | Ernst | 21/09/04 | first code
--
-- $Revision: 1.5 $
--
-- $Log: wbmon64.vhd,v $
-- Revision 1.5 2015/06/15 16:40:06 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Removed bte signals from wishbone monitor
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.4 2010/03/01 09:28:36 SKrieger
-- R: Evaluation of master outputs / slave inputs should be done when stb and cyc are both different from '0'.
-- M: Changed accordingly
--
-- Revision 1.3 2009/09/30 07:14:35 mmiehling
-- added cti=011 support
--
-- Revision 1.2 2008/12/08 09:30:30 mmiehling
-- added unaligned read burst support
--
-- Revision 1.1 2008/10/08 17:25:49 mmiehling
-- Initial Revision
--
-- Revision 1.1 2008/09/16 09:33:52 mmiehling
-- Initial Revision
--
-- Revision 1.5 2008/07/04 11:25:09 mernst
-- - Added enable signal for simulation (use signal_force to deactivate output temporarily)
-- - Data lines are only checked while they have to be valid now
--
-- Revision 1.4 2007/11/20 11:55:46 FWombacher
-- Cosmetics: Removed obsoltete address decoding
--
-- Revision 1.3 2005/09/15 08:18:17 flenhardt
-- Fixed bug in error indication
--
-- Revision 1.2 2005/04/29 08:23:05 MMiehling
-- added reset values
--
-- Revision 1.1 2005/02/07 13:09:30 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
--
--Errorcoding:
--
-- 0x00
-- Acknowledge without Strobe or cycle:
-- an Acknowledge was given by the module alltough the module was not
-- addressed with strobe or cycle
--
-- 0x01
-- Address changed during transaction!
-- The address changed during a normal cycle or within a burst cycle
-- Not if it happens in a burst cycle it only asserts inside a single
-- transaction of the burst, address increment is handled in error 0x09
--
-- 0x02
-- Data in of slave changed during transaction!
-- data in of the slave changed during a write cycle
--
-- 0x03
-- Select Bits changed during transaction!
--
-- 0x04
-- CTI changed during transaction!
--
-- 0x05
-- Burst with not allowed cti:
-- in the current wishbone specification only cti of 000,010,111 are defined
--
-- 0x07
-- WE changed during burst!
--
-- 0x08
-- SEL changed during burst!
--
-- 0x09
-- wrong address increment or address changed during burst cycle:
-- the address has to increment by 4 in burst mode
--
-- 0x0a
-- Missing End Of Burst:
-- the end of a burst has to be shown by setting cti to 111 in the last
-- burst cycle. This signal is missing here
--
-- 0x0b
-- We changed during transaction!
--
-- 0x0c
-- Sel changed during transaction!
--
-- 0x0d
-- Strobe went low without acknowledge:
-- no acknowledge was given by the module but strobe was reset to 0
--
-- 0x0e
-- U Z X in statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
USE std.textio.all;
USE ieee.std_logic_textio.all;
-- synthesis translate_on
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY wbmon64 IS
GENERIC(
wbname : string := "wbmon";
-- Output Settings
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(63 DOWNTO 0);
sldat_o : IN std_logic_vector(63 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
sel : IN std_logic_vector(7 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic;
er : OUT std_logic;
co : OUT std_logic_vector(7 DOWNTO 0)
);
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
);
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(63 DOWNTO 0);
ende : string := "OK"
);
END wbmon64;
ARCHITECTURE wbmon64_arch OF wbmon64 IS
function to_string
(
constant val : in std_logic_vector
) return string is
constant reglen : INTEGER := val'LENGTH;
variable result_str : string(1 to reglen);
variable slv : std_logic_vector(1 to reglen) := val;
begin
for i in reglen downto 1 loop
case slv(i) is
when 'U' => result_str(i) := 'U';
when 'X' => result_str(i) := 'X';
when '0' => result_str(i) := '0';
when '1' => result_str(i) := '1';
when 'Z' => result_str(i) := 'Z';
when 'W' => result_str(i) := 'W';
when 'L' => result_str(i) := 'L';
when 'H' => result_str(i) := 'H';
when '-' => result_str(i) := '-';
when others => -- an unknown std_logic value was passed
assert false
report "to_string -- unknown std_logic_vector value"
severity error;
end case;
end loop;
return result_str;
end;
FUNCTION to_hstring
(
CONSTANT val : in std_logic_vector(31 DOWNTO 0)
) RETURN string is
CONSTANT reglen : natural := 7;
VARIABLE result_str : string(1 to reglen + 1);
VARIABLE slv : std_logic_vector(31 DOWNTO 0) := val;
VARIABLE temp : std_logic_vector(3 DOWNTO 0);
BEGIN
FOR i in reglen DOWNTO 0 LOOP
temp := slv(i*4 + 3 DOWNTO (i *4));
CASE temp IS
WHEN "0000" => result_str(8 - i) := '0';
WHEN "0001" => result_str(8 - i) := '1';
WHEN "0010" => result_str(8 - i) := '2';
WHEN "0011" => result_str(8 - i) := '3';
WHEN "0100" => result_str(8 - i) := '4';
WHEN "0101" => result_str(8 - i) := '5';
WHEN "0110" => result_str(8 - i) := '6';
WHEN "0111" => result_str(8 - i) := '7';
WHEN "1000" => result_str(8 - i) := '8';
WHEN "1001" => result_str(8 - i) := '9';
WHEN "1010" => result_str(8 - i) := 'a';
WHEN "1011" => result_str(8 - i) := 'b';
WHEN "1100" => result_str(8 - i) := 'c';
WHEN "1101" => result_str(8 - i) := 'd';
WHEN "1110" => result_str(8 - i) := 'e';
WHEN "1111" => result_str(8 - i) := 'f';
WHEN others => result_str(8 - i) := ' ';
-- an unknown std_logic value was passed
END CASE;
END LOOP;
RETURN result_str;
END;
FUNCTION to_hstring64
(
CONSTANT val : in std_logic_vector(63 DOWNTO 0)
) RETURN string is
VARIABLE temp : string (1 TO 16);
BEGIN
temp := to_hstring(val(63 DOWNTO 32))&to_hstring(val(31 DOWNTO 0));
RETURN temp;
END;
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
)
IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
VARIABLE ol : line;
-- synthesis translate_on
BEGIN
IF NOT(condition) AND enable = '1' THEN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " 0x");
hwrite(wl, code);
WRITELINE(Output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
IF (sev = ERROR) THEN
e := '1';
c := code;
END IF;
END IF;
END;
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(63 DOWNTO 0);
ende : string := "OK"
) IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" DATA: "));
IF sel(7) = '1' THEN
hwrite(wl,data(63 DOWNTO 56));
END IF;
IF sel(6) = '1' THEN
hwrite(wl,data(55 DOWNTO 48));
END IF;
IF sel(5) = '1' THEN
hwrite(wl,data(47 DOWNTO 40));
END IF;
IF sel(4) = '1' THEN
hwrite(wl,data(39 DOWNTO 32));
END IF;
IF sel(3) = '1' THEN
hwrite(wl,data(31 DOWNTO 24));
END IF;
IF sel(2) = '1' THEN
hwrite(wl,data(23 DOWNTO 16));
END IF;
IF sel(1) = '1' THEN
hwrite(wl,data(15 DOWNTO 8));
END IF;
IF sel(0) = '1' THEN
hwrite(wl,data(7 DOWNTO 0));
END IF;
write(wl,string'(" SEL: "));
hwrite(wl, sel);
-- Output ende
WRITE(wl, ende);
WRITELINE(output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" DATA: "));
IF sel(7) = '1' THEN
hwrite(wl,data(63 DOWNTO 56));
END IF;
IF sel(6) = '1' THEN
hwrite(wl,data(55 DOWNTO 48));
END IF;
IF sel(5) = '1' THEN
hwrite(wl,data(47 DOWNTO 40));
END IF;
IF sel(4) = '1' THEN
hwrite(wl,data(39 DOWNTO 32));
END IF;
IF sel(3) = '1' THEN
hwrite(wl,data(31 DOWNTO 24));
END IF;
IF sel(2) = '1' THEN
hwrite(wl,data(23 DOWNTO 16));
END IF;
IF sel(1) = '1' THEN
hwrite(wl,data(15 DOWNTO 8));
END IF;
IF sel(0) = '1' THEN
hwrite(wl,data(7 DOWNTO 0));
END IF;
write(wl,string'(" SEL: "));
hwrite(wl, sel);
-- Output ende
WRITE(wl, ende);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
END;
-- SIGNALS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Write_Mode
IS wbname & "_transcript.txt"; -- Write- File
-- synthesis translate_on
TYPE wb_state_type IS (IDLE, CYCLE, BURST);
SIGNAL wb_state : wb_state_type;
SIGNAL adr_s : std_logic_vector(31 DOWNTO 0);
SIGNAL sldat_i_s : std_logic_vector(63 DOWNTO 0);
SIGNAL we_s : std_logic;
SIGNAL cti_s : std_logic_vector(2 DOWNTO 0);
SIGNAL sel_s : std_logic_vector (7 DOWNTO 0);
SIGNAL cti_b : std_logic_vector(2 DOWNTO 0);
SIGNAL sldat_i_b : std_logic_vector(63 DOWNTO 0);
SIGNAL new_b : std_logic;
SIGNAL enable : std_logic;
BEGIN
enable <= '1';
-- synthesis translate_off
PROCESS(clk)
VARIABLE burst : string (1 TO 5);
BEGIN
IF rising_edge(clk) THEN
IF (cti /= "000") THEN
burst := "Burst";
ELSE
burst := " ";
END IF;
IF (ack = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> OK");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> OK");
END IF;
END IF;
IF (err = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> ERROR");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> ERROR");
END IF;
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
-- Create Cycle start time
PROCESS(clk)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF (rst = '1') THEN
sel_s <= (OTHERS => '0');
adr_s <= (OTHERS => '0');
sldat_i_s <= (OTHERS => '0');
sldat_i_b <= (OTHERS => '0');
we_s <= '0';
new_b <= '0';
e := '0';
c := (OTHERS => '0');
er <= '0';
co <= (OTHERS => '0');
cti_b <= (OTHERS => '0');
cti_s <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
CASE wb_state IS
WHEN IDLE =>
IF (stb = '1' AND cyc = '1') THEN
IF (cti = "111" OR cti = "000") THEN
-- Normal Cycle SAVE DATA
wb_state <= CYCLE;
cti_s <= cti;
adr_s <= adr;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "010") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' THEN
adr_s <= adr + 8;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "011") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' AND adr(4 DOWNTO 3) = "11" THEN
adr_s <= adr - 24;
ELSIF ack = '1' THEN
adr_s <= adr + 8;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSE
outp(e,c,"Unsupported CTI " & to_string(cti),x"05", enable , ERROR);
END IF;
IF ack = '1' THEN
IF cti /= "010" AND cti /= "011" THEN
-- stay in idle if single cycle with acknowledge
wb_state <= IDLE;
END IF;
END IF;
ELSE
IF ack = '1' THEN
outp(e,c,"acknowledge without cycle and/or strobe",x"00", enable , ERROR);
END IF;
END IF;
WHEN BURST =>
IF (cti /= "010" AND cti /= "011" AND cti /="111") THEN
-- ERROR missing End of burst
outp(e,c,"Missing end of burst", x"0a", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
-- CHECK SIGNALS which can change after ack
IF (new_b = '1') THEN
cti_b <= cti;
sldat_i_b <= sldat_i;
new_b <= '0';
ELSE
outp(e,c,"CTI changed during burst cycle ("&to_string(cti)&" sb "&to_string(cti_b)&")", x"04", enable , ERROR, cti = cti_b);
outp(e,c,
"Master Data Out changed during burst cycle (0x"&to_hstring64(sldat_i)&" sb 0x"&to_hstring64(sldat_i_b)&")",
x"02",
enable ,
ERROR,
sldat_i = sldat_i_b OR we = '0');
END IF;
IF (ack = '1' AND cti = "111") THEN
-- End of Burst
wb_state <= IDLE;
ELSIF (ack = '1' AND (cti = "011" OR cti_b = "011") AND adr_s(4 DOWNTO 3) = "11") THEN
-- Addrress Increment on acknowledge for unaligned burst
adr_s <= adr_s - 24;
new_b <= '1';
wb_state <= BURST;
ELSIF (ack = '1') THEN
-- Addrress Increment on acknowledge
adr_s <= adr_s + 8;
new_b <= '1';
wb_state <= BURST;
END IF;
-- CHECK SIGNALS:
-- we has to stay the same throughout the burst
outp(e,c,"We changed during burst (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"07", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during burst (0x"&to_hstring(adr)&" sb 0x"&to_hstring(adr_s)&")", x"09", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during burst ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"08", enable , ERROR, sel = sel_s);
WHEN CYCLE =>
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge ", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (ack = '1') THEN
wb_state <= IDLE;
END IF;
-- we has to stay the same throughout the burst
outp(e,c,"We changed during cycle (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"0b", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during cycle (0x"&to_hstring(adr)&" sb 0x"&to_hstring(adr_s)&")", x"01", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during cycle ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"0c", enable , ERROR, sel = sel_s);
outp(e,c,"CTI changed during cycle ("&to_string(cti)&" sb "&to_string(cti_s)&")", x"04", enable , ERROR, cti = cti_s);
outp(e,c,"Master Data Out changed during cycle (0x"&to_hstring64(sldat_i)&" sb 0x"&to_hstring64(sldat_i_s)&")", x"02", enable , ERROR, sldat_i = sldat_i_s OR we = '0');
WHEN OTHERS =>
ASSERT FALSE REPORT "AHH OHHHHHHH" SEVERITY failure;
END CASE;
co <= c;
er <= e;
END IF;
END PROCESS;
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS( clk, rst, cyc, stb, we, ack, err, cti, adr, sldat_i, sldat_o)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF(NOT (NOW = 0 ps)) THEN
IF (rst = '0' OR rst = 'U') AND (cyc = 'U' OR cyc = 'Z' OR cyc = 'X') THEN
outp(e,c,"cyc is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (clk = 'U' OR clk = 'Z' OR clk = 'X') THEN
outp(e,c,"clk is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (stb = 'U' OR stb = 'Z' OR stb = 'X') THEN
outp(e,c,"stb is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (we = 'U' OR we = 'Z' OR we = 'X') AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"we is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (ack = 'U' OR ack = 'Z' OR ack = 'X') THEN
outp(e,c,"ack is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (err = 'U' OR err = 'Z' OR err = 'X') THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sel) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(cti) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"cti is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(adr) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"adr is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_i) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"data_in is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_o) AND ack /= '0' THEN
outp(e,c,"data_o is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
END wbmon64_arch; Synthesis/ 0000775 0000000 0000000 00000000000 14574545710 0031517 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src constraints_16z100.tcl 0000664 0000000 0000000 00000001464 14574545710 0035520 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z100-00_src/Synthesis # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
# files to be included
set_global_assignment -name VHDL_FILE "../16z100-00_src/Source/wb_pkg.vhd"
set_global_assignment -name VHDL_FILE "../16z100-00_src/Source/switch_fab_1.vhd"
set_global_assignment -name VHDL_FILE "../16z100-00_src/Source/switch_fab_2.vhd"
set_global_assignment -name VHDL_FILE "../16z100-00_src/Source/switch_fab_3.vhd"
set_global_assignment -name VHDL_FILE "../16z100-00_src/Source/switch_fab_4.vhd"
set_global_assignment -name VHDL_FILE "../16z100-00_src/Source/wbmon.vhd"
set_global_assignment -name VHDL_FILE "../Source/wb_bus.vhd"
set_global_assignment -name VHDL_FILE "../16z100-00_src/Source/fifo_d1.vhd"
set_global_assignment -name VHDL_FILE "../16z100-00_src/Source/clk_trans_wb2wb.vhd"
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/ 0000775 0000000 0000000 00000000000 14574545710 0027616 5 ustar 00root root 0000000 0000000 Manifest.py 0000664 0000000 0000000 00000001032 14574545710 0031653 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
files = [
"Source/z126_01_clk_trans_wb2wb.vhd",
"Source/z126_01_fifo_d1.vhd",
"Source/z126_01_indi_if_ctrl_regs.vhd",
"Source/z126_01_pkg.vhd",
"Source/z126_01_ru_ctrl_cyc5.vhd",
"Source/z126_01_ru_ctrl.vhd",
"Source/z126_01_switch_fab_2.vhd",
"Source/z126_01_top.vhd",
"Source/z126_01_wb2pasmi.vhd",
"Source/z126_01_wb_if_arbiter.vhd",
"Source/z126_01_wbmon.vhd",
"Source/z126_01_wb_pkg.vhd",
]
README.rst 0000664 0000000 0000000 00000001140 14574545710 0031222 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src .. SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
..
.. SPDX-License-Identifier: CC-BY-SA-4.0+
16z126-01 IP core for serial flash with integrated remote update controller
===========================================================================
General description
-------------------
This IP core allows the flash update at runtime. It implements an interface for
direct addressing and an interface for indirect addressing. A remote update
controller is included.
Integration advice for top levels:
TBD
For more details please refer to:
inStep -> 1208_PASON_VSPME -> 16z126-01 documents
Source/ 0000775 0000000 0000000 00000000000 14574545710 0030777 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src z126_01_clk_trans_wb2wb.vhd 0000664 0000000 0000000 00000022616 14574545710 0035656 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Adaption from clk a to clk b
-- Project : A15
---------------------------------------------------------------
-- File : z126_01_clk_trans_wb2wb.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--
-- This Module transforms the request and acknoledge signals to
-- connect to a a MHz internal bus. Also the data must be
-- transformed in order to fit into the a MHz clk domain.
---------------------------------------------------------------
-- Hierarchy:
--
-- sys_unit
-- z126_01_clk_trans_wb2wb
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_clk_trans_wb2wb.vhd,v $
-- Revision 1.1 2014/03/03 17:49:39 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY z126_01_clk_trans_wb2wb IS
GENERIC (
NBR_OF_CYC : integer range 1 TO 100 := 1;
NBR_OF_TGA : integer range 1 TO 100 := 6
);
PORT (
rstn : IN std_logic;
-- a MHz domain
clk_a : IN std_logic;
cyc_a : IN std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_a : IN std_logic; -- request signal from a MHz side
ack_a : OUT std_logic; -- adopted acknoledge signal to b MHz
err_a : OUT std_logic;
we_a : IN std_logic; -- '1' = write, '0' = read
tga_a : IN std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_a : IN std_logic_vector(2 DOWNTO 0); -- transfer type
bte_a : IN std_logic_vector(1 DOWNTO 0); -- incremental burst
adr_a : IN std_logic_vector(31 DOWNTO 0); -- adr from a MHz side
sel_a : IN std_logic_vector(3 DOWNTO 0); -- byte enables from a MHz side
dat_i_a : IN std_logic_vector(31 DOWNTO 0); -- data from a MHz side
dat_o_a : OUT std_logic_vector(31 DOWNTO 0); -- data from b MHz side to a MHz side
-- b MHz domain
clk_b : IN std_logic;
cyc_b : OUT std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_b : OUT std_logic; -- request signal adopted to b MHz
ack_b : IN std_logic; -- acknoledge signal from internal bus
err_b : IN std_logic;
we_b : OUT std_logic; -- '1' = write, '0' = read
tga_b : OUT std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_b : OUT std_logic_vector(2 DOWNTO 0); -- transfer type
bte_b : OUT std_logic_vector(1 DOWNTO 0); -- incremental burst
adr_b : OUT std_logic_vector(31 DOWNTO 0); -- adr from b MHz side
sel_b : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for b MHz side
dat_i_b : IN std_logic_vector(31 DOWNTO 0); -- data from b MHz side
dat_o_b : OUT std_logic_vector(31 DOWNTO 0) -- data from a MHz side to b MHz side
);
END z126_01_clk_trans_wb2wb;
ARCHITECTURE z126_01_clk_trans_wb2wb_arch OF z126_01_clk_trans_wb2wb IS
COMPONENT z126_01_fifo_d1
GENERIC (
width : IN integer
);
PORT (
rstn : IN std_logic;
clk_a : IN std_logic;
wr_a : IN std_logic;
data_a : IN std_logic_vector(width-1 DOWNTO 0);
full_a : OUT std_logic;
clk_b : IN std_logic;
rd_b : IN std_logic;
data_b : OUT std_logic_vector(width-1 DOWNTO 0);
full_b : OUT std_logic
);
END COMPONENT;
TYPE ct_states IS (idle, waitstate, acknoledge);
SIGNAL ct_state : ct_states;
CONSTANT WR_FIFO_WIDTH : integer:= 69 + NBR_OF_CYC + NBR_OF_TGA; -- cyc + dat + adr + sel + we = 32+32+4+1 = 69
CONSTANT RD_FIFO_WIDTH : integer:= 32; -- dat = 32
SIGNAL ff1_rd : std_logic;
SIGNAL ff1_wr : std_logic;
SIGNAL ff1_full_a : std_logic;
SIGNAL ff1_full_b : std_logic;
SIGNAL ff2_rd : std_logic;
SIGNAL ff2_wr : std_logic;
SIGNAL ff2_full_b : std_logic;
SIGNAL stb_b_int : std_logic;
SIGNAL ff1_dat_a : std_logic_vector((WR_FIFO_WIDTH - 1) DOWNTO 0);
SIGNAL ff1_dat_b : std_logic_vector((WR_FIFO_WIDTH - 1) DOWNTO 0);
SIGNAL ack_a_int : std_logic;
BEGIN
ack_a <= ack_a_int;
stb_b <= stb_b_int;
err_a <= '0'; -- errors will not reported: error-access will never end!
ff1_dat_a <= tga_a & cyc_a & dat_i_a & adr_a & sel_a & we_a;
tga_b <= ff1_dat_b(68+NBR_OF_CYC+NBR_OF_TGA DOWNTO 69+NBR_OF_CYC);
cyc_b <= ff1_dat_b(68+NBR_OF_CYC DOWNTO 69) WHEN stb_b_int = '1' ELSE (OTHERS => '0');
dat_o_b <= ff1_dat_b(68 DOWNTO 37);
adr_b <= ff1_dat_b(36 DOWNTO 5);
sel_b <= ff1_dat_b(4 DOWNTO 1);
we_b <= ff1_dat_b(0);
cti_b <= (OTHERS => '0');
bte_b <= (OTHERS => '0');
ff1 : z126_01_fifo_d1
GENERIC MAP (
width => WR_FIFO_WIDTH )
PORT MAP (
rstn => rstn,
clk_a => clk_a,
wr_a => ff1_wr,
data_a => ff1_dat_a,
full_a => ff1_full_a,
clk_b => clk_b,
rd_b => ff1_rd,
data_b => ff1_dat_b,
full_b => ff1_full_b
);
ff2 : z126_01_fifo_d1
GENERIC MAP (
width => RD_FIFO_WIDTH )
PORT MAP (
rstn => rstn,
clk_a => clk_b,
wr_a => ff2_wr,
data_a => dat_i_b,
clk_b => clk_a,
rd_b => ff2_rd,
data_b => dat_o_a,
full_b => ff2_full_b
);
ff1_wr <= '1' WHEN (ct_state = idle AND stb_a = '1' AND cyc_a(0) = '1' AND ff1_full_a = '0') ELSE '0';
ff2_rd <= '1' WHEN ff2_full_b = '1' ELSE '0'; -- read data from ff when available
proca : PROCESS (clk_a, rstn)
BEGIN
IF rstn = '0' THEN
ack_a_int <= '0';
ct_state <= idle;
ELSIF clk_a'EVENT AND clk_a = '1' THEN
CASE ct_state IS
WHEN idle =>
IF (ff1_wr = '1' AND we_a = '1') THEN -- write
ct_state <= acknoledge;
ack_a_int <= '1';
ELSIF (ff1_wr = '1' AND we_a = '0') THEN -- read
ct_state <= waitstate;
ack_a_int <= '0';
ELSE
ct_state <= idle;
ack_a_int <= '0';
END IF;
WHEN waitstate =>
IF ff2_full_b = '1' THEN
ct_state <= acknoledge;
ack_a_int <= '1';
ELSE
ct_state <= waitstate;
ack_a_int <= '0';
END IF;
WHEN acknoledge =>
ack_a_int <= '0';
ct_state <= idle;
WHEN OTHERS =>
ct_state <= idle;
ack_a_int <= '0';
END CASE;
END IF;
END PROCESS proca;
------------------------------------------------------------------
-- side b: stb_b is not dependent on we_a
------------------------------------------------------------------
-- for read and write equal:
ff1_rd <= '1' WHEN ((ack_b = '0' AND err_b = '0') AND ff1_full_b = '1' AND stb_b_int = '0') OR -- first data phase
((ack_b = '1' OR err_b = '1') AND ff1_full_b = '1' AND stb_b_int = '1') -- within a burst (not the last)
ELSE '0';
ff2_wr <= '1' WHEN stb_b_int = '1' AND (ack_b = '1' OR err_b = '1') AND ff1_dat_b(0) = '0' ELSE '0'; -- store read-data
-- ack_b stb_b ff1_full stb_b(+1)
-- x 0 1 1
-- x 1 1 1
-- x 0 0 0
-- 1 1 0 0
-- 0 1 0 1
procb : PROCESS (clk_b, rstn)
BEGIN
IF rstn = '0' THEN
stb_b_int <= '0';
ELSIF clk_b'EVENT AND clk_b = '1' THEN
IF ff1_full_b = '1' THEN
IF stb_b_int = '0' THEN
stb_b_int <= '1'; -- start next data phase
ELSE
-- end of current data phase, start of next
stb_b_int <= '1'; -- or no end of current data phase
END IF;
ELSE
IF stb_b_int = '0' THEN -- no current access and no next access
stb_b_int <= '0';
ELSE
IF ack_b = '1' OR err_b = '1' THEN -- end of current data phase, no next
stb_b_int <= '0';
ELSE
stb_b_int <= '1'; -- no end of current data phase
END IF;
END IF;
END IF;
END IF;
END PROCESS procb;
END z126_01_clk_trans_wb2wb_arch;
z126_01_fifo_d1.vhd 0000664 0000000 0000000 00000006375 14574545710 0034106 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : FIFO with depth one word
-- Project :
---------------------------------------------------------------
-- File : z126_01_fifo_d1.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--
-- This module describes a fifo with depth one word.
-- No EAB-Block is required, just registers.
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_fifo_d1.vhd,v $
-- Revision 1.1 2014/03/03 17:49:40 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY z126_01_fifo_d1 IS
GENERIC (
width : IN integer:=8 );
PORT (
rstn : IN std_logic;
clk_a : IN std_logic;
wr_a : IN std_logic;
data_a : IN std_logic_vector(width-1 DOWNTO 0);
full_a : OUT std_logic;
clk_b : IN std_logic;
rd_b : IN std_logic;
data_b : OUT std_logic_vector(width-1 DOWNTO 0);
full_b : OUT std_logic
);
END z126_01_fifo_d1;
ARCHITECTURE z126_01_fifo_d1_arch OF z126_01_fifo_d1 IS
SIGNAL wr_ptr : std_logic;
SIGNAL rd_ptr : std_logic;
SIGNAL wr_ptr_b : std_logic;
SIGNAL rd_ptr_a : std_logic;
SIGNAL full_a_int : std_logic;
SIGNAL full_b_int : std_logic;
SIGNAL data_a_q : std_logic_vector(width-1 DOWNTO 0);
BEGIN
full_a_int <= '1' WHEN (wr_ptr = '1' AND rd_ptr_a = '0') OR (wr_ptr = '0' AND rd_ptr_a = '1') ELSE '0';
full_a <= full_a_int;
full_b_int <= '1' WHEN (wr_ptr_b = '1' AND rd_ptr = '0') OR (wr_ptr_b = '0' AND rd_ptr = '1') ELSE '0';
full_b <= full_b_int;
proca : PROCESS (clk_a, rstn)
BEGIN
IF rstn = '0' THEN
data_a_q <= (OTHERS => '0');
wr_ptr <= '0';
rd_ptr_a <= '0';
ELSIF clk_a'EVENT AND clk_a = '1' THEN
rd_ptr_a <= rd_ptr;
IF wr_a = '1' AND full_a_int = '0' THEN
data_a_q <= data_a;
wr_ptr <= NOT wr_ptr;
END IF;
END IF;
END PROCESS proca;
procb : PROCESS (clk_b, rstn)
BEGIN
IF rstn = '0' THEN
data_b <= (OTHERS => '0');
rd_ptr <= '0';
wr_ptr_b <= '0';
ELSIF clk_b'EVENT AND clk_b = '1' THEN
wr_ptr_b <= wr_ptr;
IF rd_b = '1' AND full_b_int = '1' THEN
data_b <= data_a_q;
rd_ptr <= NOT rd_ptr;
END IF;
END IF;
END PROCESS procb;
END z126_01_fifo_d1_arch;
z126_01_indi_if_ctrl_regs.vhd 0000664 0000000 0000000 00000042477 14574545710 0036247 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : 16z126-01 Indirect Interface Control Registers
-- Project : 16z126-01
---------------------------------------------------------------
-- File : z126_01_indi_if_ctrl_regs.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
-- The state machine transforms an wishbone access from the
-- slave input to a wishbone master access to the master output.
-- The state machine consits of one address and one data
-- register in order to realize an indirect memory access.
-- The indirect memory access is initiated at the wishbone
-- slave input and is transformed to an wishbone master output
-- (in order to access an 16z100 Module)
--
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_top
-- z126_01_indi_if_ctrl_regs
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: z126_01_indi_if_ctrl_regs.vhd,v $
-- Revision 1.3 2014/11/24 16:44:12 AGeissler
-- R1: Complex FSM for WBM to remote update controller and WBM to PASMI interface
-- M1: Simplified the FSM by reduced states
-- R2: Misleading signal name
-- M2: Renamed signal adr_reg to ctrl_reg
-- R3: Unused signal
-- M3: Removed ctrl_busy_q
-- R4: Code optimization
-- M4: Moved signal reconfig_int into write access condition of the wishbone bus
-- slave
--
-- Revision 1.2 2014/03/05 11:19:36 AGeissler
-- R: Missing reset for signal
-- M: Added reset
--
-- Revision 1.1 2014/03/03 17:49:41 AGeissler
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY z126_01_indi_if_ctrl_regs IS
PORT (
clk : IN std_logic; -- Wishbone clock (66 MHz)
rst : IN std_logic; -- Reset
-- wishbone signals master interface (ru_ctrl interface)
wbm_ru_cyc : OUT std_logic;
wbm_ru_ack : IN std_logic;
wbm_ru_we : OUT std_logic;
wbm_ru_sel : OUT std_logic_vector(3 DOWNTO 0);
wbm_ru_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ru_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : OUT std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : IN std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : IN std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- wishbone signals master interface (wb2pasmi interface)
wbm_stb : OUT std_logic; -- strobe
wbm_adr : OUT std_logic_vector(31 DOWNTO 0); -- address
wbm_ack : IN std_logic; -- acknowledge
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
wbm_cyc : OUT std_logic; -- chip select
-- wishbone signals slave interface (indirect interface)
wbs_stb : IN std_logic; -- strobe
wbs_ack : OUT std_logic; -- acknowledge
wbs_we : IN std_logic; -- write=1 read=0
wbs_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc : IN std_logic; -- chip select
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr : IN std_logic_vector(31 DOWNTO 0); -- address
-- ctrl signals from registers
ctrl_read_sid : OUT std_logic;
ctrl_sector_protect : OUT std_logic;
ctrl_write : OUT std_logic;
ctrl_read_status : OUT std_logic;
ctrl_sector_erase : OUT std_logic;
ctrl_bulk_erase : OUT std_logic;
ctrl_illegal_write : IN std_logic;
ctrl_illegal_erase : IN std_logic;
ctrl_busy : IN std_logic
);
END z126_01_indi_if_ctrl_regs;
ARCHITECTURE z126_01_indi_if_ctrl_regs_arch OF z126_01_indi_if_ctrl_regs IS
TYPE wb_states IS (IDLE, PER_REQ, ACKNOWLEDGE);
SIGNAL ctrl_reg : std_logic_vector(31 DOWNTO 0); -- control register
SIGNAL flash_adr : std_logic_vector(23 DOWNTO 0); -- flash adress register
SIGNAL reconfig_int : std_logic;
SIGNAL wbs_ack_int : std_logic;
SIGNAL wbm_state : wb_states := IDLE;
SIGNAL wbm_start : std_logic;
SIGNAL wbm_done : std_logic;
SIGNAL wbm_cyc_int : std_logic;
SIGNAL wbm_ru_state : wb_states := IDLE;
SIGNAL wbm_ru_start : std_logic;
SIGNAL wbm_ru_done : std_logic;
SIGNAL ctrl_read_sid_q : std_logic;
SIGNAL ctrl_sector_protect_q : std_logic;
SIGNAL ctrl_sector_erase_q : std_logic;
SIGNAL ctrl_bulk_erase_q : std_logic;
SIGNAL ctrl_read_status_q : std_logic;
SIGNAL ctrl_illegal_write_q : std_logic;
SIGNAL ctrl_illegal_erase_q : std_logic;
BEGIN
-- wishbone connection to remote update controller
wbm_ru_dat_o <= wbs_dat_i;
wbm_ru_sel <= wbs_sel;
wbm_ru_we <= wbs_we;
-- control signals to wb2pasmi module
ctrl_read_sid <= ctrl_read_sid_q;
ctrl_sector_protect <= ctrl_sector_protect_q;
ctrl_read_status <= ctrl_read_status_q;
ctrl_sector_erase <= ctrl_sector_erase_q;
ctrl_bulk_erase <= ctrl_bulk_erase_q;
-- control register of indirect interface
ctrl_reg <= reconfig_int & ctrl_busy & ctrl_illegal_erase_q & ctrl_illegal_write_q & "0000" & flash_adr;
wbm_cyc <= wbm_cyc_int;
wbm_stb <= wbm_cyc_int;
wbm_adr <= x"00" & ctrl_reg(23 DOWNTO 0);
wbs_ack <= wbs_ack_int;
reg_reconfig <= reconfig_int; -- reconfiguration is generated from bit 31 of ctrl_reg
-- Process for register access
z126_01_wbs_regs: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
flash_adr <= (OTHERS => '0');
ctrl_read_sid_q <= '0';
ctrl_sector_protect_q <= '0';
ctrl_read_status_q <= '0';
ctrl_sector_erase_q <= '0';
ctrl_bulk_erase_q <= '0';
ctrl_write <= '0';
ctrl_illegal_write_q <= '0';
ctrl_illegal_erase_q <= '0';
reconfig_int <= '0';
wbs_ack_int <= '0';
wbm_start <= '0';
wbm_ru_start <= '0';
wbs_dat_o <= (OTHERS => '0');
ELSIF clk'EVENT AND clk ='1' THEN
----------------------------------------
-- write access to indirect interface --
----------------------------------------
IF wbs_stb = '1' AND wbs_cyc = '1' AND wbs_ack_int = '0' AND wbs_we = '1' THEN
IF wbs_adr(3 DOWNTO 2) = "00" THEN -- Write to Address Register 0x00
wbs_ack_int <= '1'; -- Issue acknowledge immediately
wbm_start <= '0'; -- Don't perform a wishbone master access
IF wbs_sel(0) = '1' THEN
flash_adr(7 DOWNTO 0) <= wbs_dat_i(7 DOWNTO 0);
END IF;
IF wbs_sel(1) = '1' THEN
flash_adr(15 DOWNTO 8) <= wbs_dat_i(15 DOWNTO 8);
END IF;
IF wbs_sel(2) = '1' THEN
flash_adr(23 DOWNTO 16) <= wbs_dat_i(23 DOWNTO 16);
END IF;
IF wbs_sel(3) = '1' THEN
ctrl_read_sid_q <= wbs_dat_i(25);
ctrl_sector_protect_q <= wbs_dat_i(26);
ctrl_read_status_q <= wbs_dat_i(27);
ctrl_sector_erase_q <= wbs_dat_i(28);
ctrl_bulk_erase_q <= wbs_dat_i(29);
ctrl_write <= wbs_dat_i(30);
reconfig_int <= wbs_dat_i(31); -- Bit 31 indicates reconfiguration
ctrl_illegal_write_q <= '0'; -- reset status bits
ctrl_illegal_erase_q <= '0';
END IF;
ELSIF wbs_adr(3 DOWNTO 2) = "01" THEN -- write to data register 0x04
wbs_ack_int <= wbm_done; -- issue acknowledge when wb access is done
wbm_start <= NOT wbm_done; -- start wisbone master access when
-- no former access is in work
flash_adr <= flash_adr;
ctrl_read_sid_q <= '0';
ctrl_sector_protect_q <= ctrl_sector_protect_q;
ctrl_read_status_q <= '0';
ctrl_sector_erase_q <= ctrl_sector_erase_q;
ctrl_bulk_erase_q <= ctrl_bulk_erase_q;
ctrl_write <= '0';
ctrl_illegal_write_q <= ctrl_illegal_write_q;
ctrl_illegal_erase_q <= ctrl_illegal_erase_q;
ELSIF wbs_adr(3 DOWNTO 2) = "10" THEN -- board status register (read-only)
wbs_ack_int <= '1'; -- Issue acknowledge immediately
ELSIF wbs_adr(3 DOWNTO 2) = "11" THEN
-- write boot address of remote update controller
-- perform wishbone master access to ru_ctrl
wbs_ack_int <= wbm_ru_done;
wbm_ru_start <= NOT wbm_ru_done;
END IF;
---------------------------------------
-- read access to indirect interface --
---------------------------------------
ELSIF wbs_stb = '1' AND wbs_cyc = '1' AND wbs_ack_int = '0' AND wbs_we = '0' THEN
CASE wbs_adr(3 DOWNTO 2) IS
WHEN "00" => -- read 0x00 Control Register
wbm_start <= '0'; -- Don't perform a wishbone master access
wbs_ack_int <= '1'; -- Issue acknowledge immediately
flash_adr <= flash_adr;
ctrl_read_sid_q <= '0';
ctrl_sector_protect_q <= '0';
ctrl_read_status_q <= '0';
ctrl_sector_erase_q <= '0';
ctrl_bulk_erase_q <= '0';
ctrl_write <= '0';
ctrl_illegal_write_q <= ctrl_illegal_write_q;
ctrl_illegal_erase_q <= ctrl_illegal_erase_q;
WHEN "01" => -- read 0x04 Data Register
wbm_start <= NOT wbm_done;
wbs_ack_int <= wbm_done;
flash_adr <= flash_adr;
ctrl_read_sid_q <= ctrl_read_sid_q;
ctrl_sector_protect_q <= '0';
ctrl_write <= '0';
ctrl_read_status_q <= ctrl_read_status_q;
ctrl_sector_erase_q <= '0';
ctrl_bulk_erase_q <= '0';
ctrl_illegal_write_q <= ctrl_illegal_write_q;
ctrl_illegal_erase_q <= ctrl_illegal_erase_q;
WHEN "10" => -- read 0x08 board status register (read-only)
wbs_ack_int <= '1'; -- issue acknowledge immediately
WHEN "11" => -- "11" = 0x0C
-- read boot address of remote update controller
-- perform wishbone master access to ru_ctrl
wbm_ru_start <= NOT wbm_ru_done;
wbs_ack_int <= wbm_ru_done;
WHEN OTHERS =>
wbs_ack_int <= '1'; -- issue acknowledge immediately
END CASE;
ELSE
wbs_ack_int <= '0';
wbm_start <= '0';
wbm_ru_start <= '0';
flash_adr <= flash_adr;
ctrl_read_sid_q <= ctrl_read_sid_q;
ctrl_sector_protect_q <= ctrl_sector_protect_q;
ctrl_read_status_q <= ctrl_read_status_q;
ctrl_sector_erase_q <= ctrl_sector_erase_q;
ctrl_bulk_erase_q <= ctrl_bulk_erase_q;
ctrl_write <= '0';
IF ctrl_illegal_write = '1' THEN
ctrl_illegal_write_q <= '1';
ELSE
ctrl_illegal_write_q <= ctrl_illegal_write_q;
END IF;
IF ctrl_illegal_erase = '1' THEN
ctrl_illegal_erase_q <= '1';
ELSE
ctrl_illegal_erase_q <= ctrl_illegal_erase_q;
END IF;
END IF;
-- wbs data out (read)
IF wbs_adr(3 DOWNTO 2) = "00" THEN
wbs_dat_o <= ctrl_reg;
ELSIF wbs_adr(3 DOWNTO 2) = "01" THEN
wbs_dat_o <= wbm_dat_i;
ELSIF wbs_adr(3 DOWNTO 2) = "10" THEN
wbs_dat_o <= x"000000" & "0" & reg_reconfig_cond & reg_board_status;
ELSIF wbs_adr(3 DOWNTO 2) = "11" THEN
wbs_dat_o <= wbm_ru_dat_i;
END IF;
END IF;
END PROCESS z126_01_wbs_regs;
-- generating wishbone master access for remote update unit
z126_01_wbm_ru_fsm_proc: PROCESS(clk, rst)
BEGIN
IF rst ='1' THEN
wbm_ru_done <= '0';
wbm_ru_state <= IDLE;
wbm_ru_cyc <= '0';
ELSIF clk'EVENT AND clk ='1' THEN
CASE wbm_ru_state IS
WHEN IDLE =>
wbm_ru_done <= '0';
IF wbm_ru_start = '1' THEN
wbm_ru_state <= PER_REQ;
wbm_ru_cyc <= '1';
ELSE
wbm_ru_state <= IDLE;
wbm_ru_cyc <= '0';
END IF;
WHEN PER_REQ =>
IF wbm_ru_ack = '1' THEN
wbm_ru_state <= ACKNOWLEDGE;
wbm_ru_cyc <= '0';
wbm_ru_done <= '1';
ELSE
wbm_ru_state <= PER_REQ;
wbm_ru_cyc <= '1';
wbm_ru_done <= '0';
END IF;
WHEN ACKNOWLEDGE =>
wbm_ru_state <= IDLE;
wbm_ru_cyc <= '0';
wbm_ru_done <= '0';
-- coverage off
WHEN OTHERS =>
wbm_ru_state <= IDLE;
wbm_ru_cyc <= '0';
wbm_ru_done <= '0';
ASSERT FALSE REPORT "Undecoded State" SEVERITY WARNING;
-- coverage on
END CASE;
END IF;
END PROCESS z126_01_wbm_ru_fsm_proc;
-- state machine for generating wishbone master access from a wishbone slave access
z126_01_wbm_fsm_proc: PROCESS(clk, rst)
BEGIN
IF rst ='1' THEN
wbm_cyc_int <= '0';
wbm_done <= '0';
wbm_state <= IDLE;
ELSIF clk'EVENT AND clk ='1' THEN
CASE wbm_state IS
WHEN IDLE =>
wbm_done <= '0';
IF wbm_start = '1' THEN
wbm_state <= PER_REQ;
wbm_cyc_int <= '1';
ELSE
wbm_state <= IDLE;
wbm_cyc_int <= '0';
END IF;
WHEN PER_REQ =>
IF wbm_ack = '1' THEN
wbm_state <= ACKNOWLEDGE;
wbm_done <= '1';
wbm_cyc_int <= '0';
ELSE
wbm_state <= PER_REQ;
wbm_done <= '0';
wbm_cyc_int <= '1';
END IF;
WHEN ACKNOWLEDGE =>
wbm_state <= IDLE;
wbm_done <= '0';
wbm_cyc_int <= '0';
-- coverage off
WHEN OTHERS =>
wbm_state <= IDLE;
wbm_done <= '0';
wbm_cyc_int <= '0';
ASSERT FALSE REPORT "Undecoded State" SEVERITY WARNING;
-- coverage on
END CASE;
END IF;
END PROCESS z126_01_wbm_fsm_proc;
END z126_01_indi_if_ctrl_regs_arch;
z126_01_pasmi/ 0000775 0000000 0000000 00000000000 14574545710 0033172 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source .gitignore 0000664 0000000 0000000 00000000203 14574545710 0035155 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source/z126_01_pasmi # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!*.txt
!gen_m25p32.tcl
gen_m25p32.tcl 0000664 0000000 0000000 00000000211 14574545710 0035451 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source/z126_01_pasmi # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
qmegawiz { z126_01_pasmi_m25p32 }
z126_01_pasmi_m25p32.txt 0000664 0000000 0000000 00000012504 14574545710 0037140 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source/z126_01_pasmi -- megafunction wizard: %ALTASMI_PARALLEL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTASMI_PARALLEL
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: DATA_WIDTH STRING "STANDARD"
-- Retrieval info: CONSTANT: ENABLE_SIM STRING "FALSE"
-- Retrieval info: CONSTANT: EPCS_TYPE STRING "EPCS16"
-- Retrieval info: CONSTANT: FLASH_RSTPIN STRING "FALSE"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altasmi_parallel"
-- Retrieval info: CONSTANT: PAGE_SIZE NUMERIC "256"
-- Retrieval info: CONSTANT: PORT_BULK_ERASE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_DIE_ERASE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_EN4B_ADDR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_EX4B_ADDR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FAST_READ STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_ILLEGAL_ERASE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_ILLEGAL_WRITE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_RDID_OUT STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_READ_ADDRESS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_READ_DUMMYCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_READ_RDID STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_READ_SID STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_READ_STATUS STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SECTOR_ERASE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SECTOR_PROTECT STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SHIFT_BYTES STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_WREN STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_WRITE STRING "PORT_USED"
-- Retrieval info: CONSTANT: USE_ASMIBLOCK STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_DUMMY_CLK NUMERIC "0"
-- Retrieval info: USED_PORT: addr 0 0 24 0 INPUT NODEFVAL "addr[23..0]"
-- Retrieval info: CONNECT: @addr 0 0 24 0 addr 0 0 24 0
-- Retrieval info: USED_PORT: bulk_erase 0 0 0 0 INPUT NODEFVAL "bulk_erase"
-- Retrieval info: CONNECT: @bulk_erase 0 0 0 0 bulk_erase 0 0 0 0
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: USED_PORT: clkin 0 0 0 0 INPUT NODEFVAL "clkin"
-- Retrieval info: CONNECT: @clkin 0 0 0 0 clkin 0 0 0 0
-- Retrieval info: USED_PORT: data_valid 0 0 0 0 OUTPUT NODEFVAL "data_valid"
-- Retrieval info: CONNECT: data_valid 0 0 0 0 @data_valid 0 0 0 0
-- Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]"
-- Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0
-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
-- Retrieval info: USED_PORT: fast_read 0 0 0 0 INPUT NODEFVAL "fast_read"
-- Retrieval info: CONNECT: @fast_read 0 0 0 0 fast_read 0 0 0 0
-- Retrieval info: USED_PORT: illegal_erase 0 0 0 0 OUTPUT NODEFVAL "illegal_erase"
-- Retrieval info: CONNECT: illegal_erase 0 0 0 0 @illegal_erase 0 0 0 0
-- Retrieval info: USED_PORT: illegal_write 0 0 0 0 OUTPUT NODEFVAL "illegal_write"
-- Retrieval info: CONNECT: illegal_write 0 0 0 0 @illegal_write 0 0 0 0
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT NODEFVAL "rden"
-- Retrieval info: CONNECT: @rden 0 0 0 0 rden 0 0 0 0
-- Retrieval info: USED_PORT: rdid_out 0 0 8 0 OUTPUT NODEFVAL "rdid_out[7..0]"
-- Retrieval info: CONNECT: rdid_out 0 0 8 0 @rdid_out 0 0 8 0
-- Retrieval info: USED_PORT: read_rdid 0 0 0 0 INPUT NODEFVAL "read_rdid"
-- Retrieval info: CONNECT: @read_rdid 0 0 0 0 read_rdid 0 0 0 0
-- Retrieval info: USED_PORT: read_status 0 0 0 0 INPUT NODEFVAL "read_status"
-- Retrieval info: CONNECT: @read_status 0 0 0 0 read_status 0 0 0 0
-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
-- Retrieval info: USED_PORT: sector_erase 0 0 0 0 INPUT NODEFVAL "sector_erase"
-- Retrieval info: CONNECT: @sector_erase 0 0 0 0 sector_erase 0 0 0 0
-- Retrieval info: USED_PORT: sector_protect 0 0 0 0 INPUT NODEFVAL "sector_protect"
-- Retrieval info: CONNECT: @sector_protect 0 0 0 0 sector_protect 0 0 0 0
-- Retrieval info: USED_PORT: shift_bytes 0 0 0 0 INPUT NODEFVAL "shift_bytes"
-- Retrieval info: CONNECT: @shift_bytes 0 0 0 0 shift_bytes 0 0 0 0
-- Retrieval info: USED_PORT: status_out 0 0 8 0 OUTPUT NODEFVAL "status_out[7..0]"
-- Retrieval info: CONNECT: status_out 0 0 8 0 @status_out 0 0 8 0
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
-- Retrieval info: USED_PORT: write 0 0 0 0 INPUT NODEFVAL "write"
-- Retrieval info: CONNECT: @write 0 0 0 0 write 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_m25p32.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_m25p32.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_m25p32.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_m25p32_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_m25p32.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_pasmi_m25p32.cmp FALSE TRUE
z126_01_pkg.vhd 0000664 0000000 0000000 00000014274 14574545710 0033355 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Package for flash types
-- Project :
---------------------------------------------------------------
-- File : z126_01_pkg.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--! \desid
--! \archid
--! \desbody
---------------------------------------------------------------
--!\hierarchy
--!\endofhierarchy
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: z126_01_pkg.vhd,v $
-- Revision 1.2 2014/11/24 16:44:14 AGeissler
-- R1: Magic numbers
-- M1: Added constants for used coded signals
--
-- Revision 1.1 2014/03/03 17:49:48 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.fpga_pkg_2.ALL;
PACKAGE z126_01_pkg IS
TYPE flash_type IS (NONE, M25P32, M25P64, M25P128);
TYPE supported_flash_types IS array (natural range <>) OF flash_type; -- for mor than one supported devices
SUBTYPE supported_flash_type IS flash_type; -- for exactly one supported device
--------------------------------------------------------------------
-- Remote update parameters
--------------------------------------------------------------------
-- CYCLONE V
CONSTANT Z126_01_RU_RECONF_CON_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "000";
CONSTANT Z126_01_RU_WDOG_VAL_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "010";
CONSTANT Z126_01_RU_WDOG_EN_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "011";
CONSTANT Z126_01_RU_PAGE_SEL_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "100";
CONSTANT Z126_01_RU_CONF_MODE_PAR_CYC5 : std_logic_vector(2 DOWNTO 0) := "101";
-- CYCLONE IV and CYCLONE III
CONSTANT Z126_01_RU_STATE_MODE_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "000";
CONSTANT Z126_01_RU_CONF_DONE_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "001";
CONSTANT Z126_01_RU_WDOG_VAL_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "010";
CONSTANT Z126_01_RU_WDOG_EN_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "011";
CONSTANT Z126_01_RU_BOOT_ADR_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "100";
CONSTANT Z126_01_RU_INT_OSCI_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "110";
CONSTANT Z126_01_RU_RECONF_CON_PAR_CYC4 : std_logic_vector(2 DOWNTO 0) := "111";
--------------------------------------------------------------------
-- Remote update read source (only for cyclone III and cyclone IV
--------------------------------------------------------------------
CONSTANT Z126_01_RU_RD_SRC_CURRENT : std_logic_vector(1 DOWNTO 0) := "00";
CONSTANT Z126_01_RU_RD_SRC_PREVIOUS_1 : std_logic_vector(1 DOWNTO 0) := "01";
CONSTANT Z126_01_RU_RD_SRC_PREVIOUS_2 : std_logic_vector(1 DOWNTO 0) := "10";
CONSTANT Z126_01_RU_RD_SRC_INPUT_REG : std_logic_vector(1 DOWNTO 0) := "11";
TYPE pasmi_out_type IS record
addr : std_logic_vector(23 DOWNTO 0);
bulk_erase : std_logic;
data : std_logic_vector(7 DOWNTO 0);
fast_read : std_logic;
rden : std_logic;
read_sid : std_logic;
read_rdid : std_logic;
read_status : std_logic;
sector_erase : std_logic;
sector_protect : std_logic;
shift_bytes : std_logic;
wren : std_logic;
write : std_logic;
read : std_logic;
END record;
TYPE pasmi_in_type IS record
illegal_erase : std_logic;
illegal_write : std_logic;
epcs_id : std_logic_vector(7 DOWNTO 0);
rdid : std_logic_vector(7 DOWNTO 0);
status : std_logic_vector(7 DOWNTO 0);
busy : std_logic;
data_valid : std_logic;
data : std_logic_vector(7 DOWNTO 0);
END record;
TYPE ctrl_wb2pasmi_out_type IS record
read_sid : std_logic;
sector_protect : std_logic;
write : std_logic;
read_status : std_logic;
sector_erase : std_logic;
bulk_erase : std_logic;
END record;
TYPE ctrl_wb2pasmi_in_type IS record
illegal_write : std_logic;
illegal_erase : std_logic;
busy : std_logic;
END record;
FUNCTION no_valid_device(
supported_devices : IN supported_flash_types;
device : IN flash_type )
RETURN boolean;
FUNCTION no_valid_device(
supported_device : IN supported_flash_type;
device : IN flash_type )
RETURN boolean;
END z126_01_pkg;
PACKAGE BODY z126_01_pkg IS
FUNCTION no_valid_device(
supported_devices : IN supported_flash_types;
device : IN flash_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
FOR i IN supported_devices'range LOOP
IF(device = supported_devices(i)) THEN
no_valid := FALSE;
ELSE
no_valid := no_valid;
END IF;
END LOOP;
RETURN no_valid;
END no_valid_device;
FUNCTION no_valid_device(
supported_device : IN supported_flash_type;
device : IN flash_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
IF(device = supported_device) THEN
no_valid := FALSE;
ELSE
no_valid := TRUE;
END IF;
RETURN no_valid;
END no_valid_device;
END;
z126_01_ru/ 0000775 0000000 0000000 00000000000 14574545710 0032507 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source .gitignore 0000664 0000000 0000000 00000000177 14574545710 0034504 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source/z126_01_ru # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!*.txt
!gen_ru.tcl
gen_ru.tcl 0000664 0000000 0000000 00000000211 14574545710 0034464 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source/z126_01_ru # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
qmegawiz { z126_01_ru_cycloneiv }
z126_01_ru_cycloneiv.txt 0000664 0000000 0000000 00000006122 14574545710 0037034 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source/z126_01_ru -- megafunction wizard: %ALTREMOTE_UPDATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altremote_update
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: SIM_INIT_PAGE_SELECT_COMBO STRING "0"
-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT0_CHECK STRING "0"
-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT1_CHECK STRING "0"
-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT2_CHECK STRING "0"
-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT3_CHECK STRING "0"
-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT4_CHECK STRING "0"
-- Retrieval info: PRIVATE: SIM_INIT_WATCHDOG_VALUE_EDIT STRING "1"
-- Retrieval info: PRIVATE: SUPPORT_WRITE_CHECK STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WATCHDOG_ENABLE_CHECK STRING "0"
-- Retrieval info: CONSTANT: CHECK_APP_POF STRING "false"
-- Retrieval info: CONSTANT: CONFIG_DEVICE_ADDR_WIDTH NUMERIC "24"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: IN_DATA_WIDTH NUMERIC "24"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "REMOTE"
-- Retrieval info: CONSTANT: OUT_DATA_WIDTH NUMERIC "29"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data_in 0 0 24 0 INPUT NODEFVAL "data_in[23..0]"
-- Retrieval info: USED_PORT: data_out 0 0 29 0 OUTPUT NODEFVAL "data_out[28..0]"
-- Retrieval info: USED_PORT: param 0 0 3 0 INPUT NODEFVAL "param[2..0]"
-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
-- Retrieval info: USED_PORT: read_source 0 0 2 0 INPUT NODEFVAL "read_source[1..0]"
-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
-- Retrieval info: USED_PORT: reset_timer 0 0 0 0 INPUT NODEFVAL "reset_timer"
-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_in 0 0 24 0 data_in 0 0 24 0
-- Retrieval info: CONNECT: @param 0 0 3 0 param 0 0 3 0
-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
-- Retrieval info: CONNECT: @read_source 0 0 2 0 read_source 0 0 2 0
-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
-- Retrieval info: CONNECT: @reset_timer 0 0 0 0 reset_timer 0 0 0 0
-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: data_out 0 0 29 0 @data_out 0 0 29 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_ru_cycloneiv.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_ru_cycloneiv.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_ru_cycloneiv.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_ru_cycloneiv.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL z126_01_ru_cycloneiv_inst.vhd FALSE
-- Retrieval info: LIB_FILE: cycloneiv
-- Retrieval info: LIB_FILE: lpm
z126_01_ru_ctrl.vhd 0000664 0000000 0000000 00000071706 14574545710 0034251 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Remote Update Control
-- Project : General IP-core
---------------------------------------------------------------
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description : The module is used to control the
-- serial loading of the FPGA image using the
-- altera remote update block.
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_ru_ctrl.vhd
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.6 $
--
-- $Log: z126_01_ru_ctrl.vhd,v $
-- Revision 1.6 2014/12/02 10:32:24 AGeissler
-- R1: The watchdog value is not correctly set, so that the user image could not
-- be loaded
-- M1: Changed param value from enable to value
--
-- Revision 1.5 2014/11/24 16:44:16 AGeissler
-- R1: Magic numbers
-- M1: Added constants for used coded signals
-- R2: New naming convention of FPGA images
-- M2.1: Renamed application image to FPGA Image
-- M2.2: Renamed factor image to FPGA Fallback Image
--
-- Revision 1.4 2014/07/11 09:58:14 AGeissler
-- R1: If the 16z126-01 is used with a high freqency (wishbone clock) the
-- loading of a user image always failed. The reset_timer signal is not
-- long enough active. The reset must be active for at least 250ns at cyclone IV
-- devices (the altera device handbook).
-- M1: Added a clock divider to increase the active time of the reset_timer signal
--
-- Revision 1.3 2014/06/18 17:06:04 AGeissler
-- R1: MAIN_PR001588:
-- When nStatus is set instead of crc error when a user image is corrupt and generic USER_IMAGE is true the system will hang up completely.
-- M1: Added nStatus as an error in FSM condition
--
-- Revision 1.2 2014/03/05 11:19:39 AGeissler
-- R: Missing reset for signal
-- M: Added reset
--
-- Revision 1.1 2014/03/03 17:49:49 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
USE work.z126_01_pkg.all;
ENTITY z126_01_ru_ctrl IS
GENERIC
(
FPGA_FAMILY : family_type := CYCLONE4; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT
(
clk : IN std_logic; -- system clock
rst : IN std_logic; -- unit ru_ctrl_reset
-- register interface
wbs_reg_cyc : IN std_logic;
wbs_reg_ack : OUT std_logic;
wbs_reg_we : IN std_logic;
wbs_reg_sel : IN std_logic_vector(3 DOWNTO 0);
wbs_reg_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_reg_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : IN std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : OUT std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : OUT std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- ALTREMOTE_UPDATE interface
ru_ctrl_busy : IN std_logic;
ru_ctrl_data_out : IN std_logic_vector(28 DOWNTO 0); -- data from altera remote update module
ru_ctrl_data_in : OUT std_logic_vector(23 DOWNTO 0); -- data to altera remote update module
ru_ctrl_param : OUT std_logic_vector(2 DOWNTO 0);
ru_ctrl_read_param : OUT std_logic;
ru_ctrl_read_source : OUT std_logic_vector(1 DOWNTO 0);
ru_ctrl_reconfig : OUT std_logic;
ru_ctrl_reset_timer : OUT std_logic;
ru_ctrl_reset : OUT std_logic;
ru_ctrl_write_param : OUT std_logic
);
END z126_01_ru_ctrl;
ARCHITECTURE z126_01_ru_ctrl_arch OF z126_01_ru_ctrl IS
TYPE ru_ctrl_states IS (IDLE,
READ_CURR_STATE,
READ_RECONFIG_COND,
CHECK_STATE,
WRITE_BOOT_ADDR,
WRITE_WATCHDOG_VALUE,
WRITE_WATCHDOG_ENABLE,
RECONFIGURE,
FPGA_IMAGE,
FALLBACK_IMAGE,
WRITE_BOOT_ADDR_WB_FALLBACK,
READ_BOOT_ADDR_WB_FALLBACK,
READ_BOOT_ADDR_WB_FGPA_IMAGE
);
CONSTANT SUPPORTED_DEVICES : supported_family_types := (CYCLONE3, CYCLONE4);
SIGNAL ru_ctrl_state : ru_ctrl_states := IDLE; -- remote update control block state signal
-- registers
SIGNAL reconfig_cond : std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
SIGNAL curr_state : std_logic_vector(1 DOWNTO 0); -- current state of fpga
SIGNAL boot_addr : std_logic_vector(23 DOWNTO 0); -- fpga boot addr (only write able in Factory Mode)
SIGNAL board_status : std_logic_vector(1 DOWNTO 0); -- current state of fpga
-- delayed busy signal
SIGNAL ru_ctrl_busy_q : std_logic := '0'; -- used for edge detection
SIGNAL ru_ctrl_busy_qq : std_logic := '0'; -- used for delayed edge detection (for generate wb ack)
-- wishbone ack
SIGNAL wbs_reg_ack_int : std_logic := '0'; -- wishbone acknowledge internal
-- reset
SIGNAL reset_timer_int : std_logic := '0'; -- reset watchdog timer (triggers on falling edge)
SIGNAL reset_timer_cnt : std_logic_vector(15 DOWNTO 0); -- counter for reset watchdog timer (the watchdog reset must
-- be active for at least 250 ns!!)
BEGIN
-- wishbone data out
wbs_reg_dat_o <= x"00" & boot_addr;
wbs_reg_ack <= wbs_reg_ack_int;
-- data to remote update controller
ru_ctrl_dat_in_proc : PROCESS (ru_ctrl_state, boot_addr) IS
BEGIN
CASE ru_ctrl_state IS
WHEN WRITE_BOOT_ADDR_WB_FALLBACK =>
ru_ctrl_data_in <= boot_addr(23 DOWNTO 0);
WHEN WRITE_BOOT_ADDR =>
ru_ctrl_data_in <= LOAD_FPGA_IMAGE_ADR(23 DOWNTO 0);
WHEN WRITE_WATCHDOG_ENABLE =>
-- enable watchdog
ru_ctrl_data_in <= x"000001";
WHEN WRITE_WATCHDOG_VALUE =>
-- the first 12 bit are the highest 12 bit (of 29 bit) in the watchdog timer value
ru_ctrl_data_in <= x"000" & x"100"; -- => 33554432 clock cycle (2^25) => ~1 sec
WHEN OTHERS =>
ru_ctrl_data_in <= x"000000";
END CASE;
END PROCESS;
-- reset remote update controller when reconfiguration from FPGA Image
ru_ctrl_reset <= rst; -- reset remote update controller
ru_ctrl_reconfig <= '1' WHEN ru_ctrl_state = RECONFIGURE ELSE '0'; -- start reconfiguration
ru_ctrl_reset_timer <= reset_timer_int; -- reset watchdog timer
-- register out
reg_reconfig_cond <= reconfig_cond; -- reconfiguration trigger condition of last reconfiguration
reg_board_status <= board_status; -- gives information whether the loading process was successful or not
-- wishbone acknowledge and watchdog counter
ru_ctrl_wb_ack_and_wdog_cnt_proc : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
wbs_reg_ack_int <= '0';
reset_timer_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN
-- wishbone acknowledge
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' AND wbs_reg_ack_int = '0' THEN
wbs_reg_ack_int <= '1';
ELSIF wbs_reg_cyc = '1' AND wbs_reg_we = '0' AND ru_ctrl_busy_qq = '1' AND ru_ctrl_busy_q = '0' THEN
-- read acknowledge when busy falling edge delayed by 1 cycle (1 cycle needed to write the register)
wbs_reg_ack_int <= '1';
ELSE
wbs_reg_ack_int <= '0';
END IF;
-- watchdog counter
IF ru_ctrl_state = FPGA_IMAGE THEN
reset_timer_cnt <= std_logic_vector(unsigned(reset_timer_cnt) + 1);
ELSE
reset_timer_cnt <= (OTHERS=>'0');
END IF;
END IF;
END PROCESS;
ru_ctrl_cyc3_cyc4_proc : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
ru_ctrl_state <= IDLE;
ru_ctrl_param <= (OTHERS=>'0');
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= (OTHERS=>'0');
ru_ctrl_write_param <= '0';
ru_ctrl_busy_q <= '0';
ru_ctrl_busy_qq <= '0';
reconfig_cond <= (OTHERS=>'0');
curr_state <= (OTHERS=>'0');
board_status <= (OTHERS=>'0');
boot_addr <= (OTHERS=>'0');
reset_timer_int <= '0';
ELSIF falling_edge(clk) THEN
ru_ctrl_busy_q <= ru_ctrl_busy;
ru_ctrl_busy_qq <= ru_ctrl_busy_q;
-- board status register
IF (ru_ctrl_state = CHECK_STATE
AND ( reconfig_cond(3) = '1' -- CRC-Error
OR reconfig_cond(2) = '1' -- nStatus triggered
OR reconfig_cond(1) = '1' -- watchdog timeout
) ) THEN
board_status <= "10"; -- error while loading image (FPGA Fallback Image is loaded!)
ELSIF curr_state /= "00" THEN
board_status <= "01"; -- FPGA Image loaded
END IF;
-- last reconfiguration condition register
IF ru_ctrl_state = READ_RECONFIG_COND AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
reconfig_cond <= ru_ctrl_data_out(4 DOWNTO 0); -- get data from remote update block
END IF;
-- current state register
IF ru_ctrl_state = READ_CURR_STATE AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
curr_state <= ru_ctrl_data_out(1 DOWNTO 0); -- get data from remote update block
END IF;
-- boot address register
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' THEN
IF wbs_reg_sel(0) = '1' THEN
boot_addr(7 DOWNTO 2) <= wbs_reg_dat_i(7 DOWNTO 2);
END IF;
IF wbs_reg_sel(1) = '1' THEN
boot_addr(15 DOWNTO 8) <= wbs_reg_dat_i(15 DOWNTO 8);
END IF;
IF wbs_reg_sel(2) = '1' THEN
boot_addr(23 DOWNTO 16) <= wbs_reg_dat_i(23 DOWNTO 16);
END IF;
ELSIF ru_ctrl_state = READ_BOOT_ADDR_WB_FALLBACK AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- read boot address from remote update controller at falling edge of busy signal
-- on FPGA Fallback Image the boot address width is 22 bit
boot_addr <= ru_ctrl_data_out(21 DOWNTO 0) & "00";
ELSIF ru_ctrl_state = READ_BOOT_ADDR_WB_FGPA_IMAGE AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- read boot address from remote update controller at falling edge of busy signal
-- on FPGA Image the boot address width is 22 bit
boot_addr <= ru_ctrl_data_out(23 DOWNTO 0);
END IF;
CASE ru_ctrl_state IS
WHEN IDLE =>
-- read current state of remote update controller
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_STATE_MODE_PAR_CYC4; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= (OTHERS=>'0'); -- read from current source
ru_ctrl_write_param <= '0';
WHEN READ_CURR_STATE =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' AND curr_state = "00" THEN
-- read reconfiguration trigger condition source when in Factory Mode
ru_ctrl_state <= READ_RECONFIG_COND;
ru_ctrl_param <= Z126_01_RU_RECONF_CON_PAR_CYC4; -- reconfiguration trigger condition source
ru_ctrl_read_param <= '1';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_PREVIOUS_1; -- read from past source
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- the FPGA Image is successfully loaded
-- the reconfiguration condition can only be read in Factory Mode!
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle longer to store data in curr_state register
-- disable remote update controller access
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSE
-- read current state of remote update controller
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_STATE_MODE_PAR_CYC4; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT; -- read from current source
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_RECONFIG_COND =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- check in which state is the FPGA
ru_ctrl_state <= CHECK_STATE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSE
-- read reconfiguration trigger condition source
ru_ctrl_state <= READ_RECONFIG_COND;
ru_ctrl_param <= Z126_01_RU_RECONF_CON_PAR_CYC4; -- reconfiguration trigger condition source
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_PREVIOUS_1; -- read from past source
ru_ctrl_write_param <= '0';
END IF;
WHEN CHECK_STATE =>
IF LOAD_FPGA_IMAGE = TRUE AND reconfig_cond(3) = '0' AND reconfig_cond(2) = '0' AND reconfig_cond(1) = '0' THEN
-- we are still in the FPGA Fallback Image and no error
-- start loading the FPGA Image (enable watchdog)
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR;
ru_ctrl_param <= Z126_01_RU_BOOT_ADR_PAR_CYC4; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- the FPGA Fallback Image is loaded
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
END IF;
WHEN WRITE_WATCHDOG_VALUE =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- enable watchdog
ru_ctrl_state <= WRITE_WATCHDOG_ENABLE;
ru_ctrl_param <= Z126_01_RU_WDOG_EN_PAR_CYC4; -- watchdog enable
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- write watchdog time out value
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC4; -- watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_WATCHDOG_ENABLE =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- reconfiguration
ru_ctrl_state <= RECONFIGURE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSE
-- enable watchdog
ru_ctrl_state <= WRITE_WATCHDOG_ENABLE;
ru_ctrl_param <= Z126_01_RU_WDOG_EN_PAR_CYC4; -- watchdog enable
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_BOOT_ADDR =>
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- write watchdog time out value and start reconfiguration
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC4; -- watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR;
ru_ctrl_param <= Z126_01_RU_BOOT_ADR_PAR_CYC4; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN RECONFIGURE =>
-- start reconfiguration
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
-- fpga should be reconfigurated so the fsm should stay in this state
-- until the reconfiguration is finished
ru_ctrl_state <= RECONFIGURE;
WHEN FPGA_IMAGE =>
-- reset the watchdog timer if the FPGA Image is successfully loaded
-- (the watchdog timer is reset on falling edge of reset_timer_int)
-- if the watchdog expires the FPGA Fallback Image will be loaded again
reset_timer_int <= reset_timer_cnt(reset_timer_cnt'high);
IF wbs_reg_cyc = '1' AND wbs_reg_we = '0' THEN
-- indirecte interface register access read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= Z126_01_RU_BOOT_ADR_PAR_CYC4; -- boot address
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_PREVIOUS_2; -- current Application Mode boot address
ru_ctrl_write_param <= '0';
ELSIF reg_reconfig = '1' THEN
-- start reconfiguration
ru_ctrl_state <= RECONFIGURE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSE
-- stay in FPGA Image
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
END IF;
WHEN FALLBACK_IMAGE =>
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' THEN
-- indirecte interface register access write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_BOOT_ADR_PAR_CYC4; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
ELSIF wbs_reg_cyc = '1' AND wbs_reg_we = '0' THEN
-- indirecte interface register access read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_BOOT_ADR_PAR_CYC4; -- boot address
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_INPUT_REG; -- read boot address from Factory Mode
-- (current contents is in input register)
ru_ctrl_write_param <= '0';
ELSIF reg_reconfig = '1' THEN
-- enable watchdog and start reconfiguration
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC4; -- set watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_BOOT_ADDR_WB_FALLBACK =>
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSE
-- read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_BOOT_ADR_PAR_CYC4; -- boot address
ru_ctrl_read_param <= '1'; -- write access
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_INPUT_REG; -- read boot address from Factory Mode
-- (current contents is in input register)
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_BOOT_ADDR_WB_FGPA_IMAGE =>
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- stay in FPGA Image
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- disable remote update controller access
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSE
-- read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= Z126_01_RU_BOOT_ADR_PAR_CYC4; -- boot address
ru_ctrl_read_param <= '1'; -- write access
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_PREVIOUS_2; -- current Application Mode boot address
ru_ctrl_write_param <= '0';
END IF;
WHEN WRITE_BOOT_ADDR_WB_FALLBACK =>
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
ELSE
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_BOOT_ADR_PAR_CYC4; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '1'; -- write access
END IF;
-- coverage off
WHEN OTHERS =>
ru_ctrl_state <= IDLE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_read_source <= Z126_01_RU_RD_SRC_CURRENT;
ru_ctrl_write_param <= '0';
-- coverage on
END CASE;
END IF;
END PROCESS;
END z126_01_ru_ctrl_arch;
z126_01_ru_ctrl_cyc5.vhd 0000664 0000000 0000000 00000072226 14574545710 0035172 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Remote Update Control
-- Project : General IP-core
---------------------------------------------------------------
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 14.0.2
---------------------------------------------------------------
-- Description : The module is used to control the
-- serial loading of the FPGA image using the
-- altera remote update block.
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_ru_ctrl_cyc5.vhd
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: z126_01_ru_ctrl_cyc5.vhd,v $
-- Revision 1.3 2015/02/18 16:58:36 AGeissler
-- R1: The remote update controller for CYCLONE V from altera
-- needs a startup time to initialize the internal registers
-- M1: Added state START_UP_WAIT to wait 128 clock cycles
-- R2: Missing data out for state WRITE_CURR_STATE
-- M2: Write 1 to configuration mode (AnF)
-- R3: Wrong bit ordering for reconfig_cond register because of change
-- internal register bits meaning for CYCLONE V
-- M3: Changed assignment to connect the register that the bit meaning
-- is equal to CYCLONE IV
-- R4: Wrong transition from CHECK_STATE to WRITE_CURR_STATE
-- M4: Changed transition to WRITE_BOOT_ADDR and adjust ru_ctrl_param
-- R5: The boot address is read wrong, it could be connected directly
-- M5: Changed boot address assignment
--
-- Revision 1.2 2014/12/02 10:32:27 AGeissler
-- R1: The watchdog value is not correctly set, so that the user image could not
-- be loaded
-- M1: Changed param value from enable to value
--
-- Revision 1.1 2014/11/24 16:44:18 AGeissler
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
USE work.z126_01_pkg.all;
ENTITY z126_01_ru_ctrl_cyc5 IS
GENERIC
(
FPGA_FAMILY : family_type := CYCLONE5; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT
(
clk : IN std_logic; -- system clock
rst : IN std_logic; -- unit ru_ctrl_reset
-- register interface
wbs_reg_cyc : IN std_logic;
wbs_reg_ack : OUT std_logic;
wbs_reg_we : IN std_logic;
wbs_reg_sel : IN std_logic_vector(3 DOWNTO 0);
wbs_reg_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_reg_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : IN std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : OUT std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : OUT std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- ALTREMOTE_UPDATE interface
ru_ctrl_busy : IN std_logic;
ru_ctrl_data_out : IN std_logic_vector(23 DOWNTO 0); -- data from altera remote update module
ru_ctrl_data_in : OUT std_logic_vector(23 DOWNTO 0); -- data to altera remote update module
ru_ctrl_param : OUT std_logic_vector(2 DOWNTO 0);
ru_ctrl_read_param : OUT std_logic;
ru_ctrl_reconfig : OUT std_logic;
ru_ctrl_reset_timer : OUT std_logic;
ru_ctrl_reset : OUT std_logic;
ru_ctrl_write_param : OUT std_logic
);
END z126_01_ru_ctrl_cyc5;
ARCHITECTURE z126_01_ru_ctrl_cyc5_arch OF z126_01_ru_ctrl_cyc5 IS
TYPE ru_ctrl_states IS (IDLE,
START_UP_WAIT,
READ_CURR_STATE,
READ_RECONFIG_COND,
CHECK_STATE,
WRITE_CURR_STATE,
WRITE_BOOT_ADDR,
WRITE_WATCHDOG_VALUE,
WRITE_WATCHDOG_ENABLE,
RECONFIGURE,
FPGA_IMAGE,
FALLBACK_IMAGE,
WRITE_BOOT_ADDR_WB_FALLBACK,
READ_BOOT_ADDR_WB_FALLBACK,
READ_BOOT_ADDR_WB_FGPA_IMAGE
);
CONSTANT SUPPORTED_DEVICES : supported_family_types := (CYCLONE3, CYCLONE4);
SIGNAL ru_ctrl_state : ru_ctrl_states := IDLE; -- remote update control block state signal
-- registers
SIGNAL reconfig_cond : std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
SIGNAL curr_state : std_logic; -- current state of fpga
-- '1' => A FPGA image is loaded
-- '0' => Fallback FPGA image is loaded
SIGNAL boot_addr : std_logic_vector(23 DOWNTO 0); -- fpga boot addr (only write able in Factory Mode)
SIGNAL board_status : std_logic_vector(1 DOWNTO 0); -- current state of fpga
-- delayed busy signal
SIGNAL ru_ctrl_busy_q : std_logic := '0'; -- used for edge detection
SIGNAL ru_ctrl_busy_qq : std_logic := '0'; -- used for delayed edge detection (for generate wb ack)
-- wishbone ack
SIGNAL wbs_reg_ack_int : std_logic := '0'; -- wishbone acknowledge internal
-- reset
SIGNAL reset_timer_int : std_logic := '0'; -- reset watchdog timer (triggers on falling edge)
SIGNAL reset_timer_cnt : std_logic_vector(15 DOWNTO 0); -- counter for reset watchdog timer (the watchdog reset must
-- be active for at least 250 ns!!)
-- startup counter
SIGNAL startup_cnt : unsigned(7 DOWNTO 0); -- startup count for FPGA initialization
BEGIN
-- wishbone data out
wbs_reg_dat_o <= x"00" & boot_addr;
wbs_reg_ack <= wbs_reg_ack_int;
-- data to remote update controller
ru_ctrl_dat_in_proc : PROCESS (ru_ctrl_state, boot_addr) IS
BEGIN
CASE ru_ctrl_state IS
WHEN WRITE_BOOT_ADDR_WB_FALLBACK =>
ru_ctrl_data_in <= boot_addr(23 DOWNTO 0);
WHEN WRITE_BOOT_ADDR =>
ru_ctrl_data_in <= LOAD_FPGA_IMAGE_ADR(23 DOWNTO 0);
WHEN WRITE_WATCHDOG_ENABLE =>
-- enable watchdog
ru_ctrl_data_in <= x"000001";
WHEN WRITE_WATCHDOG_VALUE =>
-- the first 12 bit are the highest 12 bit (of 29 bit) in the watchdog timer value
ru_ctrl_data_in <= x"000" & x"100"; -- => 33554432 clock cycle (2^25) => ~1 sec
WHEN WRITE_CURR_STATE =>
ru_ctrl_data_in <= x"000001"; -- write '1' to Configuration Mode (AnF)
WHEN OTHERS =>
ru_ctrl_data_in <= x"000000";
END CASE;
END PROCESS;
-- reset remote update controller when reconfiguration from FPGA Image
ru_ctrl_reset <= rst; -- reset remote update controller
ru_ctrl_reconfig <= '1' WHEN ru_ctrl_state = RECONFIGURE ELSE '0'; -- start reconfiguration
ru_ctrl_reset_timer <= reset_timer_int; -- reset watchdog timer
-- register out
reg_reconfig_cond <= reconfig_cond; -- reconfiguration trigger condition of last reconfiguration
reg_board_status <= board_status; -- gives information whether the loading process was successful or not
-- wishbone acknowledge and watchdog counter
ru_ctrl_wb_ack_and_wdog_cnt_proc : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
wbs_reg_ack_int <= '0';
reset_timer_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN
-- wishbone acknowledge
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' AND wbs_reg_ack_int = '0' THEN
wbs_reg_ack_int <= '1';
ELSIF wbs_reg_cyc = '1' AND wbs_reg_we = '0' AND ru_ctrl_busy_qq = '1' AND ru_ctrl_busy_q = '0' THEN
-- read acknowledge when busy falling edge delayed by 1 cycle (1 cycle needed to write the register)
wbs_reg_ack_int <= '1';
ELSE
wbs_reg_ack_int <= '0';
END IF;
-- watchdog counter
IF ru_ctrl_state = FPGA_IMAGE THEN
reset_timer_cnt <= std_logic_vector(unsigned(reset_timer_cnt) + 1);
ELSE
reset_timer_cnt <= (OTHERS=>'0');
END IF;
END IF;
END PROCESS;
ru_ctrl_cyc5_proc : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
ru_ctrl_state <= IDLE;
ru_ctrl_param <= (OTHERS=>'0');
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ru_ctrl_busy_q <= '0';
ru_ctrl_busy_qq <= '0';
reconfig_cond <= (OTHERS=>'0');
curr_state <= '0';
board_status <= (OTHERS=>'0');
boot_addr <= (OTHERS=>'0');
startup_cnt <= (OTHERS=>'0');
reset_timer_int <= '0';
ELSIF falling_edge(clk) THEN
ru_ctrl_busy_q <= ru_ctrl_busy;
ru_ctrl_busy_qq <= ru_ctrl_busy_q;
-- board status register
IF (ru_ctrl_state = CHECK_STATE
AND ( reconfig_cond(3) = '1' -- CRC-Error
OR reconfig_cond(2) = '1' -- nStatus triggered
OR reconfig_cond(1) = '1' -- watchdog timeout
) ) THEN
board_status <= "10"; -- error while loading image (FPGA Fallback Image is loaded!)
ELSIF curr_state = '1' THEN
board_status <= "01"; -- FPGA Image loaded
END IF;
-- last reconfiguration condition register
IF ru_ctrl_state = READ_RECONFIG_COND AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- The register reconfig_cond shall have the same bit meaning as for Cyclone IV devices
reconfig_cond(0) <= ru_ctrl_data_out(2); -- runconfig_source - Configuration reset triggered from logic array.
reconfig_cond(1) <= ru_ctrl_data_out(4); -- wdtimer_source - User Watchdog Timer timeout.
reconfig_cond(2) <= ru_ctrl_data_out(1); -- nstatus_source - nSTATUS asserted by an external device as the result of an error
reconfig_cond(3) <= ru_ctrl_data_out(0); -- crcerror_source - CRC error during application configuration
reconfig_cond(4) <= ru_ctrl_data_out(3); -- nconfig_source - External configuration reset (nCONFIG) assertion.
END IF;
-- current state register
IF ru_ctrl_state = READ_CURR_STATE AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
curr_state <= ru_ctrl_data_out(0); -- get data from remote update block
END IF;
-- boot address register
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' THEN
IF wbs_reg_sel(0) = '1' THEN
boot_addr(7 DOWNTO 2) <= wbs_reg_dat_i(7 DOWNTO 2);
END IF;
IF wbs_reg_sel(1) = '1' THEN
boot_addr(15 DOWNTO 8) <= wbs_reg_dat_i(15 DOWNTO 8);
END IF;
IF wbs_reg_sel(2) = '1' THEN
boot_addr(23 DOWNTO 16) <= wbs_reg_dat_i(23 DOWNTO 16);
END IF;
ELSIF ru_ctrl_state = READ_BOOT_ADDR_WB_FALLBACK AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- read boot address from remote update controller at falling edge of busy signal
-- on FPGA Fallback Image the boot address width is 22 bit
boot_addr <= ru_ctrl_data_out(23 DOWNTO 0);
ELSIF ru_ctrl_state = READ_BOOT_ADDR_WB_FGPA_IMAGE AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- read boot address from remote update controller at falling edge of busy signal
-- on FPGA Image the boot address width is 22 bit
boot_addr <= ru_ctrl_data_out(23 DOWNTO 0);
END IF;
CASE ru_ctrl_state IS
WHEN IDLE =>
-- read current state of remote update controller
ru_ctrl_state <= START_UP_WAIT;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
WHEN START_UP_WAIT =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF startup_cnt(startup_cnt'HIGH) = '1' THEN
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
startup_cnt <= (OTHERS=>'0');
ELSE
ru_ctrl_state <= START_UP_WAIT;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
startup_cnt <= startup_cnt + 1;
END IF;
WHEN READ_CURR_STATE =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' AND curr_state = '0' THEN
-- read reconfiguration trigger condition source when in Factory Mode
ru_ctrl_state <= READ_RECONFIG_COND;
ru_ctrl_param <= Z126_01_RU_RECONF_CON_PAR_CYC5; -- reconfiguration trigger condition source
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- the FPGA Image is successfully loaded
-- the reconfiguration condition can only be read in Factory Mode!
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle longer to store data in curr_state register
-- disable remote update controller access
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read current state of remote update controller
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- read current state
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_RECONFIG_COND =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- check in which state is the FPGA
ru_ctrl_state <= CHECK_STATE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read reconfiguration trigger condition source
ru_ctrl_state <= READ_RECONFIG_COND;
ru_ctrl_param <= Z126_01_RU_RECONF_CON_PAR_CYC5; -- reconfiguration trigger condition source
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
END IF;
WHEN CHECK_STATE =>
IF LOAD_FPGA_IMAGE = TRUE AND reconfig_cond(3) = '0' AND reconfig_cond(2) = '0' AND reconfig_cond(1) = '0' THEN
-- we are still in the FPGA Fallback Image and no error
-- start loading the FPGA Image (enable watchdog, write boot address and write current state)
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- the FPGA Fallback Image is loaded
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN WRITE_WATCHDOG_VALUE =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- enable watchdog
ru_ctrl_state <= WRITE_WATCHDOG_ENABLE;
ru_ctrl_param <= Z126_01_RU_WDOG_EN_PAR_CYC5; -- watchdog enable
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- write watchdog time out value
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_WATCHDOG_ENABLE =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- write current mode to '1' => FPGA Image
ru_ctrl_state <= WRITE_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- write current mode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- enable watchdog
ru_ctrl_state <= WRITE_WATCHDOG_ENABLE;
ru_ctrl_param <= Z126_01_RU_WDOG_EN_PAR_CYC5; -- watchdog enable
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_CURR_STATE =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- reconfiguration
ru_ctrl_state <= RECONFIGURE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- write current mode to '1' => FPGA Image
ru_ctrl_state <= WRITE_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- write current mode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_BOOT_ADDR =>
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- write watchdog time out value and start reconfiguration
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN RECONFIGURE =>
-- start reconfiguration
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
-- fpga should be reconfigurated so the fsm should stay in this state
-- until the reconfiguration is finished
ru_ctrl_state <= RECONFIGURE;
WHEN FPGA_IMAGE =>
-- reset the watchdog timer if the FPGA Image is successfully loaded
-- (the watchdog timer is reset on falling edge of reset_timer_int)
-- if the watchdog expires the FPGA Fallback Image will be loaded again
reset_timer_int <= reset_timer_cnt(reset_timer_cnt'high);
IF wbs_reg_cyc = '1' AND wbs_reg_we = '0' THEN
-- indirecte interface register access read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF reg_reconfig = '1' THEN
-- start reconfiguration
ru_ctrl_state <= RECONFIGURE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- stay in FPGA Image
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN FALLBACK_IMAGE =>
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' THEN
-- indirecte interface register access write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSIF wbs_reg_cyc = '1' AND wbs_reg_we = '0' THEN
-- indirecte interface register access read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF reg_reconfig = '1' THEN
-- enable watchdog and start reconfiguration
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- set watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_BOOT_ADDR_WB_FALLBACK =>
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- write access
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_BOOT_ADDR_WB_FGPA_IMAGE =>
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- stay in FPGA Image
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- disable remote update controller access
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- write access
ru_ctrl_write_param <= '0';
END IF;
WHEN WRITE_BOOT_ADDR_WB_FALLBACK =>
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
-- coverage off
WHEN OTHERS =>
ru_ctrl_state <= IDLE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
-- coverage on
END CASE;
END IF;
END PROCESS;
END z126_01_ru_ctrl_cyc5_arch;
z126_01_switch_fab_2.vhd 0000664 0000000 0000000 00000022737 14574545710 0035131 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : z126_01_switch_fab_2.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
-- This module is derived from switch_fab_2.vhd of the 16z100-.
-- It contaions an additional arbitration of control
-- signals for the z126_01_wb2pasmi.vhd module in the 16z126-01
-- design.
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_switch_fab_2.vhd,v $
-- Revision 1.1 2014/03/03 17:49:53 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.z126_01_wb_pkg.ALL;
USE work.z126_01_pkg.ALL;
ENTITY z126_01_switch_fab_2 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic;
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END z126_01_switch_fab_2;
ARCHITECTURE z126_01_switch_fab_2_arch OF z126_01_switch_fab_2 IS
SUBTYPE sw_states IS std_logic_vector(1 DOWNTO 0);
CONSTANT sw_0 : sw_states := "01";
CONSTANT sw_1 : sw_states := "10";
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL wbi_slave_stb : std_logic;
BEGIN
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.bte, wbo_1.bte)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.bte <= wbo_0.bte;
WHEN sw_1 => wbi_slave.bte <= wbo_1.bte;
WHEN OTHERS => wbi_slave.bte <= wbo_0.bte;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
-- mux for wb2pasmi control signals
PROCESS( sw_state, ctrlmo_0, ctrlmo_1)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
ctrlsi_0.read_sid <= ctrlmo_0.read_sid;
ctrlsi_0.sector_protect <= ctrlmo_0.sector_protect;
ctrlsi_0.write <= ctrlmo_0.write;
ctrlsi_0.read_status <= ctrlmo_0.read_status;
ctrlsi_0.sector_erase <= ctrlmo_0.sector_erase;
ctrlsi_0.bulk_erase <= ctrlmo_0.bulk_erase;
WHEN sw_1 =>
ctrlsi_0.read_sid <= ctrlmo_1.read_sid;
ctrlsi_0.sector_protect <= ctrlmo_1.sector_protect;
ctrlsi_0.write <= ctrlmo_1.write;
ctrlsi_0.read_status <= ctrlmo_1.read_status;
ctrlsi_0.sector_erase <= ctrlmo_1.sector_erase;
ctrlsi_0.bulk_erase <= ctrlmo_1.bulk_erase;
WHEN OTHERS =>
ctrlsi_0.read_sid <= ctrlmo_0.read_sid;
ctrlsi_0.sector_protect <= ctrlmo_0.sector_protect;
ctrlsi_0.write <= ctrlmo_0.write;
ctrlsi_0.read_status <= ctrlmo_0.read_status;
ctrlsi_0.sector_erase <= ctrlmo_0.sector_erase;
ctrlsi_0.bulk_erase <= ctrlmo_0.bulk_erase;
END CASE;
END PROCESS;
ctrlmi_0.illegal_write <= ctrlso_0.illegal_write WHEN sw_state = sw_0 ELSE '0';
ctrlmi_0.illegal_erase <= ctrlso_0.illegal_erase WHEN sw_state = sw_0 ELSE '0';
ctrlmi_0.busy <= ctrlso_0.busy WHEN sw_state = sw_0 ELSE '0';
ctrlmi_1.illegal_write <= ctrlso_0.illegal_write WHEN sw_state = sw_1 ELSE '0';
ctrlmi_1.illegal_erase <= ctrlso_0.illegal_erase WHEN sw_state = sw_1 ELSE '0';
ctrlmi_1.busy <= ctrlso_0.busy WHEN sw_state = sw_1 ELSE '0';
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
END z126_01_switch_fab_2_arch;
z126_01_top.vhd 0000664 0000000 0000000 00000156201 14574545710 0033373 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Wishbone to Serial Flash Interface
-- Project : 16z126-01
---------------------------------------------------------------
-- File : z126_01_top.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
-- 16z126-01 is a Wishbone to Serial Flash interface Altera EPCS
-- Devices. Derived from 16z126-.
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_top
-- z126_01_ru_
-- z126_01_ru_ctrl
-- z126_01_indi_if_ctrl_regs
-- z126_01_clk_trans_indirect
-- z126_01_clk_trans_direct
-- z126_01_wb_if_arbiter
-- z126_01_wb2pasmi
-- z126_01_pasmi_
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.6 $
--
-- $Log: z126_01_top.vhd,v $
-- Revision 1.6 2015/02/19 14:01:52 AGeissler
-- R1: Warning message from quartus because of unused signal
-- M1: Only describe this signal when direct interface is used
--
-- Revision 1.5 2014/11/24 16:44:20 AGeissler
-- R1: New naming convention of FPGA images
-- M1.1: Renamed application image to FPGA Image
-- M1.2: Renamed factor image to FPGA Fallback Image
-- R2: Missing Cyclone V support
-- M2.1: Added z126_01_ru_ctrl_cyc5
-- M2.2: Added z126_01_ru_cyclonev_m25p32
-- M2.3: Added z126_01_ru_cyclonev_m25p64
-- M2.4: Added z126_01_ru_cyclonev_m25p128
--
-- Revision 1.4 2014/07/11 09:58:16 AGeissler
-- R1: Components are needed even if they are not used
-- M1: Added components instead of entities
--
-- Revision 1.3 2014/06/18 17:06:07 AGeissler
-- R1: The z126_01_pasmi_sim_m25p32 was be added in the source fileset
-- M1: Added a component instead of using the entity directly
--
-- Revision 1.2 2014/03/05 11:19:41 AGeissler
-- R: Missing signal connection
-- M: Added
--
-- Revision 1.1 2014/03/03 17:49:54 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.z126_01_wb_pkg.ALL;
USE work.z126_01_pkg.ALL;
USE work.fpga_pkg_2.ALL;
ENTITY z126_01_top IS
GENERIC (
SIMULATION : boolean := FALSE; -- true => use the altasmi parallel of an older quartus version (11.1 SP2) the new one can not be simulated
-- (only the M25P32 is supported for simulation!!)
-- false => use the newest altasmi parallel (13.0)
FPGA_FAMILY : family_type := CYCLONE5; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
FLASH_TYPE : flash_type := M25P32; -- see SUPPORTED_DEVICES for supported serial flash device types
USE_DIRECT_INTERFACE : boolean := TRUE; -- true => the direct interfaces is included and arbitrated with the indirect interface
-- false => only the indirect interface is available (reducing resource consumption)
USE_REMOTE_UPDATE : boolean := TRUE; -- true => the remote update controller is included and more than one FPGA image can be selected
-- false => only the FPGA Fallback Image can be used for FPGA configuration (reducing resource consumption)
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT (
clk_40mhz : IN std_logic; -- serial flash clock (maximum 40 MHz)
rst_clk_40mhz : IN std_logic; -- this reset should be a power up reset to
-- reduce the reconfiguration (load FPGA Image) time when LOAD_FPGA_IMAGE = TRUE.
-- this reset must be deasserted synchronous to the clk_40mhz
clk_dir : IN std_logic; -- wishbone clock for direct interface
rst_dir : IN std_logic; -- wishbone async high active reset
-- this reset must be deasserted synchronous to the clk_dir
clk_indi : IN std_logic; -- wishbone clock for indirect interface
rst_indi : IN std_logic; -- wishbone async high active reset
-- this reset must be deasserted synchronous to the clk_indi
board_status : OUT std_logic_vector(1 DOWNTO 0);
-- wishbone signals slave interface 0 (direct addressing)
wbs_stb_dir : IN std_logic; -- request
wbs_ack_dir : OUT std_logic; -- acknoledge
wbs_we_dir : IN std_logic; -- write=1 read=0
wbs_sel_dir : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc_dir : IN std_logic; -- chip select
wbs_dat_o_dir : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i_dir : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr_dir : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_err_dir : OUT std_logic; -- error
-- wishbone signals slave interface 1 (indirect addressing)
wbs_stb_indi : IN std_logic; -- request
wbs_ack_indi : OUT std_logic; -- acknoledge
wbs_we_indi : IN std_logic; -- write=1 read=0
wbs_sel_indi : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc_indi : IN std_logic; -- chip select
wbs_dat_o_indi : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i_indi : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr_indi : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_err_indi : OUT std_logic -- error
);
END z126_01_top;
ARCHITECTURE z126_01_top_arch OF z126_01_top IS
--------------------------------------------------------
-- components
--------------------------------------------------------
COMPONENT z126_01_pasmi_m25p32 IS
PORT
(
addr : IN std_logic_vector(23 DOWNTO 0);
bulk_erase : IN std_logic ;
clkin : IN std_logic ;
datain : IN std_logic_vector(7 DOWNTO 0);
fast_read : IN std_logic ;
rden : IN std_logic ;
read_rdid : IN std_logic ;
read_status : IN std_logic ;
reset : IN STD_LOGIC ;
sector_erase : IN std_logic ;
sector_protect : IN std_logic ;
shift_bytes : IN std_logic ;
wren : IN std_logic ;
write : IN std_logic ;
busy : OUT std_logic ;
data_valid : OUT std_logic ;
dataout : OUT std_logic_vector (7 DOWNTO 0);
illegal_erase : OUT std_logic ;
illegal_write : OUT std_logic ;
rdid_out : OUT std_logic_vector(7 DOWNTO 0);
status_out : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT z126_01_pasmi_sim_m25p32 IS
PORT
(
addr : IN std_logic_vector(23 DOWNTO 0);
bulk_erase : IN std_logic;
clkin : IN std_logic;
datain : IN std_logic_vector(7 DOWNTO 0);
fast_read : IN std_logic;
rden : IN std_logic;
read_rdid : IN std_logic;
read_status : IN std_logic;
sector_erase : IN std_logic;
sector_protect : IN std_logic;
shift_bytes : IN std_logic;
wren : IN std_logic;
write : IN std_logic;
busy : OUT std_logic;
data_valid : OUT std_logic;
dataout : OUT std_logic_vector(7 DOWNTO 0);
illegal_erase : OUT std_logic ;
illegal_write : OUT std_logic ;
rdid_out : OUT std_logic_vector(7 DOWNTO 0);
status_out : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT z126_01_pasmi_m25p64 IS
PORT
(
addr : IN std_logic_vector(23 DOWNTO 0);
bulk_erase : IN std_logic ;
clkin : IN std_logic ;
datain : IN std_logic_vector(7 DOWNTO 0);
fast_read : IN std_logic ;
rden : IN std_logic ;
read_rdid : IN std_logic ;
read_status : IN std_logic ;
reset : IN std_logic ;
sector_erase : IN std_logic ;
sector_protect : IN std_logic ;
shift_bytes : IN std_logic ;
wren : IN std_logic ;
write : IN std_logic ;
busy : OUT std_logic ;
data_valid : OUT std_logic ;
dataout : OUT std_logic_vector (7 DOWNTO 0);
illegal_erase : OUT std_logic ;
illegal_write : OUT std_logic ;
rdid_out : OUT std_logic_vector(7 DOWNTO 0);
status_out : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT z126_01_pasmi_m25p128 IS
PORT
(
addr : IN std_logic_vector(23 DOWNTO 0);
bulk_erase : IN std_logic ;
clkin : IN std_logic ;
datain : IN std_logic_vector(7 DOWNTO 0);
fast_read : IN std_logic ;
rden : IN std_logic ;
read_rdid : IN std_logic ;
read_status : IN std_logic ;
reset : IN std_logic ;
sector_erase : IN std_logic ;
sector_protect : IN std_logic ;
shift_bytes : IN std_logic ;
wren : IN std_logic ;
write : IN std_logic ;
busy : OUT std_logic ;
data_valid : OUT std_logic ;
dataout : OUT std_logic_vector (7 DOWNTO 0);
illegal_erase : OUT std_logic ;
illegal_write : OUT std_logic ;
rdid_out : OUT std_logic_vector(7 DOWNTO 0);
status_out : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT z126_01_ru_cycloneiii IS
PORT
(
clock : IN std_logic;
data_in : IN std_logic_vector(23 DOWNTO 0);
param : IN std_logic_vector(2 DOWNTO 0);
read_param : IN std_logic;
read_source : IN std_logic_vector(1 DOWNTO 0);
reconfig : IN std_logic;
reset : IN std_logic;
reset_timer : IN std_logic;
write_param : IN std_logic;
busy : OUT std_logic;
data_out : OUT std_logic_vector(28 DOWNTO 0)
);
END COMPONENT;
COMPONENT z126_01_ru_cycloneiv IS
PORT
(
clock : IN std_logic;
data_in : IN std_logic_vector(23 DOWNTO 0);
param : IN std_logic_vector(2 DOWNTO 0);
read_param : IN std_logic;
read_source : IN std_logic_vector(1 DOWNTO 0);
reconfig : IN std_logic;
reset : IN std_logic;
reset_timer : IN std_logic;
write_param : IN std_logic;
busy : OUT std_logic;
data_out : OUT std_logic_vector(28 DOWNTO 0)
);
END COMPONENT;
--COMPONENT z126_01_ru_cyclonev_m25p32 IS
-- PORT
-- (
-- clock : IN std_logic;
-- data_in : IN std_logic_vector(23 DOWNTO 0);
-- param : IN std_logic_vector(2 DOWNTO 0);
-- read_param : IN std_logic;
-- reconfig : IN std_logic;
-- reset : IN std_logic;
-- reset_timer : IN std_logic;
-- write_param : IN std_logic;
-- busy : OUT std_logic;
-- data_out : OUT std_logic_vector(23 DOWNTO 0)
-- );
--END COMPONENT;
--
--COMPONENT z126_01_ru_cyclonev_m25p64 IS
-- PORT
-- (
-- clock : IN std_logic;
-- data_in : IN std_logic_vector(23 DOWNTO 0);
-- param : IN std_logic_vector(2 DOWNTO 0);
-- read_param : IN std_logic;
-- reconfig : IN std_logic;
-- reset : IN std_logic;
-- reset_timer : IN std_logic;
-- write_param : IN std_logic;
-- busy : OUT std_logic;
-- data_out : OUT std_logic_vector(23 DOWNTO 0)
-- );
--END COMPONENT;
--
--COMPONENT z126_01_ru_cyclonev_m25p128 IS
-- PORT
-- (
-- clock : IN std_logic;
-- data_in : IN std_logic_vector(23 DOWNTO 0);
-- param : IN std_logic_vector(2 DOWNTO 0);
-- read_param : IN std_logic;
-- reconfig : IN std_logic;
-- reset : IN std_logic;
-- reset_timer : IN std_logic;
-- write_param : IN std_logic;
-- busy : OUT std_logic;
-- data_out : OUT std_logic_vector(23 DOWNTO 0)
-- );
--END COMPONENT;
COMPONENT z126_01_clk_trans_wb2wb IS
GENERIC (
NBR_OF_CYC : integer range 1 TO 100 := 1;
NBR_OF_TGA : integer range 1 TO 100 := 6
);
PORT (
rstn : IN std_logic;
-- a MHz domain
clk_a : IN std_logic;
cyc_a : IN std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_a : IN std_logic; -- request signal from a MHz side
ack_a : OUT std_logic; -- adopted acknoledge signal to b MHz
err_a : OUT std_logic;
we_a : IN std_logic; -- '1' = write, '0' = read
tga_a : IN std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_a : IN std_logic_vector(2 DOWNTO 0); -- transfer type
bte_a : IN std_logic_vector(1 DOWNTO 0); -- incremental burst
adr_a : IN std_logic_vector(31 DOWNTO 0); -- adr from a MHz side
sel_a : IN std_logic_vector(3 DOWNTO 0); -- byte enables from a MHz side
dat_i_a : IN std_logic_vector(31 DOWNTO 0); -- data from a MHz side
dat_o_a : OUT std_logic_vector(31 DOWNTO 0); -- data from b MHz side to a MHz side
-- b MHz domain
clk_b : IN std_logic;
cyc_b : OUT std_logic_vector(NBR_OF_CYC-1 DOWNTO 0);
stb_b : OUT std_logic; -- request signal adopted to b MHz
ack_b : IN std_logic; -- acknoledge signal from internal bus
err_b : IN std_logic;
we_b : OUT std_logic; -- '1' = write, '0' = read
tga_b : OUT std_logic_vector(NBR_OF_TGA-1 DOWNTO 0);
cti_b : OUT std_logic_vector(2 DOWNTO 0); -- transfer type
bte_b : OUT std_logic_vector(1 DOWNTO 0); -- incremental burst
adr_b : OUT std_logic_vector(31 DOWNTO 0); -- adr from b MHz side
sel_b : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for b MHz side
dat_i_b : IN std_logic_vector(31 DOWNTO 0); -- data from b MHz side
dat_o_b : OUT std_logic_vector(31 DOWNTO 0) -- data from a MHz side to b MHz side
);
END COMPONENT;
COMPONENT z126_01_wb_if_arbiter IS
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- master 0 interface
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic;
-- wb2pasmi master 0 control signals
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
-- master 1 interface
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic;
-- wb2pasmi master 1 control signals
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
-- slave 0 interface
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
-- wb2pasmi slave 0 control signals
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END COMPONENT;
COMPONENT z126_01_indi_if_ctrl_regs IS
PORT (
clk : IN std_logic; -- Wishbone clock (66 MHz)
rst : IN std_logic; -- Reset
-- wishbone signals master interface (ru_ctrol interace)
wbm_ru_cyc : OUT std_logic;
wbm_ru_ack : IN std_logic;
wbm_ru_we : OUT std_logic;
wbm_ru_sel : OUT std_logic_vector(3 DOWNTO 0);
wbm_ru_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ru_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : OUT std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : IN std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : IN std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- wishbone signals master interface (wb2pasmi interface)
wbm_stb : OUT std_logic; -- strobe
wbm_adr : OUT std_logic_vector(31 DOWNTO 0); -- address
wbm_ack : IN std_logic; -- acknowledge
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
wbm_cyc : OUT std_logic; -- chip select
-- wishbone signals slave interface (indirect interface)
wbs_stb : IN std_logic; -- strobe
wbs_ack : OUT std_logic; -- acknowledge
wbs_we : IN std_logic; -- write=1 read=0
wbs_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc : IN std_logic; -- chip select
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr : IN std_logic_vector(31 DOWNTO 0); -- address
-- ctrl signals from registers
ctrl_read_sid : OUT std_logic;
ctrl_sector_protect : OUT std_logic;
ctrl_write : OUT std_logic;
ctrl_read_status : OUT std_logic;
ctrl_sector_erase : OUT std_logic;
ctrl_bulk_erase : OUT std_logic;
ctrl_illegal_write : IN std_logic;
ctrl_illegal_erase : IN std_logic;
ctrl_busy : IN std_logic
);
END COMPONENT;
COMPONENT z126_01_ru_ctrl IS
GENERIC
(
FPGA_FAMILY : family_type := CYCLONE4; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT
(
clk : IN std_logic; -- system clock
rst : IN std_logic; -- unit ru_ctrl_reset
-- register interface
wbs_reg_cyc : IN std_logic;
wbs_reg_ack : OUT std_logic;
wbs_reg_we : IN std_logic;
wbs_reg_sel : IN std_logic_vector(3 DOWNTO 0);
wbs_reg_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_reg_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : IN std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : OUT std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : OUT std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- ALTREMOTE_UPDATE interface
ru_ctrl_busy : IN std_logic;
ru_ctrl_data_out : IN std_logic_vector(28 DOWNTO 0); -- data from altera remote update module
ru_ctrl_data_in : OUT std_logic_vector(23 DOWNTO 0); -- data to altera remote update module
ru_ctrl_param : OUT std_logic_vector(2 DOWNTO 0);
ru_ctrl_read_param : OUT std_logic;
ru_ctrl_read_source : OUT std_logic_vector(1 DOWNTO 0);
ru_ctrl_reconfig : OUT std_logic;
ru_ctrl_reset_timer : OUT std_logic;
ru_ctrl_reset : OUT std_logic;
ru_ctrl_write_param : OUT std_logic
);
END COMPONENT;
COMPONENT z126_01_ru_ctrl_cyc5 IS
GENERIC
(
FPGA_FAMILY : family_type := CYCLONE5; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT
(
clk : IN std_logic; -- system clock
rst : IN std_logic; -- unit ru_ctrl_reset
-- register interface
wbs_reg_cyc : IN std_logic;
wbs_reg_ack : OUT std_logic;
wbs_reg_we : IN std_logic;
wbs_reg_sel : IN std_logic_vector(3 DOWNTO 0);
wbs_reg_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_reg_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : IN std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : OUT std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : OUT std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- ALTREMOTE_UPDATE interface
ru_ctrl_busy : IN std_logic;
ru_ctrl_data_out : IN std_logic_vector(23 DOWNTO 0); -- data from altera remote update module
ru_ctrl_data_in : OUT std_logic_vector(23 DOWNTO 0); -- data to altera remote update module
ru_ctrl_param : OUT std_logic_vector(2 DOWNTO 0);
ru_ctrl_read_param : OUT std_logic;
ru_ctrl_reconfig : OUT std_logic;
ru_ctrl_reset_timer : OUT std_logic;
ru_ctrl_reset : OUT std_logic;
ru_ctrl_write_param : OUT std_logic
);
END COMPONENT;
--------------------------------------------------------
-- constants
--------------------------------------------------------
CONSTANT SUPPORTED_DEVICES : supported_flash_types := (M25P32, M25P64, M25P128);
CONSTANT SUPPORTED_FPGA_FAMILIES : supported_family_types := (CYCLONE3, CYCLONE4, CYCLONE5);
--------------------------------------------------------
-- signals
--------------------------------------------------------
-- reset signals
SIGNAL rstn_indi : std_logic;
SIGNAL rstn_dir : std_logic;
-- MASTER SIGNALS
SIGNAL wbmo_1 : wbo_type;
SIGNAL wbmi_1 : wbi_type;
SIGNAL wbmo_1_cyc : std_logic;
-- SLAVE SIGNALS
SIGNAL wbso_0 : wbi_type;
SIGNAL wbsi_0 : wbo_type;
SIGNAL wbsi_0_cyc : std_logic;
-- synchronised wishbone slave signals from direct interface
SIGNAL fc_stb_dir : std_logic;
SIGNAL fc_cyc_dir : std_logic;
SIGNAL fc_ack_dir : std_logic;
SIGNAL fc_err_dir : std_logic;
SIGNAL fc_we_dir : std_logic;
SIGNAL fc_adr_dir : std_logic_vector(31 DOWNTO 0);
SIGNAL fc_sel_dir : std_logic_vector( 3 DOWNTO 0);
SIGNAL fc_dat_i_dir : std_logic_vector(31 DOWNTO 0);
SIGNAL fc_dat_o_dir : std_logic_vector(31 DOWNTO 0);
-- synchronised wishbone slave signals from indirect interface
SIGNAL fc_stb_indi : std_logic;
SIGNAL fc_cyc_indi : std_logic;
SIGNAL fc_ack_indi : std_logic;
SIGNAL fc_adr_indi : std_logic_vector(31 DOWNTO 0);
SIGNAL fc_dat_o_indi : std_logic_vector(31 DOWNTO 0);
-- pasmi master signals from/to wishbone to pasmi
SIGNAL wb_pasmi_m_o : pasmi_out_type;
SIGNAL wb_pasmi_m_i : pasmi_in_type;
-- wb direct interface control master signals for wb2pasmi interface
SIGNAL wb_dir_ctrlm_o : ctrl_wb2pasmi_out_type;
-- wb indirect interface control master signals for wb2pasmi interface
SIGNAL wb_indi_ctrlm_o : ctrl_wb2pasmi_out_type;
SIGNAL wb_indi_ctrlm_i : ctrl_wb2pasmi_in_type;
-- control slave signals for wb2pasmi interface
SIGNAL wb_ctrls_o : ctrl_wb2pasmi_in_type;
SIGNAL wb_ctrls_i : ctrl_wb2pasmi_out_type;
-- remote update control unit signals
SIGNAL ru_ctrl_busy : std_logic;
SIGNAL ru_ctrl_data_out : std_logic_vector(28 DOWNTO 0);
SIGNAL ru_ctrl_data_in : std_logic_vector(23 DOWNTO 0);
SIGNAL ru_ctrl_param : std_logic_vector(2 DOWNTO 0);
SIGNAL ru_ctrl_read_param : std_logic;
SIGNAL ru_ctrl_read_source : std_logic_vector(1 DOWNTO 0);
SIGNAL ru_ctrl_reconfig : std_logic;
SIGNAL ru_ctrl_reset : std_logic;
SIGNAL ru_ctrl_reset_timer : std_logic;
SIGNAL ru_ctrl_write_param : std_logic;
-- wishbone master to remote update controler (read write boot address register)
SIGNAL wbm_ru_cyc : std_logic;
SIGNAL wbm_ru_ack : std_logic;
SIGNAL wbm_ru_we : std_logic;
SIGNAL wbm_ru_sel : std_logic_vector(3 DOWNTO 0);
SIGNAL wbm_ru_dat_o : std_logic_vector(31 DOWNTO 0);
SIGNAL wbm_ru_dat_i : std_logic_vector(31 DOWNTO 0);
-- register from remote update controller
SIGNAL reg_reconfig : std_logic; -- reconfiguration trigger from register interface
SIGNAL reg_reconfig_cond : std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
SIGNAL reg_board_status : std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
BEGIN
rstn_indi <= NOT rst_indi;
board_status <= reg_board_status;
-----------------------------------------------------------
-- Indirect interface clock bridge
-----------------------------------------------------------
z126_01_clk_trans_indirect_i0 : z126_01_clk_trans_wb2wb
GENERIC MAP (
NBR_OF_CYC => 1,
NBR_OF_TGA => 6
)
PORT MAP (
rstn => rstn_indi,
-- a MHz domain
clk_a => clk_indi,
stb_a => wbs_stb_indi, -- request signal from a MHz side
cyc_a(0) => wbs_cyc_indi,
ack_a => wbs_ack_indi, -- adopted acknoledge signal to b MHz
err_a => wbs_err_indi,
we_a => wbs_we_indi, -- '1' = write, '0' = read
tga_a => "000000",
cti_a => "000", -- transfer type
bte_a => "00", -- incremental burst
adr_a => wbs_adr_indi, -- adr from a MHz side
sel_a => wbs_sel_indi, -- byte enables from a MHz side
dat_i_a => wbs_dat_i_indi, -- data from a MHz side
dat_o_a => wbs_dat_o_indi, -- data from b MHz side to a MHz side
-- b MHz domain
clk_b => clk_40mhz,
stb_b => fc_stb_indi, -- request signal adopted to b MHz
cyc_b(0) => fc_cyc_indi,
ack_b => fc_ack_indi, -- acknoledge signal from internal bus
err_b => '0',
we_b => wbmo_1.we, -- '1' = write, '0' = read
tga_b => open,
cti_b => open, -- transfer type
bte_b => open, -- incremental burst
adr_b => fc_adr_indi, -- adr from b MHz side
sel_b => wbmo_1.sel, -- byte enables for b MHz side
dat_i_b => fc_dat_o_indi, -- data from b MHz side
dat_o_b => wbmo_1.dat -- data from a MHz side to b MHz side
);
wbmo_1.tga <= "000000"; --tga=0 --> used for address generation
wbmo_1.cti <= "000";
wbmo_1.bte <= "00";
-----------------------------------------------------------
-- Direct interface clock bridge
-----------------------------------------------------------
z126_01_use_direct_with_clk_bridge: IF USE_DIRECT_INTERFACE GENERATE
rstn_dir <= NOT rst_dir;
z126_01_clk_trans_direct_i0 : z126_01_clk_trans_wb2wb
PORT MAP (
rstn => rstn_dir,
-- a MHz domain
clk_a => clk_dir,
stb_a => wbs_stb_dir, -- request signal from a MHz side
cyc_a(0) => wbs_cyc_dir,
ack_a => wbs_ack_dir, -- adopted acknoledge signal to b MHz
err_a => wbs_err_dir,
we_a => wbs_we_dir, -- '1' = write, '0' = read
tga_a => "000000",
cti_a => "000", -- transfer type
bte_a => "00", -- incremental burst
adr_a => wbs_adr_dir, -- adr from a MHz side
sel_a => wbs_sel_dir, -- byte enables from a MHz side
dat_i_a => wbs_dat_i_dir, -- data from a MHz side
dat_o_a => wbs_dat_o_dir, -- data from b MHz side to a MHz side
-- b MHz domain
clk_b => clk_40mhz,
stb_b => fc_stb_dir, -- request signal adopted to b MHz
cyc_b(0) => fc_cyc_dir,
ack_b => fc_ack_dir, -- acknoledge signal from internal bus
err_b => fc_err_dir,
we_b => fc_we_dir, -- '1' = write, '0' = read
tga_b => open,
cti_b => open, -- transfer type
bte_b => open, -- incremental burst
adr_b => fc_adr_dir, -- adr from b MHz side
sel_b => fc_sel_dir, -- byte enables for b MHz side
dat_i_b => fc_dat_o_dir, -- data from b MHz side
dat_o_b => fc_dat_i_dir -- data from a MHz side to b MHz side
);
END GENERATE z126_01_use_direct_with_clk_bridge;
-- set default values for direct interface when it is not used
z126_01_not_use_direct: IF NOT USE_DIRECT_INTERFACE GENERATE
wbs_ack_dir <= '0';
wbs_err_dir <= '0';
wbs_dat_o_dir <= (OTHERS => '0');
fc_stb_dir <= '0';
fc_cyc_dir <= '0';
fc_we_dir <= '0';
fc_adr_dir <= (OTHERS => '0');
fc_sel_dir <= (OTHERS => '0');
fc_dat_i_dir <= (OTHERS => '0');
END GENERATE z126_01_not_use_direct;
-- always read operation for the direct interface
wb_dir_ctrlm_o.read_sid <= '0';
wb_dir_ctrlm_o.sector_protect <= '0';
wb_dir_ctrlm_o.write <= '0';
wb_dir_ctrlm_o.read_status <= '0';
wb_dir_ctrlm_o.sector_erase <= '0';
wb_dir_ctrlm_o.bulk_erase <= '0';
-----------------------------------------------------------
-- Arbiter between wishbone direct and indirect interface
-----------------------------------------------------------
-- instantiation of 16z100 (renamed to wb_bus_16z045_01)
z126_01_wb_if_arbiter_i0: z126_01_wb_if_arbiter
GENERIC MAP (
sets => "0000",
timeout => 5000
)
PORT MAP (
clk => clk_40mhz, -- wishbone clock
rst => rst_clk_40mhz,
wbmo_0.stb => fc_stb_dir, -- Master Interface
wbmo_0.sel => fc_sel_dir, -- for direct addressing interface
wbmo_0.adr => fc_adr_dir,
wbmo_0.we => fc_we_dir,
wbmo_0.dat => fc_dat_i_dir,
wbmo_0.tga => "000001",
wbmo_0.cti => "000",
wbmo_0.bte => "00",
wbmi_0.ack => fc_ack_dir,
wbmi_0.err => fc_err_dir,
wbmi_0.dat => fc_dat_o_dir,
wbmo_0_cyc => fc_cyc_dir,
ctrlmo_0 => wb_dir_ctrlm_o,
ctrlmi_0 => OPEN,
wbmo_1 => wbmo_1, -- Master Interface
wbmi_1 => wbmi_1, -- for indirect addressing Interface
wbmo_1_cyc => wbmo_1_cyc,
ctrlmo_1 => wb_indi_ctrlm_o,
ctrlmi_1 => wb_indi_ctrlm_i,
wbso_0 => wbso_0, -- Slave Interface
wbsi_0 => wbsi_0, -- for wb2pasmi Interface
wbsi_0_cyc => wbsi_0_cyc,
ctrlso_0 => wb_ctrls_o,
ctrlsi_0 => wb_ctrls_i
);
----------------------------------------------------
-- Indirect interface registers
----------------------------------------------------
-- instantiation of FSM which handles indirect access
z126_01_indi_if_ctrl_regs_i0 : z126_01_indi_if_ctrl_regs
PORT MAP (
clk => clk_40mhz, -- Wishbone clock (66 MHz)
rst => rst_clk_40mhz, -- Reset
-- wishbone signals master interface (ru_ctrol interace)
wbm_ru_cyc => wbm_ru_cyc,
wbm_ru_ack => wbm_ru_ack,
wbm_ru_we => wbm_ru_we,
wbm_ru_sel => wbm_ru_sel,
wbm_ru_dat_o => wbm_ru_dat_o,
wbm_ru_dat_i => wbm_ru_dat_i,
reg_reconfig => reg_reconfig, -- reconfiguration trigger from register interface
reg_reconfig_cond => reg_reconfig_cond, -- reconfiguration trigger condition of last reconfiguration
reg_board_status => reg_board_status, -- gives information whether the loading process was successful or not
-- wishbone signals master interface
wbm_stb => wbmo_1.stb, -- strobe
wbm_adr => wbmo_1.adr, -- addrees
wbm_ack => wbmi_1.ack, -- acknowledge
wbm_dat_i => wbmi_1.dat, -- data in
wbm_cyc => wbmo_1_cyc,
-- wishbone signals slave interface
wbs_stb => fc_stb_indi, -- strobe
wbs_ack => fc_ack_indi, -- acknowledge
wbs_we => wbmo_1.we, -- write=1 read=0
wbs_sel => wbmo_1.sel, -- byte enables
wbs_cyc => fc_cyc_indi, -- chip select
wbs_dat_o => fc_dat_o_indi, -- data out
wbs_dat_i => wbmo_1.dat, -- data in
wbs_adr => fc_adr_indi, -- address
-- control signals for wb2pasmi
ctrl_read_sid => wb_indi_ctrlm_o.read_sid,
ctrl_sector_protect => wb_indi_ctrlm_o.sector_protect,
ctrl_write => wb_indi_ctrlm_o.write,
ctrl_read_status => wb_indi_ctrlm_o.read_status,
ctrl_sector_erase => wb_indi_ctrlm_o.sector_erase,
ctrl_bulk_erase => wb_indi_ctrlm_o.bulk_erase,
ctrl_illegal_write => wb_indi_ctrlm_i.illegal_write,
ctrl_illegal_erase => wb_indi_ctrlm_i.illegal_erase,
ctrl_busy => wb_indi_ctrlm_i.busy
);
----------------------------------------------------
-- Wishbone to pasmi
----------------------------------------------------
z126_01_wb2pasmi_i0: ENTITY work.z126_01_wb2pasmi
GENERIC MAP (
FLASH_TYPE => FLASH_TYPE
)
PORT MAP (
clk => clk_40mhz, -- flash clk 40 Mhz
rst => rst_clk_40mhz, -- global async high active reset
-- pasmi interface
pasmi_addr => wb_pasmi_m_o.addr,
pasmi_bulk_erase => wb_pasmi_m_o.bulk_erase,
pasmi_busy => wb_pasmi_m_i.busy,
pasmi_data_valid => wb_pasmi_m_i.data_valid,
pasmi_datain => wb_pasmi_m_i.data,
pasmi_dataout => wb_pasmi_m_o.data,
pasmi_epcs_id => wb_pasmi_m_i.epcs_id,
pasmi_rdid => wb_pasmi_m_i.rdid,
pasmi_fast_read => wb_pasmi_m_o.fast_read,
pasmi_illegal_erase => wb_pasmi_m_i.illegal_erase,
pasmi_illegal_write => wb_pasmi_m_i.illegal_write,
pasmi_rden => wb_pasmi_m_o.rden,
pasmi_read_sid => wb_pasmi_m_o.read_sid,
pasmi_read_rdid => wb_pasmi_m_o.read_rdid,
pasmi_read_status => wb_pasmi_m_o.read_status,
pasmi_sector_erase => wb_pasmi_m_o.sector_erase,
pasmi_sector_protect => wb_pasmi_m_o.sector_protect,
pasmi_shift_bytes => wb_pasmi_m_o.shift_bytes,
pasmi_status_out => wb_pasmi_m_i.status,
pasmi_wren => wb_pasmi_m_o.wren,
pasmi_write => wb_pasmi_m_o.write,
-- wishbone signals slave interface 0 (direct addressing)
wbs_stb => wbsi_0.stb, -- request
wbs_ack => wbso_0.ack, -- acknoledge
wbs_we => wbsi_0.we, -- write=1 read=0
wbs_sel => wbsi_0.sel, -- byte enables
wbs_cyc => wbsi_0_cyc, -- chip select
wbs_dat_o => wbso_0.dat, -- data out
wbs_dat_i => wbsi_0.dat, -- data in
wbs_adr => wbsi_0.adr, -- address
wbs_tga => wbsi_0.tga, -- address extension dir=0/indir=1, used for address generation
wbs_err => wbso_0.err, -- error
-- control interface
ctrl_read_sid => wb_ctrls_i.read_sid,
ctrl_sector_protect => wb_ctrls_i.sector_protect,
ctrl_write => wb_ctrls_i.write,
ctrl_read_status => wb_ctrls_i.read_status,
ctrl_sector_erase => wb_ctrls_i.sector_erase,
ctrl_bulk_erase => wb_ctrls_i.bulk_erase,
ctrl_busy => wb_ctrls_o.busy
);
-- unsued pasmi master signals
wb_pasmi_m_o.read <= '0';
----------------------------------------------------
-- ALTASMI_PARALLEL
----------------------------------------------------
-- pasmi instance for 32MBit serial flash
z126_01_pasmi_m25p32_gen: IF (FLASH_TYPE = M25P32) GENERATE
z126_01_pasmi_m25p32_i0 : z126_01_pasmi_m25p32
PORT MAP (
clkin => clk_40mhz,
reset => rst_clk_40mhz,
addr => wb_pasmi_m_o.addr,
bulk_erase => wb_pasmi_m_o.bulk_erase,
busy => wb_pasmi_m_i.busy,
data_valid => wb_pasmi_m_i.data_valid,
datain => wb_pasmi_m_o.data,
dataout => wb_pasmi_m_i.data,
rdid_out => wb_pasmi_m_i.rdid,
fast_read => wb_pasmi_m_o.fast_read,
illegal_erase => wb_pasmi_m_i.illegal_erase,
illegal_write => wb_pasmi_m_i.illegal_write,
rden => wb_pasmi_m_o.rden,
read_rdid => wb_pasmi_m_o.read_rdid,
read_status => wb_pasmi_m_o.read_status,
sector_erase => wb_pasmi_m_o.sector_erase,
sector_protect => wb_pasmi_m_o.sector_protect,
shift_bytes => wb_pasmi_m_o.shift_bytes,
status_out => wb_pasmi_m_i.status,
wren => wb_pasmi_m_o.wren,
write => wb_pasmi_m_o.write
);
END GENERATE;
-- pasmi instance for 64MBit serial flash
z126_01_pasmi_m25p64_gen : IF FLASH_TYPE = M25P64 GENERATE
z126_01_the_pasmi_m25p64_i0 : z126_01_pasmi_m25p64
PORT MAP (
clkin => clk_40mhz,
reset => rst_clk_40mhz,
addr => wb_pasmi_m_o.addr,
bulk_erase => wb_pasmi_m_o.bulk_erase,
busy => wb_pasmi_m_i.busy,
data_valid => wb_pasmi_m_i.data_valid,
datain => wb_pasmi_m_o.data,
dataout => wb_pasmi_m_i.data,
rdid_out => wb_pasmi_m_i.rdid,
fast_read => wb_pasmi_m_o.fast_read,
illegal_erase => wb_pasmi_m_i.illegal_erase,
illegal_write => wb_pasmi_m_i.illegal_write,
rden => wb_pasmi_m_o.rden,
read_rdid => wb_pasmi_m_o.read_rdid,
read_status => wb_pasmi_m_o.read_status,
sector_erase => wb_pasmi_m_o.sector_erase,
sector_protect => wb_pasmi_m_o.sector_protect,
shift_bytes => wb_pasmi_m_o.shift_bytes,
status_out => wb_pasmi_m_i.status,
wren => wb_pasmi_m_o.wren,
write => wb_pasmi_m_o.write
);
END GENERATE;
-- pasmi instance for 128MBit serial flash
z126_01_pasmi_m25p128_gen : IF FLASH_TYPE = M25P128 GENERATE
z126_01_the_pasmi_m25p128_i0 : z126_01_pasmi_m25p128
PORT MAP (
clkin => clk_40mhz,
reset => rst_clk_40mhz,
addr => wb_pasmi_m_o.addr,
bulk_erase => wb_pasmi_m_o.bulk_erase,
busy => wb_pasmi_m_i.busy,
data_valid => wb_pasmi_m_i.data_valid,
datain => wb_pasmi_m_o.data,
dataout => wb_pasmi_m_i.data,
rdid_out => wb_pasmi_m_i.rdid,
fast_read => wb_pasmi_m_o.fast_read,
illegal_erase => wb_pasmi_m_i.illegal_erase,
illegal_write => wb_pasmi_m_i.illegal_write,
rden => wb_pasmi_m_o.rden,
read_rdid => wb_pasmi_m_o.read_rdid,
read_status => wb_pasmi_m_o.read_status,
sector_erase => wb_pasmi_m_o.sector_erase,
sector_protect => wb_pasmi_m_o.sector_protect,
shift_bytes => wb_pasmi_m_o.shift_bytes,
status_out => wb_pasmi_m_i.status,
wren => wb_pasmi_m_o.wren,
write => wb_pasmi_m_o.write
);
END GENERATE;
wb_pasmi_m_i.epcs_id <= (OTHERS=>'0');
wb_ctrls_o.illegal_erase <= wb_pasmi_m_i.illegal_erase;
wb_ctrls_o.illegal_write <= wb_pasmi_m_i.illegal_write;
----------------------------------------------------
-- ALTREMOTE_UPDATE
----------------------------------------------------
z126_01_ru_gen: IF USE_REMOTE_UPDATE = TRUE GENERATE
-- remote update controller altera module for cyclone 3 device
z126_01_ru_cycloneiii_gen: IF FPGA_FAMILY = CYCLONE3 GENERATE
z126_01_ru_cycloneiii_i0 : z126_01_ru_cycloneiii
PORT MAP (
clock => clk_40mhz,
reset => ru_ctrl_reset,
param => ru_ctrl_param,
read_param => ru_ctrl_read_param,
read_source => ru_ctrl_read_source,
reconfig => ru_ctrl_reconfig,
reset_timer => ru_ctrl_reset_timer,
write_param => ru_ctrl_write_param,
data_in => ru_ctrl_data_in,
data_out => ru_ctrl_data_out,
busy => ru_ctrl_busy
);
END GENERATE;
-- remote update controller altera module for cyclone 4 device
z126_01_ru_cycloneiv_gen: IF FPGA_FAMILY = CYCLONE4 GENERATE
z126_01_ru_cycloneiv_i0 : z126_01_ru_cycloneiv
PORT MAP (
clock => clk_40mhz,
reset => ru_ctrl_reset,
param => ru_ctrl_param,
read_param => ru_ctrl_read_param,
read_source => ru_ctrl_read_source,
reconfig => ru_ctrl_reconfig,
reset_timer => ru_ctrl_reset_timer,
write_param => ru_ctrl_write_param,
data_in => ru_ctrl_data_in,
data_out => ru_ctrl_data_out,
busy => ru_ctrl_busy
);
END GENERATE;
-- remote update controller altera module for cyclone 5 device
ASSERT NOT (FPGA_FAMILY = CYCLONE5) REPORT "Z126: for Cyclone V support, please first generate Altera Remote Update IP-core for your Flash" SEVERITY failure;
--z126_01_ru_cyclonev_gen: IF FPGA_FAMILY = CYCLONE5 GENERATE
-- z126_01_ru_cyclonev_m25p128_gen: IF FLASH_TYPE = M25P128 GENERATE
--
-- z126_01_ru_cyclonev_i0 : z126_01_ru_cyclonev_m25p128
-- PORT MAP (
-- clock => clk_40mhz,
-- reset => ru_ctrl_reset,
--
-- param => ru_ctrl_param,
-- read_param => ru_ctrl_read_param,
-- reconfig => ru_ctrl_reconfig,
-- reset_timer => ru_ctrl_reset_timer,
-- write_param => ru_ctrl_write_param,
-- data_in => ru_ctrl_data_in,
-- data_out => ru_ctrl_data_out(23 DOWNTO 0),
-- busy => ru_ctrl_busy
-- );
-- END GENERATE;
--
-- z126_01_ru_cyclonev_m25p64_gen: IF FLASH_TYPE = M25P64 GENERATE
-- z126_01_ru_cyclonev_i0 : z126_01_ru_cyclonev_m25p64
-- PORT MAP (
-- clock => clk_40mhz,
-- reset => ru_ctrl_reset,
--
-- param => ru_ctrl_param,
-- read_param => ru_ctrl_read_param,
-- reconfig => ru_ctrl_reconfig,
-- reset_timer => ru_ctrl_reset_timer,
-- write_param => ru_ctrl_write_param,
-- data_in => ru_ctrl_data_in,
-- data_out => ru_ctrl_data_out(23 DOWNTO 0),
-- busy => ru_ctrl_busy
-- );
-- END GENERATE;
--
-- z126_01_ru_cyclonev_m25p32_gen: IF FLASH_TYPE = M25P32 GENERATE
-- z126_01_ru_cyclonev_i0 : z126_01_ru_cyclonev_m25p32
-- PORT MAP (
-- clock => clk_40mhz,
-- reset => ru_ctrl_reset,
--
-- param => ru_ctrl_param,
-- read_param => ru_ctrl_read_param,
-- reconfig => ru_ctrl_reconfig,
-- reset_timer => ru_ctrl_reset_timer,
-- write_param => ru_ctrl_write_param,
-- data_in => ru_ctrl_data_in,
-- data_out => ru_ctrl_data_out(23 DOWNTO 0),
-- busy => ru_ctrl_busy
-- );
-- END GENERATE;
--END GENERATE;
-- remote update controller
z126_01_ru_gen: IF FPGA_FAMILY /= CYCLONE5 GENERATE
z126_01_ru_ctrl_i0 : z126_01_ru_ctrl
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY, -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
LOAD_FPGA_IMAGE => LOAD_FPGA_IMAGE, -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR => LOAD_FPGA_IMAGE_ADR -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
)
PORT MAP (
clk => clk_40mhz, -- system clock
rst => rst_clk_40mhz, -- unit reset
-- register interface
wbs_reg_cyc => wbm_ru_cyc,
wbs_reg_ack => wbm_ru_ack,
wbs_reg_we => wbm_ru_we,
wbs_reg_sel => wbm_ru_sel,
wbs_reg_dat_o => wbm_ru_dat_i,
wbs_reg_dat_i => wbm_ru_dat_o,
reg_reconfig => reg_reconfig, -- reconfiguration trigger from register interface
reg_reconfig_cond => reg_reconfig_cond, -- reconfiguration trigger condition of last reconfiguration
reg_board_status => reg_board_status, -- gives information whether the loading process was successful or not
-- ALTREMOTE_UPDATE interface
ru_ctrl_busy => ru_ctrl_busy,
ru_ctrl_data_out => ru_ctrl_data_out, -- data from altera remote update module
ru_ctrl_data_in => ru_ctrl_data_in, -- data to altera remote update module
ru_ctrl_param => ru_ctrl_param,
ru_ctrl_read_param => ru_ctrl_read_param,
ru_ctrl_read_source => ru_ctrl_read_source,
ru_ctrl_reconfig => ru_ctrl_reconfig,
ru_ctrl_reset_timer => ru_ctrl_reset_timer,
ru_ctrl_reset => ru_ctrl_reset,
ru_ctrl_write_param => ru_ctrl_write_param
);
END GENERATE z126_01_ru_gen;
z126_01_ru_ctrl_cyclonev_gen: IF FPGA_FAMILY = CYCLONE5 GENERATE
z126_01_ru_ctrl_cyc5_i0 : z126_01_ru_ctrl_cyc5
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY, -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
LOAD_FPGA_IMAGE => LOAD_FPGA_IMAGE, -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR => LOAD_FPGA_IMAGE_ADR -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
)
PORT MAP (
clk => clk_40mhz, -- system clock
rst => rst_clk_40mhz, -- unit reset
-- register interface
wbs_reg_cyc => wbm_ru_cyc,
wbs_reg_ack => wbm_ru_ack,
wbs_reg_we => wbm_ru_we,
wbs_reg_sel => wbm_ru_sel,
wbs_reg_dat_o => wbm_ru_dat_i,
wbs_reg_dat_i => wbm_ru_dat_o,
reg_reconfig => reg_reconfig, -- reconfiguration trigger from register interface
reg_reconfig_cond => reg_reconfig_cond, -- reconfiguration trigger condition of last reconfiguration
reg_board_status => reg_board_status, -- gives information whether the loading process was successful or not
-- ALTREMOTE_UPDATE interface
ru_ctrl_busy => ru_ctrl_busy,
ru_ctrl_data_out => ru_ctrl_data_out(23 DOWNTO 0), -- data from altera remote update module
ru_ctrl_data_in => ru_ctrl_data_in, -- data to altera remote update module
ru_ctrl_param => ru_ctrl_param,
ru_ctrl_read_param => ru_ctrl_read_param,
ru_ctrl_reconfig => ru_ctrl_reconfig,
ru_ctrl_reset_timer => ru_ctrl_reset_timer,
ru_ctrl_reset => ru_ctrl_reset,
ru_ctrl_write_param => ru_ctrl_write_param
);
ru_ctrl_data_out(28 DOWNTO 24) <= (OTHERS=>'0');
END GENERATE z126_01_ru_ctrl_cyclonev_gen;
END GENERATE z126_01_ru_gen;
z126_01_without_ru_gen: IF USE_REMOTE_UPDATE = FALSE GENERATE
-- default values for unused signals when remote update controller is not included
wbm_ru_ack <= '1';
wbm_ru_dat_i <= (OTHERS=>'0');
reg_reconfig_cond <= (OTHERS=>'0');
reg_board_status <= (OTHERS=>'0');
END GENERATE;
-- if a not supported device is selected, a FAILURE will be generated
ASSERT NOT no_valid_device(supported_devices => SUPPORTED_DEVICES, device => FLASH_TYPE) REPORT "Z126: No valid Flash!" SEVERITY failure;
-- if a not supported FPGA family is selected, a FAILURE will be generated
ASSERT NOT no_valid_device(supported_devices => SUPPORTED_FPGA_FAMILIES, device => FPGA_FAMILY) REPORT "Z126: No valid FPGA family!" SEVERITY failure;
--coverage on
END z126_01_top_arch;
z126_01_wb2pasmi.vhd 0000664 0000000 0000000 00000060557 14574545710 0034325 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Wishbone to PASMI
-- Project : 16z126-01
---------------------------------------------------------------
-- File : z126_01_wb2pasmi.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
-- wb2pasmi is a Wishbone to Parallel Active Serial Flash IF
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_top
-- z126_01_wb2pasmi_i0
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: z126_01_wb2pasmi.vhd,v $
-- Revision 1.4 2014/11/24 16:44:22 AGeissler
-- R1: Clearness
-- M1.1: Changed spacing
-- M1.2: Changed comment
--
-- Revision 1.3 2014/04/02 09:28:04 AGeissler
-- R: Wrong data when reading with byte or word access
-- M: Changed conditions for read fsm b2lw_state
--
-- Revision 1.2 2014/03/05 11:19:43 AGeissler
-- R: Missing reset for signal
-- M: Added reset
--
-- Revision 1.1 2014/03/03 17:49:55 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.z126_01_pkg.ALL;
ENTITY z126_01_wb2pasmi IS
GENERIC (
FLASH_TYPE : flash_type := NONE
);
PORT (
clk : IN std_logic; -- flash clk 40 MHz
rst : IN std_logic; -- global async high active reset
-- PASMI interface
pasmi_addr : OUT std_logic_vector(23 DOWNTO 0);
pasmi_bulk_erase : OUT std_logic;
pasmi_busy : IN std_logic;
pasmi_data_valid : IN std_logic;
pasmi_datain : IN std_logic_vector(7 DOWNTO 0); -- data from altera pasmi interface
pasmi_dataout : OUT std_logic_vector(7 DOWNTO 0); -- data to altera pasmi
pasmi_epcs_id : IN std_logic_vector(7 DOWNTO 0);
pasmi_rdid : IN std_logic_vector(7 DOWNTO 0);
pasmi_fast_read : OUT std_logic;
pasmi_illegal_erase : IN std_logic;
pasmi_illegal_write : IN std_logic;
pasmi_rden : OUT std_logic;
pasmi_read_sid : OUT std_logic;
pasmi_read_rdid : OUT std_logic;
pasmi_read_status : OUT std_logic;
pasmi_sector_erase : OUT std_logic;
pasmi_sector_protect : OUT std_logic;
pasmi_shift_bytes : OUT std_logic;
pasmi_status_out : IN std_logic_vector(7 DOWNTO 0);
pasmi_wren : OUT std_logic;
pasmi_write : OUT std_logic;
-- wishbone signals slave interface 0 (direct addressing)
wbs_stb : IN std_logic; -- request
wbs_ack : OUT std_logic; -- acknoledge
wbs_we : IN std_logic; -- write=1 read=0
wbs_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc : IN std_logic; -- chip select
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_tga : IN std_logic_vector(5 DOWNTO 0); -- address extension for address generation 0=dir/1=indir
wbs_err : OUT std_logic; -- error
-- control interface
ctrl_read_sid : IN std_logic;
ctrl_sector_protect : IN std_logic;
ctrl_write : IN std_logic;
ctrl_read_status : IN std_logic;
ctrl_sector_erase : IN std_logic;
ctrl_bulk_erase : IN std_logic;
ctrl_busy : OUT std_logic
);
END z126_01_wb2pasmi;
ARCHITECTURE z126_01_wb2pasmi_arch OF z126_01_wb2pasmi IS
TYPE sel_states IS (IDLE,SEL_0,SEL_1,SEL_2,SEL_3, END_ACCESS);
SIGNAL b2lw_state : sel_states;
SIGNAL lw2b_state : sel_states;
SIGNAL pasmi_busy_q : std_logic;
SIGNAL pasmi_busy_qq : std_logic;
SIGNAL pasmi_data_write_fin : std_logic;
SIGNAL pasmi_data_read_fin : std_logic;
-- internal pasmi signals
SIGNAL pasmi_rden_fsm_int : std_logic;
SIGNAL pasmi_wren_fsm_int : std_logic;
SIGNAL pasmi_shift_bytes_fsm_int : std_logic;
SIGNAL pasmi_fast_read_fsm_int : std_logic;
SIGNAL pasmi_rden_int : std_logic;
SIGNAL pasmi_wren_int : std_logic;
SIGNAL pasmi_shift_bytes_int : std_logic;
SIGNAL pasmi_bulk_erase_int : std_logic;
SIGNAL pasmi_fast_read_int : std_logic;
SIGNAL pasmi_read_rdid_int : std_logic;
SIGNAL pasmi_read_status_int : std_logic;
SIGNAL pasmi_sector_erase_int : std_logic;
SIGNAL pasmi_write_int : std_logic;
SIGNAL pasmi_sector_protect_int : std_logic;
SIGNAL id_oe : std_logic; -- select wishbone data out to serial flash id from altera component
SIGNAL status_oe : std_logic; -- select wishbone data out to status from altera component
SIGNAL wbs_ack_int : std_logic;
SIGNAL dat_32_reg : std_logic_vector(31 DOWNTO 0); -- internal register for shifting read data from pasmi interface
SIGNAL dat_8_reg : std_logic_vector(7 DOWNTO 0); -- internal register for writing data to pasmi interface
SIGNAL pasmi_datain_swapped_int : std_logic_vector(7 DOWNTO 0); -- swapped pasmi data in (MSB <-> LSB)
SIGNAL pasmi_dataout_swapped_int : std_logic_vector(7 DOWNTO 0); -- swapped pasmi data out (MSB <-> LSB)
BEGIN
ctrl_busy <= pasmi_busy_q;
-- wishbone signals
wbs_ack <= wbs_ack_int;
wbs_err <= '0';
-- if flash type M25P32 or M25P64 is used the driver expect the sid instead of the rdid
-- this means to be backwards compatible the rdid is subtracted by 1
-- M25P32 : sid = 15; rdid = 16
-- M25P64 : sid = 16; rdid = 17
-- M25P128: rdid = 18 (there is no sid for the M25P128)
z126_01_wb2pasmi_m25p32_gen: IF FLASH_TYPE = M25P32 GENERATE
wbs_dat_o <= x"0000_00" & std_logic_vector((unsigned (pasmi_rdid)) - 1) WHEN id_oe = '1' ELSE
x"0000_00" & pasmi_status_out WHEN status_oe = '1' ELSE
dat_32_reg;
END GENERATE;
z126_01_wb2pasmi_m25p64_gen: IF FLASH_TYPE = M25P64 GENERATE
wbs_dat_o <= x"0000_00" & std_logic_vector((unsigned (pasmi_rdid)) - 1) WHEN id_oe = '1' ELSE
x"0000_00" & pasmi_status_out WHEN status_oe = '1' ELSE
dat_32_reg;
END GENERATE;
z126_01_wb2pasmi_m25p128_gen: IF FLASH_TYPE = M25P128 GENERATE
wbs_dat_o <= x"0000_00" & pasmi_rdid WHEN id_oe = '1' ELSE
x"0000_00" & pasmi_status_out WHEN status_oe = '1' ELSE
dat_32_reg;
END GENERATE;
-- pasmi signals
pasmi_read_sid <= '0'; -- read sid is not used any longer (rdid is used instead)
pasmi_read_rdid <= pasmi_read_rdid_int;
pasmi_fast_read <= pasmi_fast_read_fsm_int;
pasmi_write <= pasmi_write_int;
pasmi_read_status <= pasmi_read_status_int;
pasmi_sector_erase <= pasmi_sector_erase_int;
pasmi_bulk_erase <= pasmi_bulk_erase_int;
pasmi_rden <= pasmi_rden_fsm_int;
pasmi_dataout <= pasmi_dataout_swapped_int;
pasmi_wren <= '1' WHEN pasmi_wren_fsm_int = '1' OR
pasmi_write_int = '1' OR
pasmi_sector_erase_int = '1' OR
pasmi_bulk_erase_int = '1' ELSE
'0';
pasmi_shift_bytes <= pasmi_shift_bytes_fsm_int;
pasmi_sector_protect <= pasmi_sector_protect_int WHEN pasmi_wren_fsm_int = '1' ELSE '0';
pasmi_addr <= wbs_adr(23 DOWNTO 0) WHEN wbs_we = '1' ELSE --write access depends on adr_register
wbs_adr(23 DOWNTO 2) & "00" WHEN wbs_sel(0) = '1' ELSE --read access depends on byte-sel
wbs_adr(23 DOWNTO 2) & "01" WHEN wbs_sel(1) = '1' ELSE
wbs_adr(23 DOWNTO 2) & "10" WHEN wbs_sel(2) = '1' ELSE
wbs_adr(23 DOWNTO 2) & "11" ;
-- bit-swapping of data lines
bit_swapping: FOR i IN 0 TO 7 GENERATE
pasmi_dataout_swapped_int(i) <= dat_8_reg(7-i) WHEN pasmi_sector_protect_int = '0' ELSE
dat_8_reg(i);
pasmi_datain_swapped_int(i) <= pasmi_datain(7-i);
END GENERATE;
------------------------------
-- Byte to long word (READ) --
------------------------------
z126_01_pasmi_read_access_fsm : PROCESS (b2lw_state, rst, clk)
BEGIN
IF b2lw_state = END_ACCESS THEN
pasmi_data_read_fin <= '1';
ELSE
pasmi_data_read_fin <= '0';
END IF;
IF rst = '1' THEN
b2lw_state <= IDLE;
pasmi_rden_fsm_int <= '0';
pasmi_fast_read_fsm_int <= '0';
dat_32_reg <= (OTHERS=>'0');
ELSIF falling_edge(clk) THEN
CASE b2lw_state IS
WHEN IDLE =>
dat_32_reg <= dat_32_reg;
IF pasmi_fast_read_int = '1' THEN
pasmi_rden_fsm_int <= '1';
pasmi_fast_read_fsm_int <= '1';
IF (wbs_sel(0) = '1') THEN
b2lw_state <= SEL_0;
ELSIF(wbs_sel(1) = '1') THEN
b2lw_state <= SEL_1;
ELSIF(wbs_sel(2) = '1') THEN
b2lw_state <= SEL_2;
ELSE
b2lw_state <= SEL_3;
END IF;
ELSE
pasmi_rden_fsm_int <= '0';
b2lw_state <= IDLE;
END IF;
WHEN SEL_0 =>
dat_32_reg(7 DOWNTO 0) <= pasmi_datain_swapped_int;
pasmi_fast_read_fsm_int <= '0';
IF wbs_sel(1) = '0' AND pasmi_data_valid = '1' THEN
b2lw_state <= END_ACCESS;
pasmi_rden_fsm_int <= '0';
ELSIF pasmi_data_valid = '1' THEN
b2lw_state <= SEL_1;
pasmi_rden_fsm_int <= '1';
ELSE
pasmi_rden_fsm_int <= '1';
END IF;
WHEN SEL_1 =>
dat_32_reg(15 DOWNTO 8) <= pasmi_datain_swapped_int;
pasmi_fast_read_fsm_int <= '0';
IF wbs_sel(2) = '0' AND pasmi_data_valid = '1' THEN
b2lw_state <= END_ACCESS;
pasmi_rden_fsm_int <= '0';
ELSIF pasmi_data_valid = '1' THEN
b2lw_state <= SEL_2;
pasmi_rden_fsm_int <= '1';
ELSE
pasmi_rden_fsm_int <= '1';
END IF;
WHEN SEL_2 =>
dat_32_reg(23 DOWNTO 16) <= pasmi_datain_swapped_int;
pasmi_fast_read_fsm_int <= '0';
IF wbs_sel(3) = '0' AND pasmi_data_valid = '1' THEN
b2lw_state <= END_ACCESS;
pasmi_rden_fsm_int <= '0';
ELSIF pasmi_data_valid = '1' THEN
b2lw_state <= SEL_3;
pasmi_rden_fsm_int <= '1';
ELSE
pasmi_rden_fsm_int <= '1';
END IF;
WHEN SEL_3 =>
dat_32_reg(31 DOWNTO 24) <= pasmi_datain_swapped_int;
pasmi_fast_read_fsm_int <= '0';
pasmi_rden_fsm_int <= '0';
IF pasmi_data_valid = '1' THEN
b2lw_state <= END_ACCESS;
END IF;
WHEN END_ACCESS =>
dat_32_reg <= dat_32_reg;
pasmi_rden_fsm_int <= '0';
pasmi_fast_read_fsm_int <= '0';
b2lw_state <= IDLE;
-- coverage off
WHEN OTHERS =>
b2lw_state <= IDLE;
dat_32_reg <= dat_32_reg;
pasmi_rden_fsm_int <= '0';
pasmi_fast_read_fsm_int <= '0';
ASSERT FALSE REPORT "Undeocded State" SEVERITY WARNING;
-- coverage on
END CASE;
END IF;
END PROCESS z126_01_pasmi_read_access_fsm;
-------------------------------
-- Long word to Byte (WRITE) --
-------------------------------
z126_01_pasmi_write_access_fsm : PROCESS (lw2b_state, clk, rst)
BEGIN
IF lw2b_state = END_ACCESS THEN
pasmi_data_write_fin <= '1';
ELSE
pasmi_data_write_fin <= '0';
END IF;
IF rst = '1' THEN
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
lw2b_state <= IDLE;
dat_8_reg <= (OTHERS=>'0');
ELSIF falling_edge(clk) THEN
CASE lw2b_state IS
WHEN IDLE =>
IF pasmi_wren_int = '1' AND pasmi_shift_bytes_int = '1' THEN
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= pasmi_shift_bytes_int;
IF(wbs_sel(0) = '1') THEN
lw2b_state <= SEL_0;
dat_8_reg <= wbs_dat_i(7 DOWNTO 0);
ELSIF(wbs_sel(1) = '1') THEN
lw2b_state <= SEL_1;
dat_8_reg <= wbs_dat_i(15 DOWNTO 8);
ELSIF(wbs_sel(2) = '1') THEN
lw2b_state <= SEL_2;
dat_8_reg <= wbs_dat_i(23 DOWNTO 16);
ELSE
lw2b_state <= SEL_3;
dat_8_reg <= wbs_dat_i(31 DOWNTO 24);
END IF;
ELSIF pasmi_wren_int = '1' AND pasmi_sector_protect_int = '1' THEN
lw2b_state <= IDLE;
dat_8_reg <= wbs_dat_i(7 DOWNTO 0);
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= '0';
ELSE
lw2b_state <= IDLE;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
END IF;
WHEN SEL_0 =>
IF(wbs_sel(1) = '1') THEN
lw2b_state <= SEL_1;
dat_8_reg <= wbs_dat_i(15 DOWNTO 8);
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= pasmi_shift_bytes_int;
ELSE
lw2b_state <= END_ACCESS;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
END IF;
WHEN SEL_1 =>
IF(wbs_sel(2) = '1') THEN
lw2b_state <= SEL_2;
dat_8_reg <= wbs_dat_i(23 DOWNTO 16);
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= pasmi_shift_bytes_int;
ELSE
lw2b_state <= END_ACCESS;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
END IF;
WHEN SEL_2 =>
IF(wbs_sel(3) = '1') THEN
lw2b_state <= SEL_3;
dat_8_reg <= wbs_dat_i(31 DOWNTO 24);
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= pasmi_shift_bytes_int;
ELSE
lw2b_state <= END_ACCESS;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
END IF;
WHEN SEL_3 =>
lw2b_state <= END_ACCESS;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
WHEN END_ACCESS =>
lw2b_state <= IDLE;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
-- coverage off
WHEN OTHERS =>
lw2b_state <= IDLE;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
ASSERT FALSE REPORT "Undeocded State" SEVERITY WARNING;
-- coverage on
END CASE;
END IF;
END PROCESS z126_01_pasmi_write_access_fsm;
----------------------
-- WBS to PASMI FSM --
----------------------
z126_01_pasmi_fsm_proc : PROCESS (rst, clk)
BEGIN
IF rst = '1' THEN
wbs_ack_int <= '0';
pasmi_busy_q <= '0';
pasmi_busy_qq <= '0';
pasmi_wren_int <= '0';
pasmi_rden_int <= '0';
pasmi_shift_bytes_int <= '0';
pasmi_read_rdid_int <= '0';
pasmi_sector_protect_int <= '0';
pasmi_fast_read_int <= '0';
pasmi_write_int <= '0';
pasmi_read_status_int <= '0';
pasmi_sector_erase_int <= '0';
pasmi_bulk_erase_int <= '0';
id_oe <= '0';
status_oe <= '0';
ELSIF rising_edge(clk) THEN
pasmi_busy_q <= pasmi_busy;
pasmi_busy_qq <= pasmi_busy_q;
IF ( ctrl_sector_protect = '1' OR ctrl_sector_erase = '1'
OR ctrl_bulk_erase = '1' OR ctrl_write = '1')
AND wbs_cyc = '1' AND wbs_stb = '1' THEN
-- control actions shall be acknowledged after start
IF pasmi_busy_q = '0' AND pasmi_busy = '1' THEN -- if action is started
wbs_ack_int <= '1';
ELSE
wbs_ack_int <= '0';
END IF;
ELSIF wbs_cyc = '1' AND wbs_stb = '1'
AND pasmi_busy_q = '1' AND pasmi_busy = '0' THEN
-- read and write access shall be acknowledged when finnished
wbs_ack_int <= '1';
ELSIF wbs_cyc = '1' AND wbs_stb = '1'
AND pasmi_wren_int = '1' AND pasmi_shift_bytes_int = '1' AND pasmi_data_write_fin = '1' THEN
-- write access shall be acknowledged when byte shifting has finished (no busy signal from pasmi)
wbs_ack_int <= '1';
ELSE
wbs_ack_int <= '0';
END IF;
ELSIF falling_edge(clk) THEN
IF ctrl_write = '1' AND pasmi_busy = '0' THEN
-- for the page write command no wishbone access for ctrl_write is needed
pasmi_wren_int <= '1';
pasmi_write_int <= '1';
ELSIF pasmi_busy_q = '1' AND pasmi_busy = '0' THEN
-- reset pasmi control signals at the same moment when wishbone access acknowledged
pasmi_wren_int <= '0';
pasmi_write_int <= '0';
pasmi_shift_bytes_int <= '0';
pasmi_rden_int <= '0';
pasmi_read_rdid_int <= '0';
pasmi_sector_protect_int <= '0';
pasmi_fast_read_int <= '0';
pasmi_read_status_int <= '0';
pasmi_sector_erase_int <= '0';
pasmi_bulk_erase_int <= '0';
ELSIF wbs_cyc = '1' AND wbs_stb = '1' AND wbs_ack_int = '0' THEN
-- wishbone acces
IF pasmi_busy_qq = '0' AND pasmi_busy_q = '0' AND pasmi_busy = '0' THEN
-- set control signals until they are recognized
id_oe <= '0';
status_oe <= '0';
IF ctrl_read_sid = '1' THEN
pasmi_read_rdid_int <= '1';
id_oe <= '1';
ELSIF ctrl_sector_protect = '1' THEN
pasmi_wren_int <= '1';
pasmi_sector_protect_int <= '1';
ELSIF ctrl_read_status = '1' THEN
pasmi_read_status_int <= '1';
status_oe <= '1';
ELSIF ctrl_sector_erase = '1' THEN
pasmi_wren_int <= '1';
pasmi_sector_erase_int <= '1';
ELSIF ctrl_bulk_erase = '1' THEN
pasmi_wren_int <= '1';
pasmi_bulk_erase_int <= '1';
ELSIF wbs_we = '1' THEN
-- programm page (fill buffer)
pasmi_wren_int <= '1';
pasmi_shift_bytes_int <= '1';
ELSE
-- we = '0' (read)
pasmi_fast_read_int <= '1';
pasmi_rden_int <= '1';
END IF;
ELSE
-- the pasmi access is recognized, so the control signals can be cleared
pasmi_wren_int <= '0';
pasmi_shift_bytes_int <= '0';
pasmi_read_rdid_int <= '0';
pasmi_sector_protect_int <= '0';
pasmi_fast_read_int <= '0';
pasmi_write_int <= '0';
pasmi_read_status_int <= '0';
pasmi_sector_erase_int <= '0';
pasmi_bulk_erase_int <= '0';
-- continue read until wishbone access is finished
IF pasmi_data_read_fin = '0' THEN
pasmi_rden_int <= pasmi_rden_int;
ELSE
pasmi_rden_int <= '0';
END IF;
id_oe <= id_oe;
status_oe <= status_oe;
END IF;
ELSE
-- reset pasmi control signals after wishbone acknowledged
pasmi_wren_int <= '0';
pasmi_write_int <= '0';
pasmi_shift_bytes_int <= '0';
pasmi_rden_int <= '0';
pasmi_read_rdid_int <= '0';
pasmi_sector_protect_int <= '0';
pasmi_fast_read_int <= '0';
pasmi_read_status_int <= '0';
pasmi_sector_erase_int <= '0';
pasmi_bulk_erase_int <= '0';
END IF; -- wishbone acces
END IF; -- clk
END PROCESS z126_01_pasmi_fsm_proc;
END z126_01_wb2pasmi_arch;
z126_01_wb_if_arbiter.vhd 0000664 0000000 0000000 00000022001 14574545710 0035355 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Whisbone Bus Interconnection
-- Project :
---------------------------------------------------------------
-- File : z126_01_wb_if_arbiter.vhd
-- Author : ....
-- Email : ....
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created :
---------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : Quartus II
---------------------------------------------------------------
-- Description :
-- Master # 0 1
-- Slave : 0 1 1
-- Master 0 = 1 connection(s)
-- Master 1 = 1 connection(s)
-- Slave 0 = 2 connection(s)
--
-- This module is derived from the 16z100-
-- It contaions an additional arbitration of control
-- signals for the z126_01_wb2pasmi.vhd module in the 16z126-01
-- design.
---------------------------------------------------------------
-- Hierarchy:
--
-- z126_01_wb_pkg.vhd
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_wb_if_arbiter.vhd,v $
-- Revision 1.1 2014/03/03 17:49:57 AGeissler
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.z126_01_pkg.ALL;
USE work.z126_01_wb_pkg.ALL;
ENTITY z126_01_wb_if_arbiter IS
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- master 0 interface
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic;
-- wb2pasmi master 0 control signals
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
-- master 1 interface
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic;
-- wb2pasmi master 1 control signals
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
-- slave 0 interface
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
-- wb2pasmi slave 0 control signals
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END z126_01_wb_if_arbiter;
ARCHITECTURE z126_01_wb_if_arbiter_arch OF z126_01_wb_if_arbiter IS
-- COMPONENT DECLARATIONS
COMPONENT z126_01_switch_fab_2 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic;
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END COMPONENT;
-- synthesis translate_off
COMPONENT z126_01_wbmon IS
GENERIC (
wbname : string := "wbmon";
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
bte : IN std_logic_vector(1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic
);
END COMPONENT;
-- synthesis translate_on
-- SIGNAL DEFINITIONS
SIGNAL wbs_0_ack : std_logic_vector(1 DOWNTO 0);
SIGNAL wbs_0_err : std_logic_vector(1 DOWNTO 0);
SIGNAL wbsi_0_int : wbo_type;
SIGNAL wbsi_0_cyc_int : std_logic;
SIGNAL wbmi_0_int : wbi_type;
SIGNAL wbmo_0_cyc_s : std_logic;
SIGNAL wbmi_1_int : wbi_type;
SIGNAL wbmo_1_cyc_s : std_logic;
BEGIN
wbsi_0 <= wbsi_0_int;
wbsi_0_cyc <= wbsi_0_cyc_int;
wbmi_0 <= wbmi_0_int;
wbmi_1 <= wbmi_1_int;
-- no data multiplexer for master #0 is needed, because of connection to one slave only
wbmi_0_int.dat <= wbso_0.dat;
wbmi_0_int.ack <= wbs_0_ack(0);
wbmi_0_int.err <= wbs_0_err(0);
-- no data multiplexer for master #1 is needed, because of connection to one slave only
wbmi_1_int.dat <= wbso_0.dat;
wbmi_1_int.ack <= wbs_0_ack(1);
wbmi_1_int.err <= wbs_0_err(1);
-- sf for slave #0:
sf_0: z126_01_switch_fab_2
PORT MAP (
clk => clk,
rst => rst,
-- master busses:
wbo_0 => wbmo_0,
cyc_0 => wbmo_0_cyc,
ack_0 => wbs_0_ack(0),
err_0 => wbs_0_err(0),
wbo_1 => wbmo_1,
cyc_1 => wbmo_1_cyc,
ack_1 => wbs_0_ack(1),
err_1 => wbs_0_err(1),
-- slave bus:
wbo_slave => wbso_0,
wbi_slave => wbsi_0_int,
wbi_slave_cyc => wbsi_0_cyc_int,
-- wb2pasmi control signals
ctrlmo_0 => ctrlmo_0,
ctrlmi_0 => ctrlmi_0,
ctrlmo_1 => ctrlmo_1,
ctrlmi_1 => ctrlmi_1,
ctrlso_0 => ctrlso_0,
ctrlsi_0 => ctrlsi_0
);
-- synthesis translate_off
wbmo_0_cyc_s <= '1' WHEN wbmo_0_cyc = '0' ELSE '1';
wbm_0: z126_01_wbmon
GENERIC MAP (
wbname => "wbm_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_0.adr,
sldat_i => wbmo_0.dat,
sldat_o => wbmi_0_int.dat,
cti => wbmo_0.cti,
bte => wbmo_0.bte,
sel => wbmo_0.sel,
cyc => wbmo_0_cyc_s,
stb => wbmo_0.stb,
ack => wbmi_0_int.ack,
err => wbmi_0_int.err,
we => wbmo_0.we
);
wbmo_1_cyc_s <= '1' WHEN wbmo_1_cyc = '0' ELSE '1';
wbm_1: z126_01_wbmon
GENERIC MAP (
wbname => "wbm_1",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbmo_1.adr,
sldat_i => wbmo_1.dat,
sldat_o => wbmi_1_int.dat,
cti => wbmo_1.cti,
bte => wbmo_1.bte,
sel => wbmo_1.sel,
cyc => wbmo_1_cyc_s,
stb => wbmo_1.stb,
ack => wbmi_1_int.ack,
err => wbmi_1_int.err,
we => wbmo_1.we
);
wbs_0: z126_01_wbmon
GENERIC MAP (
wbname => "wbs_0",
sets => sets,
timeout => timeout
)
PORT MAP (
clk => clk,
rst => rst,
adr => wbsi_0_int.adr,
sldat_i => wbsi_0_int.dat,
sldat_o => wbso_0.dat,
cti => wbsi_0_int.cti,
bte => wbsi_0_int.bte,
sel => wbsi_0_int.sel,
cyc => wbsi_0_cyc_int,
stb => wbsi_0_int.stb,
ack => wbso_0.ack,
err => wbso_0.err,
we => wbsi_0_int.we
);
-- synthesis translate_on
END z126_01_wb_if_arbiter_arch;
z126_01_wb_pkg.vhd 0000664 0000000 0000000 00000223600 14574545710 0034040 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : system unit package
-- Project : Embedded System Module
---------------------------------------------------------------
-- File : z126_01_wb_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 17/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Package for wishbone bus functions.
-- Consists of data mux for x chip selects.
-- Wishbone bus input and output type definition.
-- This package is used for wb_bus (busmaker).
--
-- Switch-fab naming convention is:
-- All signal names are based on the source of the signal
-- (wbo_slave = output singals of slave)
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_wb_pkg.vhd,v $
-- Revision 1.1 2014/03/03 17:49:58 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE z126_01_wb_pkg IS
TYPE wbo_type IS record
stb : std_logic;
sel : std_logic_vector(3 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
bte : std_logic_vector(1 DOWNTO 0);
END record;
TYPE wbi_type IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
END record;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_22 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) ;
END z126_01_wb_pkg;
PACKAGE BODY z126_01_wb_pkg IS
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "01" => data_out <= data_in_0;
WHEN "10" => data_out <= data_in_1;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "001" => data_out <= data_in_0;
WHEN "010" => data_out <= data_in_1;
WHEN "100" => data_out <= data_in_2;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0001" => data_out <= data_in_0;
WHEN "0010" => data_out <= data_in_1;
WHEN "0100" => data_out <= data_in_2;
WHEN "1000" => data_out <= data_in_3;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00001" => data_out <= data_in_0;
WHEN "00010" => data_out <= data_in_1;
WHEN "00100" => data_out <= data_in_2;
WHEN "01000" => data_out <= data_in_3;
WHEN "10000" => data_out <= data_in_4;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000001" => data_out <= data_in_0;
WHEN "000010" => data_out <= data_in_1;
WHEN "000100" => data_out <= data_in_2;
WHEN "001000" => data_out <= data_in_3;
WHEN "010000" => data_out <= data_in_4;
WHEN "100000" => data_out <= data_in_5;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000001" => data_out <= data_in_0;
WHEN "0000010" => data_out <= data_in_1;
WHEN "0000100" => data_out <= data_in_2;
WHEN "0001000" => data_out <= data_in_3;
WHEN "0010000" => data_out <= data_in_4;
WHEN "0100000" => data_out <= data_in_5;
WHEN "1000000" => data_out <= data_in_6;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000001" => data_out <= data_in_0;
WHEN "00000010" => data_out <= data_in_1;
WHEN "00000100" => data_out <= data_in_2;
WHEN "00001000" => data_out <= data_in_3;
WHEN "00010000" => data_out <= data_in_4;
WHEN "00100000" => data_out <= data_in_5;
WHEN "01000000" => data_out <= data_in_6;
WHEN "10000000" => data_out <= data_in_7;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000001" => data_out <= data_in_0;
WHEN "000000010" => data_out <= data_in_1;
WHEN "000000100" => data_out <= data_in_2;
WHEN "000001000" => data_out <= data_in_3;
WHEN "000010000" => data_out <= data_in_4;
WHEN "000100000" => data_out <= data_in_5;
WHEN "001000000" => data_out <= data_in_6;
WHEN "010000000" => data_out <= data_in_7;
WHEN "100000000" => data_out <= data_in_8;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000001" => data_out <= data_in_0;
WHEN "0000000010" => data_out <= data_in_1;
WHEN "0000000100" => data_out <= data_in_2;
WHEN "0000001000" => data_out <= data_in_3;
WHEN "0000010000" => data_out <= data_in_4;
WHEN "0000100000" => data_out <= data_in_5;
WHEN "0001000000" => data_out <= data_in_6;
WHEN "0010000000" => data_out <= data_in_7;
WHEN "0100000000" => data_out <= data_in_8;
WHEN "1000000000" => data_out <= data_in_9;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000001" => data_out <= data_in_0;
WHEN "00000000010" => data_out <= data_in_1;
WHEN "00000000100" => data_out <= data_in_2;
WHEN "00000001000" => data_out <= data_in_3;
WHEN "00000010000" => data_out <= data_in_4;
WHEN "00000100000" => data_out <= data_in_5;
WHEN "00001000000" => data_out <= data_in_6;
WHEN "00010000000" => data_out <= data_in_7;
WHEN "00100000000" => data_out <= data_in_8;
WHEN "01000000000" => data_out <= data_in_9;
WHEN "10000000000" => data_out <= data_in_10;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000001" => data_out <= data_in_0;
WHEN "000000000010" => data_out <= data_in_1;
WHEN "000000000100" => data_out <= data_in_2;
WHEN "000000001000" => data_out <= data_in_3;
WHEN "000000010000" => data_out <= data_in_4;
WHEN "000000100000" => data_out <= data_in_5;
WHEN "000001000000" => data_out <= data_in_6;
WHEN "000010000000" => data_out <= data_in_7;
WHEN "000100000000" => data_out <= data_in_8;
WHEN "001000000000" => data_out <= data_in_9;
WHEN "010000000000" => data_out <= data_in_10;
WHEN "100000000000" => data_out <= data_in_11;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000001" => data_out <= data_in_0;
WHEN "0000000000010" => data_out <= data_in_1;
WHEN "0000000000100" => data_out <= data_in_2;
WHEN "0000000001000" => data_out <= data_in_3;
WHEN "0000000010000" => data_out <= data_in_4;
WHEN "0000000100000" => data_out <= data_in_5;
WHEN "0000001000000" => data_out <= data_in_6;
WHEN "0000010000000" => data_out <= data_in_7;
WHEN "0000100000000" => data_out <= data_in_8;
WHEN "0001000000000" => data_out <= data_in_9;
WHEN "0010000000000" => data_out <= data_in_10;
WHEN "0100000000000" => data_out <= data_in_11;
WHEN "1000000000000" => data_out <= data_in_12;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000001" => data_out <= data_in_0;
WHEN "00000000000010" => data_out <= data_in_1;
WHEN "00000000000100" => data_out <= data_in_2;
WHEN "00000000001000" => data_out <= data_in_3;
WHEN "00000000010000" => data_out <= data_in_4;
WHEN "00000000100000" => data_out <= data_in_5;
WHEN "00000001000000" => data_out <= data_in_6;
WHEN "00000010000000" => data_out <= data_in_7;
WHEN "00000100000000" => data_out <= data_in_8;
WHEN "00001000000000" => data_out <= data_in_9;
WHEN "00010000000000" => data_out <= data_in_10;
WHEN "00100000000000" => data_out <= data_in_11;
WHEN "01000000000000" => data_out <= data_in_12;
WHEN "10000000000000" => data_out <= data_in_13;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000001" => data_out <= data_in_0;
WHEN "000000000000010" => data_out <= data_in_1;
WHEN "000000000000100" => data_out <= data_in_2;
WHEN "000000000001000" => data_out <= data_in_3;
WHEN "000000000010000" => data_out <= data_in_4;
WHEN "000000000100000" => data_out <= data_in_5;
WHEN "000000001000000" => data_out <= data_in_6;
WHEN "000000010000000" => data_out <= data_in_7;
WHEN "000000100000000" => data_out <= data_in_8;
WHEN "000001000000000" => data_out <= data_in_9;
WHEN "000010000000000" => data_out <= data_in_10;
WHEN "000100000000000" => data_out <= data_in_11;
WHEN "001000000000000" => data_out <= data_in_12;
WHEN "010000000000000" => data_out <= data_in_13;
WHEN "100000000000000" => data_out <= data_in_14;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000001" => data_out <= data_in_0;
WHEN "0000000000000010" => data_out <= data_in_1;
WHEN "0000000000000100" => data_out <= data_in_2;
WHEN "0000000000001000" => data_out <= data_in_3;
WHEN "0000000000010000" => data_out <= data_in_4;
WHEN "0000000000100000" => data_out <= data_in_5;
WHEN "0000000001000000" => data_out <= data_in_6;
WHEN "0000000010000000" => data_out <= data_in_7;
WHEN "0000000100000000" => data_out <= data_in_8;
WHEN "0000001000000000" => data_out <= data_in_9;
WHEN "0000010000000000" => data_out <= data_in_10;
WHEN "0000100000000000" => data_out <= data_in_11;
WHEN "0001000000000000" => data_out <= data_in_12;
WHEN "0010000000000000" => data_out <= data_in_13;
WHEN "0100000000000000" => data_out <= data_in_14;
WHEN "1000000000000000" => data_out <= data_in_15;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000001" => data_out <= data_in_0;
WHEN "00000000000000010" => data_out <= data_in_1;
WHEN "00000000000000100" => data_out <= data_in_2;
WHEN "00000000000001000" => data_out <= data_in_3;
WHEN "00000000000010000" => data_out <= data_in_4;
WHEN "00000000000100000" => data_out <= data_in_5;
WHEN "00000000001000000" => data_out <= data_in_6;
WHEN "00000000010000000" => data_out <= data_in_7;
WHEN "00000000100000000" => data_out <= data_in_8;
WHEN "00000001000000000" => data_out <= data_in_9;
WHEN "00000010000000000" => data_out <= data_in_10;
WHEN "00000100000000000" => data_out <= data_in_11;
WHEN "00001000000000000" => data_out <= data_in_12;
WHEN "00010000000000000" => data_out <= data_in_13;
WHEN "00100000000000000" => data_out <= data_in_14;
WHEN "01000000000000000" => data_out <= data_in_15;
WHEN "10000000000000000" => data_out <= data_in_16;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000100" => data_out <= data_in_2;
WHEN "000000000000001000" => data_out <= data_in_3;
WHEN "000000000000010000" => data_out <= data_in_4;
WHEN "000000000000100000" => data_out <= data_in_5;
WHEN "000000000001000000" => data_out <= data_in_6;
WHEN "000000000010000000" => data_out <= data_in_7;
WHEN "000000000100000000" => data_out <= data_in_8;
WHEN "000000001000000000" => data_out <= data_in_9;
WHEN "000000010000000000" => data_out <= data_in_10;
WHEN "000000100000000000" => data_out <= data_in_11;
WHEN "000001000000000000" => data_out <= data_in_12;
WHEN "000010000000000000" => data_out <= data_in_13;
WHEN "000100000000000000" => data_out <= data_in_14;
WHEN "001000000000000000" => data_out <= data_in_15;
WHEN "010000000000000000" => data_out <= data_in_16;
WHEN "100000000000000000" => data_out <= data_in_17;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000100000" => data_out <= data_in_5;
WHEN "0000000000001000000" => data_out <= data_in_6;
WHEN "0000000000010000000" => data_out <= data_in_7;
WHEN "0000000000100000000" => data_out <= data_in_8;
WHEN "0000000001000000000" => data_out <= data_in_9;
WHEN "0000000010000000000" => data_out <= data_in_10;
WHEN "0000000100000000000" => data_out <= data_in_11;
WHEN "0000001000000000000" => data_out <= data_in_12;
WHEN "0000010000000000000" => data_out <= data_in_13;
WHEN "0000100000000000000" => data_out <= data_in_14;
WHEN "0001000000000000000" => data_out <= data_in_15;
WHEN "0010000000000000000" => data_out <= data_in_16;
WHEN "0100000000000000000" => data_out <= data_in_17;
WHEN "1000000000000000000" => data_out <= data_in_18;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000100000" => data_out <= data_in_5;
WHEN "00000000000001000000" => data_out <= data_in_6;
WHEN "00000000000010000000" => data_out <= data_in_7;
WHEN "00000000000100000000" => data_out <= data_in_8;
WHEN "00000000001000000000" => data_out <= data_in_9;
WHEN "00000000010000000000" => data_out <= data_in_10;
WHEN "00000000100000000000" => data_out <= data_in_11;
WHEN "00000001000000000000" => data_out <= data_in_12;
WHEN "00000010000000000000" => data_out <= data_in_13;
WHEN "00000100000000000000" => data_out <= data_in_14;
WHEN "00001000000000000000" => data_out <= data_in_15;
WHEN "00010000000000000000" => data_out <= data_in_16;
WHEN "00100000000000000000" => data_out <= data_in_17;
WHEN "01000000000000000000" => data_out <= data_in_18;
WHEN "10000000000000000000" => data_out <= data_in_19;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000000100" => data_out <= data_in_2;
WHEN "000000000000000001000" => data_out <= data_in_3;
WHEN "000000000000000010000" => data_out <= data_in_4;
WHEN "000000000000000100000" => data_out <= data_in_5;
WHEN "000000000000001000000" => data_out <= data_in_6;
WHEN "000000000000010000000" => data_out <= data_in_7;
WHEN "000000000000100000000" => data_out <= data_in_8;
WHEN "000000000001000000000" => data_out <= data_in_9;
WHEN "000000000010000000000" => data_out <= data_in_10;
WHEN "000000000100000000000" => data_out <= data_in_11;
WHEN "000000001000000000000" => data_out <= data_in_12;
WHEN "000000010000000000000" => data_out <= data_in_13;
WHEN "000000100000000000000" => data_out <= data_in_14;
WHEN "000001000000000000000" => data_out <= data_in_15;
WHEN "000010000000000000000" => data_out <= data_in_16;
WHEN "000100000000000000000" => data_out <= data_in_17;
WHEN "001000000000000000000" => data_out <= data_in_18;
WHEN "010000000000000000000" => data_out <= data_in_19;
WHEN "100000000000000000000" => data_out <= data_in_20;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000000100000" => data_out <= data_in_5;
WHEN "0000000000000001000000" => data_out <= data_in_6;
WHEN "0000000000000010000000" => data_out <= data_in_7;
WHEN "0000000000000100000000" => data_out <= data_in_8;
WHEN "0000000000001000000000" => data_out <= data_in_9;
WHEN "0000000000010000000000" => data_out <= data_in_10;
WHEN "0000000000100000000000" => data_out <= data_in_11;
WHEN "0000000001000000000000" => data_out <= data_in_12;
WHEN "0000000010000000000000" => data_out <= data_in_13;
WHEN "0000000100000000000000" => data_out <= data_in_14;
WHEN "0000001000000000000000" => data_out <= data_in_15;
WHEN "0000010000000000000000" => data_out <= data_in_16;
WHEN "0000100000000000000000" => data_out <= data_in_17;
WHEN "0001000000000000000000" => data_out <= data_in_18;
WHEN "0010000000000000000000" => data_out <= data_in_19;
WHEN "0100000000000000000000" => data_out <= data_in_20;
WHEN "1000000000000000000000" => data_out <= data_in_21;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_22 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000000100000" => data_out <= data_in_5;
WHEN "00000000000000001000000" => data_out <= data_in_6;
WHEN "00000000000000010000000" => data_out <= data_in_7;
WHEN "00000000000000100000000" => data_out <= data_in_8;
WHEN "00000000000001000000000" => data_out <= data_in_9;
WHEN "00000000000010000000000" => data_out <= data_in_10;
WHEN "00000000000100000000000" => data_out <= data_in_11;
WHEN "00000000001000000000000" => data_out <= data_in_12;
WHEN "00000000010000000000000" => data_out <= data_in_13;
WHEN "00000000100000000000000" => data_out <= data_in_14;
WHEN "00000001000000000000000" => data_out <= data_in_15;
WHEN "00000010000000000000000" => data_out <= data_in_16;
WHEN "00000100000000000000000" => data_out <= data_in_17;
WHEN "00001000000000000000000" => data_out <= data_in_18;
WHEN "00010000000000000000000" => data_out <= data_in_19;
WHEN "00100000000000000000000" => data_out <= data_in_20;
WHEN "01000000000000000000000" => data_out <= data_in_21;
WHEN "10000000000000000000000" => data_out <= data_in_22;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) IS
BEGIN
IF rst = '1' THEN
wbi_slave.stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave.stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave.stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave.stb <= '0';
ELSE
wbi_slave.stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave.stb <= '0';
END IF;
END IF;
wbi_slave_cyc <= cyc_0;
ack_0 <= wbo_slave.ack;
err_0 <= wbo_slave.err;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.bte <= wbo_0.bte;
wbi_slave.tga <= wbo_0.tga;
END switch_fab;
END;
z126_01_wbmon.vhd 0000664 0000000 0000000 00000053252 14574545710 0033715 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : z126_01_wbmon.vhd
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description : This Wishbone Monitor asserts that all signals
-- and transaction on a wishbone bus are handled
-- correct. It outputs errors on std_out and the
-- rest into a file
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_wbmon.vhd,v $
-- Revision 1.1 2014/03/03 17:49:59 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
--Errorcoding:
--
-- 0x00
-- Acknowledge without Strobe or cycle:
-- an Acknowledge was given by the module alltough the module was not
-- addressed with strobe or cycle
--
-- 0x01
-- Address changed during transaction!
-- The address changed during a normal cycle or within a burst cycle
-- Not if it happens in a burst cycle it only asserts inside a single
-- transaction of the burst, address increment is handled in error 0x09
--
-- 0x02
-- Data in of slave changed during transaction!
-- data in of the slave changed during a write cycle
--
-- 0x03
-- Select Bits changed during transaction!
--
-- 0x04
-- CTI changed during transaction!
--
-- 0x05
-- Burst with not allowed cti:
-- in the current wishbone specification only cti of 000,010,111 are defined
--
-- 0x06
-- unsupported BTE:
-- only an address increment of 4 is supported by the current wishbone bus and
-- its modules. Other BTEs are unsupported at the moment
--
-- 0x07
-- WE changed during burst!
--
-- 0x08
-- SEL changed during burst!
--
-- 0x09
-- wrong address increment or address changed during burst cycle:
-- the address has to increment by 4 in burst mode
--
-- 0x0a
-- Missing End Of Burst:
-- the end of a burst has to be shown by setting cti to 111 in the last
-- burst cycle. This signal is missing here
--
-- 0x0b
-- We changed during transaction!
--
-- 0x0c
-- Sel changed during transaction!
--
-- 0x0d
-- Strobe went low without acknowledge:
-- no acknowledge was given by the module but strobe was reset to 0
--
-- 0x0e
-- U Z X in statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
USE std.textio.all;
USE ieee.std_logic_textio.all;
-- synthesis translate_on
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY z126_01_wbmon IS
GENERIC(
wbname : string := "z126_01_wbmon";
-- Output Settings
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(31 DOWNTO 0);
sldat_o : IN std_logic_vector(31 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
bte : IN std_logic_vector(1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic;
er : OUT std_logic;
co : OUT std_logic_vector(7 DOWNTO 0)
);
PROCEDURE outp (
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
);
PROCEDURE outp_cycle (
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
);
END z126_01_wbmon;
ARCHITECTURE z126_01_wbmon_arch OF z126_01_wbmon IS
FUNCTION to_string (
constant val : in std_logic_vector
) RETURN string IS
constant reglen : INTEGER := val'LENGTH;
variable result_str : string(1 to reglen);
variable slv : std_logic_vector(1 to reglen) := val;
BEGIN
FOR i IN reglen DOWNTO 1 LOOP
CASE slv(i) IS
WHEN 'U' => result_str(i) := 'U';
WHEN 'X' => result_str(i) := 'X';
WHEN '0' => result_str(i) := '0';
WHEN '1' => result_str(i) := '1';
WHEN 'Z' => result_str(i) := 'Z';
WHEN 'W' => result_str(i) := 'W';
WHEN 'L' => result_str(i) := 'L';
WHEN 'H' => result_str(i) := 'H';
WHEN '-' => result_str(i) := '-';
WHEN OTHERS => -- an unknown std_logic value was passed
ASSERT FALSE
REPORT "to_string - unknown std_logic_vector value"
SEVERITY ERROR;
END CASE;
END LOOP;
return result_str;
END;
FUNCTION to_hstring
(
CONSTANT bitaccess : IN natural;
CONSTANT val : in std_logic_vector--(7 DOWNTO 0)
) RETURN string is
VARIABLE reglen : natural := 1;
VARIABLE result_str : string(1 to (bitaccess / 4));
VARIABLE slv : std_logic_vector(bitaccess-1 DOWNTO 0);-- := val;
VARIABLE temp : std_logic_vector(3 DOWNTO 0);
BEGIN
slv := val;
IF bitaccess = 8 THEN
reglen := 1;
ELSIF bitaccess = 16 THEN
reglen := 3;
ELSIF bitaccess = 32 THEN
reglen := 7;
ELSIF bitaccess = 64 THEN
reglen := 15;
ELSE
END IF;
FOR i in reglen DOWNTO 0 LOOP
temp := slv(i*4 + 3 DOWNTO (i *4));
CASE temp IS
WHEN "0000" => result_str(reglen + 1 - i) := '0';
WHEN "0001" => result_str(reglen + 1 - i) := '1';
WHEN "0010" => result_str(reglen + 1 - i) := '2';
WHEN "0011" => result_str(reglen + 1 - i) := '3';
WHEN "0100" => result_str(reglen + 1 - i) := '4';
WHEN "0101" => result_str(reglen + 1 - i) := '5';
WHEN "0110" => result_str(reglen + 1 - i) := '6';
WHEN "0111" => result_str(reglen + 1 - i) := '7';
WHEN "1000" => result_str(reglen + 1 - i) := '8';
WHEN "1001" => result_str(reglen + 1 - i) := '9';
WHEN "1010" => result_str(reglen + 1 - i) := 'A';
WHEN "1011" => result_str(reglen + 1 - i) := 'B';
WHEN "1100" => result_str(reglen + 1 - i) := 'C';
WHEN "1101" => result_str(reglen + 1 - i) := 'D';
WHEN "1110" => result_str(reglen + 1 - i) := 'E';
WHEN "1111" => result_str(reglen + 1 - i) := 'F';
WHEN others => result_str(reglen + 1 - i) := ' ';
-- an unknown std_logic value was passed
END CASE;
END LOOP;
RETURN result_str;
END;
FUNCTION data_out (sel : std_logic_vector(3 downto 0); dat : std_logic_vector(31 downto 0)) RETURN string IS
variable byte0 : string(1 to 2);
variable byte1 : string(1 to 2);
variable byte2 : string(1 to 2);
variable byte3 : string(1 to 2);
BEGIN
if sel(0) = '1' then
byte0 := to_hstring(8,dat( 7 downto 0));
else
byte0 := "XX";
end if;
if sel(1) = '1' then
byte1 := to_hstring(8,dat(15 downto 8));
else
byte1 := "XX";
end if;
if sel(2) = '1' then
byte2 := to_hstring(8,dat(23 downto 16));
else
byte2 := "XX";
end if;
if sel(3) = '1' then
byte3 := to_hstring(8,dat(31 downto 24));
else
byte3 := "XX";
end if;
return (byte3 & byte2 & "_" & byte1 & byte0);
end data_out;
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
)
IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
VARIABLE ol : line;
-- synthesis translate_on
BEGIN
IF NOT(condition) AND enable = '1' THEN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " 0x");
hwrite(wl, code);
WRITELINE(Output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
IF (sev = ERROR) THEN
e := '1';
c := code;
END IF;
END IF;
END;
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
ende : string := "OK"
) IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 4);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" SEL: "));
WRITE(wl, sel, field => 8);
write(wl,string'(" DATA: "));
WRITE(wl,string'(data_out(sel, data)));
-- Output ende
WRITE(wl, ende);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
END;
-- SIGNALS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Write_Mode
IS wbname & "_transcript.txt"; -- Write- File
-- synthesis translate_on
TYPE wb_state_type IS (IDLE, CYCLE, BURST);
SIGNAL wb_state : wb_state_type;
SIGNAL adr_s : std_logic_vector(31 DOWNTO 0);
SIGNAL sldat_i_s : std_logic_vector(31 DOWNTO 0);
SIGNAL we_s : std_logic;
SIGNAL cti_s : std_logic_vector(2 DOWNTO 0);
SIGNAL sel_s : std_logic_vector (3 DOWNTO 0);
SIGNAL cti_b : std_logic_vector(2 DOWNTO 0);
SIGNAL sldat_i_b : std_logic_vector(31 DOWNTO 0);
SIGNAL new_b : std_logic;
SIGNAL enable : std_logic;
BEGIN
enable <= '1';
-- synthesis translate_off
PROCESS(clk)
VARIABLE burst : string (1 TO 5);
BEGIN
IF rising_edge(clk) THEN
IF (cti /= "000") THEN
burst := "Burst";
ELSE
burst := " ";
END IF;
IF (ack = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> OK");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> OK");
END IF;
END IF;
IF (err = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> ERROR");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> ERROR");
END IF;
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
-- Create Cycle start time
PROCESS(clk)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF (rst = '1') THEN
sel_s <= (OTHERS => '0');
adr_s <= (OTHERS => '0');
sldat_i_s <= (OTHERS => '0');
sldat_i_b <= (OTHERS => '0');
we_s <= '0';
new_b <= '0';
e := '0';
c := (OTHERS => '0');
er <= '0';
co <= (OTHERS => '0');
cti_b <= (OTHERS => '0');
cti_s <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
CASE wb_state IS
WHEN IDLE =>
IF (stb = '1' AND cyc = '1') THEN
IF (cti = "111" OR cti = "000") THEN
-- Normal Cycle SAVE DATA
wb_state <= CYCLE;
cti_s <= cti;
adr_s <= adr;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "010") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' THEN
adr_s <= adr + 4;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSE
outp(e,c,"Unsupported CTI " & to_string(cti),x"05", enable , ERROR);
END IF;
IF ack = '1' THEN
IF cti /= "010" THEN
-- stay in idle if single cycle with acknowledge
wb_state <= IDLE;
END IF;
END IF;
ELSE
IF ack = '1' THEN
outp(e,c,"acknowledge without cycle and/or strobe",x"00", enable , ERROR);
END IF;
END IF;
WHEN BURST =>
outp(e,c,"Unsupported BTE ("&to_string(bte)&" sb 00)", x"06", enable , ERROR, bte = "00");
IF (cti /= "010" AND cti /="111") THEN
-- ERROR missing End of burst
outp(e,c,"Missing end of burst", x"0a", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
-- CHECK SIGNALS which can change after ack
IF (new_b = '1') THEN
cti_b <= cti;
sldat_i_b <= sldat_i;
new_b <= '0';
ELSE
outp(e,c,"CTI changed during burst cycle ("&to_string(cti)&" sb "&to_string(cti_b)&")", x"04", enable , ERROR, cti = cti_b);
outp(e,c,"Master Data Out changed during burst cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_b)&")", x"02", enable , ERROR, sldat_i = sldat_i_b OR we = '0');
END IF;
IF (ack = '1' AND cti = "111") THEN
-- End of Burst
wb_state <= IDLE;
ELSIF (ack = '1') THEN
-- Addrress Increment on acknowledge
adr_s <= adr_s + 4;
new_b <= '1';
wb_state <= BURST;
END IF;
-- CHECK SIGNALS:
-- we has to stay the same throughout the burst
outp(e,c,"We changed during burst (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"07", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during burst (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"09", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during burst ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"08", enable , ERROR, sel = sel_s);
WHEN CYCLE =>
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge ", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (ack = '1') THEN
wb_state <= IDLE;
END IF;
-- we has to stay the same throughout the burst
outp(e,c,"We changed during cycle (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"0b", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during cycle (0x"&to_hstring(32,adr)&" sb 0x"&to_hstring(32,adr_s)&")", x"01", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during cycle ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"0c", enable , ERROR, sel = sel_s);
outp(e,c,"CTI changed during cycle ("&to_string(cti)&" sb "&to_string(cti_s)&")", x"04", enable , ERROR, cti = cti_s);
outp(e,c,"Master Data Out changed during cycle (0x"&to_hstring(32,sldat_i)&" sb 0x"&to_hstring(32,sldat_i_s)&")", x"02", enable , ERROR, sldat_i = sldat_i_s OR we = '0');
WHEN OTHERS =>
ASSERT FALSE REPORT "AHH OHHHHHHH" SEVERITY failure;
END CASE;
co <= c;
er <= e;
END IF;
END PROCESS;
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS( clk, rst, cyc, stb, we, ack, err, bte, cti, adr, sldat_i, sldat_o)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF(NOT (NOW = 0 ps)) THEN
IF (rst = '0' OR rst = 'U') AND (cyc = 'U' OR cyc = 'Z' OR cyc = 'X') THEN
outp(e,c,"cyc is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (clk = 'U' OR clk = 'Z' OR clk = 'X') THEN
outp(e,c,"clk is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (stb = 'U' OR stb = 'Z' OR stb = 'X') THEN
outp(e,c,"stb is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (we = 'U' OR we = 'Z' OR we = 'X') AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"we is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (ack = 'U' OR ack = 'Z' OR ack = 'X') THEN
outp(e,c,"ack is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (err = 'U' OR err = 'Z' OR err = 'X') THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sel) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(bte) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"bte is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(cti) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"cti is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(adr) AND stb = '1' AND cyc /= '0' THEN
outp(e,c,"adr is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_i) AND cyc /= '0' AND stb = '1' THEN
outp(e,c,"data_in is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_o) AND ack /= '0' THEN
outp(e,c,"data_o is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
END z126_01_wbmon_arch; Synthesis/ 0000775 0000000 0000000 00000000000 14574545710 0031530 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src 16z126-01_syn.tcl 0000664 0000000 0000000 00000005262 14574545710 0034221 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/16z126-01_src/Synthesis # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_wbmon.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_wb2pasmi.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_wb_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_wb_if_arbiter.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_top.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_indi_if_ctrl_regs.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_fifo_d1.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_clk_trans_wb2wb.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_switch_fab_2.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_pasmi/z126_01_pasmi_m25p32.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_pasmi/z126_01_pasmi_m25p64.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_pasmi/z126_01_pasmi_m25p128.vhd"
#For CYCLONE V
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_ru_ctrl_cyc5.vhd"
#For CYCLONE V AND EPCS16
set_global_assignment -name QIP_FILE "../../../16z126-01/Source/z126_01_ru/z126_01_ru_cyclonev_m25p32/synthesis/z126_01_ru_cyclonev_m25p32.qip"
#For CYCLONE V AND EPCS64
set_global_assignment -name QIP_FILE "../../../16z126-01/Source/z126_01_ru/z126_01_ru_cyclonev_m25p64/synthesis/z126_01_ru_cyclonev_m25p64.qip"
#For CYCLONE V AND EPCS128
set_global_assignment -name QIP_FILE "../../../16z126-01/Source/z126_01_ru/z126_01_ru_cyclonev_m25p128/synthesis/z126_01_ru_cyclonev_m25p128.qip"
#For CYCLONE IV
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_ru_ctrl_cyc.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_ru/z126_01_ru_cycloneiv.vhd.vhd"
#For CYCLONE III
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_ru_ctrl_cyc.vhd"
set_global_assignment -name VHDL_FILE "../../../16z126-01/Source/z126_01_ru/z126_01_ru_cycloneiii.vhd.vhd"
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/README.md 0000664 0000000 0000000 00000001367 14574545710 0027146 0 ustar 00root root 0000000 0000000
Contents of this folder
=======================
``16z000-00_src``: VHDL package for technology definitions.
``16z024-01_src``: VHDL source for FPGA internal ROM (used for storing the Chameleon table).
``16z091-01_src``: VHDL source and Altera IP cores for PCIe to Wisbhone interface.
``16z100-01_src``: VHDL source for Wishbone interconnect.
``16z126-01_src``: VHDL source and Altera IP cores for serial flash remote update.
``syn``: Altera Quartus synthesis (including top-level HDLmake manifest).
``testbench``: HDL simulation testbench (more info in README inside folder).
``top``: VHDL top-level module, Altera PCIe PLL IP core, peripherals and Chameleon table.
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/ 0000775 0000000 0000000 00000000000 14574545710 0026471 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/.gitignore 0000664 0000000 0000000 00000000224 14574545710 0030457 0 ustar 00root root 0000000 0000000 # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
*
!.gitignore
!Manifest.py
!*.sdc
!scripts
!scripts/*
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/A25_top.sdc 0000664 0000000 0000000 00000066062 14574545710 0030407 0 ustar 00root root 0000000 0000000 # SPDX-FileCopyrightText: 2016 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk_16mhz} -period 62.500 -waveform { 0.000 31.250 } [get_ports {clk_16mhz}]
create_clock -name {refclk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {refclk}]
#**************************************************************
# Create Generated Clock
# clk[0] - clk_125
# clk[1] - clk_50
# clk[2] - sys_clkl
# clk[3] - sr_clk_ext
# clk[4] - clk_33
#**************************************************************
derive_pll_clocks
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {clk_16mhz}] -rise_to [get_clocks {clk_16mhz}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {clk_16mhz}] -fall_to [get_clocks {clk_16mhz}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {pcie_sys_clk}] -rise_to [get_clocks {pcie_sys_clk}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {pcie_sys_clk}] -fall_to [get_clocks {pcie_sys_clk}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {clk_125}] -rise_to [get_clocks {clk_125}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {clk_125}] -fall_to [get_clocks {clk_125}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {sys_clk}] -rise_to [get_clocks {sys_clk}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {sys_clk}] -fall_to [get_clocks {sys_clk}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {clk_33}] -rise_to [get_clocks {clk_33}] 0.020
#set_clock_uncertainty -rise_from [get_clocks {clk_33}] -fall_to [get_clocks {clk_33}] 0.020
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 10.000 [get_ports {fpga_test*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {fpga_test*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 8.500 [get_ports {sr_d[*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 3.100 [get_ports {sr_d[*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_a[*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_a[*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_acfail_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_acfail_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_am[*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_am[*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_as_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_as_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_bbsy_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_bbsy_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_bclr_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_bclr_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_berr_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_berr_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_bg_i_n*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_bg_i_n*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_br_i_n*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_br_i_n*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_d[*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_d[*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_ds_i_n*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_ds_i_n*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_dtack_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_dtack_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_iack_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_iack_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_iack_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_iack_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_irq_i_n*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_irq_i_n*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_retry_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_retry_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_sysfail_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_sysfail_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_sysres_i_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_sysres_i_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_write_n}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_write_n}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_ga[*}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_ga[*}]
set_input_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 12.000 [get_ports {vme_gap}]
set_input_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_gap}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 1.000 [get_ports {fpga_test*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {fpga_test*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 2.000 [get_ports {led*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {led*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 2.700 [get_ports {sr_a[*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -0.200 [get_ports {sr_a[*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 2.700 [get_ports {sr_adsc_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -0.200 [get_ports {sr_adsc_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 2.700 [get_ports {sr_bw_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -0.200 [get_ports {sr_bw_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 2.700 [get_ports {sr_bwa_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -0.200 [get_ports {sr_bwa_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 2.700 [get_ports {sr_bwb_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -0.200 [get_ports {sr_bwb_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 2.700 [get_ports {sr_cs1_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -0.200 [get_ports {sr_cs1_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 2.700 [get_ports {sr_d*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -0.200 [get_ports {sr_d*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] 2.700 [get_ports {sr_oe_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -0.200 [get_ports {sr_oe_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 5.000 [get_ports {v2p_rstn}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {v2p_rstn}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_br_o*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_br_o*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_am[*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_am[*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_a[*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_a[*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_a_dir}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_a_dir}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_a_oe_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_a_oe_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_am_dir}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_am_dir}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_am_oe_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_am_oe_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_as_o_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_as_o_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_as_oe}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_as_oe}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_bbsy_o}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_bbsy_o}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_bclr_o_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_bclr_o_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_berr_o}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_berr_o}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_bg_o_n*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_bg_o_n*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_d[*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_d[*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_d_dir}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_d_dir}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_d_oe_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_d_oe_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_ds_o_n*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_ds_o_n*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_ds_oe}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_ds_oe}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_dtack_o}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_dtack_o}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_iack_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_iack_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_iack_o_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_iack_o_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_irq_o*}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_irq_o*}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_retry_o_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_retry_o_n}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_retry_oe}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_retry_oe}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_scon}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_scon}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_sysclk}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_sysclk}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_sysfail_o}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_sysfail_o}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_sysres_o}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_sysres_o}]
set_output_delay -add_delay -max -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 4.000 [get_ports {vme_write_n}]
set_output_delay -add_delay -min -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 0.000 [get_ports {vme_write_n}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#set_clock_groups -asynchronous -group [get_clocks {clk_125}]
#set_clock_groups -asynchronous -group [get_clocks {clk_50}]
#set_clock_groups -asynchronous -group [get_clocks {sys_clk}]
#set_clock_groups -asynchronous -group [get_clocks {sr_clk}]
#set_clock_groups -asynchronous -group [get_clocks {clk_33}]
#set_clock_groups -asynchronous -group [get_clocks {clk_16mhz}]
#set_clock_groups -asynchronous -group [get_clocks {refclk}]
#set_clock_groups -asynchronous -group [get_clocks {pcie_sys_clk}]
set_clock_groups -exclusive -group {refclk} \
-group {pll|altpll_component|auto_generated|pll1|clk[0]} \
-group {pll|altpll_component|auto_generated|pll1|clk[1]} \
-group {pll|altpll_component|auto_generated|pll1|clk[2]} \
-group {pll|altpll_component|auto_generated|pll1|clk[4]} \
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {pcie_sys_clk}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pcie_sys_clk}]
#set_false_path -from [get_clocks {clk_16mhz}] -to [get_clocks {altera_reserved_tck}]
set_false_path -from [get_clocks {clk_16mhz}] -to [get_clocks {refclk}]
set_false_path -from [get_clocks {clk_16mhz}] -to [get_clocks {pcie_sys_clk}]
set_false_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {pcie_sys_clk}]
set_false_path -from [get_clocks {pcie_sys_clk}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]
#set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe18|dffe19a*}]
#set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_qe9:dffpipe14|dffe15a*}]
set_false_path -to [get_keepers {*fifo_ram*}]
set_false_path -to [get_keepers {*~OBSERVABLEDPRIODISABLE*}]
set_false_path -to [get_keepers {*~OBSERVABLEDPRIOLOAD*}]
set_false_path -to [get_keepers {*~OBSERVABLERXDIGITALRESET*}]
set_false_path -to [get_keepers {*~OBSERVABLETXDIGITALRESET*}]
set_false_path -to [get_keepers {*~OBSERVABLE_DIGITAL_RESET*}]
set_false_path -from [get_keepers {*~ALTERA_DATA0*}]
set_false_path -to [get_keepers {*~ALTERA_DCLK*}]
set_false_path -to [get_keepers {*~ALTERA_SCE*}]
set_false_path -to [get_keepers {*~ALTERA_SDO*}]
set_false_path -from [get_clocks {clk_16mhz}] -to [get_ports {vme_sysclk}]
set_false_path -from [get_ports {hreset_n}]
set_false_path -from [get_keepers {porst_n}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
set_max_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|transmit_pcs0~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|transmit_pcs0~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|receive_pcs0~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|receive_pcs0~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|cent_unit0~OBSERVABLEDPRIODISABLE }] 20.000
set_max_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|cent_unit0~OBSERVABLERXDIGITALRESET }] 20.000
set_max_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|cent_unit0~OBSERVABLETXDIGITALRESET }] 20.000
set_max_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|cent_unit0~OBSERVABLEDPRIOLOAD }] 20.000
#**************************************************************
# Set Minimum Delay
#**************************************************************
set_min_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|transmit_pcs0~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|transmit_pcs0~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|receive_pcs0~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|receive_pcs0~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|cent_unit0~OBSERVABLEDPRIODISABLE }] 0.000
set_min_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|cent_unit0~OBSERVABLERXDIGITALRESET }] 0.000
set_min_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|cent_unit0~OBSERVABLETXDIGITALRESET }] 0.000
set_min_delay -to [get_ports { ip_16z091_01_top:pcie|Hard_IP_x4:\gen_x4:Hard_IP_x4_comp|Hard_IP_x4_serdes:serdes|Hard_IP_x4_serdes_alt_c3gxb_41f8:Hard_IP_x4_serdes_alt_c3gxb_41f8_component|cent_unit0~OBSERVABLEDPRIOLOAD }] 0.000
#**************************************************************
# Set Input Transition
#**************************************************************
#*******************************************************************************************************************************************
# set false path to signal tap instance
# will be ignored if signal tap is not included
#*******************************************************************************************************************************************
set_false_path -from * -to [get_registers sld*]
set_false_path -from [get_registers sld*] -to *
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/Manifest.py 0000664 0000000 0000000 00000000756 14574545710 0030621 0 ustar 00root root 0000000 0000000 # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
action = "synthesis"
syn_family = "Cyclone IV GX"
syn_device = "EP4CGX30"
syn_package = "CF23"
syn_grade = "I7"
syn_top = "A25_top"
syn_project = "A25_top"
syn_tool = "quartus"
target="altera"
quartus_preflow = "scripts/quartus_preflow.tcl"
quartus_postmodule = "scripts/gen_programming_files.tcl"
files = [
"A25_top.sdc",
]
modules = {
"local" : [
"../top/",
]
}
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/quartus.ini 0000664 0000000 0000000 00000000220 14574545710 0030670 0 ustar 00root root 0000000 0000000 # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
pgm_allow_epcs32=on
PGMIO_IGNORE_EPCS_ID_CHECK=1
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/scripts/ 0000775 0000000 0000000 00000000000 14574545710 0030160 5 ustar 00root root 0000000 0000000 gen_ip_cores.tcl 0000664 0000000 0000000 00000003110 14574545710 0033234 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/scripts # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
#
# Author: Grzegorz Daniluk
# Borrowed and adjusted from GSI bel-projects
proc qmegawiz {files} {
set dir [file dirname [info script]]
post_message "Testing for megawizard regeneration in $dir:$files"
set device [ get_global_assignment -name DEVICE ]
set family [ get_global_assignment -name FAMILY ]
foreach i $files {
if {![file exists "$dir/$i.qip"] || [file mtime "$dir/$i.txt"] > [file mtime "$dir/$i.qip"]} {
post_message -type info "Regenerating $i using qmegawiz"
file delete "$dir/$i.qip"
file copy -force "$dir/$i.txt" "$dir/$i.vhd"
set sf [open "| qmegawiz -silent \"-defaultfamily:$family\" \"-defaultdevice:$device\" OPTIONAL_FILES=SIM_NETLIST \"$dir/$i.vhd\" 2>@stderr" r]
while {[gets $sf line] >= 0} { post_message -type info "$line" }
if {[catch {close $sf} err]} {
post_message -type error "Executing qmegawiz: $err"
exit 1
}
if {![file exists "$dir/$i.qip"]} {
post_message -type error "Executing qmegawiz: did not create $dir/$i.qip!"
exit 1
}
file mtime "$dir/$i.qip" [file mtime "$dir/$i.vhd"]
}
set_global_assignment -name QIP_FILE "$dir/$i.qip"
}
}
source ../16z091-01_src/Source/x4/x4.tcl
source ../16z091-01_src/Source/alt_reconf/gen_alt_reconf.tcl
source ../top/pll_pcie/gen_pll_pcie.tcl
source ../16z126-01_src/Source/z126_01_pasmi/gen_m25p32.tcl
source ../16z126-01_src/Source/z126_01_ru/gen_ru.tcl
# Needed for testbench
source ../16z091-01_src/Source/x1/x1.tcl
gen_pin_assignments.tcl 0000664 0000000 0000000 00000024116 14574545710 0034643 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/scripts # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led_green_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led_red_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to sr_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vme_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vme_v2p_rstn
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to *z091_01_top*hip*core_clk_out
set_instance_assignment -name INPUT_TERMINATION OFF -to refclk
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio
set_location_assignment PIN_A10 -to vme_ds_oe
set_location_assignment PIN_A11 -to vme_bg_o_n[2]
set_location_assignment PIN_A12 -to vme_acfail_i_n
set_location_assignment PIN_A13 -to vme_br_i_n[1]
set_location_assignment PIN_A14 -to vme_a[19]
set_location_assignment PIN_A15 -to vme_a[16]
set_location_assignment PIN_A16 -to vme_irq_i_n[7]
set_location_assignment PIN_A17 -to vme_am_dir
set_location_assignment PIN_A18 -to vme_am[0]
set_location_assignment PIN_A19 -to vme_am[3]
set_location_assignment PIN_A1 -to fpga_test[2]
set_location_assignment PIN_A20 -to vme_iack_n
set_location_assignment PIN_A21 -to vme_irq_i_n[5]
set_location_assignment PIN_A22 -to vme_a[0]
set_location_assignment PIN_A2 -to fpga_test[1]
set_location_assignment PIN_A3 -to vme_d[0]
set_location_assignment PIN_A4 -to vme_d[2]
set_location_assignment PIN_A5 -to vme_dtack_i_n
set_location_assignment PIN_A6 -to vme_berr_o
set_location_assignment PIN_A7 -to vme_d[4]
set_location_assignment PIN_A8 -to vme_d[7]
set_location_assignment PIN_AA13 -to sr_a[0]
set_location_assignment PIN_AA15 -to sr_a[3]
set_location_assignment PIN_AA16 -to sr_a[5]
set_location_assignment PIN_AA18 -to sr_d[13]
set_location_assignment PIN_AA19 -to sr_d[11]
set_location_assignment PIN_AA20 -to sr_d[9]
set_location_assignment PIN_AA21 -to sr_a[7]
set_location_assignment PIN_AA22 -to vme_sysclk
set_location_assignment PIN_AA4 -to v2p_rstn
set_location_assignment PIN_AB10 -to sr_bwa_n
set_location_assignment PIN_AB11 -to sr_bwb_n
set_location_assignment PIN_AB13 -to sr_a[11]
set_location_assignment PIN_AB14 -to sr_a[1]
set_location_assignment PIN_AB15 -to sr_a[2]
set_location_assignment PIN_AB16 -to sr_a[4]
set_location_assignment PIN_AB17 -to sr_d[15]
set_location_assignment PIN_AB18 -to sr_d[14]
set_location_assignment PIN_AB19 -to sr_d[12]
set_location_assignment PIN_AB20 -to sr_d[10]
set_location_assignment PIN_AB21 -to sr_d[8]
set_location_assignment PIN_AB3 -to hreset_n
set_location_assignment PIN_AB4 -to vme_ga[0]
set_location_assignment PIN_AB5 -to vme_ga[1]
set_location_assignment PIN_AB6 -to vme_ga[2]
set_location_assignment PIN_AB7 -to vme_ga[3]
set_location_assignment PIN_AB8 -to vme_ga[4]
set_location_assignment PIN_AB9 -to vme_gap
set_location_assignment PIN_B10 -to vme_ds_o_n[0]
set_location_assignment PIN_B12 -to vme_br_i_n[2]
set_location_assignment PIN_B13 -to vme_a[22]
set_location_assignment PIN_B15 -to vme_a[17]
set_location_assignment PIN_B16 -to vme_as_o_n
set_location_assignment PIN_B18 -to vme_am[1]
set_location_assignment PIN_B19 -to vme_am_oe_n
set_location_assignment PIN_B1 -to fpga_test[3]
set_location_assignment PIN_B20 -to vme_irq_i_n[6]
set_location_assignment PIN_B21 -to vme_a[15]
set_location_assignment PIN_B22 -to vme_a[14]
set_location_assignment PIN_B3 -to vme_d[8]
set_location_assignment PIN_B4 -to vme_d[10]
set_location_assignment PIN_B6 -to vme_dtack_o
set_location_assignment PIN_B7 -to vme_d[13]
set_location_assignment PIN_C10 -to vme_bg_o_n[1]
set_location_assignment PIN_C11 -to vme_bg_o_n[0]
set_location_assignment PIN_C12 -to vme_iack_o_n
set_location_assignment PIN_C13 -to vme_br_i_n[3]
set_location_assignment PIN_C14 -to vme_a[21]
set_location_assignment PIN_C15 -to vme_a[18]
set_location_assignment PIN_C16 -to vme_as_i_n
set_location_assignment PIN_C19 -to vme_am[4]
set_location_assignment PIN_C1 -to fpga_test[5]
set_location_assignment PIN_C20 -to vme_a[7]
set_location_assignment PIN_C22 -to vme_a[5]
set_location_assignment PIN_C2 -to fpga_test[4]
set_location_assignment PIN_C3 -to vme_br_o[0]
set_location_assignment PIN_C4 -to vme_br_o[1]
set_location_assignment PIN_C5 -to vme_d[1]
set_location_assignment PIN_C6 -to vme_berr_i_n
set_location_assignment PIN_C7 -to vme_d[3]
set_location_assignment PIN_C8 -to vme_d[14]
set_location_assignment PIN_C9 -to vme_ds_o_n[1]
set_location_assignment PIN_D10 -to led_red_n
set_location_assignment PIN_D11 -to led_green_n
set_location_assignment PIN_D14 -to vme_a[23]
set_location_assignment PIN_D15 -to vme_a[20]
set_location_assignment PIN_D17 -to vme_am[5]
set_location_assignment PIN_D19 -to vme_irq_o[5]
set_location_assignment PIN_D20 -to vme_a[12]
set_location_assignment PIN_D21 -to vme_irq_i_n[4]
set_location_assignment PIN_D22 -to vme_irq_i_n[3]
set_location_assignment PIN_D4 -to vme_br_o[2]
set_location_assignment PIN_D5 -to vme_d[9]
set_location_assignment PIN_D6 -to vme_d[12]
set_location_assignment PIN_D7 -to vme_d[6]
set_location_assignment PIN_D8 -to vme_d[15]
set_location_assignment PIN_D9 -to vme_ds_i_n[0]
set_location_assignment PIN_E17 -to vme_write_n
set_location_assignment PIN_E20 -to vme_irq_o[4]
set_location_assignment PIN_E21 -to vme_irq_o[3]
set_location_assignment PIN_E22 -to vme_a[11]
set_location_assignment PIN_E5 -to vme_br_o[3]
set_location_assignment PIN_E6 -to vme_d[11]
set_location_assignment PIN_E8 -to vme_ds_i_n[1]
set_location_assignment PIN_F16 -to vme_irq_o[7]
set_location_assignment PIN_F17 -to vme_am[2]
set_location_assignment PIN_F18 -to vme_irq_o[6]
set_location_assignment PIN_F20 -to vme_a[10]
set_location_assignment PIN_F22 -to vme_a[3]
set_location_assignment PIN_F2 -to pcie_tx[3]
set_location_assignment PIN_F8 -to vme_d[5]
set_location_assignment PIN_G12 -to vme_bg_i_n[1]
set_location_assignment PIN_G14 -to vme_br_i_n[0]
set_location_assignment PIN_G15 -to vme_as_oe
set_location_assignment PIN_G16 -to vme_a[6]
set_location_assignment PIN_G17 -to vme_a[13]
set_location_assignment PIN_G19 -to vme_a[4]
set_location_assignment PIN_G20 -to vme_a[9]
set_location_assignment PIN_G21 -to vme_a[2]
set_location_assignment PIN_G22 -to vme_a[8]
set_location_assignment PIN_H12 -to vme_bg_o_n[3]
set_location_assignment PIN_H13 -to vme_bg_i_n[2]
set_location_assignment PIN_H14 -to vme_iack_i_n
set_location_assignment PIN_H20 -to vme_a[1]
set_location_assignment PIN_H21 -to vme_irq_i_n[2]
set_location_assignment PIN_H22 -to vme_irq_i_n[1]
set_location_assignment PIN_H2 -to pcie_rx[3]
set_location_assignment PIN_H9 -to sr_clk
set_location_assignment PIN_J13 -to vme_bg_i_n[0]
set_location_assignment PIN_J14 -to vme_bg_i_n[3]
set_location_assignment PIN_J19 -to vme_irq_o[2]
set_location_assignment PIN_J20 -to vme_irq_o[1]
set_location_assignment PIN_J21 -to vme_d[31]
set_location_assignment PIN_J22 -to vme_d[30]
set_location_assignment PIN_K19 -to vme_d[27]
set_location_assignment PIN_K20 -to vme_d[28]
set_location_assignment PIN_K22 -to vme_d[29]
set_location_assignment PIN_K2 -to pcie_tx[2]
set_location_assignment PIN_L13 -to vme_bclr_i_n
set_location_assignment PIN_L14 -to vme_bbsy_i_n
set_location_assignment PIN_L15 -to vme_d[24]
set_location_assignment PIN_L19 -to vme_d[26]
set_location_assignment PIN_L20 -to vme_d[25]
set_location_assignment PIN_M13 -to vme_bclr_o_n
set_location_assignment PIN_M17 -to vme_bbsy_o
set_location_assignment PIN_M18 -to vme_scon
set_location_assignment PIN_M19 -to vme_sysfail_o
set_location_assignment PIN_M22 -to clk_16mhz
set_location_assignment PIN_M2 -to pcie_rx[2]
set_location_assignment PIN_M7 -to refclk
set_location_assignment PIN_N17 -to vme_sysres_o
set_location_assignment PIN_N19 -to vme_d_dir
set_location_assignment PIN_N20 -to vme_d[22]
set_location_assignment PIN_N21 -to vme_d[23]
set_location_assignment PIN_N22 -to vme_retry_oe
set_location_assignment PIN_P13 -to vme_d[20]
set_location_assignment PIN_P14 -to vme_d[19]
set_location_assignment PIN_P22 -to vme_d[21]
set_location_assignment PIN_P2 -to pcie_tx[1]
set_location_assignment PIN_R13 -to sr_a[18]
set_location_assignment PIN_R14 -to sr_a[15]
set_location_assignment PIN_R16 -to vme_a[28]
set_location_assignment PIN_R17 -to vme_a_dir
set_location_assignment PIN_R19 -to vme_d_oe_n
set_location_assignment PIN_R20 -to vme_d[16]
set_location_assignment PIN_R21 -to vme_d[17]
set_location_assignment PIN_R22 -to vme_d[18]
set_location_assignment PIN_T13 -to sr_a[12]
set_location_assignment PIN_T14 -to sr_a[16]
set_location_assignment PIN_T17 -to sr_cs1_n
set_location_assignment PIN_T18 -to sr_adsc_n
set_location_assignment PIN_T19 -to vme_a_oe_n
set_location_assignment PIN_T20 -to vme_a[29]
set_location_assignment PIN_T21 -to vme_a[30]
set_location_assignment PIN_T22 -to vme_sysfail_i_n
set_location_assignment PIN_T2 -to pcie_rx[1]
set_location_assignment PIN_U14 -to sr_a[17]
set_location_assignment PIN_U15 -to sr_d[2]
set_location_assignment PIN_U20 -to vme_a[24]
set_location_assignment PIN_U22 -to vme_a[31]
set_location_assignment PIN_V20 -to vme_sysres_i_n
set_location_assignment PIN_V21 -to vme_a[26]
set_location_assignment PIN_V22 -to vme_a[27]
set_location_assignment PIN_V2 -to pcie_tx[0]
set_location_assignment PIN_W13 -to sr_a[13]
set_location_assignment PIN_W14 -to sr_d[1]
set_location_assignment PIN_W15 -to sr_d[3]
set_location_assignment PIN_W17 -to sr_d[6]
set_location_assignment PIN_W18 -to sr_a[10]
set_location_assignment PIN_W19 -to sr_a[8]
set_location_assignment PIN_W20 -to sr_oe_n
set_location_assignment PIN_W21 -to vme_retry_o_n
set_location_assignment PIN_W22 -to vme_a[25]
set_location_assignment PIN_Y13 -to sr_a[14]
set_location_assignment PIN_Y14 -to sr_d[0]
set_location_assignment PIN_Y15 -to sr_d[4]
set_location_assignment PIN_Y16 -to sr_d[5]
set_location_assignment PIN_Y17 -to sr_d[7]
set_location_assignment PIN_Y18 -to sr_a[9]
set_location_assignment PIN_Y19 -to sr_bw_n
set_location_assignment PIN_Y20 -to sr_a[6]
set_location_assignment PIN_Y22 -to vme_retry_i_n
set_location_assignment PIN_Y2 -to pcie_rx[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx[*]
set_instance_assignment -name IO_STANDARD "HCSL" -to refclk
gen_programming_files.tcl 0000664 0000000 0000000 00000023024 14574545710 0035143 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/scripts # SPDX-FileCopyrightText: 2014 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
##############################################################-
## File : gen_programming_files.tcl
## Author : Andreas Geissler
## Email : Andreas.Geissler@men.de
## Organization : MEN Mikroelektronik Nuernberg GmbH
## Created : 05/12/14
##############################################################-
## Description : This TCL script shall be used to generate
## all importen programming files for a Altera FPGA:
##
## *.rbf -> Raw binary file (compressed)
## *.bin -> Raw binary file with MEN Header (compressed)
## *.dedi -> Dediprog file (= *.rbf + *.bin)
## *.hex -> Intel HEX format file (= *.bin)
## *.sof -> Altera nonvolatile FPGA programming file
## *.jic -> Altera Flash FPGA programming file (depends on *.cof)
## *.jam -> STAPL format file (depends on *.jic)
##
##############################################################-
set module [lindex $quartus(args) 0]
# all paths are relative to the synthesis folder (for example "D:\work_16g216c01\HWARE\Artikel\16\16g216c01\ic001a\synthesis")
# project files and directories
#Path of the synthesis folder
variable PROJECT_SYNTHESIS "./"
#Name of the quartus project
variable PROJECT_FILE_NAME "A25_top"
#Name of the programming files which are generated
variable PROJECT_RELEASE_NAME "16A025-00_03_16"
#Folder of the programming files which are generated
variable PROJECT_RELEASE_FOLDER "./fpga_files/"
#Folder of the Quartus automatically generated programming files relative to the PROJECT_SYNTHESIS
#For quartus version < 14.0 the programming files are always in the synthesis folder
variable PROJECT_QUARTUS_PROG_DIR "./"
#For quartus version >= 14.0 the default path is "./output_files/"
#variable PROJECT_QUARTUS_PROG_DIR "./output_files/"
#Name of the converstion file to generate *.jic
variable COF_FILE_NAME "A25_top.cof"
# NOTE: the *.cof file can be generate with Quartus in menu -> File/Convert Programming Files...
# A *.cof file is need because quartus_cpf does not offere a console input for complex designs.
# Use the generated *.hex file for the FPGA Image with the MEN Header in Convert Programming File
# tool. For the FPGA Fallback Image the *.sof file shall be used (do not forget to enable the compression).
# project configurations
variable HWARE_BOARD_NAME "16A025-00"
variable DEVICE "EP4CGX30"
variable FLASH "EPCS32"
variable FPGA_IMAGE_OFFSET 200000
#8MByte Flash
variable FLASH_SIZE_IN_BYTE_HEX 800000
# program paths for Windows synthesis
# variable BIN2IHEX "../../software/tools/16t029-00_src/Bin/bin2ihex.exe"
# variable GENDEDIPROG "../../software/tools/16t032-00_src/Bin/genDediprog.exe"
#variable ALTERA_QUARTUS_CPF "$::env(QUARTUS_ROOTDIR)bin64/quartus_cpf.exe"
#variable FPGA_ADDHEADER "../../software/tools/16t036-00_src/Bin/fpga_addheader.exe"
# program paths for Linux synthesis
variable BIN2IHEX "../../software/tools/16t029-00_src/Bin/bin2ihex"
variable GENDEDIPROG "../../software/tools/16t032-00_src/Bin/genDediProg"
variable ALTERA_QUARTUS_CPF "$::env(QUARTUS_ROOTDIR)bin/quartus_cpf"
variable FPGA_ADDHEADER "../../software/tools/16t036-00_src/Bin/fpga_addheader"
if [string match "quartus_asm" $module] {
# include commands here that are run after the assember
post_message "+--------------------------------------------------------------+"
post_message "| Running after assembler..."
post_message "| now generating ${PROJECT_RELEASE_NAME}.jic automatically"
post_message "+--------------------------------------------------------------+"
# command run after the assember
post_message "Used QUARTUS: $::env(QUARTUS_ROOTDIR)"
post_message "Used quartus_cpf: ${ALTERA_QUARTUS_CPF}"
post_message "Used bin2ihex: ${BIN2IHEX}"
post_message "Used genDediprog: ${GENDEDIPROG}"
post_message "Used fpga_addheader: ${FPGA_ADDHEADER}"
# delete existing files
#--------------------------------------------
# delete *.jic file
if {[file exists ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.jic]} {
post_message "Delete existing ${PROJECT_QUARTUS_PROG_DIR}$PROJECT_FILE_NAME.jic"
file delete ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.jic
}
# delete *.jam file
if {[file exists ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.jam]} {
post_message "Delete existing ${PROJECT_QUARTUS_PROG_DIR}$PROJECT_FILE_NAME.jam"
file delete ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.jam
}
# delete Intel HEX file *.hex
if {[file exists ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.hex]} {
post_message "Delete existing ${PROJECT_QUARTUS_PROG_DIR}$PROJECT_FILE_NAME.hex"
file delete ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.hex
}
# delete binary file with MEN Header *.bin
if {[file exists ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.bin]} {
post_message "Delete existing ${PROJECT_QUARTUS_PROG_DIR}$PROJECT_FILE_NAME.bin"
file delete ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.bin
}
# delete binary file with MEN Header *.dedi
if {[file exists ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.dedi]} {
post_message "Delete existing ${PROJECT_QUARTUS_PROG_DIR}$PROJECT_FILE_NAME.dedi"
file delete ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.dedi
}
# create folders
#--------------------------------------------
# create release folder if it not exist
if {![file exists ${PROJECT_RELEASE_FOLDER}]} {
post_message "Create $PROJECT_RELEASE_FOLDER"
file mkdir ${PROJECT_RELEASE_FOLDER}
}
post_message "+-------------------------------+"
post_message "| Generate programming files:"
post_message "+-------------------------------+"
# bin file generation
#----------------------------------------------------------
post_message "Generate *.bin: "
post_message "----------------"
if { [catch {exec ${FPGA_ADDHEADER} -l ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.rbf ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.bin ${DEVICE} ${HWARE_BOARD_NAME} ${FPGA_IMAGE_OFFSET}} input] } {
return -code error $input
} else {
post_message $input
}
# hex file generation
#----------------------------------------------------------
post_message "Generate *.hex: "
post_message "----------------"
if { [catch {exec ${BIN2IHEX} -s -b ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.bin ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.hex} input] } {
return -code error $input
} else {
post_message $input
}
# Dediprog file generation
#----------------------------------------------------------
post_message "Generate *.dedi: "
post_message "-----------------"
if { [catch {exec ${GENDEDIPROG} -s -x=0xFF -o=0x${FPGA_IMAGE_OFFSET} -f=0x${FLASH_SIZE_IN_BYTE_HEX} ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.rbf ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.bin ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.dedi} input] } {
return -code error $input
} else {
post_message $input
}
################################################################################
# Please generate *.jic and *.jam manually. TCL script fails in Ubuntu Linux
# sue to libboost_system version incompatibility
################################################################################
# jic file generation
#----------------------------------------------------------
# post_message "Generate *.jic: "
# post_message "----------------"
#
# if { [catch {exec ${ALTERA_QUARTUS_CPF} -c ${PROJECT_SYNTHESIS}${COF_FILE_NAME}} input] } {
# return -code error $input
# } else {
# post_message $input
# }
#
# # jam file generation
# #----------------------------------------------------------
# post_message "Generate *.jam: "
# post_message "----------------"
#
# if { [catch {exec ${ALTERA_QUARTUS_CPF} -c ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.jic ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.jam} input] } {
# return -code error $input
# } else {
# post_message $input
# }
# rbf file generation
#----------------------------------------------------------
# quartus generates this file automatically from the *.sof file
# go to Quartus -> Assignments -> Device -> Device and Pin Options... -> Programming files and enable Raw Binary File (.rbf)
post_message "Copy programming files from Quartus synthesis: "
post_message "-----------------------------------------------"
file copy -force ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.rbf ${PROJECT_RELEASE_FOLDER}${PROJECT_RELEASE_NAME}.rbf
file copy -force ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.bin ${PROJECT_RELEASE_FOLDER}${PROJECT_RELEASE_NAME}.bin
file copy -force ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.dedi ${PROJECT_RELEASE_FOLDER}${PROJECT_RELEASE_NAME}.dedi
file copy -force ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.hex ${PROJECT_RELEASE_FOLDER}${PROJECT_RELEASE_NAME}.hex
file copy -force ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.sof ${PROJECT_RELEASE_FOLDER}${PROJECT_RELEASE_NAME}.sof
# file copy -force ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.jic ${PROJECT_RELEASE_FOLDER}${PROJECT_RELEASE_NAME}.jic
# file copy -force ${PROJECT_QUARTUS_PROG_DIR}${PROJECT_FILE_NAME}.jam ${PROJECT_RELEASE_FOLDER}${PROJECT_RELEASE_NAME}.jam
}
quartus_preflow.tcl 0000664 0000000 0000000 00000006770 14574545710 0034061 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/syn/scripts # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
# Load Quartus II Tcl Project package
package require ::quartus::project
# SCRIPT EXECUTION STARTS HERE
post_message "Executing A25 pre-flow script"
set project_name "A25_top"
set make_assignments 0
# Make sure that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) $project_name]} {
project_close
project_open -force $project_name
}
} else {
project_open -force $project_name
}
# project settings copied over from original A25 QSF file
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
set_global_assignment -name CRC_ERROR_CHECKING OFF
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name DEVICE_MIGRATION_LIST "EP4CGX30CF23I7,EP4CGX150CF23I7,EP4CGX75CF23I7,EP4CGX50CF23I7"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ""
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id refclk
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
source scripts/gen_ip_cores.tcl
source scripts/gen_pin_assignments.tcl
# Commit assignments
export_assignments
# SCRIPT EXECUTION ENDS HERE
post_message "A25 pre-flow script execution complete"
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/ 0000775 0000000 0000000 00000000000 14574545710 0027637 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/.gitignore0000664 0000000 0000000 00000001464 14574545710 0031634 0 ustar 00root root 0000000 0000000 # SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
# +---------------------------------------------------------------------------+
# | general ignore setup |
# +---------------------------------------------------------------------------+
# ignore temporary files from editor
*.bak
*.elc
*.swp
*.s
*.tmp
*.vhd.~y.yy~
*.vhd.~
*.old
# ignore editor configuration settings
Session.vim
tags
# ignore CVS directories if present
/**/CVS
# ignore ModelSim files
*.wlf
Simulation/modelsim.ini
# ignore all compiled simulation libraries
/Simulation/lib/*
/Simulation/wlf*
/Simulation/*transcript*
/Simulation/vsim*
/Simulation/pciebfm0*
/Simulation/transcript
/Simulation/test_report.txt
/Simulation/work/
/Simulation/a25.cr.mti
16x001-00_src/ 0000775 0000000 0000000 00000000000 14574545710 0031503 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench README.rst 0000664 0000000 0000000 00000021460 14574545710 0033175 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x001-00_src .. SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
..
.. SPDX-License-Identifier: CC-BY-SA-4.0+
+--------------------------------+
| 16x001-00 test bench framework |
+--------------------------------+
Description :
Simulation Model of a dynamic internal 64-bit wide RAM with wishbone slave interface for single and burst accesses.
Features:
1. Functions
This sim-model provides the following functions: conf_iram, wr_iram, rd_iram and deallocate_iram.
1.1 conf_iram: configure the following parameters: startdelay of address and data phase, waitstates of address and data
phase, break delay of address and data phase, enable external waitstate interface
1.2 wr_iram: write data directly to the IRAM (the wishbone interface will not be used).
1.3 rd_iram: read data directly from the IRAM (the wishbone interface will not be used).
1.4 deallocate_iram: free the memory of the IRAM (clear the whole content). The depth of the RAM is 0 afterwards.
2. Split transactions
The IRAM supports split transactions. Therefore the address phases and the dataphases are seperated (separate acknowledge for address
phase and for data phase). To use the IRAM for regular transactions (not split transactions) the address acknowledge shall be used as
acknowledge and all data waitstates have to be configured to 0.
3. External waitstate interface
When the external waitstate interface is enabled by the conf_iram function, the parameters for start delay, waitstates and break delay
are not considered. Instead the external waitstate interface is used in the following way.
3.1 Waitstate for one address / data phase are requested by the iram (*_ws_req = true).
3.2 Number of waitstates is provided to the IRAM (*_ws_in).
3.3 Waitstate is acknowledged to the IRAM (*_ws_ack = true).
3.4 Waitstate interface is reset (*_ws_req = false, *_ws_ack = false).
4. Internal waitstate generation
When the external waitstate interface is disabled by the conf_iram function, the parameters for start delay, waitstates and break delay
are considered for address and data acknowledge generation.
4.1 Address startdelay: The address startdelay is the amount of clock cycles from the time where wishbone strobe and cycle are both
be active till the first rising edge of the address acknowledge (this is usable for single as well as for
burst accesses). The value 0 is invalid for the address startdelay and will be treated as 1.
4.2 Address waitstates: The amount of address waitstates represents the amount of clock cycles between a falling edge of wishbone
address acknowledge and the rising edge of wishbone address acknowledge of the next data phase of a burst
(this is usable for burst accesses only).
4.3 Address break delay: The address break delay has two parameter for configuration: length and position. The position parameter
specifies the amount of dataphases (of a burst) where the break-delay shall appear. The length-parameter is
comparative with the waitstates (0 = break delay disabled). If the break-delay is enabled (break delay
length > 0) and appears within a burst, no additional waitstates will be produced (even if they are different
from 0).
4.4 Data startdelay: The data startdelay is the amount of clock cycles from the time where wishbone address acknowledge is active
for the first time till the first rising edge of the data acknowledge (this is usable for single as well as
for burst accesses). The value 0 is valid for the address startdelay.
4.5 Data waitstates: The amount of data waitstates represents the amount of clock cycles between a falling edge of wishbone data
acknowledge and the rising edge of wishbone data acknowledge of the next data phase of a burst (this is
usable for burst accesses only).
4.6 Data break delay: The address break delay has two parameter for configuration: length and position. The position parameter
specifies the amount of dataphases (of a burst) where the break-delay shall appear. The length-parameter is
comparative with the waitstates (0 = break delay disabled). If the break-delay is enabled (break delay
length > 0) and appears within a burst, no additional waitstates will be produced (even if they are different
from 0).
Generation of acknowledge:
external_ws
|
+------------+ |
| Address | +-----+ +-------------+
| Waitstate |------>| MUX |-------->| Address |-----+-------------------------------------------------------> aack
| Generation | | | | Acknowledge | |
+------------+ | | | Generation | |
| | +-------------+ |
ext. address waitstates ------>| | |
+-----+ | +-------------+
| | Data |
+-->| Phase |
| FIFO |
+-------------+
|
|
|
external_ws |
| | +-------------+
+------------+ | +->| Data |-----+------------------------> ack
| Data | +-----+ | Acknowledge | |
| Waitstates |------>| MUX |--------------------------------------->| Generation | |
| Generation | | | +-------------+ |
+------------+ | | |
| | | +-------------+
ext. data waitstates ------>| | +-------------+ +-->| Process |------> dat_o
+-----+ | Internal | | Data |
| Memory |<--------| Phase |<------ dat_i
| | +-------------+
+-------------+
Source/ 0000775 0000000 0000000 00000000000 14574545710 0032743 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x001-00_src iram32_pkg.vhd 0000664 0000000 0000000 00000050356 14574545710 0035415 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x001-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Wishbone RAM for simulation
-- Project : -
---------------------------------------------------------------
-- File : iram32_sim.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13.12.2007
---------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : -
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
-- iram32_sim.vhd
-- iram_pkg.vhd
---------------------------------------------------------------
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE work.print_pkg.all;
USE work.conversions.to_hex_str;
PACKAGE iram32_pkg IS
CONSTANT ADR_BITS : integer := 32;
CONSTANT DAT_BITS : integer := 32;
CONSTANT SEL_BITS : integer := DAT_BITS/8;
CONSTANT ACC_REQ_BUFFER_SIZE : integer:=1000;
CONSTANT WRDAT_BUFFER_SIZE : integer:=1000;
CONSTANT WRADR_BUFFER_SIZE : integer:=1000;
CONSTANT DISABLE_DATA_WAITSTATES_FOR_NON_SPLIT_TRANSACTION: boolean := TRUE;
TYPE iram32_in_type IS record
d_waitstates : integer; -- number of waitstates for data phases
d_startdelay : integer; -- number of additional waitstates for first data phase acknowledge (a_startdelay will be added)
d_break_delay_position : integer; -- number of data phases of one access after which the break delay appears
d_break_delay_length : integer; -- number of clock cycles as length of break delay
a_waitstates : integer; -- number of waitstates for address phases
a_startdelay : integer; -- number of additional waitstates for first address phase acknowledge
a_break_delay_position : integer; -- number of data phases of one access after which the break delay appears
a_break_delay_length : integer; -- number of clock cycles as length of break delay
config : boolean; -- enable iram configuration
err_answer : boolean; -- if true, requests will be answered with error
conf_req : boolean; -- changes on signal will call iram subfunctions
write_req : boolean; -- if TRUE during conf_req state changes, write request to iram is requested
-- if FALSE during conf_req state changes, read request from iram is requested
adr : std_logic_vector(ADR_BITS-1 DOWNTO 0); -- address for config read write access
wr_dat : std_logic_vector(DAT_BITS-1 DOWNTO 0); -- write data to iram
dealloc_iram : boolean; -- if TRUE during conf_req state changes, iram contents will be cleared
external_ws : boolean; -- if TRUE, external waitstate interface is used for generation of waitstates
-- if FALSE, iram parameters a_waitstates, a_startdelay, d_waitstates, d_startdelay,
-- break_delay_position, break_delay_lengthare used for generation of waitstates
END record;
TYPE iram32_out_type IS record
conf_ack : boolean; -- if conf_req has changed state, subfunction end will result in conf_ack state change
rd_dat : std_logic_vector(DAT_BITS-1 DOWNTO 0); -- read data to iram
END record;
TYPE iram32_acc_req_type IS record
we : std_logic;
adr : std_logic_vector(ADR_BITS-1 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
time_cnt : natural;
st_flag : boolean;
eob_flag : boolean;
END record;
TYPE iram32_acc_req_buffer IS array (0 TO ACC_REQ_BUFFER_SIZE-1) OF iram32_acc_req_type;
TYPE iram32_wrdat_type IS record
dat : std_logic_vector(DAT_BITS-1 DOWNTO 0);
sel : std_logic_vector((DAT_BITS/8)-1 DOWNTO 0);
END record;
TYPE iram32_wrdat_buffer IS array (0 TO ACC_REQ_BUFFER_SIZE-1) OF iram32_wrdat_type;
TYPE iram32_wradr_type IS record
adr : std_logic_vector(ADR_BITS-1 DOWNTO 0);
END record;
TYPE iram32_wradr_buffer IS array (0 TO ACC_REQ_BUFFER_SIZE-1) OF iram32_wradr_type;
TYPE iram32_mem_entry;
TYPE iram32_entry_ptr IS access iram32_mem_entry;
TYPE iram32_mem_entry IS record
address : integer;
data : std_logic_vector(DAT_BITS-1 DOWNTO 0);
nxt : iram32_entry_ptr;
END record;
TYPE iram32_head IS record
num_entries : integer;
list_ptr : iram32_entry_ptr;
END record;
TYPE iram32_head_ptr IS access iram32_head;
TYPE protected_shared_variable_natural IS protected
PROCEDURE set(value : natural);
impure FUNCTION get RETURN natural;
END protected protected_shared_variable_natural;
PROCEDURE incr( value : INOUT natural;
limit : IN natural;
wrap : IN boolean
) ;
CONSTANT WRAP_ON : boolean := TRUE;
CONSTANT WRAP_OFF: boolean := FALSE;
PROCEDURE gen_req(
SIGNAL req : OUT boolean;
SIGNAL ack : IN boolean
);
PROCEDURE gen_ack(
SIGNAL req : IN boolean;
SIGNAL ack : OUT boolean
);
PROCEDURE wr_data (
CONSTANT location : IN integer;
CONSTANT data : IN std_logic_vector(DAT_BITS-1 DOWNTO 0);
CONSTANT byte : IN std_logic_vector(SEL_BITS-1 DOWNTO 0);
VARIABLE first : INOUT iram32_head_ptr;
VARIABLE msg_on : IN boolean
);
PROCEDURE rd_data (
CONSTANT location : IN integer;
VARIABLE data : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0);
VARIABLE allocated : OUT boolean;
VARIABLE first : INOUT iram32_head_ptr;
VARIABLE msg_on : IN boolean
);
PROCEDURE dealloc_data (
VARIABLE first : INOUT iram32_head_ptr
) ;
PROCEDURE rd_iram ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
adr : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
dat : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0)
);
PROCEDURE wr_iram ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
adr : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
dat : IN std_logic_vector(DAT_BITS-1 DOWNTO 0)
) ;
PROCEDURE deallocate_iram (
SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type
) ;
PROCEDURE conf_iram32 ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
external_ws : IN boolean;
a_startdelay : IN integer;
a_waitstates : IN integer;
d_startdelay : IN integer;
d_waitstates : IN integer;
a_break_delay_pos : IN integer;
a_break_delay_len : IN integer;
d_break_delay_pos : IN integer;
d_break_delay_len : IN integer
);
END iram32_pkg;
PACKAGE BODY iram32_pkg IS
TYPE protected_shared_variable_natural IS protected BODY
VARIABLE stored: natural;
PROCEDURE set(value : natural) IS
BEGIN
stored := value;
END PROCEDURE set;
impure FUNCTION get RETURN natural IS
BEGIN
RETURN stored;
END FUNCTION get;
END protected BODY protected_shared_variable_natural;
--------------------------------------------------------------------------------------------
PROCEDURE incr( value : INOUT natural;
limit : IN natural;
wrap : IN boolean
) IS
BEGIN
IF value = limit-1 THEN
IF wrap THEN
value := 0;
END IF;
ELSE
value := value + 1;
END IF;
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE gen_req(
SIGNAL req : OUT boolean;
SIGNAL ack : IN boolean
) IS
BEGIN
IF ack /= FALSE THEN
WAIT until ack = FALSE;
END IF;
req <= TRUE;
WAIT until ack = TRUE;
req <= FALSE;
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE gen_ack(
SIGNAL req : IN boolean;
SIGNAL ack : OUT boolean
) IS
BEGIN
IF req /= TRUE THEN
WAIT until req = TRUE;
END IF;
ack <= TRUE;
WAIT until req = FALSE;
ack <= FALSE;
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE conf_iram32 ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
external_ws : IN boolean;
a_startdelay : IN integer;
a_waitstates : IN integer;
d_startdelay : IN integer;
d_waitstates : IN integer;
a_break_delay_pos : IN integer;
a_break_delay_len : IN integer;
d_break_delay_pos : IN integer;
d_break_delay_len : IN integer
) IS
BEGIN
IF iram_out.conf_ack /= FALSE THEN WAIT until iram_out.conf_ack = FALSE; END IF;
iram_in.write_req <= FALSE;
iram_in.adr <= (OTHERS => '0');
iram_in.config <= TRUE;
iram_in.a_startdelay <= a_startdelay;
iram_in.a_waitstates <= a_waitstates;
iram_in.d_startdelay <= d_startdelay;
iram_in.d_waitstates <= d_waitstates;
iram_in.a_break_delay_position <= a_break_delay_pos;
iram_in.a_break_delay_length <= a_break_delay_len;
iram_in.d_break_delay_position <= d_break_delay_pos;
iram_in.d_break_delay_length <= d_break_delay_len;
iram_in.external_ws <= external_ws;
iram_in.conf_req <= TRUE;
IF iram_out.conf_ack /= TRUE THEN
WAIT until iram_out.conf_ack = TRUE;
END IF;
iram_in.conf_req <= FALSE;
IF iram_out.conf_ack /= FALSE THEN
WAIT until iram_out.conf_ack = FALSE;
END IF;
iram_in.dealloc_iram <= FALSE;
iram_in.config <= FALSE;
WAIT FOR 1 us;
END PROCEDURE conf_iram32;
--------------------------------------------------------------------------------------------
PROCEDURE deallocate_iram (
SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type
) IS
BEGIN
IF iram_out.conf_ack /= FALSE THEN WAIT until iram_out.conf_ack = FALSE; END IF;
iram_in.write_req <= FALSE;
iram_in.wr_dat <= (OTHERS => '0');
iram_in.adr <= (OTHERS => '0');
iram_in.dealloc_iram <= TRUE;
iram_in.conf_req <= TRUE;
WAIT until iram_out.conf_ack = TRUE;
iram_in.conf_req <= FALSE;
WAIT until iram_out.conf_ack = FALSE;
iram_in.dealloc_iram <= FALSE;
END PROCEDURE deallocate_iram;
--------------------------------------------------------------------------------------------
PROCEDURE wr_iram ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
adr : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
dat : IN std_logic_vector(DAT_BITS-1 DOWNTO 0)
) IS
BEGIN
IF iram_out.conf_ack /= FALSE THEN WAIT until iram_out.conf_ack = FALSE; END IF;
iram_in.write_req <= TRUE;
iram_in.wr_dat <= dat;
iram_in.adr <= adr;
iram_in.conf_req <= TRUE;
WAIT until iram_out.conf_ack = TRUE;
iram_in.conf_req <= FALSE;
WAIT until iram_out.conf_ack = FALSE;
END PROCEDURE wr_iram;
--------------------------------------------------------------------------------------------
PROCEDURE rd_iram ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
adr : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
dat : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0)
) IS
BEGIN
IF iram_out.conf_ack /= FALSE THEN WAIT until iram_out.conf_ack = FALSE; END IF;
iram_in.write_req <= FALSE;
iram_in.adr <= adr;
iram_in.conf_req <= TRUE;
WAIT until iram_out.conf_ack = TRUE;
iram_in.conf_req <= FALSE;
WAIT until iram_out.conf_ack = FALSE;
dat := iram_out.rd_dat;
END PROCEDURE rd_iram;
--------------------------------------------------------------------------------------------
PROCEDURE wr_data (
CONSTANT location : IN integer;
CONSTANT data : IN std_logic_vector(DAT_BITS-1 DOWNTO 0);
CONSTANT byte : IN std_logic_vector(SEL_BITS-1 DOWNTO 0);
VARIABLE first : INOUT iram32_head_ptr;
VARIABLE msg_on : IN boolean
) IS
VARIABLE temp_ptr : iram32_entry_ptr;
VARIABLE new_ptr : iram32_entry_ptr;
VARIABLE prev_ptr : iram32_entry_ptr;
VARIABLE done : boolean:=FALSE;
VARIABLE long_location: integer;
BEGIN
done:= FALSE; -- set done to true when allocation occurs
long_location := location/((data'high+1)/8);
IF msg_on THEN
print_cycle(" IRAM - wr_data: ", CONV_STD_LOGIC_VECTOR(location, ADR_BITS), data, byte(3 DOWNTO 0), " ");
END IF;
IF first.num_entries = 0 THEN -- first access to memory
first.list_ptr := new iram32_mem_entry;
first.num_entries := 1;
first.list_ptr.address := long_location;
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
first.list_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
first.list_ptr.nxt := null;
done := TRUE;
ELSIF long_location < first.list_ptr.address THEN -- address is lowest value so far in allocation to put at head of list
new_ptr := new iram32_mem_entry;
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
new_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
new_ptr.nxt := first.list_ptr;
new_ptr.address := long_location;
first.list_ptr := new_ptr;
first.num_entries := first.num_entries + 1;
done := TRUE;
ELSE -- location must be >= first.list_ptr.address
temp_ptr := first.list_ptr;
while temp_ptr /= null AND NOT done LOOP
IF temp_ptr.address = long_location THEN -- address already allocated
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
temp_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
done := TRUE;
ELSIF temp_ptr.address > long_location THEN
new_ptr := new iram32_mem_entry;
new_ptr.address := long_location;
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
new_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
new_ptr.nxt := temp_ptr;
prev_ptr.nxt := new_ptr; -- break pointer chain and insert new_ptr
first.num_entries := first.num_entries + 1;
done := TRUE;
ELSE
prev_ptr := temp_ptr;
temp_ptr := temp_ptr.nxt;
END IF;
END LOOP;
IF NOT done THEN
new_ptr := new iram32_mem_entry;
new_ptr.address := long_location;
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
new_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
new_ptr.nxt := null; -- add new_ptr TO END OF chain
prev_ptr.nxt := new_ptr;
first.num_entries := first.num_entries + 1;
done := TRUE;
END IF;
END IF;
END wr_data;
--------------------------------------------------------------------------------------------
PROCEDURE rd_data (
CONSTANT location : IN integer;
VARIABLE data : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0);
VARIABLE allocated : OUT boolean;
VARIABLE first : INOUT iram32_head_ptr;
VARIABLE msg_on : IN boolean
) IS
VARIABLE temp_ptr : iram32_entry_ptr;
VARIABLE is_allocated : boolean;
VARIABLE data_int : std_logic_vector(data'range);
VARIABLE long_location: integer;
BEGIN
-- set allocated to true when read hits already allocated spot
is_allocated := FALSE;
long_location := location/((data'high+1)/8);
IF (first.list_ptr /= null AND first.num_entries /= 0 AND long_location >= first.list_ptr.address) THEN
temp_ptr := first.list_ptr;
while (temp_ptr /= null AND NOT is_allocated AND long_location >= temp_ptr.address) LOOP
IF temp_ptr.address = long_location THEN -- address has been allocated
data_int := temp_ptr.data;
is_allocated := TRUE;
ELSE
temp_ptr := temp_ptr.nxt;
END IF;
END LOOP;
END IF;
IF NOT is_allocated THEN
data_int := (data_int'range => '1');
END IF;
IF msg_on THEN
print_cycle(" IRAM - rd_data: ", CONV_STD_LOGIC_VECTOR(location, ADR_BITS), data_int, "1111", " ");
END IF;
allocated := is_allocated;
data := data_int;
END rd_data;
--------------------------------------------------------------------------------------------
PROCEDURE dealloc_data (
VARIABLE first : INOUT iram32_head_ptr
) IS
VARIABLE next_ptr : iram32_entry_ptr;
BEGIN
WHILE first.list_ptr.nxt /= NULL LOOP
next_ptr := first.list_ptr.nxt;
deallocate(first.list_ptr);
first.list_ptr := next_ptr;
END LOOP;
deallocate(first.list_ptr);
first.num_entries := 0;
END dealloc_data;
END;
iram32_sim.vhd 0000664 0000000 0000000 00000135664 14574545710 0035432 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x001-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Wishbone RAM for simulation
-- Project : -
---------------------------------------------------------------
-- File : iram32_sim.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13.12.2007
---------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : -
---------------------------------------------------------------
-- Description :
--
-- Simulation Model of a dynamic internal 64-bit wide RAM with wishbone slave interface for single and burst accesses.
--
-- Features:
-- 1. Functions
-- This sim-model provides the following functions: conf_iram, wr_iram, rd_iram and deallocate_iram.
-- 1.1 conf_iram: configure the following parameters: startdelay of address and data phase, waitstates of address and data
-- phase, break delay of address and data phase, enable external waitstate interface
-- 1.2 wr_iram: write data directly to the IRAM (the wishbone interface will not be used).
-- 1.3 rd_iram: read data directly from the IRAM (the wishbone interface will not be used).
-- 1.4 deallocate_iram: free the memory of the IRAM (clear the whole content). The depth of the RAM is 0 afterwards.
--
-- 2. Split transactions
-- The IRAM supports split transactions. Therefore the address phases and the dataphases are seperated (separate acknowledge for address
-- phase and for data phase). To use the IRAM for regular transactions (not split transactions) the address acknowledge shall be used as
-- acknowledge and all data waitstates have to be configured to 0.
--
-- 3. External waitstate interface
-- When the external waitstate interface is enabled by the conf_iram function, the parameters for start delay, waitstates and break delay
-- are not considered. Instead the external waitstate interface is used in the following way.
-- 3.1 Waitstate for one address / data phase are requested by the iram (*_ws_req = true).
-- 3.2 Number of waitstates is provided to the IRAM (*_ws_in).
-- 3.3 Waitstate is acknowledged to the IRAM (*_ws_ack = true).
-- 3.4 Waitstate interface is reset (*_ws_req = false, *_ws_ack = false).
--
-- 4. Internal waitstate generation
-- When the external waitstate interface is disabled by the conf_iram function, the parameters for start delay, waitstates and break delay
-- are considered for address and data acknowledge generation.
-- 4.1 Address startdelay: The address startdelay is the amount of clock cycles from the time where wishbone strobe and cycle are both
-- be active till the first rising edge of the address acknowledge (this is usable for single as well as for
-- burst accesses). The value 0 is invalid for the address startdelay and will be treated as 1.
-- 4.2 Address waitstates: The amount of address waitstates represents the amount of clock cycles between a falling edge of wishbone
-- address acknowledge and the rising edge of wishbone address acknowledge of the next data phase of a burst
-- (this is usable for burst accesses only).
-- 4.3 Address break delay: The address break delay has two parameter for configuration: length and position. The position parameter
-- specifies the amount of dataphases (of a burst) where the break-delay shall appear. The length-parameter is
-- comparative with the waitstates (0 = break delay disabled). If the break-delay is enabled (break delay
-- length > 0) and appears within a burst, no additional waitstates will be produced (even if they are different
-- from 0).
-- 4.4 Data startdelay: The data startdelay is the amount of clock cycles from the time where wishbone address acknowledge is active
-- for the first time till the first rising edge of the data acknowledge (this is usable for single as well as
-- for burst accesses). The value 0 is valid for the address startdelay.
-- 4.5 Data waitstates: The amount of data waitstates represents the amount of clock cycles between a falling edge of wishbone data
-- acknowledge and the rising edge of wishbone data acknowledge of the next data phase of a burst (this is
-- usable for burst accesses only).
-- 4.6 Data break delay: The address break delay has two parameter for configuration: length and position. The position parameter
-- specifies the amount of dataphases (of a burst) where the break-delay shall appear. The length-parameter is
-- comparative with the waitstates (0 = break delay disabled). If the break-delay is enabled (break delay
-- length > 0) and appears within a burst, no additional waitstates will be produced (even if they are different
-- from 0).
--
--
--
--
-- Generation of acknowledge:
--
-- external_ws
-- |
-- +------------+ |
-- | Address | +-----+ +-------------+
-- | Waitstate |------>| MUX |-------->| Address |-----+-------------------------------------------------------> aack
-- | Generation | | | | Acknowledge | |
-- +------------+ | | | Generation | |
-- | | +-------------+ |
-- ext. address waitstates ------>| | |
-- +-----+ | +-------------+
-- | | Data |
-- +-->| Phase |
-- | FIFO |
-- +-------------+
-- |
-- |
-- |
-- external_ws |
-- | | +-------------+
-- +------------+ | +->| Data |-----+------------------------> ack
-- | Data | +-----+ | Acknowledge | |
-- | Waitstates |------>| MUX |--------------------------------------->| Generation | |
-- | Generation | | | +-------------+ |
-- +------------+ | | |
-- | | | +-------------+
-- ext. data waitstates ------>| | +-------------+ +-->| Process |------> dat_o
-- +-----+ | Internal | | Data |
-- | Memory |<--------| Phase |<------ dat_i
-- | | +-------------+
-- +-------------+
--
--
--
---------------------------------------------------------------
-- Hierarchy:
--
-- iram32_sim.vhd
-- iram_pkg.vhd
---------------------------------------------------------------
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
USE ieee.std_logic_textio.all;
USE work.print_pkg.all;
USE work.conversions.to_hex_str;
USE work.iram32_pkg.all;
ENTITY iram32_sim IS
GENERIC (
rddata_sel : boolean := TRUE; -- use wishbone byte select signal for read data
wbname : string := "wbmon";
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100;
file_name : string :="iram.txt"
);
PORT (
iram_in : IN iram32_in_type;
iram_out : OUT iram32_out_type;
clk : IN std_logic;
rst : IN std_logic;
stb_i : IN std_logic;
ack_o : OUT std_logic;
aack_o : OUT std_logic;
err_o : OUT std_logic;
we_i : IN std_logic;
sel_i : IN std_logic_vector((DAT_BITS/8)-1 DOWNTO 0);
cti_i : IN std_logic_vector(2 DOWNTO 0);
bte_i : IN std_logic_vector(1 DOWNTO 0);
cyc_i : IN std_logic;
dat_o : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0);
dat_i : IN std_logic_vector(DAT_BITS-1 DOWNTO 0);
adr_i : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
a_ws_req : OUT boolean;
a_ws_ack : IN boolean;
a_ws_in : IN natural;
d_ws_req : OUT boolean;
d_ws_ack : IN boolean;
d_ws_in : IN natural
);
END iram32_sim;
ARCHITECTURE iram32_sim_arch OF iram32_sim IS
SIGNAL dat_o_int : std_logic_vector(dat_o'range);
SIGNAL ack_o_int : std_logic;
SIGNAL aack_o_int : std_logic;
SIGNAL err_o_int : std_logic;
SIGNAL conf_ack : boolean;
SIGNAL a_ws_req_int: boolean;
SIGNAL a_ws_ack_internal: boolean;
SIGNAL a_ws_ack_int: boolean;
SIGNAL a_ws_end_acc: boolean;
SIGNAL a_ws_int: natural;
SIGNAL a_ws_internal: natural;
SIGNAL d_ws_req_int: boolean;
SIGNAL d_ws_ack_internal: boolean;
SIGNAL d_ws_ack_int: boolean;
SIGNAL d_ws_end_acc: boolean;
SIGNAL d_ws_int: natural;
SIGNAL d_ws_internal: natural;
SIGNAL external_ws: boolean;
SIGNAL aack_enable : boolean;
shared VARIABLE a_sd_stored : protected_shared_variable_natural ;
shared VARIABLE a_ws_stored : protected_shared_variable_natural ;
shared VARIABLE d_sd_stored : protected_shared_variable_natural ;
shared VARIABLE d_ws_stored : protected_shared_variable_natural ;
shared VARIABLE a_bd_pos_stored : protected_shared_variable_natural ;
shared VARIABLE a_bd_len_stored : protected_shared_variable_natural ;
shared VARIABLE d_bd_pos_stored : protected_shared_variable_natural ;
shared VARIABLE d_bd_len_stored : protected_shared_variable_natural ;
CONSTANT DEBUG_MEM_ADR_PHASE : boolean := FALSE;
CONSTANT DEBUG_FIFO_ENTRY : boolean := FALSE;
CONSTANT DEBUG_MEM_DAT_PHASE : boolean := FALSE;
CONSTANT DEBUG_MEM_DATA : boolean := FALSE;
CONSTANT DEBUG_ACK_CHECK : boolean := FALSE;
SIGNAL err: std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL dbg_a_sd: integer := 0;
SIGNAL dbg_a_ws: integer := 0;
SIGNAL dbg_a_sd_valid: boolean := FALSE;
SIGNAL dbg_a_ws_valid: boolean := FALSE;
SIGNAL time_cnt_sig: natural := 0;
SIGNAL dgb_ack: std_logic;
SIGNAL dgb_ack_dut: std_logic;
SIGNAL dbg_a_ws_dat_cnt: integer := 0;
BEGIN
dat_o <= dat_o_int;
ack_o <= ack_o_int;
aack_o <= aack_o_int;
err_o <= err_o_int;
iram_out.conf_ack <= conf_ack;
----------------------------------------------------------------------------------------
-- map internal / external waitstate generation
----------------------------------------------------------------------------------------
a_ws_req <= a_ws_req_int WHEN external_ws ELSE FALSE;
a_ws_ack_int <= a_ws_ack WHEN external_ws ELSE a_ws_ack_internal;
a_ws_int <= a_ws_in WHEN external_ws ELSE a_ws_internal;
d_ws_req <= d_ws_req_int WHEN external_ws ELSE FALSE;
d_ws_ack_int <= d_ws_ack WHEN external_ws ELSE d_ws_ack_internal;
d_ws_int <= d_ws_in WHEN external_ws ELSE d_ws_internal;
----------------------------------------------------------------------------------------
-- internal address waitstate generation
----------------------------------------------------------------------------------------
address_waitstates: PROCESS
VARIABLE dat_cnt : natural;
BEGIN
dat_cnt := 0;
a_ws_ack_internal <= FALSE;
a_ws_internal <= 0;
LOOP
WAIT until a_ws_req_int'event;
IF a_ws_req_int'event AND a_ws_req_int AND NOT external_ws THEN
IF a_ws_end_acc THEN
dat_cnt := 0;
END IF;
IF dat_cnt = 0 THEN
a_ws_internal <= a_sd_stored.get;
ELSIF dat_cnt = a_bd_pos_stored.get AND a_bd_pos_stored.get > 0 AND a_bd_len_stored.get > 0 THEN
a_ws_internal <= a_bd_len_stored.get;
ELSE
a_ws_internal <= a_ws_stored.get;
END IF;
dat_cnt := dat_cnt + 1;
gen_ack(a_ws_req_int, a_ws_ack_internal);
END IF;
dbg_a_ws_dat_cnt <= dat_cnt;
END LOOP;
END PROCESS;
----------------------------------------------------------------------------------------
-- internal data waitstate generation
----------------------------------------------------------------------------------------
data_waitstates: PROCESS
VARIABLE dat_cnt : natural;
BEGIN
dat_cnt := 0;
d_ws_ack_internal <= FALSE;
d_ws_internal <= 0;
LOOP
WAIT until d_ws_req_int'event;
IF d_ws_end_acc THEN
dat_cnt := 0;
END IF;
IF d_ws_req_int'event AND d_ws_req_int AND NOT external_ws THEN
IF dat_cnt = 0 THEN
d_ws_internal <= d_sd_stored.get;
ELSIF dat_cnt = d_bd_pos_stored.get AND d_bd_pos_stored.get > 0 AND d_bd_len_stored.get > 0 THEN
d_ws_internal <= d_bd_len_stored.get;
ELSE
d_ws_internal <= d_ws_stored.get;
END IF;
dat_cnt := dat_cnt + 1;
gen_ack(d_ws_req_int, d_ws_ack_internal);
END IF;
END LOOP;
END PROCESS;
----------------------------------------------------------------------------------------
-- main
----------------------------------------------------------------------------------------
PROCESS
VARIABLE data : std_logic_vector(dat_o'range);
VARIABLE astart_done, dstart_done :boolean;
VARIABLE mem_head : iram32_head_ptr;
VARIABLE allocated : boolean;
VARIABLE acc_req_buf : iram32_acc_req_buffer;
VARIABLE acc_req_wrptr : integer:=0;
VARIABLE acc_req_rdptr : integer:=0;
VARIABLE wradr_buf : iram32_wradr_buffer;
VARIABLE wradr_wrptr : integer:=0;
VARIABLE wradr_rdptr : integer:=0;
VARIABLE wrdat_buf : iram32_wrdat_buffer;
VARIABLE wrdat_wrptr : integer:=0;
VARIABLE wrdat_rdptr : integer:=0;
VARIABLE msg_rd : boolean := FALSE;
VARIABLE msg_wr : boolean := FALSE;
VARIABLE conf_ack_int : boolean;
VARIABLE a_ws_cnt : integer := 0;
VARIABLE d_ws_cnt : integer := 0;
VARIABLE temp_stb_i : std_logic;
VARIABLE temp_ack_o : std_logic;
VARIABLE temp_aack_o : std_logic;
VARIABLE temp_err_o : std_logic;
VARIABLE temp_we_i : std_logic;
VARIABLE temp_sel_i : std_logic_vector(sel_i'range);
VARIABLE temp_cti_i : std_logic_vector(cti_i'range);
VARIABLE temp_bte_i : std_logic_vector(bte_i'range);
VARIABLE temp_cyc_i : std_logic;
VARIABLE temp_dat_o : std_logic_vector(dat_o'range);
VARIABLE temp_dat_i : std_logic_vector(dat_i'range);
VARIABLE temp_adr_i : std_logic_vector(adr_i'range);
VARIABLE aack_o_int_var : std_logic;
VARIABLE ack_o_int_var : std_logic;
VARIABLE adr_int_read : std_logic_vector(adr_i'range);
VARIABLE acc_running : boolean;
VARIABLE time_cnt_var: natural := 0;
VARIABLE st_flag : boolean;
VARIABLE rising_edge_clk: boolean;
BEGIN
mem_head := new iram32_head'(0,null);
IF sets(0) = '1' THEN
msg_rd := TRUE;
msg_wr := TRUE;
END IF;
ack_o_int <= '0';
aack_o_int <= '0';
err_o_int <= '0';
dat_o_int <= (OTHERS => '0');
conf_ack <= iram_in.conf_req;
iram_out.rd_dat <= (OTHERS => '0');
a_ws_req_int <= FALSE;
a_ws_end_acc <= FALSE;
d_ws_req_int <= FALSE;
d_ws_end_acc <= FALSE;
acc_running := FALSE;
acc_req_wrptr := 0;
acc_req_rdptr := 0;
wradr_wrptr := 0;
wradr_rdptr := 0;
wrdat_wrptr := 0;
wrdat_rdptr := 0;
a_ws_cnt := 0;
d_ws_cnt := 0;
astart_done := FALSE;
dstart_done := FALSE;
conf_ack_int := FALSE;
WAIT until rising_edge(clk) AND rst = '0'; -- wait until bus has initialized
a_ws_cnt := 0;
gen_loop: LOOP
-- access running indication (used to delay config accesses when whishbone access is being performed)
IF acc_req_wrptr /= acc_req_rdptr OR (temp_stb_i = '1' AND temp_cyc_i = '1') THEN
acc_running := TRUE;
ELSE
acc_running := FALSE;
END IF;
rising_edge_clk := FALSE;
IF rising_edge(clk) THEN
WAIT FOR 1 ps;
-- store Wishbone signals at delayed rising edge of clk
temp_stb_i := stb_i ;
temp_ack_o := ack_o_int ;
temp_aack_o := aack_o_int ;
temp_err_o := err_o_int ;
temp_we_i := we_i ;
temp_sel_i := sel_i ;
temp_cti_i := cti_i ;
temp_bte_i := bte_i ;
temp_cyc_i := cyc_i ;
temp_dat_o := dat_o_int ;
temp_dat_i := dat_i ;
temp_adr_i := adr_i ;
rising_edge_clk := TRUE;
END IF;
--**************************************************************************************
-- Config Access
--
-- Wait until running accesses have finished and handle config request.
--**************************************************************************************
IF iram_in.conf_req = TRUE AND conf_ack_int = FALSE AND acc_running = FALSE THEN -- config access is only performed when no access is running
IF iram_in.config = TRUE THEN
a_sd_stored.set(iram_in.a_startdelay);
a_ws_stored.set(iram_in.a_waitstates);
d_sd_stored.set(iram_in.d_startdelay);
d_ws_stored.set(iram_in.d_waitstates);
a_bd_pos_stored.set(iram_in.a_break_delay_position);
a_bd_len_stored.set(iram_in.a_break_delay_length);
d_bd_pos_stored.set(iram_in.d_break_delay_position);
d_bd_len_stored.set(iram_in.d_break_delay_length);
external_ws <= iram_in.external_ws;
ELSIF iram_in.write_req = TRUE THEN
-- write to iram
wr_data(to_integer(signed(iram_in.adr)), iram_in.wr_dat, "1111", mem_head, msg_wr);
ELSE
-- read from iram
rd_data(to_integer(signed(iram_in.adr)), data, allocated, mem_head, msg_rd);
iram_out.rd_dat <= data;
END IF;
conf_ack_int := TRUE; -- handshake acknowledge
conf_ack <= conf_ack_int;
WAIT until iram_in.conf_req = FALSE;
conf_ack_int := FALSE; -- handshake acknowledge
conf_ack <= conf_ack_int;
END IF;
IF rising_edge_clk THEN
time_cnt_var := time_cnt_var + 1;
--**************************************************************************************
-- Wishbone Access
--
--**************************************************************************************
IF temp_stb_i = '1' AND temp_cyc_i = '1' THEN
--**************************************************************************************
-- Generate Address Acknowledge
--
-- Detect start of Wishbone access. Request waitstates for the current data phase.
-- Generate address acknowledge after the waitstates have been processed.
-- Indicate the end of an access to the address waitstate generation engine.
--**************************************************************************************
IF temp_we_i = '0' OR (temp_we_i = '1' AND acc_req_wrptr = acc_req_rdptr) THEN
IF NOT astart_done THEN -- detected start of burst
IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 1: first address phase detected" SEVERITY NOTE; END IF;
astart_done := TRUE; -- mark start of burst as done
gen_req(a_ws_req_int, a_ws_ack_int); -- get address waitstates
a_ws_end_acc <= FALSE; -- acknowledged by gen_req()
a_ws_cnt := 0; -- set address waitstate counter
adr_int_read := temp_adr_i; -- store address because internally incremented
IF temp_cti_i = "001" OR temp_cti_i = "011" THEN
st_flag := TRUE;
ELSE
st_flag := FALSE;
END IF;
ELSIF temp_aack_o = '1' THEN -- end of burst and acknowledge was set for the last clock cycle
IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 2: address phase finished" SEVERITY NOTE; END IF;
gen_req(a_ws_req_int, a_ws_ack_int); -- get address waitstates
-- a_ws_end_acc <= FALSE; -- acknowledged by gen_req()
a_ws_cnt := 0; -- set address waitstate counter
ELSE -- insert waitstate
IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 5: ELSE" SEVERITY NOTE; END IF;
IF a_ws_cnt < a_ws_int THEN
a_ws_cnt := a_ws_cnt + 1; -- increment waitstate counter
END IF;
END IF;
END IF;
END IF;
--IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 8: a_ws_cnt=" & integer'image(a_ws_cnt) & " a_ws_int=" & integer'image(a_ws_int) SEVERITY NOTE; END IF;
IF astart_done AND a_ws_cnt >= a_ws_int THEN
aack_o_int_var := '1';
ELSE
aack_o_int_var := '0';
END IF;
-- handle end of access for address phase
IF temp_stb_i = '0' OR temp_cyc_i = '0' THEN -- previous clock cycle was idle
astart_done := FALSE;
a_ws_end_acc <= TRUE;
--IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 6: set astart_done=false" SEVERITY NOTE; END IF;
ELSIF temp_stb_i = '1' AND temp_cyc_i = '1'AND aack_o_int_var = '1' AND (temp_cti_i = "000" OR temp_cti_i = "111" OR temp_cti_i = "001") THEN -- clock cycle is access and last data phase
astart_done := FALSE;
a_ws_end_acc <= TRUE;
--IF DEBUG_MEM_ADR_PHASE THEN REPORT "DEBUG_MEM_ADR_PHASE 7: set astart_done=false" SEVERITY NOTE; END IF;
END IF;
aack_o_int <= aack_o_int_var;
--**************************************************************************************
-- Store address phase into data phase FIFO
--
-- Store the current address phase.
--**************************************************************************************
IF aack_o_int_var = '1' THEN
IF temp_we_i = '1' THEN -- store address phase in FIFO in case of address acknowledge (write access)
-- store address phase to WRADR FIFO
IF DEBUG_FIFO_ENTRY THEN REPORT "DEBUG_FIFO_ENTRY 1: write: address phase = " & to_hex_str(adr_int_read) SEVERITY NOTE; END IF;
wradr_buf(wradr_wrptr).adr := adr_int_read;
incr(wradr_wrptr, WRDAT_BUFFER_SIZE, WRAP_ON);
END IF;
IF temp_we_i = '1' AND DEBUG_FIFO_ENTRY THEN REPORT "DEBUG_FIFO_ENTRY 2: write to adr_int_read = " & to_hex_str(adr_int_read) SEVERITY NOTE;
ELSIF DEBUG_FIFO_ENTRY THEN REPORT "DEBUG_FIFO_ENTRY 3: read from adr_int_read = " & to_hex_str(adr_int_read) SEVERITY NOTE;
END IF;
acc_req_buf(acc_req_wrptr).we := temp_we_i;
acc_req_buf(acc_req_wrptr).adr := adr_int_read;
acc_req_buf(acc_req_wrptr).cti := temp_cti_i;
acc_req_buf(acc_req_wrptr).eob_flag := FALSE; -- not end of burst delimiter
acc_req_buf(acc_req_wrptr).st_flag := st_flag;
acc_req_buf(acc_req_wrptr).time_cnt := time_cnt_var;
incr(acc_req_wrptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
IF DAT_BITS = 64 THEN
IF temp_cti_i = "011" AND adr_int_read(4 DOWNTO 3) = "11" THEN -- current address is stored for Linear Incrementing / Cache Line Wrap Burst
adr_int_read := std_logic_vector(unsigned(adr_int_read) - 3*8);
ELSE
adr_int_read := std_logic_vector(unsigned(adr_int_read) + 8);
END IF;
ELSIF DAT_BITS = 32 THEN
IF temp_cti_i = "011" AND adr_int_read(3 DOWNTO 2) = "11" THEN -- current address is stored for Linear Incrementing / Cache Line Wrap Burst
adr_int_read := std_logic_vector(unsigned(adr_int_read) - 3*4);
ELSE
adr_int_read := std_logic_vector(unsigned(adr_int_read) + 4);
END IF;
ELSE
REPORT "WRONG DATA WIDTH " SEVERITY NOTE;
END IF;
END IF;
--**************************************************************************************
-- Store end of access delimiter into data phase FIFO
--
-- Store a delimiter entry into data phase FIFO after the last address phases of an access
-- was stored.
--**************************************************************************************
IF aack_o_int_var = '1' AND (temp_cti_i = "000" OR temp_cti_i = "111" OR temp_cti_i = "001") THEN -- end of burst has been reached -> store delimiter
IF DEBUG_FIFO_ENTRY THEN REPORT "DEBUG_FIFO_ENTRY 1: write eob " SEVERITY NOTE; END IF;
acc_req_buf(acc_req_wrptr).we := '0';
acc_req_buf(acc_req_wrptr).adr := adr_int_read;
acc_req_buf(acc_req_wrptr).cti := temp_cti_i;
acc_req_buf(acc_req_wrptr).eob_flag := TRUE; -- end of burst delimiter
acc_req_buf(acc_req_wrptr).st_flag := FALSE;
acc_req_buf(acc_req_wrptr).time_cnt := time_cnt_var;
incr(acc_req_wrptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
END IF;
--**************************************************************************************
-- Handle end of access delimiter
--
-- Read all delimers out of data phase FIFO. Set the generation of data acknowledges to
-- an initial state.
--**************************************************************************************
while acc_req_wrptr /= acc_req_rdptr AND acc_req_buf(acc_req_rdptr).eob_flag LOOP -- special buffer entry: end of burst
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 1: eob_flag" SEVERITY NOTE; END IF;
d_ws_end_acc <= TRUE; -- set flag d_ws_end_acc (reset automatic waitstate generation)
dstart_done := FALSE; -- indicate start of read burst is not handled yet
incr(acc_req_rdptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
END LOOP;
--**************************************************************************************
-- Generate Data Acknowledge
--
-- Read data phases out of data phase FIFO. Request waitstates for the current data phase.
-- Generate data acknowledge after the waitstates have been processed.
-- Indicate the end of an access to the data waitstate generation engine.
--**************************************************************************************
ack_o_int_var := '0';
IF acc_req_wrptr /= acc_req_rdptr THEN
-- write access (any data phase)
IF acc_req_buf(acc_req_rdptr).we = '1' THEN
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 2: write: ack of write access (d_ws_int = 0)" SEVERITY NOTE; END IF;
dstart_done := TRUE; -- indicate start of access was handled
gen_req(d_ws_req_int, d_ws_ack_int); -- get waitstates
d_ws_end_acc <= FALSE;
d_ws_cnt := d_ws_int; -- set waitstate counter to immediately generate the acknowledge (no waitstates for write access)
-- read access (first or following data phase)
ELSIF dstart_done = FALSE OR d_ws_cnt >= d_ws_int THEN
gen_req(d_ws_req_int, d_ws_ack_int); -- get waitstates
d_ws_end_acc <= FALSE;
IF acc_req_buf(acc_req_rdptr).st_flag = TRUE THEN
d_ws_cnt := 0; -- enable data waitstates for split transaction
ELSE
d_ws_cnt := d_ws_int; -- disable data waitstates for non-split transaction
END IF;
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 3: read: dstart_done=" & boolean'image(dstart_done) & " d_ws_cnt=" & integer'image(d_ws_cnt) & ", d_ws_int=" & integer'image(d_ws_int) SEVERITY NOTE; END IF;
-- ensure that data startdelay is hold
IF dstart_done = FALSE THEN
WHILE acc_req_buf(acc_req_rdptr).time_cnt /= time_cnt_var LOOP
d_ws_cnt := d_ws_cnt + 1;
acc_req_buf(acc_req_rdptr).time_cnt := acc_req_buf(acc_req_rdptr).time_cnt + 1;
END LOOP;
END IF;
dstart_done := TRUE; -- indicate start of access was handled
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 3a: read: d_ws_cnt=" & integer'image(d_ws_cnt) & ", d_ws_int=" & integer'image(d_ws_int) SEVERITY NOTE; END IF;
-- insert waitstates for read access
ELSE
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 4: ELSE" SEVERITY NOTE; END IF;
IF d_ws_cnt < d_ws_int THEN
d_ws_cnt := d_ws_cnt + 1; -- increment waitstate counter
END IF;
END IF;
END IF;
-- set data acknowledge in case all waitstates have been processed
IF dstart_done AND d_ws_cnt >= d_ws_int AND acc_req_wrptr /= acc_req_rdptr THEN
ack_o_int_var := '1';
ELSE
ack_o_int_var := '0';
END IF;
--**************************************************************************************
-- Process Data Phase
--
-- Handle the current data phase when the data acknowledge is set. For write accesses
-- write the input data of Wishbone bus to internal memory For read accesses perform a
-- read access to internal memory and output the read data on Wishbone interface.
--**************************************************************************************
IF ack_o_int_var = '1' THEN
IF acc_req_buf(acc_req_rdptr).we = '0' THEN
IF DEBUG_MEM_DATA THEN REPORT "DEBUG_MEM_DATA 1: read data from address " & to_hex_str(acc_req_buf(acc_req_rdptr).adr) SEVERITY NOTE; END IF;
rd_data(to_integer(signed(acc_req_buf(acc_req_rdptr).adr)), data, allocated, mem_head, msg_rd);
dat_o_int <= (OTHERS => '0');
IF rddata_sel THEN
FOR i IN temp_sel_i'low TO temp_sel_i'high LOOP
IF temp_sel_i(i) = '1' THEN
dat_o_int(i*8+7 DOWNTO i*8) <= data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
ELSE
dat_o_int <= data;
END IF;
ELSE
wr_data(to_integer(signed(acc_req_buf(acc_req_rdptr).adr)), temp_dat_i, temp_sel_i, mem_head, msg_wr);
END IF;
incr(acc_req_rdptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
END IF;
ack_o_int <= ack_o_int_var;
--**************************************************************************************
-- Handle end of access delimiter (second time - if more access delimiters are stored
-- after end of access)
--
-- Read all delimers out of data phase FIFO. Set the generation of data acknowledges to
-- an initial state.
--**************************************************************************************
while acc_req_wrptr /= acc_req_rdptr AND acc_req_buf(acc_req_rdptr).eob_flag LOOP -- special buffer entry: end of burst
IF DEBUG_MEM_DAT_PHASE THEN REPORT "DEBUG_MEM_DAT_PHASE 1: eob_flag" SEVERITY NOTE; END IF;
d_ws_end_acc <= TRUE; -- set flag d_ws_end_acc (reset automatic waitstate generation)
dstart_done := FALSE; -- indicate start of read burst is not handled yet
incr(acc_req_rdptr, ACC_REQ_BUFFER_SIZE, WRAP_ON);
END LOOP;
END IF;
IF rst /= '1' THEN
WAIT until rising_edge(clk) OR iram_in.conf_req'event OR rst = '1';
END IF;
IF rst = '1' THEN
exit gen_loop;
END IF;
END LOOP gen_loop;
END PROCESS;
--**************************************************************************************
-- Acknowledge Check
--
-- Check address acknowledge: detect startdelay and waitstates and check against the
-- IRAM configuration
-- Check data acknowledge : use IRAM configuration to generate a reference acknowledge
-- and check against data acknowledge of IRAM model
--
-- Note: The acknowledge check is disabled for external waitstates and break delay.
--**************************************************************************************
PROCESS
BEGIN
WAIT until unsigned(err) /= 0;
WAIT until rising_edge(clk);
WAIT until rising_edge(clk);
WAIT until rising_edge(clk);
WAIT until rising_edge(clk);
WAIT until rising_edge(clk);
REPORT "IRAM: END ON ERROR" SEVERITY failure;
END PROCESS;
PROCESS
VARIABLE time_cnt: natural := 0;
CONSTANT ACK_ARRAY_SIZE: natural := 100;
TYPE ack_array_type IS array (ACK_ARRAY_SIZE-1 DOWNTO 0) OF natural;
VARIABLE ack_array: ack_array_type;
VARIABLE ack_array_wrptr: natural;
VARIABLE ack_array_rdptr: natural;
VARIABLE ack_array_last_entry: natural;
VARIABLE first_adr_phase: boolean := TRUE;
VARIABLE a_ws: integer := 0;
VARIABLE a_ws_cnt: integer := 0;
VARIABLE dbg_d_sd_stored: integer;
VARIABLE dbg_d_ws_stored: integer;
VARIABLE st_flag: boolean;
VARIABLE disable: boolean := FALSE;
VARIABLE st_rd_access: boolean;
VARIABLE st_rd_access_q: boolean;
BEGIN
-- initialize aack array
FOR i1 IN ACK_ARRAY_SIZE-1 DOWNTO 0 LOOP
ack_array(i1) := 0;
END LOOP;
ack_array_rdptr := 0;
ack_array_wrptr := 0;
LOOP
WAIT until rising_edge(clk) OR (iram_in.conf_req'event AND iram_in.conf_req = FALSE);
dbg_a_sd_valid <= FALSE;
dbg_a_ws_valid <= FALSE;
IF iram_in.conf_req'event AND iram_in.conf_req = FALSE THEN
dbg_d_sd_stored := iram_in.d_startdelay;
dbg_d_ws_stored := iram_in.d_waitstates;
IF iram_in.d_break_delay_length /= 0 OR
iram_in.d_break_delay_position /= 0 OR
iram_in.a_break_delay_length /= 0 OR
iram_in.a_break_delay_position /= 0 OR
iram_in.external_ws /= FALSE THEN
disable := TRUE;
ELSE
disable := FALSE;
END IF;
END IF;
IF rising_edge(clk) AND NOT disable THEN
dgb_ack_dut <= ack_o_int;
-- check detect aack and store expected ack in FIFO
-- detect address phases
IF stb_i = '1' AND cyc_i = '1' THEN
IF aack_o_int = '1' AND first_adr_phase = TRUE THEN
IF DEBUG_ACK_CHECK THEN print_now("IRAM DEBUG: first address phase with aack=1, a_ws=" & integer'image(a_ws)); END IF;
first_adr_phase := FALSE;
st_rd_access_q := st_rd_access;
IF (cti_i = "011" OR cti_i = "001") AND we_i = '0' THEN
st_rd_access := TRUE;
ELSE
st_rd_access := FALSE;
END IF;
dbg_a_sd <= a_ws_cnt;
IF st_rd_access_q = TRUE AND we_i = '1' THEN
dbg_a_sd_valid <= FALSE;
ELSE
dbg_a_sd_valid <= TRUE;
END IF;
IF cti_i = "001" OR cti_i = "011" THEN
st_flag := TRUE;
ELSE
st_flag := FALSE;
END IF;
IF we_i = '1' OR st_flag = FALSE THEN
ack_array(ack_array_wrptr) := time_cnt;
ELSE
ack_array(ack_array_wrptr) := time_cnt + dbg_d_sd_stored;
ack_array_last_entry := ack_array(ack_array_wrptr);
END IF;
IF ack_array_wrptr = ACK_ARRAY_SIZE-1 THEN
ack_array_wrptr := 0;
ELSE
ack_array_wrptr := ack_array_wrptr + 1;
END IF;
IF ack_array_wrptr = ack_array_rdptr THEN REPORT "FATAL ERROR: ack_array overflow" SEVERITY failure; END IF;
ELSIF aack_o_int = '1' THEN
IF DEBUG_ACK_CHECK THEN print_now("IRAM DEBUG: address phase: cti=0b010, a_ws=" & integer'image(a_ws)); END IF;
dbg_a_ws <= a_ws_cnt;
dbg_a_ws_valid <= TRUE;
IF we_i = '1' OR st_flag = FALSE THEN
ack_array(ack_array_wrptr) := time_cnt;
ELSE
IF time_cnt > ack_array_last_entry+1 THEN
ack_array(ack_array_wrptr) := time_cnt + dbg_d_ws_stored;
ELSE
ack_array(ack_array_wrptr) := ack_array_last_entry+1 + dbg_d_ws_stored;
END IF;
END IF;
ack_array_last_entry := ack_array(ack_array_wrptr);
IF ack_array_wrptr = ACK_ARRAY_SIZE-1 THEN
ack_array_wrptr := 0;
ELSE
ack_array_wrptr := ack_array_wrptr + 1;
END IF;
IF ack_array_wrptr = ack_array_rdptr THEN REPORT "FATAL ERROR: ack_array overflow" SEVERITY failure; END IF;
ELSIF aack_o_int = '0' THEN
a_ws_cnt := a_ws_cnt + 1;
END IF;
END IF;
IF (stb_i = '1' AND cyc_i = '1' AND aack_o_int = '1' AND (cti_i = "000" OR cti_i = "111" OR cti_i = "001") ) OR
stb_i = '0' OR cyc_i = '0' THEN
first_adr_phase := TRUE;
END IF;
IF (stb_i = '1' AND cyc_i = '1' AND aack_o_int = '1' ) OR
stb_i = '0' OR cyc_i = '0' THEN
a_ws_cnt := 0;
END IF;
IF stb_i = '1' AND cyc_i = '1' THEN
IF DEBUG_ACK_CHECK THEN print_now("IRAM DEBUG: a_ws_cnt=" & integer'image(a_ws_cnt)); END IF;
END IF;
-- generate reference ack
dgb_ack <= '0';
IF ack_array_wrptr /= ack_array_rdptr THEN
IF DEBUG_ACK_CHECK THEN print_now("ack_array_wrptr=" & integer'image(ack_array_wrptr) & ", ack_array_rdptr=" & integer'image(ack_array_rdptr)); END IF;
IF DEBUG_ACK_CHECK THEN print_now("ack_array(ack_array_rdptr)=" & integer'image(ack_array(ack_array_rdptr)) & ", time_cnt=" & integer'image(time_cnt)); END IF;
IF time_cnt >= ack_array(ack_array_rdptr) THEN
dgb_ack <= '1';
IF ack_array_rdptr = ACK_ARRAY_SIZE-1 THEN
ack_array_rdptr := 0;
ELSE
ack_array_rdptr := ack_array_rdptr + 1;
END IF;
END IF;
END IF;
time_cnt := time_cnt + 1;
time_cnt_sig <= time_cnt;
END IF;
END LOOP;
END PROCESS;
PROCESS
VARIABLE disable: boolean := FALSE;
BEGIN
WAIT until rising_edge(clk) OR (iram_in.conf_req'event AND iram_in.conf_req = FALSE);
IF iram_in.conf_req'event AND iram_in.conf_req = FALSE THEN
IF iram_in.d_break_delay_length /= 0 OR
iram_in.d_break_delay_position /= 0 OR
iram_in.a_break_delay_length /= 0 OR
iram_in.a_break_delay_position /= 0 OR
iram_in.external_ws /= FALSE THEN
disable := TRUE;
ELSE
disable := FALSE;
END IF;
END IF;
IF rising_edge(clk) AND NOT disable THEN
err(2) <= '0';
IF dgb_ack /= dgb_ack_dut THEN
print_now("ERROR: dgb_ack_dut = " & std_logic'image(dgb_ack_dut) & " but shall be " & std_logic'image(dgb_ack));
err(2) <= '1';
END IF;
END IF;
END PROCESS;
PROCESS
VARIABLE disable: boolean := FALSE;
VARIABLE dbg_a_sd_stored: integer;
BEGIN
WAIT until rising_edge(clk) OR (iram_in.conf_req'event AND iram_in.conf_req = FALSE);
IF iram_in.conf_req'event AND iram_in.conf_req = FALSE THEN
dbg_a_sd_stored := iram_in.a_startdelay;
IF iram_in.d_break_delay_length /= 0 OR
iram_in.d_break_delay_position /= 0 OR
iram_in.a_break_delay_length /= 0 OR
iram_in.a_break_delay_position /= 0 OR
iram_in.external_ws /= FALSE THEN
disable := TRUE;
ELSE
disable := FALSE;
END IF;
END IF;
IF rising_edge(clk) AND NOT disable THEN
IF dbg_a_sd_valid THEN
err(0) <= '0';
IF dbg_a_sd /= dbg_a_sd_stored THEN
print_now("ERROR: dbg_a_sd = " & integer'image(dbg_a_sd) & " but shall be " & integer'image(dbg_a_sd_stored));
err(0) <= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS
VARIABLE disable: boolean := FALSE;
VARIABLE dbg_a_ws_stored: integer;
BEGIN
WAIT until rising_edge(clk) OR (iram_in.conf_req'event AND iram_in.conf_req = FALSE);
IF iram_in.conf_req'event AND iram_in.conf_req = FALSE THEN
dbg_a_ws_stored := iram_in.a_waitstates;
IF iram_in.d_break_delay_length /= 0 OR
iram_in.d_break_delay_position /= 0 OR
iram_in.a_break_delay_length /= 0 OR
iram_in.a_break_delay_position /= 0 OR
iram_in.external_ws /= FALSE THEN
disable := TRUE;
ELSE
disable := FALSE;
END IF;
END IF;
IF rising_edge(clk) AND NOT disable THEN
IF dbg_a_ws_valid THEN
err(1) <= '0';
IF dbg_a_ws /= dbg_a_ws_stored THEN
print_now("ERROR: dbg_a_ws = " & integer'image(dbg_a_ws) & " but shall be " & integer'image(dbg_a_ws_stored));
err(1) <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END iram32_sim_arch;
16x004-00_src/ 0000775 0000000 0000000 00000000000 14574545710 0031506 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench Source/ 0000775 0000000 0000000 00000000000 14574545710 0032746 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-00_src pcie_x1_pkg.vhd 0000664 0000000 0000000 00000176745 14574545710 0035666 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
-------------------------------------------------------------------------------
-- Title : package for PCIe simulation model
-- Project : 16z091-
-------------------------------------------------------------------------------
-- File : pcie_x1_pkg.vhd
-- Author : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-10-02
-------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- PCIe package for x1 configuration
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.print_pkg.all;
use work.types_pkg.all;
use work.utils_pkg.all;
library pciebfm_lib;
use pciebfm_lib.pkg_plda_fio.all;
use pciebfm_lib.pkg_xbfm.all;
package pcie_x1_pkg is
-----------------------------------------------------
-- constants to use in terminal_out.tga(1 downto 0)
-----------------------------------------------------
constant IO_TRANSFER : std_logic_vector(1 downto 0) := "00";
constant MEM32_TRANSFER : std_logic_vector(1 downto 0) := "01";
constant CONFIG_TRANSFER : std_logic_vector(1 downto 0) := "10";
-----------------------------------------------------
-- constants to use in terminal_out.tga(3 downto 2)
-----------------------------------------------------
constant BFM_NBR_0 : std_logic_vector(1 downto 0) := "00";
constant BFM_NBR_1 : std_logic_vector(1 downto 0) := "01";
constant BFM_NBR_2 : std_logic_vector(1 downto 0) := "10";
constant BFM_NBR_3 : std_logic_vector(1 downto 0) := "11";
------------------------------
-- constants for general use
------------------------------
constant BFM_BUFFER_MAX_SIZE : integer := 1024;
constant DONT_CHECK32 : std_logic_vector(31 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
--! function that calculates the last byte enables of a transfer
--! @param first_dw first enabled bytes of this transfer
--! @param byte_count amount of bytes for this transfer
--! @return last_dw(3 downto 0) last enabled bytes for this transfer
function calc_last_dw(
first_dw : std_logic_vector(3 downto 0);
byte_count : integer
) return std_logic_vector; -- returns std_logic_vector(3 downto 0)
--! procedure to check a value against a reference value
--! @param caller_proc string argument which is used in error messages to define the position where
--! this procedure was called from
--! @param ref_val 32bit reference value
--! @param check_val 32bit value that is checked against ref_val
--! @param byte_valid defines which byte of check_val is valid, invalid bytes are not compared
--! @return check_ok boolean argument which states whether the check was ok (=true) or not
procedure check_val(
caller_proc : in string;
ref_val : in std_logic_vector(31 downto 0);
check_val : in std_logic_vector(31 downto 0);
byte_valid : in std_logic_vector(3 downto 0);
check_ok : out boolean
);
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
procedure init_bfm(
bfm_inst_nbr : in integer;
io_addr : in std_logic_vector(31 downto 0);
mem32_addr : in std_logic_vector(31 downto 0);
mem64_addr : in std_logic_vector(63 downto 0);
requester_id : in std_logic_vector(15 downto 0);
max_payloadsize : in integer
);
--! procedure to configure the BFM0, custom version for cfg record
--! @param cfg_i input record of type cfg_in_type
--! @return cfg_o returns record of cfg_out_type
procedure configure_bfm(
signal cfg_i : in cfg_in_type;
signal cfg_o : out cfg_out_type
);
--! procedure to configure the BFM, custom version for cfg record
--! @param cfg_i input record of type cfg_in_type
--! @return cfg_o returns record of cfg_out_type
procedure configure_bfm(
bfm_inst_nbr : in integer;
signal cfg_i : in cfg_in_type;
signal cfg_o : out cfg_out_type
);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
procedure configure_bfm (
bfm_inst_nbr : in integer;
max_payload_size : in integer;
max_read_size : in integer;
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
bar3 : in std_logic_vector(31 downto 0);
bar4 : in std_logic_vector(31 downto 0);
bar5 : in std_logic_vector(31 downto 0);
cmd_status_reg : in std_logic_vector(31 downto 0);
ctrl_status_reg : in std_logic_vector(31 downto 0)
);
--! procedure to write values to the BFM internal memory
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param nbr_of_dw number of DWORDS that will be written
--! @param io_space set to true is I/O space is targeted
--! @param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
--! @param mem_addr offset for internal memory space, start at x"0000_0000"
--! @param start_data_val first data value to write, other values are defined by data_inc
--! @param data_inc defines the data increment added to start_data_val for DW 2 to nbr_of_dw
procedure set_bfm_memory(
bfm_inst_nbr : in integer;
nbr_of_dw : in integer;
io_space : in boolean;
mem32 : in boolean;
mem_addr : in std_logic_vector(31 downto 0);
start_data_val : in std_logic_vector(31 downto 0);
data_inc : in integer
);
--! procedure to read from BFM internal memory
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param nbr_of_dw number of DWORDS that will be written
--! @param io_space set to true is I/O space is targeted
--! @param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
--! @param mem_addr offset for internal memory space, start at x"0000_0000"
--! @return databuf_out returns a dword_vector that contains all data read from BFM internal memory
procedure get_bfm_memory(
bfm_inst_nbr : in integer;
nbr_of_dw : in integer;
io_space : in boolean;
mem32 : in boolean;
mem_addr : in std_logic_vector(31 downto 0);
databuf_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0)
);
--! procedure to issue an I/O write to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to write to
--! @param data32 32bit data value to write
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_wr_io(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean -- used when wait_end = true
);
--! procedure to issue an I/O read to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to read from
--! @param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return data32_out 32bit data value returned from read
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_rd_io(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean -- used when wait_end = true
);
--! procedure to issue an single MEM32 write request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to write to
--! @param data32 32bit data value to write
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_wr_mem32(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 0);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean
);
--! procedure to issue an burst MEM32 write request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_count amount of bytes that shall be transferred
--! @param pcie_addr address at DUT to write to
--! @param data32 dword_vector that contains all data values to write
--! @param t_class defines the traffic class this transfer shall have, use "000" as default
--! @param attributes defines the attributes this transfer shall have, use "00" as default
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_wr_mem32(
bfm_inst_nbr : in integer;
byte_count : in integer;
pcie_addr : in std_logic_vector(31 downto 0);
data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
t_class : in std_logic_vector(2 downto 0);
attributes : in std_logic_vector(1 downto 0);
wait_end : in boolean;
success : out boolean
);
--! procedure to issue a single MEM32 read request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to read from
--! @param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return data32_out 32bit data value returned from read
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_rd_mem32(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean -- used when wait_end = true
);
--! procedure to issue a burst MEM32 read request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_count amount of bytes that shall be transferred
--! @param pcie_addr address at DUT to read from
--! @param ref_data32 dword_vector that contains the reference data values for read data check, use DONT_CHECK to skip check
--! @param t_class defines the traffic class this transfer shall have, use "000" as default
--! @param attributes defines the attributes this transfer shall have, use "00" as default
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return data32_out dword_vector that contains the data values returned from read
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_rd_mem32(
bfm_inst_nbr : in integer;
byte_count : in integer;
pcie_addr : in std_logic_vector(31 downto 0);
ref_data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
t_class : in std_logic_vector(2 downto 0);
attributes : in std_logic_vector(1 downto 0);
wait_end : in boolean;
data32_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
);
--! procedure to issue a configuration type 0 write request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to write to
--! @param data32 32bit data value to write
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_wr_config(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean
);
--! procedure to issue a configuration type 0 read request to the DUT
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param byte_en bytes enables for this transfer
--! @param pcie_addr address at DUT to read from
--! @param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
--! @param wait_end set to true to wait until transfer is finished and check for transfer errors
--! @return data32_out 32bit data value returned from read
--! @return success returns true if transfer is done and finished without errors (if wait_end = true)
procedure bfm_rd_config(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
);
--! procedure to configure the DUT configuration space to enable MSI
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param msi_allowed number of MSI that are allowed, coded vector as defined by PCIe spec
--! @return returns true if the configuration was successful
procedure configure_msi(
bfm_inst_nbr : in integer;
msi_allowed : in std_logic_vector(2 downto 0);
success : out boolean
);
--! procedure that waits for an assert INTx message
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param legacy interrupt number, possible values: 0=A, 1=B, 2=C, 3=D
--! @return none, procedure will NOT return if irq was not asserted
procedure wait_on_irq_assert(
bfm_inst_nbr : in integer;
irq_nbr : in integer range 3 downto 0
);
--! procedure that waits for a deassert INTx message
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param legacy interrupt number, possible values: 0=A, 1=B, 2=C, 3=D
--! @return none, procedure will NOT return if irq was not deasserted
procedure wait_on_irq_deassert(
bfm_inst_nbr : in integer;
irq_nbr : in integer range 3 downto 0
);
end pcie_x1_pkg;
package body pcie_x1_pkg is
function calc_last_dw(
first_dw : std_logic_vector(3 downto 0);
byte_count : integer
) return std_logic_vector is
variable first_bytes : integer := 0;
variable last_bytes : integer := 0;
variable return_int : std_logic_vector(3 downto 0);
begin
if first_dw(0) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(1) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(2) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(3) = '1' then
first_bytes := first_bytes +1;
end if;
last_bytes := (byte_count - first_bytes) mod 4;
if last_bytes = 0 then
return_int := "1111";
elsif last_bytes = 1 then
return_int := "0001";
elsif last_bytes = 2 then
return_int := "0011";
elsif last_bytes = 3 then
return_int := "0111";
else
return_int := "XXXX";
assert false report "ERROR in function calc_last_dw(): illegal value for variable last_bytes" severity error;
end if;
return return_int;
end;
procedure check_val(
caller_proc : in string;
ref_val : in std_logic_vector(31 downto 0);
check_val : in std_logic_vector(31 downto 0);
byte_valid : in std_logic_vector(3 downto 0);
check_ok : out boolean
) is
variable pass : boolean := true;
begin
if byte_valid(0) = '1' then
if ref_val(7 downto 0) /= check_val(7 downto 0) then
print_now("BFM ERROR in bfm_rd_mem32(): data read does not match given reference value - mismatch in byte0");
write_s_slvec("BFM ERROR in" & caller_proc & "(): reference value[7:0] = ",ref_val(7 downto 0));
write_s_slvec("BFM ERROR in" & caller_proc & "(): read value[7:0] = ",check_val(7 downto 0));
pass := false;
end if;
end if;
if byte_valid(1) = '1' then
if ref_val(15 downto 8) /= check_val(15 downto 8) then
print_now("BFM ERROR in bfm_rd_mem32(): data read does not match given reference value - mismatch in byte1");
write_s_slvec("BFM ERROR in" & caller_proc & "(): reference value[15:8] = ",ref_val(15 downto 8));
write_s_slvec("BFM ERROR in" & caller_proc & "(): read value[15:8] = ",check_val(15 downto 8));
pass := false;
end if;
end if;
if byte_valid(2) = '1' then
if ref_val(23 downto 16) /= check_val(23 downto 16) then
print_now("BFM ERROR in bfm_rd_mem32(): data read does not match given reference value - mismatch in byte2");
write_s_slvec("BFM ERROR in" & caller_proc & "(): reference value[23:16] = ",ref_val(23 downto 16));
write_s_slvec("BFM ERROR in" & caller_proc & "(): read value[23:16] = ",check_val(23 downto 16));
pass := false;
end if;
end if;
if byte_valid(3) = '1' then
if ref_val(31 downto 24) /= check_val(31 downto 24) then
print_now("BFM ERROR in bfm_rd_mem32(): data read does not match given reference value - mismatch in byte3");
write_s_slvec("BFM ERROR in" & caller_proc & "(): reference value[31:24] = ",ref_val(31 downto 24));
write_s_slvec("BFM ERROR in" & caller_proc & "(): read value[31:24] = ",check_val(31 downto 24));
pass := false;
end if;
end if;
check_ok := pass;
end procedure;
procedure init_bfm(
bfm_inst_nbr : in integer;
io_addr : in std_logic_vector(31 downto 0);
mem32_addr : in std_logic_vector(31 downto 0);
mem64_addr : in std_logic_vector(63 downto 0);
requester_id : in std_logic_vector(15 downto 0);
max_payloadsize : in integer
) is
begin
print_now_s("BFM: initialize PCIe BFM, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_init(bfm_inst_nbr,io_addr,mem32_addr,mem64_addr);
xbfm_set_requesterid(bfm_inst_nbr,requester_id);
xbfm_set_maxpayload(bfm_inst_nbr,max_payloadsize);
print_now_s("BFM: Wait until link is initialized, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_wait_linkup(bfm_inst_nbr);
print_now_s("BFM: link is up, bfm_inst_nbr ",bfm_inst_nbr);
end procedure;
procedure configure_bfm(
signal cfg_i : in cfg_in_type;
signal cfg_o : out cfg_out_type
) is
variable max_read : std_logic_vector(2 downto 0);
variable max_write : std_logic_vector(2 downto 0);
begin
------------------------------
-- set PCIe MAX_PAYLOAD_SIZE
------------------------------
if cfg_i.tstcfg.max_payload <= 128 then
max_write := "000";
elsif cfg_i.tstcfg.max_payload <= 256 then
max_write := "001";
elsif cfg_i.tstcfg.max_payload <= 512 then
max_write := "010";
elsif cfg_i.tstcfg.max_payload <= 1024 then
max_write := "011";
elsif cfg_i.tstcfg.max_payload <= 2048 then
max_write := "100";
elsif cfg_i.tstcfg.max_payload <= 4096 then
max_write := "101";
else
max_write := "000";
end if;
------------------------------
-- set PCIe MAX_READ_SIZE
------------------------------
if cfg_i.tstcfg.max_read <= 128 then
max_read := "000";
elsif cfg_i.tstcfg.max_read <= 256 then
max_read := "001";
elsif cfg_i.tstcfg.max_read <= 512 then
max_read := "010";
elsif cfg_i.tstcfg.max_read <= 1024 then
max_read := "011";
elsif cfg_i.tstcfg.max_read <= 2048 then
max_read := "100";
elsif cfg_i.tstcfg.max_read <= 4096 then
max_read := "101";
else
max_read := "000";
end if;
if(cfg_i.tstcfg.set_txt = 2) then write_label("none","configure BFM with typical values", -1); end if;
if(cfg_i.tstcfg.set_txt = 2) then print("Setup BARs and command/control/status registers"); end if;
xbfm_dword (0,XBFM_CFGWR0,x"00000010",x"F",x"11100000"); -- BAR0 4kb --> need 12Bit address --> here a 1MB (=20 Bit) address is used
xbfm_dword (0,XBFM_CFGWR0,x"00000014",x"F",x"22200000"); -- BAR1 8KB --> need 13Bit address --> here a 1MB (=20 Bit) address is used
xbfm_dword (0,XBFM_CFGWR0,x"00000018",x"F",x"33300000"); -- BAR2 is I/O mapped in z91 simulation and setup with adr.: x333......
xbfm_dword (0,XBFM_CFGWR0,x"0000001C",x"F",x"44400000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (0,XBFM_CFGWR0,x"00000020",x"F",x"55500000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (0,XBFM_CFGWR0,x"00000024",x"F",x"66600000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (0,XBFM_CFGRD0,x"00000004",x"F",x"00100000"); -- Command/Status
xbfm_dword (0,XBFM_CFGWR0,x"00000004",x"F",x"000001FF"); -- Control/Status
xbfm_wait (0);
if(cfg_i.tstcfg.set_txt = 2) then print("Set max payload & max read request registers"); end if;
xbfm_dword (0,XBFM_CFGWR0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_dword (0,XBFM_CFGRD0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_wait (0);
write_label("ns","PCIe config via BFM done", -1);
end procedure;
procedure configure_bfm(
bfm_inst_nbr : in integer;
signal cfg_i : in cfg_in_type;
signal cfg_o : out cfg_out_type
) is
variable max_read : std_logic_vector(2 downto 0);
variable max_write : std_logic_vector(2 downto 0);
begin
------------------------------
-- set PCIe MAX_PAYLOAD_SIZE
------------------------------
if cfg_i.tstcfg.max_payload <= 128 then
max_write := "000";
elsif cfg_i.tstcfg.max_payload <= 256 then
max_write := "001";
elsif cfg_i.tstcfg.max_payload <= 512 then
max_write := "010";
elsif cfg_i.tstcfg.max_payload <= 1024 then
max_write := "011";
elsif cfg_i.tstcfg.max_payload <= 2048 then
max_write := "100";
elsif cfg_i.tstcfg.max_payload <= 4096 then
max_write := "101";
else
max_write := "000";
end if;
------------------------------
-- set PCIe MAX_READ_SIZE
------------------------------
if cfg_i.tstcfg.max_read <= 128 then
max_read := "000";
elsif cfg_i.tstcfg.max_read <= 256 then
max_read := "001";
elsif cfg_i.tstcfg.max_read <= 512 then
max_read := "010";
elsif cfg_i.tstcfg.max_read <= 1024 then
max_read := "011";
elsif cfg_i.tstcfg.max_read <= 2048 then
max_read := "100";
elsif cfg_i.tstcfg.max_read <= 4096 then
max_read := "101";
else
max_read := "000";
end if;
if(cfg_i.tstcfg.set_txt = 2) then write_label("none","configure BFM with typical values", -1); end if;
if(cfg_i.tstcfg.set_txt = 2) then print("Setup BARs and command/control/status registers"); end if;
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000010",x"F",x"11100000"); -- BAR0 4kb --> need 12Bit address --> here a 1MB (=20 Bit) address is used
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000014",x"F",x"22200000"); -- BAR1 8KB --> need 13Bit address --> here a 1MB (=20 Bit) address is used
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000018",x"F",x"33300000"); -- BAR2 is I/O mapped in z91 simulation and setup with adr.: x333......
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"0000001C",x"F",x"44400000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000020",x"F",x"55500000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000024",x"F",x"66600000"); -- not used in z91 simulation but prepared for future use
xbfm_dword (bfm_inst_nbr,XBFM_CFGRD0,x"00000004",x"F",x"00100000"); -- Command/Status
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000004",x"F",x"000001FF"); -- Control/Status
xbfm_wait (bfm_inst_nbr);
if(cfg_i.tstcfg.set_txt = 2) then print("Set max payload & max read request registers"); end if;
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_dword (bfm_inst_nbr,XBFM_CFGRD0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_wait (bfm_inst_nbr);
write_label("ns","PCIe config via BFM done", -1);
end procedure;
procedure configure_bfm (
bfm_inst_nbr : in integer;
max_payload_size : in integer;
max_read_size : in integer;
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
bar3 : in std_logic_vector(31 downto 0);
bar4 : in std_logic_vector(31 downto 0);
bar5 : in std_logic_vector(31 downto 0);
cmd_status_reg : in std_logic_vector(31 downto 0);
ctrl_status_reg : in std_logic_vector(31 downto 0)
) is
variable max_read : std_logic_vector(2 downto 0);
variable max_write : std_logic_vector(2 downto 0);
begin
print_now("BFM: calculate max_payload_size and max_read_size");
------------------------------
-- set PCIe MAX_PAYLOAD_SIZE
------------------------------
if max_payload_size <= 128 then
max_write := "000";
elsif max_payload_size <= 256 then
max_write := "001";
elsif max_payload_size <= 512 then
max_write := "010";
elsif max_payload_size <= 1024 then
max_write := "011";
elsif max_payload_size <= 2048 then
max_write := "100";
elsif max_payload_size <= 4096 then
max_write := "101";
else
max_write := "000";
end if;
------------------------------
-- set PCIe MAX_READ_SIZE
------------------------------
if max_read_size <= 128 then
max_read := "000";
elsif max_read_size <= 256 then
max_read := "001";
elsif max_read_size <= 512 then
max_read := "010";
elsif max_read_size <= 1024 then
max_read := "011";
elsif max_read_size <= 2048 then
max_read := "100";
elsif max_read_size <= 4096 then
max_read := "101";
else
max_read := "000";
end if;
print_now_s("BFM: setup BARs and command/control/status registers, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000010",x"F",bar0); -- BAR0
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000014",x"F",bar1); -- BAR1
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000018",x"F",bar2); -- BAR2
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"0000001C",x"F",bar3); -- BAR3
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000020",x"F",bar4); -- BAR4
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000024",x"F",bar5); -- BAR5
xbfm_dword (bfm_inst_nbr,XBFM_CFGRD0,x"00000004",x"F",cmd_status_reg); -- Command/Status
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000004",x"F",ctrl_status_reg); -- Control/Status
print_now_s("BFM: wait until all values are set, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_wait (bfm_inst_nbr);
print_now_s("BFM: set max_payload & max_read registers, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_dword (bfm_inst_nbr,XBFM_CFGWR0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
xbfm_dword (bfm_inst_nbr,XBFM_CFGRD0,x"00000088",x"F",x"0000" & '0' & max_read & x"8" & max_write & "00000");
print_now_s("BFM: wait until all values are set, bfm_inst_nbr ",bfm_inst_nbr);
xbfm_wait (bfm_inst_nbr);
print_now_s("BFM: BARs and registers initialized, bfm_inst_nbr ",bfm_inst_nbr);
end procedure;
procedure set_bfm_memory(
bfm_inst_nbr : in integer;
nbr_of_dw : in integer;
io_space : in boolean;
mem32 : in boolean;
mem_addr : in std_logic_vector(31 downto 0);
start_data_val : in std_logic_vector(31 downto 0);
data_inc : in integer
) is
variable bfm_databuf : dword_vector(nbr_of_dw -1 downto 0);
begin
print_now_s("BFM: set BFM internal memory, bfm_inst_nbr ",bfm_inst_nbr);
print_s_i("BFM: number of dwords = ",nbr_of_dw);
print_s_std("BFM: start address = ", mem_addr);
print_s_std("BFM: initial data value = ", start_data_val);
print_s_i("BFM: data value increment = ",data_inc);
for i in 0 to nbr_of_dw -1 loop
bfm_databuf(i) := std_logic_vector(unsigned(start_data_val) + to_unsigned(i*data_inc,32));
end loop;
if io_space then
print("BFM: write data to IO space");
xbfm_memory_write(bfm_inst_nbr,XBFM_IO,mem_addr,nbr_of_dw,bfm_databuf);
else
if mem32 then
print("BFM: write data to MEM32 space");
xbfm_memory_write(bfm_inst_nbr,XBFM_MEM32,mem_addr,nbr_of_dw,bfm_databuf);
else
print("BFM: write data to MEM64 space");
xbfm_memory_write(bfm_inst_nbr,XBFM_MEM64,mem_addr,nbr_of_dw,bfm_databuf);
end if;
end if;
end procedure;
procedure get_bfm_memory(
bfm_inst_nbr : in integer;
nbr_of_dw : in integer;
io_space : in boolean;
mem32 : in boolean;
mem_addr : in std_logic_vector(31 downto 0);
databuf_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0)
) is
begin
if nbr_of_dw > BFM_BUFFER_MAX_SIZE then
print_now_s("BFM ERROR in get_bfm_memory(): nbr_of_dw exceeds BFM_BUFFER_MAX_SIZE, bfm_inst_nbr ",bfm_inst_nbr);
else
print_now_s("BFM: get values from BFM internal memory, bfm_inst_nbr ",bfm_inst_nbr);
print_s_i("BFM: number of dwords = ",nbr_of_dw);
if io_space then
print("BFM: read data from IO space");
xbfm_memory_read(bfm_inst_nbr,XBFM_IO,mem_addr,nbr_of_dw,databuf_out);
else
if mem32 then
print("BFM: read data from MEM32 space");
xbfm_memory_read(bfm_inst_nbr,XBFM_MEM32,mem_addr,nbr_of_dw,databuf_out);
else
print("BFM: read data from MEM64 space");
xbfm_memory_read(bfm_inst_nbr,XBFM_MEM64,mem_addr,nbr_of_dw,databuf_out);
end if;
end if;
end if;
end procedure;
procedure bfm_wr_io(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean -- used when wait_end = true
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM I/O write, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
xbfm_dword_id(bfm_inst_nbr,XBFM_IOWR,pcie_addr & "00",byte_en,data32,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_wr_io(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_wr_io(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_wr_io(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_wr_io(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
end if;
success := pass;
end procedure;
procedure bfm_rd_io(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean -- used when wait_end = true
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM I/O read, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
data32_out := (others => '0');
xbfm_dword_id(bfm_inst_nbr,XBFM_IORD,pcie_addr & "00",byte_en,bfm_databuf(0),bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_rd_io(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_rd_io(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_rd_io(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_rd_io(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_io",
ref_val => ref_data32,
check_val => bfm_databuf(0),
byte_valid => byte_en,
check_ok => pass
);
end if;
data32_out := bfm_databuf(0);
else
print("BFM: skipped check of read value because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_wr_mem32(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 0);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM MEM32 write (single), bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
xbfm_dword_id(bfm_inst_nbr,XBFM_MWR,pcie_addr(31 downto 2) & "00",byte_en,data32,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_wr_mem32(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
else
print("BFM: skipped tranfer check because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_wr_mem32(
bfm_inst_nbr : in integer;
byte_count : in integer;
pcie_addr : in std_logic_vector(31 downto 0);
data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
t_class : in std_logic_vector(2 downto 0);
attributes : in std_logic_vector(1 downto 0);
wait_end : in boolean;
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM MEM32 write (burst), bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
xbfm_burst_id(bfm_inst_nbr,XBFM_MWR,x"0000_0000" & pcie_addr,byte_count,data32,t_class,attributes,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_wr_mem32(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_wr_mem32(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
else
print("BFM: skipped tranfer check because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_rd_mem32(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean -- used when wait_end = true
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM MEM32 read, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
data32_out := (others => '0');
xbfm_dword_id(bfm_inst_nbr,XBFM_MRD,pcie_addr & "00",byte_en,bfm_databuf(0),bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_rd_mem32(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_mem32",
ref_val => ref_data32,
check_val => bfm_databuf(0),
byte_valid => byte_en,
check_ok => pass
);
end if;
data32_out := bfm_databuf(0);
else
print("BFM: skipped check of read value because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_rd_mem32(
bfm_inst_nbr : in integer;
byte_count : in integer;
pcie_addr : in std_logic_vector(31 downto 0);
ref_data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
t_class : in std_logic_vector(2 downto 0);
attributes : in std_logic_vector(1 downto 0);
wait_end : in boolean;
data32_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
variable byte_en : std_logic_vector(3 downto 0) := (others => '0');
variable first_DW_en : std_logic_vector(3 downto 0) := (others => '0');
variable last_DW_en : std_logic_vector(3 downto 0) := (others => '0');
begin
print_now_s("BFM: BFM MEM32 read (burst), bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
data32_out := (others => (others => '0'));
case pcie_addr(1 downto 0) is
when "00" => first_DW_en := "1111";
when "01" => first_DW_en := "1110";
when "10" => first_DW_en := "1100";
when "11" => first_DW_en := "1000";
when others => first_DW_en := "1111";
end case;
last_DW_en := calc_last_dw(
first_dw => first_DW_en,
byte_count => byte_count );
xbfm_burst_id(bfm_inst_nbr,XBFM_MRD,x"0000_0000" & pcie_addr,byte_count,bfm_databuf,t_class,attributes,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_rd_mem32(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_rd_mem32(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
for i in 0 to (byte_count /4) -1 loop
if ref_data32(i) = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
if i = 0 then
byte_en := first_DW_en;
elsif i = (byte_count /4) -1 then
byte_en := last_DW_en;
else
byte_en := x"F";
end if;
check_val(
caller_proc => "bfm_rd_mem32",
ref_val => ref_data32(i),
check_val => bfm_databuf(i),
byte_valid => byte_en,
check_ok => pass
);
end if;
wait for 0 ns;
end loop;
data32_out := bfm_databuf;
else
print("BFM: skipped check of read value because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_wr_config(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM configuration write, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,pcie_addr & "00",byte_en,data32,bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_wr_config(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_wr_config(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_wr_config(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_wr_config(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
else
print("BFM: skipped transfer check because wait_end = false");
end if;
success := pass;
end procedure;
procedure bfm_rd_config(
bfm_inst_nbr : in integer;
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
wait_end : in boolean;
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable pass : boolean := true;
begin
print_now_s("BFM: BFM configuration read, bfm_inst_nbr ",bfm_inst_nbr);
pass := true;
data32_out := (others => '0');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,pcie_addr & "00",byte_en,bfm_databuf(0),bfm_trans_id);
if wait_end then
xbfm_wait_id(bfm_inst_nbr, bfm_trans_id, bfm_status, bfm_databuf);
---------------------------------------------
-- check for BFM errors during transmission
---------------------------------------------
if bfm_status /= XBFM_SC then
if bfm_status = XBFM_CA then
print_now("BFM ERROR in bfm_rd_config(): BFM status: completer abort");
elsif bfm_status = XBFM_UR then
print_now("BFM ERROR in bfm_rd_config(): BFM status: unsupported request");
elsif bfm_status = XBFM_TIMEOUT then
print_now("BFM ERROR in bfm_rd_config(): BFM status: completion timeout");
else
print_now("BFM ERROR in bfm_rd_config(): BFM status other than successful but unknown");
end if;
pass := false;
end if;
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_config",
ref_val => ref_data32,
check_val => bfm_databuf(0),
byte_valid => byte_en,
check_ok => pass
);
end if;
data32_out := bfm_databuf(0);
else
print("BFM: skipped check of read value because wait_end = false");
end if;
success := pass;
end procedure;
procedure configure_msi(
bfm_inst_nbr : in integer;
msi_allowed : in std_logic_vector(2 downto 0);
success : out boolean
) is
variable bfm_trans_id : integer := 0;
variable bfm_status : integer;
variable bfm_databuf : dword_vector(255 downto 0);
variable nextCapAddr : std_logic_vector(7 downto 0); -- address of next capability
variable data32bit : std_logic_vector(31 downto 0);
variable capID : std_logic_vector(7 downto 0);
variable msi_addr_is_64bit : std_logic;
variable temp_addr : std_logic_vector(31 downto 0);
variable pass : boolean;
begin
pass := true;
-- if(cfg_i.tstcfg.set_txt = 2) then print_now("Test MSI generation"); end if;
----------------------------------------------
-- configure PCIe config space to enable MSI
-- MSI capabilities registers for 32bit MSI addresses:
-- 31 16 15 8 7 0
-- -----------------------------------------------------
-- | message ctrl reg | next cap pointer | cap ID=0x05 | DW0
-- -----------------------------------------------------
-- | message address register | DW1
-- -----------------------------------------------------
-- | reserved | message data register | DW2
-- -----------------------------------------------------
-- MSI capabilities registers for 64bit MSI addresses:
-- 31 16 15 8 7 0
-- -----------------------------------------------------
-- | message ctrl reg | next cap pointer | cap ID=0x05 | DW0
-- -----------------------------------------------------
-- | least signif. 32bits of message address register | DW1
-- -----------------------------------------------------
-- | most signif. 32bits of message address register | DW2
-- -----------------------------------------------------
-- | reserved | message data register | DW3
-- -----------------------------------------------------
-- cycle:
-- 1. read status register and check bit4
-- if =1 then function has extended capabilities implemented
-- and capabilities pointer is implemented @DW13 = 0x34
-- 2. read capabilities pointer value which is start address of extended capabilities list
-- 3. read register @address from step 2 and check bit 7:0
-- if 7:0=0x05 then MSI register set is present
-- else read next address @15:8
-- 4. if MSI register set is found
-- check if 64bit addresses are used
-- program message address register to DW1 with 31:2=addr and 1:0=0
-- program message data register to DW2 with 31:16=0 and 15:0=data
-- 5. program DW0 with nbr of MSI allowed and enable MSI
-- read bit 19:17 of DW0 which contains nbr of MSI requested by function
-- program nbr of MSI allowed to DW0 bit 22:20 and enable MSI bit 16=1
----------------------------------------------
-- step1: read status register but disable data value check
print_now("Step1: read status register");
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"0000_0004",x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
if data32bit(20) = '0' then
--error because no next capabilities implemented
print_now("BFM ERROR in configure_msi(): function does not implement next capabilities structure thus MSI registers can not be programmmed.");
pass := false;
else
-- step2: read capabilities pointer
print_now("Step2: read capabilities pointer");
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"0000_0034",x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
nextCapAddr := data32bit(7 downto 0);
-- step3: read byte0 of registers pointed to by capabilities pointer
print_now("Step3: read byte0 of registers pointed to by capabilities pointer");
capID := (others => '0');
while capID /= x"05" loop
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"000000" & nextCapAddr,x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
capID := data32bit(7 downto 0);
if capID /= x"05" then
nextCapAddr := data32bit(15 downto 8);
end if;
end loop;
-- step4: write MSI register set contents
print_now("Step4: write MSI register set contents");
-- check if 64bit addresses are used
msi_addr_is_64bit := '0';
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"000000" & nextCapAddr,x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
msi_addr_is_64bit := data32bit(23);
-- program message address register to DW1 with 31:2=addr and 1:0=0
-- set to zero as 64bit addresses shall not be used
if msi_addr_is_64bit = '1' then
-- function does support 64bit addresses
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(4,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"AAAA_0034",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(8,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"0000_0000",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
-- program message data register to DW2 with 31:16=0 and 15:0=data
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(12,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"0000_2222",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
else
-- fucntion does not support 64bit addresses
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(4,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"AAAA_0034",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
-- program message data register to DW2 with 31:16=0 and 15:0=data
temp_addr := x"000000" & nextCapAddr;
temp_addr := std_logic_vector(unsigned(temp_addr)+ to_unsigned(8,32));
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,temp_addr,x"F",x"0000_2222",bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
end if;
-- step5: program DW0 with nbr of MSI allowed and enable MSI
print_now("Step5: program DW0 with nbr of MSI allowed and enable MSI");
------------------------------------------------------------------------------------------------
-- if msi_allowed = Z program the value given by "MSI requested" to the register "MSI allowed"
-- otherwise program value given by msi_allowed
------------------------------------------------------------------------------------------------
-- read bit 19:17 of DW0 which contains nbr of MSI requested by function
data32bit := (others => 'X');
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGRD0,x"000000" & nextCapAddr,x"F",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
data32bit := bfm_databuf(0);
-- program nbr of MSI allowed to DW0 bit 22:20 and enable MSI bit 16=1
if msi_allowed = "ZZZ" then
data32bit(22 downto 20) := data32bit(19 downto 17);
else
data32bit(22 downto 20) := msi_allowed;
end if;
data32bit(16) := '1';
xbfm_dword_id(bfm_inst_nbr,XBFM_CFGWR0,x"000000" & nextCapAddr,"1100",data32bit,bfm_trans_id);
xbfm_wait_id(bfm_inst_nbr,bfm_trans_id,bfm_status,bfm_databuf);
if bfm_status /= XBFM_SC then
print_now("BFM ERROR in configure_msi(): completion status other than successful!");
pass := false;
end if;
end if;
success := pass;
end procedure;
procedure wait_on_irq_assert(
bfm_inst_nbr : in integer;
irq_nbr : in integer range 3 downto 0
) is
begin
if irq_nbr = 0 then
print_now("BFM: waiting on assert-INTA message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTAA_RCVD);
elsif irq_nbr = 1 then
print_now("BFM: waiting on assert-INTB message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTBA_RCVD);
elsif irq_nbr = 2 then
print_now("BFM: waiting on assert-INTC message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTCA_RCVD);
elsif irq_nbr = 3 then
print_now("BFM: waiting on assert-INTD message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTDA_RCVD);
else
assert false report "BFM ERROR in wait_on_irq_assert(): invalid value for interrupt number irq_nbr" severity failure;
end if;
end procedure wait_on_irq_assert;
procedure wait_on_irq_deassert(
bfm_inst_nbr : in integer;
irq_nbr : in integer range 3 downto 0
) is
begin
if irq_nbr = 0 then
print_now("BFM: waiting on deassert-INTA message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTAD_RCVD);
elsif irq_nbr = 1 then
print_now("BFM: waiting on deassert-INTB message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTBD_RCVD);
elsif irq_nbr = 2 then
print_now("BFM: waiting on deassert-INTC message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTCD_RCVD);
elsif irq_nbr = 3 then
print_now("BFM: waiting on deassert-INTD message");
xbfm_wait_event(bfm_inst_nbr, XBFM_INTDD_RCVD);
else
assert false report "BFM ERROR in wait_on_irq_deassert(): invalid value for interrupt number irq_nbr" severity failure;
end if;
end procedure wait_on_irq_deassert;
end;
pcie_x1_sim.vhd 0000664 0000000 0000000 00000030235 14574545710 0035654 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
-------------------------------------------------------------------------------
-- Title : PCIe simulation model
-- Project : 16z091-
-------------------------------------------------------------------------------
-- File : pcie_x1_sim.vhd
-- Author : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-10-02
-------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- PCIe simulation model for x1 configuration
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.utils_pkg.all;
use work.print_pkg.all;
use work.pcie_x1_pkg.all;
use work.terminal_pkg.all;
library pciebfm_lib;
use pciebfm_lib.pkg_plda_fio.all;
use pciebfm_lib.pkg_xbfm.all;
entity pcie_x1_sim is
generic(
INSTANCE_NBR : integer range 3 downto 0 := 0; -- nbr of BFM instance
BFM_IO_SIZE : integer range 24 downto 12 := 16; -- 12 <= x <= 24
BFM_MEM32_SIZE : integer range 24 downto 12 := 16; -- 12 <= x <= 24
BFM_MEM64_SIZE : integer range 24 downto 12 := 16 -- 12 <= x <= 24
);
port(
clk : in std_logic;
rst : in std_logic;
-- BFM signals
clk125 : in std_logic;
clk250 : in std_logic;
rstn : in std_logic;
bfm_tx_0 : in std_logic;
bfm_rx_0 : out std_logic;
term_out : in terminal_out_type;
term_in : out terminal_in_type
);
end entity pcie_x1_sim;
architecture pcie_x1_sim_arch of pcie_x1_sim is
begin
print_s_i("DEBUG(1): BFM_IO_SIZE = ", BFM_IO_SIZE);
assert BFM_IO_SIZE >= 12 report "ERROR (pcie_x1_sim): value for generic BFM_IO_SIZE is too small" severity failure;
assert BFM_IO_SIZE <= 24 report "ERROR (pcie_x1_sim): value for generic BFM_IO_SIZE is too big" severity failure;
assert BFM_MEM32_SIZE >= 12 report "ERROR (pcie_x1_sim): value for generic BFM_MEM32_SIZE is too small" severity failure;
assert BFM_MEM32_SIZE <= 24 report "ERROR (pcie_x1_sim): value for generic BFM_MEM32_SIZE is too big" severity failure;
assert BFM_MEM64_SIZE >= 12 report "ERROR (pcie_x1_sim): value for generic BFM_MEM64_SIZE is too small" severity failure;
assert BFM_MEM64_SIZE <= 24 report "ERROR (pcie_x1_sim): value for generic BFM_MEM64_SIZE is too big" severity failure;
bfm_inst : entity pciebfm_lib.pldawrap_link
generic map (
BFM_ID => INSTANCE_NBR,
BFM_TYPE => '0',
BFM_LANES => 1,
BFM_WIDTH => 1,
IO_SIZE => BFM_IO_SIZE,
MEM32_SIZE => BFM_MEM32_SIZE,
MEM64_SIZE => BFM_MEM64_SIZE
)
port map (
clk125 => clk125,
clk250 => clk250,
rstn => rstn,
tx_rate => open,
tx_in0(0) => bfm_tx_0,
tx_in1(0) => '0',
tx_in2(0) => '0',
tx_in3(0) => '0',
tx_in4(0) => '0',
tx_in5(0) => '0',
tx_in6(0) => '0',
tx_in7(0) => '0',
tx_val => x"00", -- unused in serial mode (BFM_WIDTH = 1)
rx_out0(0) => bfm_rx_0,
rx_val => open, -- unused in serial mode (BFM_WIDTH = 1)
chk_txval => open,
chk_txdata => open,
chk_txdatak => open,
chk_rxval => open,
chk_rxdata => open,
chk_rxdatak => open,
chk_ltssm => open
);
main : process
variable first_be_en : std_logic_vector(3 downto 0);
variable byte_count : integer;
variable addr32_int : std_logic_vector(31 downto 0);
variable bfm_id : integer := 0;
variable success_int : boolean := false;
variable return_data32 : std_logic_vector(31 downto 0) := (others => '0');
variable return_data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable temp_inst_nbr : std_logic_vector(1 downto 0);
begin
-- reset all
term_in.busy <= '1';
term_in.done <= true;
wait until rst = '0';
wait_clk(clk,1);
if term_out.start /= true then
wait until term_out.start = true;
end if;
loop
wait on term_out.start;
term_in.busy <= '1';
---------------------------
-- check for wrong values
---------------------------
temp_inst_nbr := std_logic_vector(to_unsigned(INSTANCE_NBR,2));
if temp_inst_nbr /= term_out.tga(3 downto 2) then
assert false report "ERROR (pcie_x1_sim): instance number in term_out.tga(3 downto 2) does not match INSTANCE_NBR for this component" severity failure;
end if;
assert term_out.typ <= 2 report "ERROR (pcie_x1_sim): illegal value for signal term_out.typ" severity failure;
assert term_out.wr <= 2 report "ERROR (pcie_x1_sim): illegal value for signal term_out.wr" severity failure;
if term_out.typ = 0 then
assert term_out.numb = 1 report "ERROR (pcie_x1_sim): illegal combination for signals term_out.typ and term_out.numb => bytewise burst is impossible" severity failure;
end if;
if term_out.typ = 1 then
assert term_out.numb = 1 report "ERROR (pcie_x1_sim): illegal combination for signals term_out.typ and term_out.numb => wordwise burst is impossible" severity failure;
end if;
assert term_out.numb <= 1024 report "ERROR (pcie_x1_sim): maximum value for signal term_out.numb is 1024" severity failure;
----------------------------
-- set values for this run
----------------------------
addr32_int := term_out.adr(31 downto 2) & "00";
byte_count := term_out.numb *4;
bfm_id := to_integer(unsigned(term_out.tga(3 downto 2)));
if term_out.typ = 0 then -- byte
if term_out.adr(1 downto 0) = "01" then
first_be_en := "0010";
elsif term_out.adr(1 downto 0) = "10" then
first_be_en := "0100";
elsif term_out.adr(1 downto 0) = "11" then
first_be_en := "1000";
else
first_be_en := "0001";
end if;
elsif term_out.typ = 1 then -- word
if term_out.adr(1) = '0' then
first_be_en := "0011";
else
first_be_en := "1100";
end if;
else -- long word
first_be_en := x"F";
end if;
for i in 0 to term_out.numb -1 loop
data_vec(i) := std_logic_vector(unsigned(term_out.dat) + to_unsigned(i,32));
return_data_vec(i) := (others => '0');
wait for 0 ns;
end loop;
if term_out.wr = 0 then -- read
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
bfm_rd_io(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
wait_end => true,
data32_out => return_data32,
success => success_int
);
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
if term_out.numb = 1 then
bfm_rd_mem32(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
wait_end => true,
data32_out => return_data32,
success => success_int
);
else
bfm_rd_mem32(
bfm_inst_nbr => bfm_id,
byte_count => byte_count,
pcie_addr => addr32_int,
ref_data32 => data_vec,
t_class => "000",
attributes => "00",
wait_end => true,
data32_out => return_data_vec,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
bfm_rd_config(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
wait_end => true,
data32_out => return_data32,
success => success_int
);
else
assert false report "ERROR (pcie_x1_sim): term_out.tga(1 downto 0) = 11 is reserved" severity failure;
end if;
elsif term_out.wr = 1 then -- write
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
bfm_wr_io(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
data32 => term_out.dat,
wait_end => true,
success => success_int
);
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
if term_out.numb = 1 then
bfm_wr_mem32(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int,
data32 => term_out.dat,
wait_end => true,
success => success_int
);
else
bfm_wr_mem32(
bfm_inst_nbr => bfm_id,
byte_count => byte_count,
pcie_addr => addr32_int,
data32 => data_vec,
t_class => "000",
attributes => "00",
wait_end => true,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
bfm_wr_config(
bfm_inst_nbr => bfm_id,
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
data32 => term_out.dat,
wait_end => true,
success => success_int
);
else
assert false report "ERROR (pcie_x1_sim): term_out.tga(1 downto 0) = 11 is reserved" severity failure;
end if;
else -- wait
wait_clk(clk,term_out.numb);
end if;
--------------------------------------
-- return values and finish transfer
--------------------------------------
term_in.dat <= return_data32;
if success_int then
term_in.err <= 0;
else
term_in.err <= 1;
end if;
term_in.busy <= '0';
term_in.done <= term_out.start;
end loop;
end process main;
end architecture pcie_x1_sim_arch;
types_pkg.vhd 0000664 0000000 0000000 00000006224 14574545710 0035462 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
-------------------------------------------------------------------------------
-- Title : 16z091-00 PCIe test bench
-- Project : 16z091-00
-------------------------------------------------------------------------------
-- File : types_pkg.vhd
-- Author : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-08-21
-------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6 Revision 2010.01
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- Constants and types common to all test bench files
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package types_pkg is
constant TST_PASS : integer := 1;
constant TST_FAIL : integer := 2;
--------------------------------------------------------
-- define all configurable settings in tst_config_type
--------------------------------------------------------
type tst_config_type is record
-- iter : integer;
-- iram_max_size : integer;
set_txt : integer;
max_payload : integer;
max_read : integer;
-- msi_nbr : integer;
-- msi_en : integer;
-- min_loop : integer;
-- max_loop : integer;
-- len_wb_burst : integer;
-- len_pcie_burst : integer;
-- start_delay_iram : integer;
-- wait_states_iram : integer;
-- break_at_iram : integer;
-- break_for_iram : integer;
end record;
-- type error_in_type is record
-- wbm_err : integer;
-- wbs_err : integer;
-- wb_mon_err : integer;
-- mon001_err : integer;
-- end record;
type watchdog_type is record
wd_start : boolean;
wd_time : time;
end record;
-- type mon001_ctrl_in_type is record
-- busy : std_logic;
-- end record;
-- type mon001_ctrl_out_type is record
-- ref_data : std_logic_vector(31 downto 0);
-- ref_sel : std_logic_vector(3 downto 0);
-- ref_addr : std_logic_vector(31 downto 0);
-- new_val : boolean; -- edge states that ref_sel and ref_data have new values
-- end record;
type cfg_in_type is record
wb_clk : std_logic;
clk : std_logic;
tstcfg : tst_config_type;
--err_in : error_in_type;
--mon001_ctrl_i : mon001_ctrl_in_type;
end record;
type cfg_out_type is record
dut_rst : std_logic;
tb_rst : std_logic;
wb_rst : std_logic;
watchdog : watchdog_type;
--mon001_ctrl_o : mon001_ctrl_out_type;
end record;
end types_pkg;
package body types_pkg is
-- empty
end;
utils_pkg.vhd 0000664 0000000 0000000 00000014326 14574545710 0035460 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
-------------------------------------------------------------------------------
-- Title : utilitiy package for 16z091-00 PCIe test bench
-- Project : 16z091-00
-------------------------------------------------------------------------------
-- File : utils_pkg.vhd
-- Author : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-08-22
-------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6 Revision 2010.01
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- Contains useful procedures
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
package utils_pkg is
procedure write_label(
constant use_time : in string;
constant string_in : in string;
integer_in : in integer
);
procedure wait_clk(
signal clk : in std_logic;
constant clk_cnt : in integer
);
procedure write_s_slvec(
string_in : in string;
slvec_in : in std_logic_vector
);
end utils_pkg;
package body utils_pkg is
-----------------------------------------------------------------------------------------------------------------------------------------
-- write_label:
-- This procedure prints out a box to the transcript which is formated according to the length of the input string.
-- use_time : provide time resolution or "none" if no time shall be printed
-- string_in : input string that will be printed to the box
-- integer_in : integer value that will be printed to the box, omitted if set to 0
-----------------------------------------------------------------------------------------------------------------------------------------
procedure write_label(
constant use_time : in string;
constant string_in : in string;
integer_in : in integer
) is
variable wrLine : line;
variable cnt : integer := 0;
constant LABEL_C : string := "-";
constant LABEL_STR : string := "--";
constant LABEL_STR1 : string := "---";
constant CORNER_C : string := "+";
constant HEADER_C : string := "=";
constant LINE_LEN : integer := 105;
constant T_WIDTH : integer := 15;
begin
write(wrLine, CORNER_C);
for i in string_in'range loop
write(wrLine, LABEL_C);
end loop;
if integer_in >= 0 then
for i in 0 to 9 loop
if (integer_in / (10**i)) /= 0 then cnt := i; end if;
end loop;
for j in 0 to cnt loop
write(wrLine, label_c);
end loop;
write(wrLine, LABEL_STR1);
else
write(wrLine, LABEL_STR);
end if;
if use_time /= "none" then
for i in 0 to T_WIDTH loop
write(wrLine, LABEL_C);
end loop;
end if;
write(wrLine, CORNER_C);
writeline(output,wrLine);
write(wrLine, string'("| "));
if use_time /= "none" then
if use_time = "fs" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> fs );
elsif use_time = "ps" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ps );
elsif use_time = "us" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> us );
elsif use_time = "ms" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ms );
else
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ns );
end if;
write(wrLine, string'(" "));
end if;
write(wrLine, string_in);
if integer_in >= 0 then
write(wrLine, string'(" "));
write(wrLine, integer_in);
end if;
write(wrLine, string'(" |"));
writeline(output,wrLine);
write(wrLine, CORNER_C);
for i in string_in'range loop
write(wrLine, LABEL_C);
end loop;
if integer_in >= 0 then
for i in 0 to 9 loop
if (integer_in / (10**i)) /= 0 then cnt := i; end if;
end loop;
for j in 0 to cnt loop
write(wrLine, label_c);
end loop;
write(wrLine, LABEL_STR1);
else
write(wrLine, LABEL_STR);
end if;
if use_time /= "none" then
for i in 0 to T_WIDTH loop
write(wrLine, LABEL_C);
end loop;
end if;
write(wrLine, CORNER_C);
writeline(output,wrLine);
end procedure write_label;
-----------------------------------------------------------------------------------------------------------------------------------------
-- wait_clk:
-- This procedure waits for the given amount of input clock cycles.
-----------------------------------------------------------------------------------------------------------------------------------------
procedure wait_clk(
signal clk : in std_logic;
constant clk_cnt : in integer
) is
begin
for i in 1 to clk_cnt loop
wait until rising_edge(clk);
end loop;
end procedure wait_clk;
-----------------------------------------------------------------------------------------------------------------------------------------
-- write_s_slvec:
-- This procedure prints std_logic_vector values in a way that collisions (e.g. 'X' or 'U') can be detected.
-----------------------------------------------------------------------------------------------------------------------------------------
procedure write_s_slvec(
string_in : in string;
slvec_in : in std_logic_vector
) is
variable l : line;
begin
write(l,string_in);
write(l, std_ulogic_vector(slvec_in), justified => right, field => 10);
writeline(output,l);
end procedure write_s_slvec;
end;
Synthesis/ 0000775 0000000 0000000 00000000000 14574545710 0033477 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-00_src 16x004-00_build_libraries.tcl 0000664 0000000 0000000 00000014443 14574545710 0040503 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-00_src/Synthesis # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
global env
## set path to Quartus install dir: "C:/altera/11.0/quartus"
set PathToQuartus $env(QUARTUS_ROOTDIR)
## set path to Riviera PRO: "C:/Aldec/Riviera-PRO-2011.06-x64"
set simulator_root $env(ALDEC_PATH)
## set path to modelsim_lib
set modelSimLib "../Testbench2"
## set path to 16x004-00 BFM
set pathToBFM "../../../16/16x004-00"
## set path to PLDA simulation library
set pathToPLDAsimlib "./PLDA"
set force_lib_compile 0
## 0 = RivieraPRO, 1 = ModelSim
if {[string compare [lindex $tmp_list 2] "ModelSim"] == 0} {
set ModelSim 1
} else {
set ModelSim 0
}
## if an Altera simulator is used no Altera libraries must be compiled
if {[string compare [lindex $tmp_list 3] "ALTERA"] == 0} {
set setup_altera_lib 0
} else {
set setup_altera_lib 1
}
## quit current simulation
if {$ModelSim} {
quit -sim
} else {
endsim;
clear;
}
#># define library and work directory structure -----------------------------------------------
set vsimversion [regsub -all { } [vsim -version] ""]
set libdir "lib/$vsimversion"
set workdir "lib/$vsimversion/work"
#<#
#># compile sources and test bench ------------------------------------------------------------
#># create directory work ---------------------------------------------------------------------
if {![file isdirectory $workdir]} {
echo "Creating Library Work"
file mkdir $workdir
vlib $workdir
vmap work $workdir
}
#<# -------------------------------------------------------------------------------------------
#># setup Altera libs if necessary ------------------------------------------------------------
if {$setup_altera_lib} {
if [file exists "$libdir\\libs"] {
} else {file mkdir "$libdir\\libs"}
if {![file isdirectory "$libdir/libs/altera"] || $force_lib_compile} {
vlib "$libdir/libs/altera"
vmap altera "$libdir/libs/altera"
vcom -work altera $PathToQuartus/eda/sim_lib/altera_europa_support_lib.vhd
}
if {![file isdirectory "$libdir/libs/altera_mf"] || $force_lib_compile} {
vlib "$libdir/libs/altera_mf"
vmap altera_mf "$libdir/libs/altera_mf"
vcom -work altera_mf \
$PathToQuartus/eda/sim_lib/altera_mf_components.vhd \
$PathToQuartus/eda/sim_lib/altera_mf.vhd
}
if {![file isdirectory "$libdir/libs/lpm"] || $force_lib_compile} {
vlib "$libdir/libs/lpm"
vmap lpm "$libdir/libs/lpm"
vcom -93 -quiet -work lpm \
$PathToQuartus/eda/sim_lib/220pack.vhd \
$PathToQuartus/eda/sim_lib/220model.vhd
}
if {![file isdirectory "$libdir/libs/sgate"] || $force_lib_compile} {
vlib "$libdir/libs/sgate"
vmap sgate "$libdir/libs/sgate"
vcom -93 -quiet -work sgate \
$PathToQuartus/eda/sim_lib/sgate_pack.vhd \
$PathToQuartus/eda/sim_lib/sgate.vhd
}
if {![file isdirectory "$libdir/libs/arriagx_hssi"] || $force_lib_compile} {
vlib "$libdir/libs/arriagx_hssi"
vmap arriagx_hssi "$libdir/libs/arriagx_hssi"
vcom -93 -quiet -work arriagx_hssi \
$PathToQuartus/eda/sim_lib/arriagx_hssi_components.vhd \
$PathToQuartus/eda/sim_lib/arriagx_hssi_atoms.vhd
}
if {![file isdirectory "$libdir/libs/arriaii_hssi"] || $force_lib_compile} {
vlib "$libdir/libs/arriaii_hssi"
vmap arriaii_hssi "$libdir/libs/arriaii_hssi"
vcom -93 -quiet -work arriaii_hssi \
$PathToQuartus/eda/sim_lib/arriaii_hssi_components.vhd \
$PathToQuartus/eda/sim_lib/arriaii_hssi_atoms.vhd
}
if {![file isdirectory "$libdir/libs/stratixiv_hssi"] || $force_lib_compile} {
vlib "$libdir/libs/stratixiv_hssi"
vmap stratixiv_hssi "$libdir/libs/stratixiv_hssi"
vcom -93 -quiet -work stratixiv_hssi \
$PathToQuartus/eda/sim_lib/stratixiv_hssi_components.vhd \
$PathToQuartus/eda/sim_lib/stratixiv_hssi_atoms.vhd
}
if {![file isdirectory "$libdir/libs/cycloneiv_hssi"] || $force_lib_compile} {
vlib "$libdir/libs/cycloneiv_hssi"
vmap cycloneiv_hssi "$libdir/libs/cycloneiv_hssi"
vcom -93 -quiet -work cycloneiv_hssi \
$PathToQuartus/eda/sim_lib/cycloneiv_hssi_components.vhd \
$PathToQuartus/eda/sim_lib/cycloneiv_hssi_atoms.vhd
}
if {![file isdirectory "$libdir/libs/stratixiigx_hssi"] || $force_lib_compile} {
vlib "$libdir/libs/stratixiigx_hssi"
vmap stratixiigx_hssi "$libdir/libs/stratixiigx_hssi"
vcom -93 -quiet -work stratixiigx_hssi \
$PathToQuartus/eda/sim_lib/stratixiigx_hssi_components.vhd \
$PathToQuartus/eda/sim_lib/stratixiigx_hssi_atoms.vhd
}
puts "..prepare ALTERA PHYPCS library"
# vmap phypcs_altera_lib "./PLDA/modelsim/phypcs_altera_lib"
vmap phypcs_altera_lib "$pathToPLDAsimlib/modelsim/phypcs_altera_lib"
vcom -force_refresh -work phypcs_altera_lib
}
#<# -------------------------------------------------------------------------------------------
#># setup modelsim_lib with own vhd file to implement signal spy functionality in RivieraPRO --
if {!$ModelSim} {
if {![file isdirectory "$libdir/libs/modelsim_lib"] || $force_lib_compile} {
vlib "$libdir/libs/modelsim_lib"
vmap modelsim_lib "$libdir/libs/modelsim_lib"
# vcom -work modelsim_lib ../Testbench_2/modelsim_lib.vhd
vcom -work modelsim_lib $modelSimLib/modelsim_lib.vhd
}
}
#<# -------------------------------------------------------------------------------------------
#># setup PLDA libraries ----------------------------------------------------------------------
if {![file isdirectory "$libdir/libs/pciebfm_lib"] || $force_lib_compile} {
if {$ModelSim} {
puts "Creating PLDA BFM library for ModelSim"
# vmap pciebfm_lib "../../../16/16x004-00/Source/PLDA_BFM/modelsim/pciebfm_lib"
vmap pciebfm_lib "$pathToBFM/Source/PLDA_BFM/modelsim/pciebfm_lib"
vcom -force_refresh -work pciebfm_lib
} else {
puts "Creating PLDA BFM library for Aldec"
vlib "libs/pciebfm_lib"
vmap pciebfm_lib "libs/pciebfm_lib"
# vcom -93 -relax -work pciebfm_lib "../../../16/16x004-00/Source/PLDA_BFM/aldec/pciebfm_lib.vhdp"
vcom -93 -relax -work pciebfm_lib "$pathToBFM/Source/PLDA_BFM/aldec/pciebfm_lib.vhdp"
}
}
#<# -------------------------------------------------------------------------------------------
readMe.rst 0000664 0000000 0000000 00000023415 14574545710 0033442 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-00_src .. SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
..
.. SPDX-License-Identifier: CC-BY-SA-4.0+
+-----------------------------------------+
| 16x004-00 Bus Functional Model for PCIe |
+-----------------------------------------+
General description:
This simulation model implements root port functionality for PCIe simulation.
Integration advice:
------------------
This is a short explanation of the constants, functions and procedures provided by the PCIe simulation model.
The simulatin model consists of
- pcie_sim.vhd
-> the PLDA BFM is included here
- pcie_pkg.vhd
----------------------
| pcie_x1_sim.vhd |
----------------------
The included BFM provides a x1 lane functionality. As a maximum of 4 BFM instances can be used, the pcie_sim
entity can be used four times in a component instantiation. Thus the instances can be controlled using
seperate terminal record connections.
------------------
| pcie_x1_pkg |
------------------
constants:
- use IO_TRANSFER, MEM32_TRANSFER and CONFIG_TRANSFER in tga[1:0] for all terminal procedure calls to define
the type of transfer that should be executed
- use BFM_NBR0 ... BFM_NBR_3 in tga[3:2] for all terminal calls to define the BFM instance that should
execute the transfer
- use DONT_CHECK32 as reference data value for every read request t should not check the read value
automatically, the check will be skipped then
functions:
- calc_last_dw
@param first_dw first enabled bytes of this transfer
@param byte_count amount of bytes for this transfer
@return last_dw(3 downto 0) last enabled bytes for this transfer
@detail This function takes the first enabled bytes of a transfer and the amount of bytes that should
be transferred as arguments and calculates the last byte enables. The return value is
std_logic_vector(3 downto 0)
procedures:
- check_val
@param caller_proc string argument which is used in error messages to define the position where
this procedure was called from
@param ref_val 32bit reference value
@param check_val 32bit value that is checked against ref_val
@param byte_valid defines which byte of check_val is valid, invalid bytes are not compared
@return check_ok boolean argument which states whether the check was ok (=true) or not
- init_bfm
@param bfm_inst_nbr number of the BFM instance that will be initialized
@param io_add start address for the BFM internal I/O space
@param mem32_addr start address for the BFM internal MEM32 space
@param mem64_addr start address for the BFM internal MEM64 space
@param requester_id defines the requester ID that is used for every BFM transfer
@param max_payloadsize defines the maximum payload size for every write request
- configure_bfm (for record)
@param cfg_i input record of type cfg_in_type
@return cfg_o returns record of cfg_out_type
- configure_bfm
@param bfm_inst_nbr number of the BFM instance that will be configured
@param max_payload_size maximum payload size for write requests
@param max_read_size maximum payload size for read requests
@param bar0 BAR0 settings
@param bar1 BAR1 settings
@param bar2 BAR2 settings
@param bar3 BAR3 settings
@param bar4 BAR4 settings
@param bar5 BAR5 settings
@param cmd_status_reg settings for the command status register
@param ctrl_status_reg settings for the control status register
- set_bfm_memory
@param bfm_inst_nbr number of the BFM instance that will be used
@param nbr_of_dw number of DWORDS that will be written
@param io_space set to true is I/O space is targeted
@param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
@param mem_addr offset for internal memory space, start at x"0000_0000"
@param start_data_val first data value to write, other values are defined by data_inc
@param data_inc defines the data increment added to start_data_val for DW 2 to nbr_of_dw
- get_bfm_memory
@param bfm_inst_nbr number of the BFM instance that will be used
@param nbr_of_dw number of DWORDS that will be written
@param io_space set to true is I/O space is targeted
@param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
@param mem_addr offset for internal memory space, start at x"0000_0000"
@return databuf_out returns a dword_vector that contains all data read from BFM internal memory
- bfm_wr_io
@param bfm_inst_nbr number of the BFM instance that will be used
@param byte_en bytes enables for this transfer
@param pcie_addr address at DUT to write to
@param data32 32bit data value to write
@param wait_end set to true to wait until transfer is finished and check for transfer errors
@return success returns true if transfer is done and finished without errors (if wait_end = true)
bfm_rd_io
@param bfm_inst_nbr number of the BFM instance that will be used
@param byte_en bytes enables for this transfer
@param pcie_addr address at DUT to read from
@param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
@param wait_end set to true to wait until transfer is finished and check for transfer errors
@return data32_out 32bit data value returned from read
@return success returns true if transfer is done and finished without errors (if wait_end = true)
- bfm_wr_mem32
@param bfm_inst_nbr number of the BFM instance that will be used
@param byte_en bytes enables for this transfer
@param pcie_addr address at DUT to write to
@param data32 32bit data value to write
@param wait_end set to true to wait until transfer is finished and check for transfer errors
@return success returns true if transfer is done and finished without errors (if wait_end = true)
- bfm_wr_mem32
@param bfm_inst_nbr number of the BFM instance that will be used
@param byte_count amount of bytes that shall be transferred
@param pcie_addr address at DUT to write to
@param data32 dword_vector that contains all data values to write
@param t_class defines the traffic class this transfer shall have, use "000" as default
@param attributes defines the attributes this transfer shall have, use "00" as default
@param wait_end set to true to wait until transfer is finished and check for transfer errors
@return success returns true if transfer is done and finished without errors (if wait_end = true)
- bfm_rd_mem32
@param bfm_inst_nbr number of the BFM instance that will be used
@param byte_en bytes enables for this transfer
@param pcie_addr address at DUT to read from
@param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
@param wait_end set to true to wait until transfer is finished and check for transfer errors
@return data32_out 32bit data value returned from read
@return success returns true if transfer is done and finished without errors (if wait_end = true)
- bfm_rd_mem32
@param bfm_inst_nbr number of the BFM instance that will be used
@param byte_count amount of bytes that shall be transferred
@param pcie_addr address at DUT to read from
@param ref_data32 dword_vector that contains the reference data values for read data check, use DONT_CHECK to skip check
@param t_class defines the traffic class this transfer shall have, use "000" as default
@param attributes defines the attributes this transfer shall have, use "00" as default
@param wait_end set to true to wait until transfer is finished and check for transfer errors
@return data32_out dword_vector that contains the data values returned from read
@return success returns true if transfer is done and finished without errors (if wait_end = true)
- bfm_wr_config
@param bfm_inst_nbr number of the BFM instance that will be used
@param byte_en bytes enables for this transfer
@param pcie_addr address at DUT to write to
@param data32 32bit data value to write
@param wait_end set to true to wait until transfer is finished and check for transfer errors
@return success returns true if transfer is done and finished without errors (if wait_end = true)
- bfm_rd_config
@param bfm_inst_nbr number of the BFM instance that will be used
@param byte_en bytes enables for this transfer
@param pcie_addr address at DUT to read from
@param ref_data32 reference data value for read data check, use DONT_CHECK to skip check
@param wait_end set to true to wait until transfer is finished and check for transfer errors
@return data32_out 32bit data value returned from read
@return success returns true if transfer is done and finished without errors (if wait_end = true)
IMPORTANT: add to vsim!! (Path may need adaption)
# Adapt all your paths:
# ---------------------
set modelSimLib "" e.g. "../16/16zxy/Testbench/modelsim_lib.vhd"
set pathToBFM "/16/16x004-00" e.g. "../../../16/16x004-00"
set pathToPLDAsimlib " \
-L altera \
-L altera_mf \
-L lpm \
-L sgate \
-L arriagx_hssi \
-L arriaii_hssi \
-L stratixiv_hssi \
-L cycloneiv_hssi \
-L stratixiigx_hssi \
-L phypcs_altera_lib \
-L pciebfm_lib \
-voptargs=+acc \
work.
- configure_msi
@param bfm_inst_nbr number of the BFM instance that will be used
@param msi_allowed number of MSI that are allowed, coded vector as defined by PCIe spec
@return returns true is the configuration was successful
16x004-01_src/ 0000775 0000000 0000000 00000000000 14574545710 0031507 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench README.rst 0000664 0000000 0000000 00000000460 14574545710 0033176 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-01_src .. SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
..
.. SPDX-License-Identifier: CC-BY-SA-4.0+
16x004-01 Bus Functional Model for PCIe
=======================================
General description
-------------------
This simulation model implements root port functionality for PCIe simulation.
Source/ 0000775 0000000 0000000 00000000000 14574545710 0032747 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-01_src pcie_sim.vhd 0000664 0000000 0000000 00000310046 14574545710 0035246 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-01_src/Source -- SPDX-FileCopyrightText: 2017, MEN Mikro Elektronik Nuremberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : PCIe simulation model
-- Project : -
--------------------------------------------------------------------------------
-- File : pcie_sim.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2017-05-26
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6
-- Synthesis : -
--------------------------------------------------------------------------------
-- Description :
-- PCIe simulation model for x1, x2, x4 and x8 configurations.
-- The BFM shared memory is configured to be 2 MBytes. It is mapped into
-- the first 2 MBytes of I/O space and also the first 2 MBytes of memory
-- space. The BFM is assigned to device number 0 on internal bus number 0.
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.altpcietb_bfm_constants.all;
use work.altpcietb_bfm_log.all;
use work.altpcietb_bfm_shmem.all;
use work.altpcietb_bfm_rdwr.all;
use work.altpcietb_bfm_configure.all;
use work.utils_pkg.all;
use work.pcie_sim_pkg.all;
use work.print_pkg.all;
use work.terminal_pkg.all;
entity pcie_sim is
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
port(
rst_i : in std_logic;
pcie_rstn_i : in std_logic;
clk_i : in std_logic;
ep_clk250_i : in std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_i : in std_logic; -- endpoint SERDES 500MHz clk output
-- PCIe lanes
bfm_tx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
bfm_rx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i : in std_logic; -- endpoint rate_ext
ep_powerdown_ext_i : in std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_i : in std_logic_vector(4 downto 0);
ep_rxvalid_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_o : out std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
-- MEN terminal connection, in/out references are terminal view
term_out : in terminal_out_type;
term_in : out terminal_in_type
);
end entity pcie_sim;
architecture pcie_sim_arch of pcie_sim is
type bar_addr_array is array (5 downto 0) of std_logic_vector(31 downto 0);
type bar_limit_array is array (5 downto 0) of natural;
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component altpcietb_bfm_rp_top_x8_pipen1b is
port(
signal rxdata4_ext : in std_logic_vector(7 downto 0);
signal rx_in7 : in std_logic;
signal phystatus5_ext : in std_logic;
signal rxdata5_ext : in std_logic_vector(7 downto 0);
signal phystatus1_ext : in std_logic;
signal pipe_mode : in std_logic;
signal rxstatus3_ext : in std_logic_vector(2 downto 0);
signal pcie_rstn : in std_logic;
signal rxelecidle7_ext : in std_logic;
signal rxelecidle0_ext : in std_logic;
signal clk500_in : in std_logic;
signal rxelecidle3_ext : in std_logic;
signal rxdatak1_ext : in std_logic;
signal phystatus0_ext : in std_logic;
signal rx_in0 : in std_logic;
signal rx_in5 : in std_logic;
signal rxelecidle5_ext : in std_logic;
signal rxvalid1_ext : in std_logic;
signal rx_in2 : in std_logic;
signal rx_in3 : in std_logic;
signal rxdatak3_ext : in std_logic;
signal clk250_in : in std_logic;
signal phystatus6_ext : in std_logic;
signal rxdata6_ext : in std_logic_vector(7 downto 0);
signal rxdata3_ext : in std_logic_vector(7 downto 0);
signal rxstatus5_ext : in std_logic_vector(2 downto 0);
signal rxstatus1_ext : in std_logic_vector(2 downto 0);
signal rxdata0_ext : in std_logic_vector(7 downto 0);
signal rxvalid7_ext : in std_logic;
signal phystatus7_ext : in std_logic;
signal rxdata2_ext : in std_logic_vector(7 downto 0);
signal rxvalid5_ext : in std_logic;
signal rxvalid0_ext : in std_logic;
signal rxdatak2_ext : in std_logic;
signal rxstatus4_ext : in std_logic_vector(2 downto 0);
signal rxdatak7_ext : in std_logic;
signal rxstatus0_ext : in std_logic_vector(2 downto 0);
signal phystatus3_ext : in std_logic;
signal rxelecidle4_ext : in std_logic;
signal phystatus2_ext : in std_logic;
signal rxvalid4_ext : in std_logic;
signal rx_in6 : in std_logic;
signal rx_in1 : in std_logic;
signal rxstatus2_ext : in std_logic_vector(2 downto 0);
signal rxdata7_ext : in std_logic_vector(7 downto 0);
signal rxdatak0_ext : in std_logic;
signal rxelecidle1_ext : in std_logic;
signal rxdata1_ext : in std_logic_vector(7 downto 0);
signal rxstatus6_ext : in std_logic_vector(2 downto 0);
signal test_in : in std_logic_vector(31 downto 0);
signal rx_in4 : in std_logic;
signal rxdatak4_ext : in std_logic;
signal rxelecidle2_ext : in std_logic;
signal rxdatak5_ext : in std_logic;
signal rxstatus7_ext : in std_logic_vector(2 downto 0);
signal rxelecidle6_ext : in std_logic;
signal rxvalid3_ext : in std_logic;
signal rxvalid2_ext : in std_logic;
signal phystatus4_ext : in std_logic;
signal rxvalid6_ext : in std_logic;
signal local_rstn : in std_logic;
signal rxdatak6_ext : in std_logic;
signal tx_out6 : out std_logic;
signal tx_out4 : out std_logic;
signal txdatak4_ext : out std_logic;
signal txelecidle0_ext : out std_logic;
signal txdatak1_ext : out std_logic;
signal test_out : out std_logic_vector(511 downto 0);
signal txelecidle2_ext : out std_logic;
signal txdatak7_ext : out std_logic;
signal txdatak2_ext : out std_logic;
signal txcompl4_ext : out std_logic;
signal rxpolarity5_ext : out std_logic;
signal rxpolarity4_ext : out std_logic;
signal powerdown7_ext : out std_logic_vector(1 downto 0);
signal txdetectrx7_ext : out std_logic;
signal txelecidle1_ext : out std_logic;
signal tx_out3 : out std_logic;
signal rxpolarity3_ext : out std_logic;
signal txdata0_ext : out std_logic_vector(7 downto 0);
signal txdetectrx1_ext : out std_logic;
signal powerdown0_ext : out std_logic_vector(1 downto 0);
signal txdata1_ext : out std_logic_vector(7 downto 0);
signal txdatak6_ext : out std_logic;
signal txdata3_ext : out std_logic_vector(7 downto 0);
signal txcompl7_ext : out std_logic;
signal txdata4_ext : out std_logic_vector(7 downto 0);
signal powerdown3_ext : out std_logic_vector(1 downto 0);
signal txcompl5_ext : out std_logic;
signal txcompl0_ext : out std_logic;
signal txdetectrx5_ext : out std_logic;
signal txcompl1_ext : out std_logic;
signal powerdown1_ext : out std_logic_vector(1 downto 0);
signal txelecidle7_ext : out std_logic;
signal swdn_out : out std_logic_vector(5 downto 0);
signal txelecidle6_ext : out std_logic;
signal tx_out0 : out std_logic;
signal powerdown6_ext : out std_logic_vector(1 downto 0);
signal rxpolarity0_ext : out std_logic;
signal tx_out2 : out std_logic;
signal txdetectrx2_ext : out std_logic;
signal txdata5_ext : out std_logic_vector(7 downto 0);
signal txelecidle3_ext : out std_logic;
signal txdatak3_ext : out std_logic;
signal txdetectrx0_ext : out std_logic;
signal rxpolarity6_ext : out std_logic;
signal powerdown2_ext : out std_logic_vector(1 downto 0);
signal rate_ext : out std_logic;
signal txcompl3_ext : out std_logic;
signal txdetectrx6_ext : out std_logic;
signal tx_out5 : out std_logic;
signal rxpolarity2_ext : out std_logic;
signal tx_out7 : out std_logic;
signal tx_out1 : out std_logic;
signal txdetectrx3_ext : out std_logic;
signal txdata6_ext : out std_logic_vector(7 downto 0);
signal txcompl2_ext : out std_logic;
signal rxpolarity1_ext : out std_logic;
signal txelecidle4_ext : out std_logic;
signal txdata2_ext : out std_logic_vector(7 downto 0);
signal powerdown4_ext : out std_logic_vector(1 downto 0);
signal txcompl6_ext : out std_logic;
signal txdatak5_ext : out std_logic;
signal txdata7_ext : out std_logic_vector(7 downto 0);
signal txdatak0_ext : out std_logic;
signal rxpolarity7_ext : out std_logic;
signal powerdown5_ext : out std_logic_vector(1 downto 0);
signal txdetectrx4_ext : out std_logic;
signal txelecidle5_ext : out std_logic
);
end component altpcietb_bfm_rp_top_x8_pipen1b;
component altpcietb_pipe_phy is
generic(
APIPE_WIDTH : natural;
BPIPE_WIDTH : natural;
LANE_NUM : natural
);
port(
signal b_powerdown : in std_logic_vector(1 downto 0);
signal a_txdatak : in std_logic_vector(0 downto 0);
signal pipe_mode : in std_logic;
signal a_powerdown : in std_logic_vector(1 downto 0);
signal b_txcompl : in std_logic;
signal b_lane_conn : in std_logic;
signal b_txdetectrx : in std_logic;
signal pclk_a : in std_logic;
signal b_txelecidle : in std_logic;
signal a_lane_conn : in std_logic;
signal resetn : in std_logic;
signal a_txdata : in std_logic_vector(7 downto 0);
signal b_rate : in std_logic;
signal a_txcompl : in std_logic;
signal pclk_b : in std_logic;
signal a_txelecidle : in std_logic;
signal a_txdetectrx : in std_logic;
signal a_rxpolarity : in std_logic;
signal b_txdata : in std_logic_vector(7 downto 0);
signal b_rxpolarity : in std_logic;
signal b_txdatak : in std_logic_vector(0 downto 0);
signal a_rate : in std_logic;
signal a_rxvalid : out std_logic;
signal a_rxstatus : out std_logic_vector(2 downto 0);
signal b_phystatus : out std_logic;
signal b_rxvalid : out std_logic;
signal a_rxdatak : out std_logic_vector(0 downto 0);
signal b_rxelecidle : out std_logic;
signal b_rxdatak : out std_logic_vector(0 downto 0);
signal a_rxdata : out std_logic_vector(7 downto 0);
signal b_rxdata : out std_logic_vector(7 downto 0);
signal a_rxelecidle : out std_logic;
signal a_phystatus : out std_logic;
signal b_rxstatus : out std_logic_vector(2 downto 0)
);
end component altpcietb_pipe_phy;
component altpcietb_ltssm_mon is
port(
signal rp_clk : in std_logic;
signal ep_ltssm : in std_logic_vector (4 downto 0);
signal rstn : in std_logic;
signal rp_ltssm : in std_logic_vector (4 downto 0);
signal dummy_out : out std_logic
);
end component altpcietb_ltssm_mon;
-- +----------------------------------------------------------------------------
-- | functions
-- +----------------------------------------------------------------------------
function get_bar_limit(bar_addr : std_logic_vector(31 downto 0); bar_num : natural)
return natural is
variable var_log2_size : natural;
variable var_is_mem : std_logic;
variable var_is_pref : std_logic;
variable var_is_64b : std_logic;
begin
ebfm_cfg_decode_bar(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
log2_size => var_log2_size,
is_mem => var_is_mem,
is_pref => var_is_pref,
is_64b => var_is_64b
);
return var_log2_size;
end function get_bar_limit;
-- +----------------------------------------------------------------------------
-- | procedures
-- +----------------------------------------------------------------------------
procedure get_pcie_addr_and_offset(
pcie_addr : in std_logic_vector(31 downto 0);
bar_addr : in bar_addr_array;
bar_limit : in bar_limit_array;
bar_num : out natural;
bar_offset : out natural
) is
variable var_act_limit : natural := 0;
variable var_act_addr : std_logic_vector(31 downto 0) := (others => '0');
variable var_act_offset : std_logic_vector(31 downto 0) := (others => '0');
variable var_bar_num : natural := 6;
begin
-- loop through all BARs and check for matches
-- address must match from MSB of address to actual limit value
-- address offset for BAR is from limit downto 0
loop_1 : for i in 0 to 5 loop
var_act_limit := bar_limit(i);
var_act_offset := ZERO_32BIT(31 downto var_act_limit) & pcie_addr(var_act_limit -1 downto 0);
var_act_addr := pcie_addr(31 downto var_act_limit) & ZERO_32BIT(var_act_limit -1 downto 0);
if bar_addr(i) = var_act_addr then
var_bar_num := i;
exit loop_1;
else
-- set to invalid value to denote error condition
var_bar_num := 6;
end if;
end loop;
if var_bar_num = 6 then
report "ERROR (pcie_sim.vhd->get_pcie_addr_and_offset(): given PCIe address does not match stored BAR addresses" severity error;
else
bar_num := var_bar_num;
bar_offset := to_integer(unsigned(var_act_offset));
end if;
end procedure get_pcie_addr_and_offset;
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
-- BFM connections
signal bfm_rate_int : std_logic;
signal bfm_pipe_mode_int : std_logic;
signal bfm_pclk_int : std_logic;
signal lane_pclk_int : std_logic;
signal bfm_rstn_delayed : std_logic := '0';
signal bfm_txcompl_0_int : std_logic;
signal bfm_txcompl_1_int : std_logic;
signal bfm_txcompl_2_int : std_logic;
signal bfm_txcompl_3_int : std_logic;
signal bfm_txcompl_4_int : std_logic;
signal bfm_txcompl_5_int : std_logic;
signal bfm_txcompl_6_int : std_logic;
signal bfm_txcompl_7_int : std_logic;
signal bfm_txdetectrx_0_int : std_logic;
signal bfm_txdetectrx_1_int : std_logic;
signal bfm_txdetectrx_2_int : std_logic;
signal bfm_txdetectrx_3_int : std_logic;
signal bfm_txdetectrx_4_int : std_logic;
signal bfm_txdetectrx_5_int : std_logic;
signal bfm_txdetectrx_6_int : std_logic;
signal bfm_txdetectrx_7_int : std_logic;
signal bfm_txelecidle_0_int : std_logic;
signal bfm_txelecidle_1_int : std_logic;
signal bfm_txelecidle_2_int : std_logic;
signal bfm_txelecidle_3_int : std_logic;
signal bfm_txelecidle_4_int : std_logic;
signal bfm_txelecidle_5_int : std_logic;
signal bfm_txelecidle_6_int : std_logic;
signal bfm_txelecidle_7_int : std_logic;
signal bfm_rxpolarity_0_int : std_logic;
signal bfm_rxpolarity_1_int : std_logic;
signal bfm_rxpolarity_2_int : std_logic;
signal bfm_rxpolarity_3_int : std_logic;
signal bfm_rxpolarity_4_int : std_logic;
signal bfm_rxpolarity_5_int : std_logic;
signal bfm_rxpolarity_6_int : std_logic;
signal bfm_rxpolarity_7_int : std_logic;
signal bfm_phystatus_0_int : std_logic;
signal bfm_phystatus_1_int : std_logic;
signal bfm_phystatus_2_int : std_logic;
signal bfm_phystatus_3_int : std_logic;
signal bfm_phystatus_4_int : std_logic;
signal bfm_phystatus_5_int : std_logic;
signal bfm_phystatus_6_int : std_logic;
signal bfm_phystatus_7_int : std_logic;
signal bfm_rxvalid_0_int : std_logic;
signal bfm_rxvalid_1_int : std_logic;
signal bfm_rxvalid_2_int : std_logic;
signal bfm_rxvalid_3_int : std_logic;
signal bfm_rxvalid_4_int : std_logic;
signal bfm_rxvalid_5_int : std_logic;
signal bfm_rxvalid_6_int : std_logic;
signal bfm_rxvalid_7_int : std_logic;
signal bfm_rxelecidle_0_int : std_logic;
signal bfm_rxelecidle_1_int : std_logic;
signal bfm_rxelecidle_2_int : std_logic;
signal bfm_rxelecidle_3_int : std_logic;
signal bfm_rxelecidle_4_int : std_logic;
signal bfm_rxelecidle_5_int : std_logic;
signal bfm_rxelecidle_6_int : std_logic;
signal bfm_rxelecidle_7_int : std_logic;
signal bfm_rxdatak_0_int : std_logic;
signal bfm_rxdatak_1_int : std_logic;
signal bfm_rxdatak_2_int : std_logic;
signal bfm_rxdatak_3_int : std_logic;
signal bfm_rxdatak_4_int : std_logic;
signal bfm_rxdatak_5_int : std_logic;
signal bfm_rxdatak_6_int : std_logic;
signal bfm_rxdatak_7_int : std_logic;
signal bfm_rx_int : std_logic_vector(7 downto 0) := (others => '1');
signal bfm_tx_int : std_logic_vector(7 downto 0) := (others => 'Z');
signal bfm_test_in_int : std_logic_vector(31 downto 0);
signal bfm_irq_int : std_logic_vector(5 downto 0);
signal bfm_ltssm_rp : std_logic_vector(4 downto 0);
signal test_out_int : std_logic_vector(511 downto 0);
signal bfm_txdata_0_int : std_logic_vector(7 downto 0);
signal bfm_txdata_1_int : std_logic_vector(7 downto 0);
signal bfm_txdata_2_int : std_logic_vector(7 downto 0);
signal bfm_txdata_3_int : std_logic_vector(7 downto 0);
signal bfm_txdata_4_int : std_logic_vector(7 downto 0);
signal bfm_txdata_5_int : std_logic_vector(7 downto 0);
signal bfm_txdata_6_int : std_logic_vector(7 downto 0);
signal bfm_txdata_7_int : std_logic_vector(7 downto 0);
signal bfm_txdatak_0_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_1_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_2_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_3_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_4_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_5_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_6_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_7_int : std_logic_vector(0 downto 0);
signal bfm_powerdown_0_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_1_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_2_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_3_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_4_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_5_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_6_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_7_int : std_logic_vector(1 downto 0);
signal bfm_rxdata_0_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_1_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_2_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_3_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_4_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_5_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_6_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_7_int : std_logic_vector(7 downto 0);
signal bfm_rxstatus_0_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_1_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_2_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_3_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_4_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_5_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_6_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_7_int : std_logic_vector(2 downto 0);
signal bar_addr : bar_addr_array;
signal bar_limit : bar_limit_array;
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
assert (BFM_LANE_WIDTH = 1 or BFM_LANE_WIDTH = 2 or BFM_LANE_WIDTH = 4 or BFM_LANE_WIDTH = 8)
report "ERROR (pcie_sim.vhd): invalid value for generic BFM_LANE_WIDTH; use 1, 2, 4, or 8!" severity failure;
-- clock switch
bfm_pclk_int <= ep_clk500_i when bfm_rate_int = '1' else ep_clk250_i;
lane_pclk_int <= ep_clk500_i when ep_rate_ext_i = '1' else ep_clk250_i;
-- delay reset for BFM by 100 ns
bfm_rstn_delayed <= transport pcie_rstn_i after 100 ns;
bfm_pipe_mode_int <= '1';
bfm_test_in_int(31 downto 8) <= (others => '0');
bfm_test_in_int(7) <= not bfm_pipe_mode_int; -- disable entrance to low power mode
bfm_test_in_int(6) <= '0';
bfm_test_in_int(5) <= '1'; -- disable polling.compliance
bfm_test_in_int(4) <= '0';
bfm_test_in_int(3) <= not bfm_pipe_mode_int; -- forces all lanes to detect the receiver
bfm_test_in_int(2 downto 1) <= (others => '0');
bfm_test_in_int(0) <= '1'; -- speed up simulation by making counters faster than normal
bfm_ltssm_rp <= test_out_int(324 downto 320);
bfm_rx_o(BFM_LANE_WIDTH -1 downto 0) <= bfm_rx_int(BFM_LANE_WIDTH -1 downto 0);
bfm_tx_int(BFM_LANE_WIDTH -1 downto 0) <= bfm_tx_i(BFM_LANE_WIDTH -1 downto 0);
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
main : process
variable first_be_en : std_logic_vector(3 downto 0);
variable byte_count : integer;
variable addr32_int : std_logic_vector(31 downto 0);
variable bfm_id : integer := 0;
variable success_int : boolean := false;
variable return_data32 : std_logic_vector(31 downto 0) := (others => '0');
variable return_data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_bar_num : natural;
variable var_bar_offset : natural;
variable var_bar0_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar1_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar2_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar3_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar4_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar5_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar0_limit : natural := 0;
variable var_bar1_limit : natural := 0;
variable var_bar2_limit : natural := 0;
variable var_bar3_limit : natural := 0;
variable var_bar4_limit : natural := 0;
variable var_bar5_limit : natural := 0;
begin
-- reset all
term_in.busy <= '1';
term_in.done <= true;
wait until rst_i = '0';
wait_clk(clk_i,1);
if term_out.start /= true then
wait until term_out.start = true;
end if;
loop
wait on term_out.start;
term_in.busy <= '1';
term_in.err <= 0;
success_int := false;
---------------------------
-- check for wrong values
---------------------------
assert term_out.typ <= 2 report "ERROR (pcie_sim): illegal value for signal term_out.typ" severity failure;
assert term_out.wr <= 2 report "ERROR (pcie_sim): illegal value for signal term_out.wr" severity failure;
if term_out.typ = 0 then
assert term_out.numb = 1 report "ERROR (pcie_sim): illegal combination for signals term_out.typ and term_out.numb => bytewise burst is impossible" severity failure;
end if;
if term_out.typ = 1 then
assert term_out.numb = 1 report "ERROR (pcie_sim): illegal combination for signals term_out.typ and term_out.numb => wordwise burst is impossible" severity failure;
end if;
assert term_out.numb <= 1024 report "ERROR (pcie_sim): maximum value for signal term_out.numb is 1024" severity failure;
----------------------------
-- set values for this run
----------------------------
addr32_int := term_out.adr(31 downto 2) & "00";
bfm_id := to_integer(unsigned(term_out.tga(3 downto 2)));
if term_out.typ = 0 then -- byte
byte_count := 1;
if term_out.adr(1 downto 0) = "01" then
first_be_en := "0010";
elsif term_out.adr(1 downto 0) = "10" then
first_be_en := "0100";
elsif term_out.adr(1 downto 0) = "11" then
first_be_en := "1000";
else
first_be_en := "0001";
end if;
elsif term_out.typ = 1 then -- word
byte_count := 2;
if term_out.adr(1) = '0' then
first_be_en := "0011";
else
first_be_en := "1100";
end if;
else -- long word
byte_count := term_out.numb *4;
first_be_en := x"F";
end if;
for i in 0 to term_out.numb -1 loop
data_vec(i) := std_logic_vector(unsigned(term_out.dat) + to_unsigned(i,32));
return_data_vec(i) := (others => '0');
wait for 0 ns;
end loop;
if term_out.wr = 0 then -- read
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
report "ERROR(pcie_sim): I/O transfer not supported" severity error;
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
get_pcie_addr_and_offset(
pcie_addr => addr32_int,
bar_addr => bar_addr,
bar_limit => bar_limit,
bar_num => var_bar_num,
bar_offset => var_bar_offset
);
if term_out.numb = 1 then
bfm_rd_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_en => first_be_en,
ref_data32 => term_out.dat,
data32_out => return_data32,
success => success_int
);
else
bfm_rd_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
ref_data32 => data_vec,
data32_out => return_data_vec,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
return_data32 := x"FADE_FADE";
bfm_rd_config(
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
data32_out => return_data32,
success => success_int
);
else
assert false report "ERROR (pcie_sim): term_out.tga(1 downto 0) = 11 is reserved for reads" severity failure;
end if;
elsif term_out.wr = 1 then -- write
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
report "ERROR(pcie_sim): I/O transfer not supported" severity error;
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
get_pcie_addr_and_offset(
pcie_addr => term_out.adr,
bar_addr => bar_addr,
bar_limit => bar_limit,
bar_num => var_bar_num,
bar_offset => var_bar_offset
);
if term_out.numb = 1 then
bfm_wr_mem32(
pcie_addr => term_out.adr(1 downto 0),
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
data32 => term_out.dat,
success => success_int
);
else
bfm_wr_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
data32 => data_vec,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
bfm_wr_config(
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
data32 => term_out.dat,
success => success_int
);
else
-- => term_out.tga(1 downto 0) = SETUP_CYCLE then -- BFM setup
if term_out.txt >= 2 then
print("pcie_sim.vhd: starting SETUP_CYCLE");
end if;
if term_out.adr(2 downto 0) = "000" then -- BAR0
var_bar0_addr := term_out.dat;
var_bar0_limit := get_bar_limit(bar_addr => var_bar0_addr, bar_num => 0);
bar_addr(0) <= var_bar0_addr;
bar_limit(0) <= var_bar0_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "001" then -- BAR1
var_bar1_addr := term_out.dat;
var_bar1_limit := get_bar_limit(bar_addr => var_bar1_addr, bar_num => 1);
bar_addr(1) <= var_bar1_addr;
bar_limit(1) <= var_bar1_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "010" then -- BAR2
var_bar2_addr := term_out.dat;
var_bar2_limit := get_bar_limit(bar_addr => var_bar2_addr, bar_num => 2);
bar_addr(2) <= var_bar2_addr;
bar_limit(2) <= var_bar2_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "011" then -- BAR3
var_bar3_addr := term_out.dat;
var_bar3_limit := get_bar_limit(bar_addr => var_bar3_addr, bar_num => 3);
bar_addr(3) <= var_bar3_addr;
bar_limit(3) <= var_bar3_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "100" then -- BAR4
var_bar4_addr := term_out.dat;
var_bar4_limit := get_bar_limit(bar_addr => var_bar4_addr, bar_num => 4);
bar_addr(4) <= var_bar4_addr;
bar_limit(4) <= var_bar4_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "101" then -- BAR5
var_bar5_addr := term_out.dat;
var_bar5_limit := get_bar_limit(bar_addr => var_bar5_addr, bar_num => 5);
bar_addr(5) <= var_bar5_addr;
bar_limit(5) <= var_bar5_limit;
success_int := true;
else
report "ERROR: pcie_sim.vhd: term_out.tga is set to SETUP_CYCLE but term_out.adr has an invalid value!" &
" Use values 000 to 101." severity error;
end if;
wait_clk(clk_i,1);
end if;
else -- wait
wait_clk(clk_i,term_out.numb);
end if;
--------------------------------------
-- return values and finish transfer
--------------------------------------
term_in.dat <= return_data32;
if success_int then
term_in.err <= 0;
else
term_in.err <= 1;
end if;
term_in.busy <= '0';
term_in.done <= term_out.start;
end loop;
end process main;
-- +----------------------------------------------------------------------------
-- | component instanciation section
-- +----------------------------------------------------------------------------
bfm_inst: altpcietb_bfm_rp_top_x8_pipen1b
port map(
pcie_rstn => bfm_rstn_delayed, --pcie_rstn_i,
local_rstn => '1',
clk250_in => ep_clk250_i,
clk500_in => ep_clk500_i,
pipe_mode => bfm_pipe_mode_int,
rxdata4_ext => bfm_rxdata_4_int,
rx_in7 => bfm_rx_int(7),
phystatus5_ext => bfm_phystatus_5_int,
rxdata5_ext => bfm_rxdata_5_int,
phystatus1_ext => bfm_phystatus_1_int,
rxstatus3_ext => bfm_rxstatus_3_int,
rxelecidle7_ext => bfm_rxelecidle_7_int,
rxelecidle0_ext => bfm_rxelecidle_0_int,
rxelecidle3_ext => bfm_rxelecidle_3_int,
rxdatak1_ext => bfm_rxdatak_1_int,
phystatus0_ext => bfm_phystatus_0_int,
rx_in0 => bfm_rx_int(0),
rx_in5 => bfm_rx_int(5),
rxelecidle5_ext => bfm_rxelecidle_5_int,
rxvalid1_ext => bfm_rxvalid_1_int,
rx_in2 => bfm_rx_int(2),
rx_in3 => bfm_rx_int(3),
rxdatak3_ext => bfm_rxdatak_3_int,
phystatus6_ext => bfm_phystatus_6_int,
rxdata6_ext => bfm_rxdata_6_int,
rxdata3_ext => bfm_rxdata_3_int,
rxstatus5_ext => bfm_rxstatus_5_int,
rxstatus1_ext => bfm_rxstatus_1_int,
rxdata0_ext => bfm_rxdata_0_int,
rxvalid7_ext => bfm_rxvalid_7_int,
phystatus7_ext => bfm_phystatus_7_int,
rxdata2_ext => bfm_rxdata_2_int,
rxvalid5_ext => bfm_rxvalid_5_int,
rxvalid0_ext => bfm_rxvalid_0_int,
rxdatak2_ext => bfm_rxdatak_2_int,
rxstatus4_ext => bfm_rxstatus_4_int,
rxdatak7_ext => bfm_rxdatak_7_int,
rxstatus0_ext => bfm_rxstatus_0_int,
phystatus3_ext => bfm_phystatus_3_int,
rxelecidle4_ext => bfm_rxelecidle_4_int,
phystatus2_ext => bfm_phystatus_2_int,
rxvalid4_ext => bfm_rxvalid_4_int,
rx_in6 => bfm_rx_int(6),
rx_in1 => bfm_rx_int(1),
rxstatus2_ext => bfm_rxstatus_2_int,
rxdata7_ext => bfm_rxdata_7_int,
rxdatak0_ext => bfm_rxdatak_0_int,
rxelecidle1_ext => bfm_rxelecidle_1_int,
rxdata1_ext => bfm_rxdata_1_int,
rxstatus6_ext => bfm_rxstatus_6_int,
test_in => bfm_test_in_int,
rx_in4 => bfm_rx_int(4),
rxdatak4_ext => bfm_rxdatak_4_int,
rxelecidle2_ext => bfm_rxelecidle_2_int,
rxdatak5_ext => bfm_rxdatak_5_int,
rxstatus7_ext => bfm_rxstatus_7_int,
rxelecidle6_ext => bfm_rxelecidle_6_int,
rxvalid3_ext => bfm_rxvalid_3_int,
rxvalid2_ext => bfm_rxvalid_2_int,
phystatus4_ext => bfm_phystatus_4_int,
rxvalid6_ext => bfm_rxvalid_6_int,
rxdatak6_ext => bfm_rxdatak_6_int,
tx_out6 => bfm_tx_int(6),
tx_out4 => bfm_tx_int(4),
txdatak4_ext => bfm_txdatak_4_int(0),
txelecidle0_ext => bfm_txelecidle_0_int,
txdatak1_ext => bfm_txdatak_1_int(0),
test_out => test_out_int,
txelecidle2_ext => bfm_txelecidle_2_int,
txdatak7_ext => bfm_txdatak_7_int(0),
txdatak2_ext => bfm_txdatak_2_int(0),
txcompl4_ext => bfm_txcompl_4_int,
rxpolarity5_ext => bfm_rxpolarity_5_int,
rxpolarity4_ext => bfm_rxpolarity_4_int,
powerdown7_ext => bfm_powerdown_7_int,
txdetectrx7_ext => bfm_txdetectrx_7_int,
txelecidle1_ext => bfm_txelecidle_1_int,
tx_out3 => bfm_tx_int(3),
rxpolarity3_ext => bfm_rxpolarity_3_int,
txdata0_ext => bfm_txdata_0_int,
txdetectrx1_ext => bfm_txdetectrx_1_int,
powerdown0_ext => bfm_powerdown_0_int,
txdata1_ext => bfm_txdata_1_int,
txdatak6_ext => bfm_txdatak_6_int(0),
txdata3_ext => bfm_txdata_3_int,
txcompl7_ext => bfm_txcompl_7_int,
txdata4_ext => bfm_txdata_4_int,
powerdown3_ext => bfm_powerdown_3_int,
txcompl5_ext => bfm_txcompl_5_int,
txcompl0_ext => bfm_txcompl_0_int,
txdetectrx5_ext => bfm_txdetectrx_5_int,
txcompl1_ext => bfm_txcompl_1_int,
powerdown1_ext => bfm_powerdown_1_int,
txelecidle7_ext => bfm_txelecidle_7_int,
swdn_out => bfm_irq_int,
txelecidle6_ext => bfm_txelecidle_6_int,
tx_out0 => bfm_tx_int(0),
powerdown6_ext => bfm_powerdown_6_int,
rxpolarity0_ext => bfm_rxpolarity_0_int,
tx_out2 => bfm_tx_int(2),
txdetectrx2_ext => bfm_txdetectrx_2_int,
txdata5_ext => bfm_txdata_5_int,
txelecidle3_ext => bfm_txelecidle_3_int,
txdatak3_ext => bfm_txdatak_3_int(0),
txdetectrx0_ext => bfm_txdetectrx_0_int,
rxpolarity6_ext => bfm_rxpolarity_6_int,
powerdown2_ext => bfm_powerdown_2_int,
rate_ext => bfm_rate_int,
txcompl3_ext => bfm_txcompl_3_int,
txdetectrx6_ext => bfm_txdetectrx_6_int,
tx_out5 => bfm_tx_int(5),
rxpolarity2_ext => bfm_rxpolarity_2_int,
tx_out7 => bfm_tx_int(7),
tx_out1 => bfm_tx_int(1),
txdetectrx3_ext => bfm_txdetectrx_3_int,
txdata6_ext => bfm_txdata_6_int,
txcompl2_ext => bfm_txcompl_2_int,
rxpolarity1_ext => bfm_rxpolarity_1_int,
txelecidle4_ext => bfm_txelecidle_4_int,
txdata2_ext => bfm_txdata_2_int,
powerdown4_ext => bfm_powerdown_4_int,
txcompl6_ext => bfm_txcompl_6_int,
txdatak5_ext => bfm_txdatak_5_int(0),
txdata7_ext => bfm_txdata_7_int,
txdatak0_ext => bfm_txdatak_0_int(0),
rxpolarity7_ext => bfm_rxpolarity_7_int,
powerdown5_ext => bfm_powerdown_5_int,
txdetectrx4_ext => bfm_txdetectrx_4_int,
txelecidle5_ext => bfm_txelecidle_5_int
);
----------------------
-- use LTSSM monitor
----------------------
ltssm_mon : altpcietb_ltssm_mon
port map(
ep_ltssm => ep_ltssm_i,
rp_clk => bfm_pclk_int,
rp_ltssm => bfm_ltssm_rp,
rstn => pcie_rstn_i,
dummy_out => open
);
------------------------
-- manage unused lanes
------------------------
--manage_lanes: if BFM_LANE_WIDTH = 1 generate
manage_x1_lanes: if BFM_LANE_WIDTH = 1 generate
-- x1 configuration, BFM connected with 1 lane, using dummy transceiver for lanes 2 to 8
x1_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x1_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_1_int,
b_txcompl => bfm_txcompl_1_int,
b_txdetectrx => bfm_txdetectrx_1_int,
b_txelecidle => bfm_txelecidle_1_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_1_int,
b_rxpolarity => bfm_rxpolarity_1_int,
b_txdatak => bfm_txdatak_1_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_1_int,
b_rxvalid => bfm_rxvalid_1_int,
b_rxelecidle => bfm_rxelecidle_1_int,
b_rxdatak(0) => bfm_rxdatak_1_int,
b_rxdata => bfm_rxdata_1_int,
b_rxstatus => bfm_rxstatus_1_int
);
x1_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_2_int,
b_txcompl => bfm_txcompl_2_int,
b_txdetectrx => bfm_txdetectrx_2_int,
b_txelecidle => bfm_txelecidle_2_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_2_int,
b_rxpolarity => bfm_rxpolarity_2_int,
b_txdatak => bfm_txdatak_2_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_2_int,
b_rxvalid => bfm_rxvalid_2_int,
b_rxelecidle => bfm_rxelecidle_2_int,
b_rxdatak(0) => bfm_rxdatak_2_int,
b_rxdata => bfm_rxdata_2_int,
b_rxstatus => bfm_rxstatus_2_int
);
x1_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_3_int,
b_txcompl => bfm_txcompl_3_int,
b_txdetectrx => bfm_txdetectrx_3_int,
b_txelecidle => bfm_txelecidle_3_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_3_int,
b_rxpolarity => bfm_rxpolarity_3_int,
b_txdatak => bfm_txdatak_3_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_3_int,
b_rxvalid => bfm_rxvalid_3_int,
b_rxelecidle => bfm_rxelecidle_3_int,
b_rxdatak(0) => bfm_rxdatak_3_int,
b_rxdata => bfm_rxdata_3_int,
b_rxstatus => bfm_rxstatus_3_int
);
x1_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x1_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x1_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x1_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x1_lanes;
--elsif BFM_LANE_WIDTH = 2 generate
manage_x2_lanes : if BFM_LANE_WIDTH = 2 generate
-- x2 configuration, BFM connected with 2 lanes, using dummy transceiver for lanes 3 to 8
x2_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x2_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x2_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_2_int,
b_txcompl => bfm_txcompl_2_int,
b_txdetectrx => bfm_txdetectrx_2_int,
b_txelecidle => bfm_txelecidle_2_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_2_int,
b_rxpolarity => bfm_rxpolarity_2_int,
b_txdatak => bfm_txdatak_2_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_2_int,
b_rxvalid => bfm_rxvalid_2_int,
b_rxelecidle => bfm_rxelecidle_2_int,
b_rxdatak(0) => bfm_rxdatak_2_int,
b_rxdata => bfm_rxdata_2_int,
b_rxstatus => bfm_rxstatus_2_int
);
x2_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_3_int,
b_txcompl => bfm_txcompl_3_int,
b_txdetectrx => bfm_txdetectrx_3_int,
b_txelecidle => bfm_txelecidle_3_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_3_int,
b_rxpolarity => bfm_rxpolarity_3_int,
b_txdatak => bfm_txdatak_3_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_3_int,
b_rxvalid => bfm_rxvalid_3_int,
b_rxelecidle => bfm_rxelecidle_3_int,
b_rxdatak(0) => bfm_rxdatak_3_int,
b_rxdata => bfm_rxdata_3_int,
b_rxstatus => bfm_rxstatus_3_int
);
x2_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x2_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x2_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x2_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x2_lanes;
--elsif BFM_LANE_WIDTH = 4 generate
manage_x4_lanes: if BFM_LANE_WIDTH = 4 generate
-- x4 configuration, BFM connected with 4 lanes, using dummy transceiver for lanes 5 to 8
x4_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(5 downto 4),
a_txdatak(0) => ep_txdatak_i(2),
a_txdata => ep_txdata_i(23 downto 16),
a_txcompl => ep_txcompl_i(2),
a_txelecidle => ep_txelecidle_i(2),
a_txdetectrx => ep_txdetectrx_i(2),
a_rxpolarity => ep_rxpolarity_i(2),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(2),
a_rxstatus => ep_rxstatus_o(8 downto 6),
a_rxdatak(0) => ep_rxdatak_o(2),
a_rxdata => ep_rxdata_o(23 downto 16),
a_rxelecidle => ep_rxelecidle_o(2),
a_phystatus => ep_phystatus_o(2),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(7 downto 6),
a_txdatak(0) => ep_txdatak_i(3),
a_txdata => ep_txdata_i(31 downto 24),
a_txcompl => ep_txcompl_i(3),
a_txelecidle => ep_txelecidle_i(3),
a_txdetectrx => ep_txdetectrx_i(3),
a_rxpolarity => ep_rxpolarity_i(3),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(3),
a_rxstatus => ep_rxstatus_o(11 downto 9),
a_rxdatak(0) => ep_rxdatak_o(3),
a_rxdata => ep_rxdata_o(31 downto 24),
a_rxelecidle => ep_rxelecidle_o(3),
a_phystatus => ep_phystatus_o(3),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x4_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x4_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x4_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x4_lanes;
--else generate
manage_x8_lanes: if BFM_LANE_WIDTH = 8 generate
-- x8 configuration, BFM connected with maximum lanes, no dummy transceiver necessary
x8_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(5 downto 4),
a_txdatak(0) => ep_txdatak_i(2),
a_txdata => ep_txdata_i(23 downto 16),
a_txcompl => ep_txcompl_i(2),
a_txelecidle => ep_txelecidle_i(2),
a_txdetectrx => ep_txdetectrx_i(2),
a_rxpolarity => ep_rxpolarity_i(2),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(2),
a_rxstatus => ep_rxstatus_o(8 downto 6),
a_rxdatak(0) => ep_rxdatak_o(2),
a_rxdata => ep_rxdata_o(23 downto 16),
a_rxelecidle => ep_rxelecidle_o(2),
a_phystatus => ep_phystatus_o(2),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(7 downto 6),
a_txdatak(0) => ep_txdatak_i(3),
a_txdata => ep_txdata_i(31 downto 24),
a_txcompl => ep_txcompl_i(3),
a_txelecidle => ep_txelecidle_i(3),
a_txdetectrx => ep_txdetectrx_i(3),
a_rxpolarity => ep_rxpolarity_i(3),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(3),
a_rxstatus => ep_rxstatus_o(11 downto 9),
a_rxdatak(0) => ep_rxdatak_o(3),
a_rxdata => ep_rxdata_o(31 downto 24),
a_rxelecidle => ep_rxelecidle_o(3),
a_phystatus => ep_phystatus_o(3),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(9 downto 8),
a_txdatak(0) => ep_txdatak_i(4),
a_txdata => ep_txdata_i(39 downto 32),
a_txcompl => ep_txcompl_i(4),
a_txelecidle => ep_txelecidle_i(4),
a_txdetectrx => ep_txdetectrx_i(4),
a_rxpolarity => ep_rxpolarity_i(4),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => ep_rxvalid_o(4),
a_rxstatus => ep_rxstatus_o(14 downto 12),
a_rxdatak(0) => ep_rxdatak_o(4),
a_rxdata => ep_rxdata_o(39 downto 32),
a_rxelecidle => ep_rxelecidle_o(4),
a_phystatus => ep_phystatus_o(4),
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x8_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(11 downto 10),
a_txdatak(0) => ep_txdatak_i(5),
a_txdata => ep_txdata_i(47 downto 40),
a_txcompl => ep_txcompl_i(5),
a_txelecidle => ep_txelecidle_i(5),
a_txdetectrx => ep_txdetectrx_i(5),
a_rxpolarity => ep_rxpolarity_i(5),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => ep_rxvalid_o(5),
a_rxstatus => ep_rxstatus_o(17 downto 15),
a_rxdatak(0) => ep_rxdatak_o(5),
a_rxdata => ep_rxdata_o(47 downto 40),
a_rxelecidle => ep_rxelecidle_o(5),
a_phystatus => ep_phystatus_o(5),
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x8_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(13 downto 12),
a_txdatak(0) => ep_txdatak_i(6),
a_txdata => ep_txdata_i(55 downto 48),
a_txcompl => ep_txcompl_i(6),
a_txelecidle => ep_txelecidle_i(6),
a_txdetectrx => ep_txdetectrx_i(6),
a_rxpolarity => ep_rxpolarity_i(6),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => ep_rxvalid_o(6),
a_rxstatus => ep_rxstatus_o(20 downto 18),
a_rxdatak(0) => ep_rxdatak_o(6),
a_rxdata => ep_rxdata_o(55 downto 48),
a_rxelecidle => ep_rxelecidle_o(6),
a_phystatus => ep_phystatus_o(6),
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x8_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(15 downto 14),
a_txdatak(0) => ep_txdatak_i(7),
a_txdata => ep_txdata_i(63 downto 56),
a_txcompl => ep_txcompl_i(7),
a_txelecidle => ep_txelecidle_i(7),
a_txdetectrx => ep_txdetectrx_i(7),
a_rxpolarity => ep_rxpolarity_i(7),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => ep_rxvalid_o(7),
a_rxstatus => ep_rxstatus_o(23 downto 21),
a_rxdatak(0) => ep_rxdatak_o(7),
a_rxdata => ep_rxdata_o(63 downto 56),
a_rxelecidle => ep_rxelecidle_o(7),
a_phystatus => ep_phystatus_o(7),
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
--end generate manage_lanes;
end generate manage_x8_lanes;
end architecture pcie_sim_arch;
pcie_sim_pkg.vhd 0000664 0000000 0000000 00000132156 14574545710 0036113 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-01_src/Source -- SPDX-FileCopyrightText: 2017, MEN Mikro Elektronik Nuremberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : simulation package for PCIe simulation model 16x004-01
-- Project :
--------------------------------------------------------------------------------
-- File : pcie_sim_pkg.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2017-05-31
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.print_pkg.all;
use work.utils_pkg.all;
use work.altpcietb_bfm_constants.all;
use work.altpcietb_bfm_log.all;
use work.altpcietb_bfm_req_intf.all;
use work.altpcietb_bfm_shmem.all;
use work.altpcietb_bfm_rdwr.all;
use work.altpcietb_bfm_configure.all;
package pcie_sim_pkg is
type dword_vector is array (integer range <>) of std_logic_vector(31 downto 0);
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-----------------------------------------------------
-- constants to use in terminal_out.tga(1 downto 0)
-----------------------------------------------------
constant IO_TRANSFER : std_logic_vector(1 downto 0) := "00";
constant MEM32_TRANSFER : std_logic_vector(1 downto 0) := "01";
constant CONFIG_TRANSFER : std_logic_vector(1 downto 0) := "10";
constant SETUP_CYCLE : std_logic_vector(1 downto 0) := "11";
-----------------------------------------------------
-- constants to use in terminal_out.tga(3 downto 2)
-----------------------------------------------------
constant BFM_NBR_0 : std_logic_vector(1 downto 0) := "00";
constant BFM_NBR_1 : std_logic_vector(1 downto 0) := "01";
constant BFM_NBR_2 : std_logic_vector(1 downto 0) := "10";
constant BFM_NBR_3 : std_logic_vector(1 downto 0) := "11";
------------------------------
-- constants for general use
------------------------------
constant BFM_BUFFER_MAX_SIZE : integer := 1024;
constant DONT_CHECK32 : std_logic_vector(31 downto 0) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
constant ZERO_32BIT : std_logic_vector(31 downto 0) := (others => '0');
-- +----------------------------------------------------------------------------
-- | functions
-- +----------------------------------------------------------------------------
--! function that calculates the last byte enables of a transfer
--! @param first_dw first enabled bytes of this transfer
--! @param byte_count amount of bytes for this transfer
--! @return last_dw(3 downto 0) last enabled bytes for this transfer
function calc_last_dw(
first_dw : std_logic_vector(3 downto 0);
byte_count : integer
) return std_logic_vector; -- returns std_logic_vector(3 downto 0)
-- +----------------------------------------------------------------------------
-- | procedures
-- +----------------------------------------------------------------------------
--! procedure to check a value against a reference value
--! @param caller_proc string argument which is used in error messages to define the position where
--! this procedure was called from
--! @param ref_val 32bit reference value
--! @param check_val 32bit value that is checked against ref_val
--! @param byte_valid defines which byte of check_val is valid, invalid bytes are not compared
--! @return check_ok boolean argument which states whether the check was ok (=true) or not
procedure check_val(
caller_proc : in string;
ref_val : in std_logic_vector(31 downto 0);
check_val : in std_logic_vector(31 downto 0);
byte_valid : in std_logic_vector(3 downto 0);
check_ok : out boolean
);
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
procedure init_bfm(
bfm_inst_nbr : in integer;
io_addr : in std_logic_vector(31 downto 0);
mem32_addr : in std_logic_vector(31 downto 0);
mem64_addr : in std_logic_vector(63 downto 0);
requester_id : in std_logic_vector(15 downto 0);
max_payloadsize : in integer
);
procedure set_bfm_memory(
nbr_of_dw : in integer;
mem_addr : in std_logic_vector(31 downto 0);
start_data_val : in std_logic_vector(31 downto 0);
data_inc : in integer
);
procedure get_bfm_memory(
nbr_of_dw : in integer;
mem_addr : in std_logic_vector(31 downto 0);
databuf_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0)
);
-----------------------------------------------
-- single memory write to 32bit address space
-----------------------------------------------
procedure bfm_wr_mem32(
pcie_addr : in std_logic_vector(1 downto 0);
bar_num : in natural;
bar_offset : in natural;
byte_count : in natural range 4 downto 1;
data32 : in std_logic_vector(31 downto 0);
success : out boolean
);
----------------------------------------------
-- burst memory write to 32bit address space
----------------------------------------------
procedure bfm_wr_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_count : in integer;
data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
);
procedure bfm_rd_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_en : in std_logic_vector(3 downto 0);
ref_data32 : in std_logic_vector(31 downto 0);
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
);
procedure bfm_rd_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_count : in integer;
ref_data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
data32_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
);
procedure bfm_wr_config(
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
success : out boolean
);
procedure bfm_rd_config(
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
);
procedure bfm_rd_shm(
addr : in natural;
len : in natural;
dat : out std_logic_vector
);
procedure bfm_wr_shm(
addr : in natural;
len : in natural;
dat : in std_logic_vector
);
procedure wait_on_irq_assert(
irq_nbr : in integer range 3 downto 0
);
procedure wait_on_irq_deassert(
irq_nbr : in integer range 3 downto 0
);
procedure bfm_configure_msi(
constant msi_addr : in natural; -- MSI address in shared memory
msi_data : in std_logic_vector(15 downto 0); -- contained in MSI message
msi_allocated : out std_logic_vector(2 downto 0); -- amount of allocated MSI
success : out boolean
);
procedure bfm_calc_msi_expected(
constant msi_allocated : in std_logic_vector(2 downto 0); -- amount of allocated MSI
constant msi_data : in std_logic_vector(15 downto 0); -- MSI data value as programmed to config space
constant msi_nbr : in integer range 32 downto 0;
variable msi_expected : out std_logic_vector(31 downto 0) -- MSI vector as expected from EP
);
procedure bfm_poll_msi(
constant track_msi : in natural;
constant msi_addr : in natural;
constant msi_expected : in std_logic_vector(31 downto 0);
constant txt_out : in integer;
success : out boolean
);
end package pcie_sim_pkg;
package body pcie_sim_pkg is
function calc_last_dw(
first_dw : std_logic_vector(3 downto 0);
byte_count : integer
) return std_logic_vector is
variable first_bytes : integer := 0;
variable last_bytes : integer := 0;
variable return_int : std_logic_vector(3 downto 0);
begin
if first_dw(0) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(1) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(2) = '1' then
first_bytes := first_bytes +1;
end if;
if first_dw(3) = '1' then
first_bytes := first_bytes +1;
end if;
last_bytes := (byte_count - first_bytes) mod 4;
if last_bytes = 0 then
return_int := "1111";
elsif last_bytes = 1 then
return_int := "0001";
elsif last_bytes = 2 then
return_int := "0011";
elsif last_bytes = 3 then
return_int := "0111";
else
return_int := "XXXX";
assert false report "ERROR in function calc_last_dw(): illegal value for variable last_bytes" severity error;
end if;
return return_int;
end;
procedure check_val(
caller_proc : in string;
ref_val : in std_logic_vector(31 downto 0);
check_val : in std_logic_vector(31 downto 0);
byte_valid : in std_logic_vector(3 downto 0);
check_ok : out boolean
) is
variable pass : boolean := true;
begin
if byte_valid(0) = '1' then
if ref_val(7 downto 0) /= check_val(7 downto 0) then
print_now("BFM ERROR in " & caller_proc & "(): data read does not match given reference value - mismatch in byte0");
write_s_slvec("BFM ERROR in " & caller_proc & "(): reference value[7:0] = ",ref_val(7 downto 0));
write_s_slvec("BFM ERROR in " & caller_proc & "(): read value[7:0] = ",check_val(7 downto 0));
pass := false;
end if;
end if;
if byte_valid(1) = '1' then
if ref_val(15 downto 8) /= check_val(15 downto 8) then
print_now("BFM ERROR in " & caller_proc & "(): data read does not match given reference value - mismatch in byte1");
write_s_slvec("BFM ERROR in " & caller_proc & "(): reference value[15:8] = ",ref_val(15 downto 8));
write_s_slvec("BFM ERROR in " & caller_proc & "(): read value[15:8] = ",check_val(15 downto 8));
pass := false;
end if;
end if;
if byte_valid(2) = '1' then
if ref_val(23 downto 16) /= check_val(23 downto 16) then
print_now("BFM ERROR in " & caller_proc & "(): data read does not match given reference value - mismatch in byte2");
write_s_slvec("BFM ERROR in " & caller_proc & "(): reference value[23:16] = ",ref_val(23 downto 16));
write_s_slvec("BFM ERROR in " & caller_proc & "(): read value[23:16] = ",check_val(23 downto 16));
pass := false;
end if;
end if;
if byte_valid(3) = '1' then
if ref_val(31 downto 24) /= check_val(31 downto 24) then
print_now("BFM ERROR in " & caller_proc & "(): data read does not match given reference value - mismatch in byte3");
write_s_slvec("BFM ERROR in " & caller_proc & "(): reference value[31:24] = ",ref_val(31 downto 24));
write_s_slvec("BFM ERROR in " & caller_proc & "(): read value[31:24] = ",check_val(31 downto 24));
pass := false;
end if;
end if;
check_ok := pass;
end procedure;
procedure init_bfm(
bfm_inst_nbr : in integer;
io_addr : in std_logic_vector(31 downto 0);
mem32_addr : in std_logic_vector(31 downto 0);
mem64_addr : in std_logic_vector(63 downto 0);
requester_id : in std_logic_vector(15 downto 0);
max_payloadsize : in integer
) is
begin
print_now("BFM: initialize PCIe BFM");
ebfm_cfg_rp_ep(
bar_table => BAR_TABLE_POINTER, -- defined in BFM shared memory
ep_bus_num => 1,
ep_dev_num => 1,
rp_max_rd_req_size => max_payloadsize,
display_ep_config => 1, -- display config space after endpoint config setup
addr_map_4GB_limit => 0 -- limit BAR assignment to 4GB address map
);
print_now("BFM: link is up");
end procedure;
procedure set_bfm_memory(
nbr_of_dw : in integer;
mem_addr : in std_logic_vector(31 downto 0);
start_data_val : in std_logic_vector(31 downto 0);
data_inc : in integer
) is
variable var_byte_len : integer;
variable var_addr : natural;
variable var_data_buf : std_logic_vector(nbr_of_dw *32 -1 downto 0);
begin
for i in 0 to nbr_of_dw -1 loop
var_data_buf(i*32+31 downto i*32) := std_logic_vector(unsigned(start_data_val) + to_unsigned(i*data_inc,32));
end loop;
var_byte_len := natural(nbr_of_dw *4);
var_addr := to_integer(unsigned(mem_addr));
-------------------------------------------------------------------------------------------
-- Altera BFM doesn't distinguish between I/O and memory space concerning rd/wr functions
-------------------------------------------------------------------------------------------
shmem_write(
addr => var_addr,
data => var_data_buf,
leng => var_byte_len
);
end procedure;
procedure get_bfm_memory(
nbr_of_dw : in integer;
mem_addr : in std_logic_vector(31 downto 0);
databuf_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0)
) is
variable var_databuf_max : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_byte_len : integer;
variable var_addr : natural;
variable var_data_buf : std_logic_vector(nbr_of_dw *32 -1 downto 0);
begin
if nbr_of_dw > BFM_BUFFER_MAX_SIZE then
print_now("BFM ERROR in get_bfm_memory(): nbr_of_dw exceeds BFM_BUFFER_MAX_SIZE");
else
var_byte_len := natural(nbr_of_dw *4);
var_addr := to_integer(unsigned(mem_addr));
var_data_buf := shmem_read(addr => var_addr, leng => var_byte_len);
for i in 0 to nbr_of_dw -1 loop
var_databuf_max(i) := var_data_buf(i*32+31 downto i*32);
end loop;
databuf_out := var_databuf_max;
end if;
end procedure;
procedure bfm_wr_mem32(
pcie_addr : in std_logic_vector(1 downto 0);
bar_num : in natural;
bar_offset : in natural;
byte_count : in natural range 4 downto 1;
data32 : in std_logic_vector(31 downto 0);
success : out boolean
) is
variable var_pass : boolean := true;
variable var_local_addr : natural := 0;
begin
var_pass := true;
-----------------------------------------
-- write user data to BFM shared memory
-----------------------------------------
var_local_addr := 0;
shmem_write(
addr => var_local_addr,
data => data32,
leng => 4 --byte_count
);
---------------------------
-- transfer data via PCIe
---------------------------
var_local_addr := 0 + (to_integer(unsigned(pcie_addr)));
ebfm_barwr(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
pcie_offset => bar_offset,
lcladdr => var_local_addr, -- shmem address
byte_len => byte_count, --4,
tclass => 0
);
--report "WARNING (bfm_wr_mem32 - single): return value for success is always true" severity warning;
success := var_pass;
end procedure;
procedure bfm_wr_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_count : in integer;
data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
) is
variable var_data_buf : std_logic_vector(8*byte_count -1 downto 0);
variable var_pass : boolean := true;
variable var_nbr_of_dw : integer;
variable var_local_addr : natural := 0;
variable var_copy_dw_cntr : natural := 0;
variable var_copy_byte_cntr : natural := 0;
begin
var_pass := true;
var_nbr_of_dw := byte_count / 4;
-----------------------------------------------------------------
-- copy user data:
-- use var_copy_counter to access the correct 32bit data vector
-- in the dword_vector structure, use i to copy the correct
-- portion of the 32bit vector
-----------------------------------------------------------------
for i in 0 to byte_count -1 loop
var_copy_byte_cntr := i mod 4;
if (i > 0) and (i mod 4 = 0) then
var_copy_dw_cntr := var_copy_dw_cntr +1;
end if;
wait for 0 ns;
var_data_buf(i*8+7 downto i*8) := data32(var_copy_dw_cntr)(var_copy_byte_cntr*8+7 downto var_copy_byte_cntr*8);
end loop;
-----------------------------------------
-- write user data to BFM shared memory
-----------------------------------------
var_local_addr := 0; -- + bar_offset;
shmem_write(
addr => var_local_addr,
data => var_data_buf,
leng => byte_count -- length in bytes
);
---------------------------
-- transfer data via PCIe
---------------------------
ebfm_barwr(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
pcie_offset => bar_offset,
lcladdr => var_local_addr, -- shmem address
byte_len => byte_count,
tclass => 0
);
report "WARNING (bfm_wr_mem32 - burst): return value for success is always true" severity warning;
success := var_pass;
end procedure;
procedure bfm_rd_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_en : in std_logic_vector(3 downto 0);
ref_data32 : in std_logic_vector(31 downto 0);
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
) is
variable var_byte_len : natural := 0;
variable var_pass : boolean := true;
variable var_databuf : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_local_addr : natural := 0;
variable var_byte_offset : natural := 0;
begin
var_pass := true;
data32_out := (others => '0');
-----------------------------------------------------
-- initialize data buffer with known default values
-----------------------------------------------------
for i in 0 to BFM_BUFFER_MAX_SIZE loop
var_databuf(i) := x"CAFE_AFFE";
end loop;
if byte_en(0) = '1' then
var_byte_len := var_byte_len +1;
end if;
if byte_en(1) = '1' then
var_byte_len := var_byte_len +1;
end if;
if byte_en(2) = '1' then
var_byte_len := var_byte_len +1;
end if;
if byte_en(3) = '1' then
var_byte_len := var_byte_len +1;
end if;
--------------------------------------------------------------------
-- bar_offset is DW aligned thus prepared for 32bit transfers
-- adapt for byte offset
--------------------------------------------------------------------
case byte_en is
when "0001" =>
var_byte_offset := 0;
when "0010" =>
var_byte_offset := 1;
when "0100" =>
var_byte_offset := 2;
when "1000" =>
var_byte_offset := 3;
when "0011" =>
var_byte_offset := 0;
when "1100" =>
var_byte_offset := 2;
when "1111" =>
var_byte_offset := 0;
when others =>
var_byte_offset := 0;
end case;
-------------------------------------------------
-- add byte offset to PCIe read function to get
-- properly formed PCIe TLP format
-------------------------------------------------
var_local_addr := 0;
ebfm_barrd_wait(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
pcie_offset => (bar_offset + var_byte_offset),
lcladdr => (var_local_addr + var_byte_offset),
byte_len => var_byte_len,
tclass => 0
);
get_bfm_memory(
nbr_of_dw => 1,
mem_addr => std_logic_vector(to_unsigned(var_local_addr,32)),
databuf_out => var_databuf
);
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_mem32 - single",
ref_val => ref_data32,
check_val => var_databuf(0),
byte_valid => byte_en,
check_ok => var_pass
);
end if;
data32_out := var_databuf(0);
success := var_pass;
end procedure;
procedure bfm_rd_mem32(
bar_num : in natural;
bar_offset : in natural;
byte_count : in integer;
ref_data32 : in dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
data32_out : out dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
success : out boolean
) is
variable var_databuf_max : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_databuf : std_logic_vector(byte_count *8 -1 downto 0);
variable var_pass : boolean := true;
variable var_pass_temp : boolean := true;
variable var_nbr_of_dw : integer;
variable var_local_addr : natural := 0;
variable byte_en : std_logic_vector(3 downto 0) := (others => '0');
variable first_DW_en : std_logic_vector(3 downto 0) := (others => '0');
variable last_DW_en : std_logic_vector(3 downto 0) := (others => '0');
variable var_copy_dw_cntr : natural := 0;
variable var_copy_byte_cntr : natural := 0;
begin
var_pass := true;
data32_out := (others => (others => '0'));
var_nbr_of_dw := byte_count /4;
wait for 0 ns;
-----------------------------------------------------
-- initialize data buffer with known default values
-----------------------------------------------------
for i in 0 to BFM_BUFFER_MAX_SIZE loop
var_databuf_max(i) := x"CAFE_AFFE";
end loop;
var_local_addr := 0;
ebfm_barrd_wait(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
pcie_offset => bar_offset,
lcladdr => var_local_addr,
byte_len => byte_count,
tclass => 0
);
var_databuf := shmem_read(addr => 0, leng => byte_count);
---------------------------------------------------------
-- copy read data:
-- use i to iterate through bytes
-- use var_copy_dw_cntr to iterate through dword vector
-- use var_copy_byte_cntr to iterate through bytes
---------------------------------------------------------
for i in 0 to byte_count -1 loop
var_copy_byte_cntr := i mod 4;
wait for 0 ns;
if (i > 0) and (i mod 4 = 0) then
var_copy_dw_cntr := var_copy_dw_cntr +1;
wait for 0 ns;
end if;
var_databuf_max(var_copy_dw_cntr)(var_copy_byte_cntr*8+7 downto var_copy_byte_cntr*8) := var_databuf(i*8+7 downto i*8);
end loop;
-----------------------------------
-- check if read value is correct
-----------------------------------
for i in 0 to var_nbr_of_dw -1 loop
if ref_data32(i) = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_mem32 - burst",
ref_val => ref_data32(i),
check_val => var_databuf_max(i),
byte_valid => x"F",
check_ok => var_pass_temp
);
end if;
var_pass := var_pass and var_pass_temp;
end loop;
data32_out := var_databuf_max;
success := var_pass;
end procedure;
procedure bfm_wr_config(
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
data32 : in std_logic_vector(31 downto 0);
success : out boolean
) is
variable var_pcie_addr : std_logic_vector(31 downto 0) := (others => '0');
variable var_compl_status : std_logic_vector(2 downto 0);
variable var_databuf : std_logic_vector(31 downto 0);
variable var_byte_len : natural := 0;
variable var_cfg_space_addr : natural := 0;
variable var_shmem_addr : natural := 0;
variable var_pass : boolean := true;
begin
var_pass := true;
var_pcie_addr(31 downto 2) := pcie_addr;
var_databuf := (others => '0');
--------------------------------------------------------------------------
-- given PCIe address is DW aligned thus address offset for byte or word
-- access must be calculated manually
-- BUT there may be no hole in bytes e.g. byte_en = "1010" is illegal
-- valid:
-- "1111" / "0111" / "0011" / "0001" / "1100" / "0010" / "0100" / "1000"
-- consider this when retrieving data from shared memory!
--------------------------------------------------------------------------
case byte_en is
when "1111" =>
var_byte_len := 4;
var_pcie_addr(1 downto 0) := "00";
var_databuf := data32;
when "0111" =>
var_byte_len := 3;
var_pcie_addr(1 downto 0) := "00";
var_databuf := data32;
when "0011" =>
var_byte_len := 2;
var_pcie_addr(1 downto 0) := "00";
var_databuf := data32;
when "0001" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "00";
var_databuf := data32;
when "1100" =>
var_byte_len := 2;
var_pcie_addr(1 downto 0) := "10";
var_databuf := data32;
when "0010" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "01";
var_databuf := data32;
when "0100" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "10";
var_databuf := data32;
when "1000" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "11";
var_databuf := data32;
when others =>
var_byte_len := 0;
var_pcie_addr := x"0000_0006"; -- status register is RO or RW1C thus safe for dummy write
var_databuf := (others => '0');
end case;
var_cfg_space_addr := to_integer(unsigned(var_pcie_addr));
ebfm_cfgwr_imm_wait(
bus_num => 1,
dev_num => 1,
fnc_num => 0,
regb_ad => var_cfg_space_addr,
regb_ln => var_byte_len,
imm_data => var_databuf,
compl_status => var_compl_status
);
if var_compl_status = "000" then
var_pass := true; -- successful completion
elsif var_compl_status = "001" then
print_now("ERROR(bfm_wr_config): return status for config write is unsupported request");
var_pass := false;
elsif var_compl_status = "010" then
print_now("ERROR(bfm_wr_config): return status for config write is configuration request retry status");
var_pass := false;
elsif var_compl_status = "100" then
print_now("ERROR(bfm_wr_config): return status for config write is completer abort");
var_pass := false;
end if;
success := var_pass;
end procedure;
procedure bfm_rd_config(
byte_en : in std_logic_vector(3 downto 0);
pcie_addr : in std_logic_vector(31 downto 2);
ref_data32 : in std_logic_vector(31 downto 0);
data32_out : out std_logic_vector(31 downto 0);
success : out boolean
) is
variable var_pcie_addr : std_logic_vector(31 downto 0) := (others => '0');
variable var_databuf : std_logic_vector(31 downto 0);
variable var_compl_status : std_logic_vector(2 downto 0);
variable var_byte_len : natural := 0;
variable var_cfg_space_addr : natural := 0;
variable var_shmem_addr : natural := 0;
variable var_pass : boolean := true;
begin
var_pass := true;
data32_out := (others => '0');
var_compl_status := (others => '1');
var_pcie_addr(31 downto 2) := pcie_addr;
var_databuf := x"FADE_FADE";
var_shmem_addr := 0;
--------------------------------------------------------------------------
-- given PCIe address is DW aligned thus address offset for byte or word
-- access must be calculated manually
-- BUT there may be no hole in bytes e.g. byte_en = "1010" is illegal
-- valid:
-- "1111" / "0111" / "0011" / "0001" / "1100" / "0010" / "0100" / "1000"
-- consider this when retrieving data from shared memory!
--------------------------------------------------------------------------
case byte_en is
when "1111" =>
var_byte_len := 4;
var_pcie_addr(1 downto 0) := "00";
when "0111" =>
var_byte_len := 3;
var_pcie_addr(1 downto 0) := "00";
when "0011" =>
var_byte_len := 2;
var_pcie_addr(1 downto 0) := "00";
when "0001" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "00";
when "1100" =>
var_byte_len := 2;
var_pcie_addr(1 downto 0) := "10";
when "0010" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "01";
when "0100" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "10";
when "1000" =>
var_byte_len := 1;
var_pcie_addr(1 downto 0) := "11";
when others =>
var_byte_len := 0;
var_pcie_addr := (others => '0');
end case;
var_cfg_space_addr := to_integer(unsigned(var_pcie_addr));
ebfm_cfgrd_wait(
bus_num => 1,
dev_num => 1,
fnc_num => 0,
regb_ad => var_cfg_space_addr,
regb_ln => var_byte_len,
lcladdr => var_shmem_addr,
compl_status => var_compl_status
);
if var_compl_status = "000" then
var_pass := true; -- successful completion
elsif var_compl_status = "001" then
print_now("ERROR(bfm_rd_config): return status for config read is unsupported request");
var_pass := false;
elsif var_compl_status = "010" then
print_now("ERROR(bfm_rd_config): return status for config read is configuration request retry status");
var_pass := false;
elsif var_compl_status = "100" then
print_now("ERROR(bfm_rd_config): return status for config read is completer abort");
var_pass := false;
end if;
--------------------------------------
-- read value from BFM shared memory
--------------------------------------
var_databuf := shmem_read(addr => var_shmem_addr, leng => var_byte_len);
---------------------------------------------------------------------------
-- copy data read from shared memory to expected position for check_val()
---------------------------------------------------------------------------
case byte_en is
when "1100" =>
var_databuf(31 downto 16) := var_databuf(15 downto 0);
when "0010" =>
var_databuf(15 downto 8) := var_databuf(7 downto 0);
when "0100" =>
var_databuf(23 downto 16) := var_databuf(7 downto 0);
when "1000" =>
var_databuf(31 downto 24) := var_databuf(7 downto 0);
when others => -- byte position ok
var_databuf := var_databuf;
end case;
-----------------------------------
-- check if read value is correct
-----------------------------------
if ref_data32 = DONT_CHECK32 then
print_now("BFM: checking of read value skipped on user command");
else
check_val(
caller_proc => "bfm_rd_config",
ref_val => ref_data32,
check_val => var_databuf,
byte_valid => byte_en,
check_ok => var_pass
);
end if;
data32_out := var_databuf;
success := var_pass;
end procedure;
procedure bfm_rd_shm(
addr : in natural;
len : in natural;
dat : out std_logic_vector) is
begin
dat := shmem_read(addr, len);
end procedure;
procedure bfm_wr_shm(
addr : in natural;
len : in natural;
dat : in std_logic_vector) is
begin
shmem_write(addr, dat, len);
end procedure;
procedure wait_on_irq_assert(
irq_nbr : in integer range 3 downto 0
) is
begin
report "ERROR: NO CONTENT IN PROCEDURE WAIT_ON_IRQ_ASSERT" severity error;
end procedure;
procedure wait_on_irq_deassert(
irq_nbr : in integer range 3 downto 0
) is
begin
report "ERROR: NO CONTENT IN PROCEDURE WAIT_ON_IRQ_DEASSERT" severity error;
end procedure;
procedure bfm_configure_msi(
constant msi_addr : in natural; -- MSI address in shared memory
msi_data : in std_logic_vector(15 downto 0); -- contained in MSI message
msi_allocated : out std_logic_vector(2 downto 0); -- amount of allocated MSI
success : out boolean
) is
function check_compl_status(
compl_status : in std_logic_vector(2 downto 0)
) return boolean is
variable var_pass : boolean := false;
begin
if compl_status = "000" then
var_pass := true; -- successful completion
elsif compl_status = "001" then
print_now("ERROR(bfm_configure_msi): return status for config read is unsupported request");
var_pass := false;
elsif compl_status = "010" then
print_now("ERROR(bfm_configure_msi): return status for config read is configuration request retry status");
var_pass := false;
elsif compl_status = "100" then
print_now("ERROR(bfm_configure_msi): return status for config read is completer abort");
var_pass := false;
end if;
return var_pass;
end function check_compl_status;
constant MSI_CAP_ADDR : natural := 80; -- MSI capabilities register
constant TRAFFIC_CLASS : std_logic_vector(2 downto 0) := "000";
constant BUS_NUM : natural := 1;
constant DEV_NUM : natural := 1;
constant FUNC_NUM : natural := 0;
variable var_pass : boolean := true;
variable var_msi_ctrl_reg : std_logic_vector(15 downto 0) := (others => '0');
variable var_msi_is_64b : std_logic_vector(0 downto 0) := (others => '0');
variable var_is_multi_mess : std_logic_vector(2 downto 0) := (others => '0');
variable var_multi_mess_en : std_logic_vector(2 downto 0) := (others => '0');
variable var_msi_en : std_logic := '0';
variable var_compl_status : std_logic_vector(2 downto 0) := (others => '0');
variable var_msi_addr : std_logic_vector(31 downto 0) := (others => '0');
begin
var_pass := true;
var_msi_addr := std_logic_vector(to_unsigned(msi_addr,32));
-- read EP config space
ebfm_cfgrd_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => MSI_CAP_ADDR,
regb_ln => 4,
lcladdr => msi_addr,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
-- check if EP has 64bit MSI and multi message enabled
var_msi_ctrl_reg := shmem_read(msi_addr +2, 2);
var_msi_is_64b := var_msi_ctrl_reg(7 downto 7);
var_is_multi_mess := var_msi_ctrl_reg(3 downto 1);
var_multi_mess_en := var_is_multi_mess;
-- enable msi
var_msi_en := '1';
-- write changed content back tp EP config space
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => MSI_CAP_ADDR,
regb_ln => 4,
imm_data => (x"00" & var_msi_is_64b &
var_multi_mess_en &
var_is_multi_mess &
var_msi_en & x"0000"),
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
msi_allocated := var_multi_mess_en;
-- program all msi capability registers (64 and 32 bit!)
if var_msi_is_64b = "1" then -- 64bit addressing
-- set lower address where MSI will be written
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +4),
regb_ln => 4,
imm_data => var_msi_addr,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
-- set upper address where MSI will be written
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +4),
regb_ln => 4,
imm_data => x"0000_0000",
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
-- set which data value shall be writen when endpoint issues MSI
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +12),
regb_ln => 4,
imm_data => x"0000" & msi_data,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
else -- 32bit addressing
-- set lower address where MSI will be written
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +4),
regb_ln => 4,
imm_data => var_msi_addr,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
-- set which data value shall be writen when endpoint issues MSI
ebfm_cfgwr_imm_wait(
bus_num => BUS_NUM,
dev_num => DEV_NUM,
fnc_num => FUNC_NUM,
regb_ad => (MSI_CAP_ADDR +8),
regb_ln => 4,
imm_data => x"0000" & msi_data,
compl_status => var_compl_status
);
var_pass := check_compl_status(var_compl_status);
end if;
-- clear MSI location in shared memory
shmem_write(msi_addr, x"FADE_FADE", 4);
success := var_pass;
end procedure;
procedure bfm_calc_msi_expected(
constant msi_allocated : in std_logic_vector(2 downto 0); -- amount of allocated MSI
constant msi_data : in std_logic_vector(15 downto 0); -- MSI data value as programmed to config space
constant msi_nbr : in integer range 32 downto 0;
variable msi_expected : out std_logic_vector(31 downto 0) -- MSI vector as expected from EP
) is
variable var_msi_expected : std_logic_vector(31 downto 0);
variable var_msi_nbr : std_logic_vector(4 downto 0) := (others => '0');
variable var_max_msi_allowed : integer range 32 downto 1 := 1;
begin
-- calculate MSI number
case msi_allocated is
when "000" =>
var_max_msi_allowed := 1;
when "001" =>
var_max_msi_allowed := 2;
when "010" =>
var_max_msi_allowed := 4;
when "011" =>
var_max_msi_allowed := 8;
when "100" =>
var_max_msi_allowed := 16;
when "101" =>
var_max_msi_allowed := 32;
when others =>
var_max_msi_allowed := 1;
end case;
-----------------------------------------------------------------------------
-- if we use more MSI than are allocated then wrap the number automatically
-----------------------------------------------------------------------------
var_msi_nbr := std_logic_vector(to_unsigned((msi_nbr mod var_max_msi_allowed),5));
if (msi_allocated = "000") then
var_msi_expected := x"0000" & msi_data(15 downto 0);
elsif (msi_allocated = "001") then
var_msi_expected := x"0000" & msi_data(15 downto 1) & var_msi_nbr(0 downto 0);
elsif (msi_allocated = "010") then
var_msi_expected := x"0000" & msi_data(15 downto 2) & var_msi_nbr(1 downto 0);
elsif (msi_allocated = "011") then
var_msi_expected := x"0000" & msi_data(15 downto 3) & var_msi_nbr(2 downto 0);
elsif (msi_allocated = "100") then
var_msi_expected := x"0000" & msi_data(15 downto 4) & var_msi_nbr(3 downto 0);
elsif (msi_allocated = "101") then
var_msi_expected := x"0000" & msi_data(15 downto 5) & var_msi_nbr(4 downto 0);
else
print_now("ERROR(bfm_calc_msi_expected): illegal value for multi message enable");
var_msi_expected := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
msi_expected := var_msi_expected;
end procedure;
procedure bfm_poll_msi(
constant track_msi : in natural;
constant msi_addr : in natural;
constant msi_expected : in std_logic_vector(31 downto 0);
constant txt_out : in integer;
success : out boolean
) is
constant POLLING_TIMEOUT : natural := 5 * 2048;
variable var_pass : boolean := true;
variable var_loop_val : natural range 1 downto 0 := 1;
variable var_poll_timer : natural := 0;
variable var_msi_received : std_logic_vector(15 downto 0) := (others => '0');
begin
var_pass := true;
track_msi_loop : for i in 1 to track_msi loop
if txt_out >=2 then print_s_i("bfm_poll_msi(): tracking MSI number: ", i); end if;
var_loop_val := 1;
while var_loop_val = 1 loop
wait for 10 ns;
--wait for 10 us;
var_poll_timer := var_poll_timer +1;
var_msi_received := (others => '0');
var_msi_received := shmem_read(msi_addr, 2);
if var_msi_received = msi_expected(15 downto 0) then
-- clear shared memory location and exit polling loop
shmem_write(msi_addr, x"FADE_FADE", 4);
var_loop_val := 0;
end if;
-- manage internal timeout
if var_poll_timer >= POLLING_TIMEOUT then
var_pass := false;
if txt_out >= 1 then
print_now("ERROR(bfm_poll_msi): no MSI captured within timeout time");
end if;
success := var_pass;
exit track_msi_loop;
end if;
end loop;
end loop track_msi_loop;
success := var_pass;
end procedure;
end package body pcie_sim_pkg;
types_pkg.vhd 0000664 0000000 0000000 00000006224 14574545710 0035463 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
-------------------------------------------------------------------------------
-- Title : 16z091-00 PCIe test bench
-- Project : 16z091-00
-------------------------------------------------------------------------------
-- File : types_pkg.vhd
-- Author : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-08-21
-------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6 Revision 2010.01
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- Constants and types common to all test bench files
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package types_pkg is
constant TST_PASS : integer := 1;
constant TST_FAIL : integer := 2;
--------------------------------------------------------
-- define all configurable settings in tst_config_type
--------------------------------------------------------
type tst_config_type is record
-- iter : integer;
-- iram_max_size : integer;
set_txt : integer;
max_payload : integer;
max_read : integer;
-- msi_nbr : integer;
-- msi_en : integer;
-- min_loop : integer;
-- max_loop : integer;
-- len_wb_burst : integer;
-- len_pcie_burst : integer;
-- start_delay_iram : integer;
-- wait_states_iram : integer;
-- break_at_iram : integer;
-- break_for_iram : integer;
end record;
-- type error_in_type is record
-- wbm_err : integer;
-- wbs_err : integer;
-- wb_mon_err : integer;
-- mon001_err : integer;
-- end record;
type watchdog_type is record
wd_start : boolean;
wd_time : time;
end record;
-- type mon001_ctrl_in_type is record
-- busy : std_logic;
-- end record;
-- type mon001_ctrl_out_type is record
-- ref_data : std_logic_vector(31 downto 0);
-- ref_sel : std_logic_vector(3 downto 0);
-- ref_addr : std_logic_vector(31 downto 0);
-- new_val : boolean; -- edge states that ref_sel and ref_data have new values
-- end record;
type cfg_in_type is record
wb_clk : std_logic;
clk : std_logic;
tstcfg : tst_config_type;
--err_in : error_in_type;
--mon001_ctrl_i : mon001_ctrl_in_type;
end record;
type cfg_out_type is record
dut_rst : std_logic;
tb_rst : std_logic;
wb_rst : std_logic;
watchdog : watchdog_type;
--mon001_ctrl_o : mon001_ctrl_out_type;
end record;
end types_pkg;
package body types_pkg is
-- empty
end;
utils_pkg.vhd 0000664 0000000 0000000 00000014326 14574545710 0035461 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x004-01_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
-------------------------------------------------------------------------------
-- Title : utilitiy package for 16z091-00 PCIe test bench
-- Project : 16z091-00
-------------------------------------------------------------------------------
-- File : utils_pkg.vhd
-- Author : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-08-22
-------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6 Revision 2010.01
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- Contains useful procedures
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
package utils_pkg is
procedure write_label(
constant use_time : in string;
constant string_in : in string;
integer_in : in integer
);
procedure wait_clk(
signal clk : in std_logic;
constant clk_cnt : in integer
);
procedure write_s_slvec(
string_in : in string;
slvec_in : in std_logic_vector
);
end utils_pkg;
package body utils_pkg is
-----------------------------------------------------------------------------------------------------------------------------------------
-- write_label:
-- This procedure prints out a box to the transcript which is formated according to the length of the input string.
-- use_time : provide time resolution or "none" if no time shall be printed
-- string_in : input string that will be printed to the box
-- integer_in : integer value that will be printed to the box, omitted if set to 0
-----------------------------------------------------------------------------------------------------------------------------------------
procedure write_label(
constant use_time : in string;
constant string_in : in string;
integer_in : in integer
) is
variable wrLine : line;
variable cnt : integer := 0;
constant LABEL_C : string := "-";
constant LABEL_STR : string := "--";
constant LABEL_STR1 : string := "---";
constant CORNER_C : string := "+";
constant HEADER_C : string := "=";
constant LINE_LEN : integer := 105;
constant T_WIDTH : integer := 15;
begin
write(wrLine, CORNER_C);
for i in string_in'range loop
write(wrLine, LABEL_C);
end loop;
if integer_in >= 0 then
for i in 0 to 9 loop
if (integer_in / (10**i)) /= 0 then cnt := i; end if;
end loop;
for j in 0 to cnt loop
write(wrLine, label_c);
end loop;
write(wrLine, LABEL_STR1);
else
write(wrLine, LABEL_STR);
end if;
if use_time /= "none" then
for i in 0 to T_WIDTH loop
write(wrLine, LABEL_C);
end loop;
end if;
write(wrLine, CORNER_C);
writeline(output,wrLine);
write(wrLine, string'("| "));
if use_time /= "none" then
if use_time = "fs" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> fs );
elsif use_time = "ps" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ps );
elsif use_time = "us" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> us );
elsif use_time = "ms" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ms );
else
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ns );
end if;
write(wrLine, string'(" "));
end if;
write(wrLine, string_in);
if integer_in >= 0 then
write(wrLine, string'(" "));
write(wrLine, integer_in);
end if;
write(wrLine, string'(" |"));
writeline(output,wrLine);
write(wrLine, CORNER_C);
for i in string_in'range loop
write(wrLine, LABEL_C);
end loop;
if integer_in >= 0 then
for i in 0 to 9 loop
if (integer_in / (10**i)) /= 0 then cnt := i; end if;
end loop;
for j in 0 to cnt loop
write(wrLine, label_c);
end loop;
write(wrLine, LABEL_STR1);
else
write(wrLine, LABEL_STR);
end if;
if use_time /= "none" then
for i in 0 to T_WIDTH loop
write(wrLine, LABEL_C);
end loop;
end if;
write(wrLine, CORNER_C);
writeline(output,wrLine);
end procedure write_label;
-----------------------------------------------------------------------------------------------------------------------------------------
-- wait_clk:
-- This procedure waits for the given amount of input clock cycles.
-----------------------------------------------------------------------------------------------------------------------------------------
procedure wait_clk(
signal clk : in std_logic;
constant clk_cnt : in integer
) is
begin
for i in 1 to clk_cnt loop
wait until rising_edge(clk);
end loop;
end procedure wait_clk;
-----------------------------------------------------------------------------------------------------------------------------------------
-- write_s_slvec:
-- This procedure prints std_logic_vector values in a way that collisions (e.g. 'X' or 'U') can be detected.
-----------------------------------------------------------------------------------------------------------------------------------------
procedure write_s_slvec(
string_in : in string;
slvec_in : in std_logic_vector
) is
variable l : line;
begin
write(l,string_in);
write(l, std_ulogic_vector(slvec_in), justified => right, field => 10);
writeline(output,l);
end procedure write_s_slvec;
end;
16x010-00_src/ 0000775 0000000 0000000 00000000000 14574545710 0031503 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench Source/ 0000775 0000000 0000000 00000000000 14574545710 0032743 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x010-00_src conversions.vhd 0000664 0000000 0000000 00000127563 14574545710 0036034 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x010-00_src/Source -- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- File Name: conversions.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1997-2008 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- This package was originally written by SEVA Technologies, Inc. and donated
-- to the FMF.
-- www.seva.com
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 97 DEC 05 Added header and formatting to SEVA file
-- V1.1 R. Munden 98 NOV 28 Corrected some comments
-- Corrected function b
-- V1.2 R. Munden 01 MAY 27 Corrected function to_nat for weak values
-- and combined into a single file
-- V1.3 M.Radmanovic 03 Aug 18 Added signed conversion function to_int
-- V1.4 M.Radmanovic 03 Nov 10 Added signed conversion function
-- int_to_slv
-- V1.5 R. Munden 04 NOV 11 Added type conversion to t_hex_str
-- V1.6 D. Rheault 07 MAY 21 Corrected int_to_slv for value of 0
-- V1.7 V.Markovic 08 Apr 24 Changed condition for variable int (in
-- function int_to_slv) from > to >=
-- V1.8 R. Munden 08 MAY 21 Fixed default base for x=0 in to_int_str
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
--------------------------------------------------------------------------------
-- CONVERSION FUNCTION SELECTION TABLES
--------------------------------------------------------------------------------
--
-- FROM TO: std_logic_vector std_logic natural time string
-- -----------------|---------------|---------|---------|---------|-----------
-- std_logic_vector | N/A | N/A | to_nat | combine | see below
-- std_logic | N/A | N/A | to_nat | combine | see below
-- natural | to_slv | to_sl | N/A | to_time | see below
-- integer | to_slv | N/A | N/A | N/A | N/A
-- time | N/A | N/A | to_nat | N/A | to_time_str
-- hex string | h | N/A | h | combine | N/A
-- decimal string | d | N/A | d | combine | N/A
-- octal string | o | N/A | o | combine | N/A
-- binary string | b | N/A | b | combine | N/A
-- -----------------|---------------|---------|---------|---------|-----------
--
-- FROM TO: hex string decimal string octal string binary string
-- -----------------|------------|-------------|------------|----------------
-- std_logic_vector | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- std_logic | N/A | N/A | N/A | to_bin_str
-- natural | to_hex_str | to_int_str | to_oct_str | to_bin_str
-- -----------------|------------|-------------|------------|----------------
--
-- FROM TO: integer
-- -----------------|---------------|
-- std_logic_vector | to_int |
--------------------------------------------------------------------------------
PACKAGE conversions IS
----------------------------------------------------------------------------
-- the conversions in this package are not intended to be synthesizable.
--
-- others functions available
-- fill creates a variable length string of the fill character
--
--
--
-- input parameters of type natural or integer can be in the form:
-- normal -> 8, 99, 4_237
-- base#value# -> 2#0101#, 16#fa4C#, 8#6_734#
-- with exponents(x10) -> 8e4, 16#2e#E4
--
-- input parameters of type string can be in the form:
-- "99", "4_237", "0101", "1010_1010"
--
-- for bit/bit_vector <-> std_logic/std_logic_vector conversions use
-- package std_logic_1164
-- to_bit(std_logic)
-- to_bitvector(std_logic_vector)
-- to_stdlogic(bit)
-- to_stdlogicvector(bit_vector)
--
-- for "synthesizable" signed/unsigned/std_logic_vector/integer
-- conversions use
-- package std_logic_arith
-- conv_integer(signed/unsigned)
-- conv_unsigned(integer/signed,size)
-- conv_signed(integer/unsigned,size)
-- conv_std_logic_vector(integer/signed/unsigned,size)
--
-- for "synthesizable" std_logic_vector -> integer conversions use
-- package std_logic_unsigned/std_logic_signed
--
-- conv_integer(std_logic_vector)
--
-- type1'(expression of type2)
--
-- most conversions have 4 parmeters:
-- x : value to be converted
-- rtn_len : size of the return value
-- justify : justify value 'left' or 'right', default is right
-- basespec : print the base of the value - 'yes'/'no', default is yes
--
-- Typical ways to call these functions:
-- simple, all defaults used
-- to_bin_str(x)
-- x will be converted to a string of minimum size with a
-- base specification appended for clarity
-- if x is 10101 then return is b"10101"
--
-- to control size of return string
-- to_hex_str(x,
-- 6)
-- length of string returned will be 6 characters
-- value will be right justified in the field
-- if x is 10101 then return is ....h"15"
-- where '.' represents a blank
-- if 'rtn_len' parm defaults or is set to 0 then
-- return string will always be minimum size
--
-- to left justify and suppress base specification
-- to_int_str(x,
-- 6,
-- justify => left,
-- basespec => yes)
-- length of return string will be 6 characters
-- the base specification will be suppressed
-- if x is 10101 then return is 21....
-- where '.' represents a blank
--
-- other usage notes
--
-- if rtn_len less than or equal to x'length then ignore
-- rtn_len and return string of x'length
-- the 'justify' parm is effectively ignored in this case
--
-- if rtn_len greater than x'length then return string
-- of rtn_len with blanks based on 'justify' parm
--
-- these routines do not handle negative numbers
----------------------------------------------------------------------------
type justify_side is (left, right);
type b_spec is (no , yes);
-- std_logic_vector to binary string
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- std_logic to binary string
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to binary string
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to hex string
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to hex string
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to octal string
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- natural to octal string
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- natural to integer string
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- see note above regarding possible formats for x
-- std_logic_vector to integer string
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string;
-- time to string
function to_time_str (x : time)
return string;
-- add characters to a string
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string;
-- usage:
-- fill
-- returns *
-- fill(' ',10)
-- returns .......... when '.' represents a blank
-- fill(lf) or fill(ht)
-- returns line feed character or tab character respectively
-- std_logic_vector to natural
function to_nat (x : std_logic_vector)
return natural;
-- std_logic to natural
function to_nat (x : std_logic)
return natural;
-- time to natural
function to_nat (x : time)
return natural;
-- hex string to std_logic_vector
function h (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F
-- or x,X,z,Z,u,U,-,w,W, result will be 0
-- decimal string to std_logic_vector
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- octal string to std_logic_vector
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 7 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- binary string to std_logic_vector
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- result will be 0
-- hex string to natural
function h (x : string)
return natural;
-- if x is other than characters 0 to 9 or a,A to f,F, result will be 0
-- decimal string to natural
function d (x : string)
return natural;
-- if x is other than characters 0 to 9, result will be 0
-- octal string to natural
function o (x : string)
return natural;
-- if x is other than characters 0 to 7, result will be 0
-- binary string to natural
function b (x : string)
return natural;
-- if x is other than characters 0 to 1, result will be 0
-- natural to std_logic_vector
function to_slv (x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- integer to std_logic_vector
function int_to_slv (x : integer;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector;
-- if rtn_len is < than sizeof(x), result will be truncated on the left
-- see note above regarding possible formats for x
-- natural to std_logic
function to_sl (x : natural)
return std_logic;
-- natural to time
function to_time (x : natural)
return time;
-- see note above regarding possible formats for x
-- std_logic_vector to integer
function to_int (x : std_logic_vector)
return integer;
END conversions;
--
--------------------------------------------------------------------------------
--
PACKAGE BODY conversions IS
-- private declarations for this package
type basetype is (binary, octal, decimal, hex);
function max(x,y: integer) return integer is
begin
if x > y then return x; else return y; end if;
end max;
function min(x,y: integer) return integer is
begin
if x < y then return x; else return y; end if;
end min;
-- consider function sizeof for string/slv/???, return natural
-- function size(len: natural) return natural is
-- begin
-- if len=0 then
-- return 31;
-- else return len;
-- end if;
-- end size;
function nextmultof (x : positive;
size : positive) return positive is
begin
case x mod size is
when 0 => return size * x/size;
when others => return size * (x/size + 1);
end case;
end nextmultof;
function rtn_base (base : basetype) return character is
begin
case base is
when binary => return 'b';
when octal => return 'o';
when decimal => return 'd';
when hex => return 'h';
end case;
end rtn_base;
function format (r : string;
base : basetype;
rtn_len : natural ;
justify : justify_side;
basespec : b_spec) return string is
variable int_rtn_len : integer;
begin
if basespec=yes then
int_rtn_len := rtn_len - 3;
else
int_rtn_len := rtn_len;
end if;
if int_rtn_len <= r'length then
case basespec is
when no => return r ;
when yes => return rtn_base(base) & '"' & r & '"';
end case;
else
case justify is
when left =>
case basespec is
when no =>
return r & fill(' ',int_rtn_len - r'length);
when yes =>
return rtn_base(base) & '"' & r & '"' &
fill(' ',int_rtn_len - r'length);
end case;
when right =>
case basespec is
when no =>
return fill(' ',int_rtn_len - r'length) & r ;
when yes =>
return fill(' ',int_rtn_len - r'length) &
rtn_base(base) & '"' & r & '"';
end case;
end case;
end if;
end format;
-- convert numeric string of any base to natural
function cnvt_base (x : string;
inbase : natural range 2 to 16) return natural is
-- assumes x is an unsigned number string of base 'inbase'
-- values larger than natural'high are not supported
variable r,t : natural := 0;
variable place : positive := 1;
begin
for i in x'reverse_range loop
case x(i) is
when '0' => t := 0;
when '1' => t := 1;
when '2' => t := 2;
when '3' => t := 3;
when '4' => t := 4;
when '5' => t := 5;
when '6' => t := 6;
when '7' => t := 7;
when '8' => t := 8;
when '9' => t := 9;
when 'a'|'A' => t := 10;
when 'b'|'B' => t := 11;
when 'c'|'C' => t := 12;
when 'd'|'D' => t := 13;
when 'e'|'E' => t := 14;
when 'f'|'F' => t := 15;
when '_' => t := 0; -- ignore these characters
place := place / inbase;
when others =>
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
if t / inbase > 1 then -- invalid value for base
assert false
report lf &
"CNVT_BASE found input value larger than base: " & lf &
"Input value: " & x(i) &
" Base: " & to_int_str(inbase) & lf &
"converting input to integer 0"
severity warning;
return 0;
else
r := r + (t * place);
place := place * inbase;
end if;
end loop;
return r;
end cnvt_base;
function extend (x : std_logic;
len : positive) return std_logic_vector is
variable v : std_logic_vector(1 to len) := (others => x);
begin
return v;
end extend;
-- implementation of public declarations
function to_bin_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : std_logic_vector(1 to x'length):=x;
variable r : string(1 to x'length):=(others=>'$');
begin
for i in int'range loop
r(i to i) := to_bin_str(int(i),basespec=>no);
end loop;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : std_logic;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable r : string(1 to 1);
begin
case x is
when '0' => r(1) := '0';
when '1' => r(1) := '1';
when 'U' => r(1) := 'U';
when 'X' => r(1) := 'X';
when 'Z' => r(1) := 'Z';
when 'W' => r(1) := 'W';
when 'H' => r(1) := 'H';
when 'L' => r(1) := 'L';
when '-' => r(1) := '-';
end case;
return format (r,binary,rtn_len,justify,basespec);
end to_bin_str;
function to_bin_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 2 to 32 := 32;
variable r : string(2 to 32):=(others=>'$');
begin
if int = 0 then
return format ("0",binary,rtn_len,justify,basespec);
end if;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_BIN_STR, shouldn't happen"
severity failure;
return "$";
null;
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),binary,rtn_len,justify,basespec);
end to_bin_str;
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/4
variable nxt : positive := nextmultof(x'length,4);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/4)+1 := 1;
variable r : string(1 to nxt/4):=(others=>'$');
subtype slv4 is std_logic_vector(1 to 4);
variable slv4_val : slv4;
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 4 /= 1;
slv4_val := int(i to i+3);
case slv4_val is
when "0000" => r(ptr) := '0';
when "0001" => r(ptr) := '1';
when "0010" => r(ptr) := '2';
when "0011" => r(ptr) := '3';
when "0100" => r(ptr) := '4';
when "0101" => r(ptr) := '5';
when "0110" => r(ptr) := '6';
when "0111" => r(ptr) := '7';
when "1000" => r(ptr) := '8';
when "1001" => r(ptr) := '9';
when "1010" => r(ptr) := 'A';
when "1011" => r(ptr) := 'B';
when "1100" => r(ptr) := 'C';
when "1101" => r(ptr) := 'D';
when "1110" => r(ptr) := 'E';
when "1111" => r(ptr) := 'F';
when "ZZZZ" => r(ptr) := 'Z';
when "WWWW" => r(ptr) := 'W';
when "LLLL" => r(ptr) := 'L';
when "HHHH" => r(ptr) := 'H';
when "UUUU" => r(ptr) := 'U';
when "XXXX" => r(ptr) := 'X';
when "----" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_HEX_STR found illegal value: " &
to_bin_str(int(i to i+3)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,hex,rtn_len,justify,basespec);
end to_hex_str;
function to_hex_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",hex,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 16 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when 10 => r(ptr) := 'A';
when 11 => r(ptr) := 'B';
when 12 => r(ptr) := 'C';
when 13 => r(ptr) := 'D';
when 14 => r(ptr) := 'E';
when 15 => r(ptr) := 'F';
when others =>
assert false report lf & "TO_HEX_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 16;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),hex,rtn_len,justify,basespec);
end to_hex_str;
function to_oct_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
-- will return x'length/3
variable nxt : positive := nextmultof(x'length,3);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/3)+1 := 1;
variable r : string(1 to nxt/3):=(others=>'$');
subtype slv3 is std_logic_vector(1 to 3);
begin
int(nxt-x'length+1 to nxt) := x;
if nxt-x'length > 0 and x(x'left) /= '1' then
int(1 to nxt-x'length) := extend(x(x'left),nxt-x'length);
end if;
for i in int'range loop
next when i rem 3 /= 1;
case slv3'(int(i to i+2)) is
when "000" => r(ptr) := '0';
when "001" => r(ptr) := '1';
when "010" => r(ptr) := '2';
when "011" => r(ptr) := '3';
when "100" => r(ptr) := '4';
when "101" => r(ptr) := '5';
when "110" => r(ptr) := '6';
when "111" => r(ptr) := '7';
when "ZZZ" => r(ptr) := 'Z';
when "WWW" => r(ptr) := 'W';
when "LLL" => r(ptr) := 'L';
when "HHH" => r(ptr) := 'H';
when "UUU" => r(ptr) := 'U';
when "XXX" => r(ptr) := 'X';
when "---" => r(ptr) := '-';
when others =>
assert false
report lf &
"TO_OCT_STR found illegal value: " &
to_bin_str(int(i to i+2)) & lf &
"converting input to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr + 1;
end loop;
return format (r,octal,rtn_len,justify,basespec);
end to_oct_str;
function to_oct_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 20 := 20;
variable r : string(1 to 20):=(others=>'$');
begin
if x=0 then return format ("0",octal,rtn_len,justify,basespec); end if;
while int > 0 loop
case int rem 8 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when others =>
assert false report lf & "TO_OCT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 8;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 20),octal,rtn_len,justify,basespec);
end to_oct_str;
function to_int_str(x : natural;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return string is
variable int : natural := x;
variable ptr : positive range 1 to 32 := 32;
variable r : string(1 to 32):=(others=>'$');
begin
if x=0 then return format ("0",decimal,rtn_len,justify,basespec);
else
while int > 0 loop
case int rem 10 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when 2 => r(ptr) := '2';
when 3 => r(ptr) := '3';
when 4 => r(ptr) := '4';
when 5 => r(ptr) := '5';
when 6 => r(ptr) := '6';
when 7 => r(ptr) := '7';
when 8 => r(ptr) := '8';
when 9 => r(ptr) := '9';
when others =>
assert false report lf & "TO_INT_STR, shouldn't happen"
severity failure;
return "$";
end case;
int := int / 10;
ptr := ptr - 1;
end loop;
return format (r(ptr+1 to 32),decimal,rtn_len,justify,basespec);
end if;
end to_int_str;
function to_int_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes)
return string is
begin
return to_int_str(to_nat(x),rtn_len,justify,basespec);
end to_int_str;
function to_time_str (x : time)
return string is
begin
return to_int_str(to_nat(x),basespec=>no) & " ns";
end to_time_str;
function fill (fill_char : character := '*';
rtn_len : integer := 1)
return string is
variable r : string(1 to max(rtn_len,1)) := (others => fill_char);
variable len : integer;
begin
if rtn_len < 2 then -- always returns at least 1 fill char
len := 1;
else
len := rtn_len;
end if;
return r(1 to len);
end fill;
function to_nat(x : std_logic_vector) return natural is
-- assumes x is an unsigned number, lsb on right,
-- more than 31 bits are truncated on left
variable t : std_logic_vector(1 to x'length) := x;
variable int : std_logic_vector(1 to 31) := (others => '0');
variable r : natural := 0;
variable place : positive := 1;
begin
if x'length < 32 then
int(max(32-x'length,1) to 31) := t(1 to x'length);
else -- x'length >= 32
int(1 to 31) := t(x'length-30 to x'length);
end if;
for i in int'reverse_range loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(int(i)) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
exit when i=1;
place := place * 2;
end loop;
return r;
end to_nat;
function to_nat (x : std_logic)
return natural is
begin
case x is
when '0' => return 0 ;
when '1' => return 1 ;
when others =>
assert false
report lf &
"TO_NAT found illegal value: " & to_bin_str(x) & lf &
"converting input to integer 0"
severity warning;
return 0;
end case;
end to_nat;
function to_nat (x : time)
return natural is
begin
return x / 1 ns;
end to_nat;
function h(x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*4, result will be truncated on the left
-- if x is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*4,rtn_len);
variable ptr : integer range -3 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-3 to ptr) := "0000";
when '1' => r(ptr-3 to ptr) := "0001";
when '2' => r(ptr-3 to ptr) := "0010";
when '3' => r(ptr-3 to ptr) := "0011";
when '4' => r(ptr-3 to ptr) := "0100";
when '5' => r(ptr-3 to ptr) := "0101";
when '6' => r(ptr-3 to ptr) := "0110";
when '7' => r(ptr-3 to ptr) := "0111";
when '8' => r(ptr-3 to ptr) := "1000";
when '9' => r(ptr-3 to ptr) := "1001";
when 'a'|'A' => r(ptr-3 to ptr) := "1010";
when 'b'|'B' => r(ptr-3 to ptr) := "1011";
when 'c'|'C' => r(ptr-3 to ptr) := "1100";
when 'd'|'D' => r(ptr-3 to ptr) := "1101";
when 'e'|'E' => r(ptr-3 to ptr) := "1110";
when 'f'|'F' => r(ptr-3 to ptr) := "1111";
when 'U' => r(ptr-3 to ptr) := "UUUU";
when 'X' => r(ptr-3 to ptr) := "XXXX";
when 'Z' => r(ptr-3 to ptr) := "ZZZZ";
when 'W' => r(ptr-3 to ptr) := "WWWW";
when 'H' => r(ptr-3 to ptr) := "HHHH";
when 'L' => r(ptr-3 to ptr) := "LLLL";
when '-' => r(ptr-3 to ptr) := "----";
when '_' => ptr := ptr + 4;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '----'"
severity warning;
r(ptr-3 to ptr) := "----";
end case;
ptr := ptr - 4;
end loop;
return r(size-rtn_len+1 to size);
end h;
function d (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than binary length of x, result will be truncated on
-- the left
-- if x is other than characters 0 to 9, result will be 0
begin
return to_slv(cnvt_base(x,10),rtn_len);
end d;
function o (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length*3, result will be truncated on the left
-- if x is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length*3,rtn_len);
variable ptr : integer range -2 to size := size;
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr-2 to ptr) := "000";
when '1' => r(ptr-2 to ptr) := "001";
when '2' => r(ptr-2 to ptr) := "010";
when '3' => r(ptr-2 to ptr) := "011";
when '4' => r(ptr-2 to ptr) := "100";
when '5' => r(ptr-2 to ptr) := "101";
when '6' => r(ptr-2 to ptr) := "110";
when '7' => r(ptr-2 to ptr) := "111";
when 'U' => r(ptr-2 to ptr) := "UUU";
when 'X' => r(ptr-2 to ptr) := "XXX";
when 'Z' => r(ptr-2 to ptr) := "ZZZ";
when 'W' => r(ptr-2 to ptr) := "WWW";
when 'H' => r(ptr-2 to ptr) := "HHH";
when 'L' => r(ptr-2 to ptr) := "LLL";
when '-' => r(ptr-2 to ptr) := "---";
when '_' => ptr := ptr + 3;
when others =>
assert false
report lf &
"O conversion found illegal input character: " &
int(i) & lf & "converting character to '---'"
severity warning;
r(ptr-2 to ptr) := "---";
end case;
ptr := ptr - 3;
end loop;
return r(size-rtn_len+1 to size);
end o;
function b (x : string;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than x'length, result will be truncated on the left
-- if x is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable int : string(1 to x'length) := x;
variable size: positive := max(x'length,rtn_len);
variable ptr : integer range 0 to size+1 := size; -- csa
variable r : std_logic_vector(1 to size) := (others=>'0');
begin
for i in int'reverse_range loop
case int(i) is
when '0' => r(ptr) := '0';
when '1' => r(ptr) := '1';
when 'U' => r(ptr) := 'U';
when 'X' => r(ptr) := 'X';
when 'Z' => r(ptr) := 'Z';
when 'W' => r(ptr) := 'W';
when 'H' => r(ptr) := 'H';
when 'L' => r(ptr) := 'L';
when '-' => r(ptr) := '-';
when '_' => ptr := ptr + 1;
when others =>
assert false
report lf &
"B conversion found illegal input character: " &
int(i) & lf & "converting character to '-'"
severity warning;
r(ptr) := '-';
end case;
ptr := ptr - 1;
end loop;
return r(size-rtn_len+1 to size);
end b;
function h (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- a,A to f,F
-- blanks, underscore
begin
return cnvt_base(x,16);
end h;
function d (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 9
-- blanks, underscore
begin
return cnvt_base(x,10);
end d;
function o (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 7
-- blanks, underscore
begin
return cnvt_base(x,8);
end o;
function b (x : string)
return natural is
-- only following characters are allowed, otherwise result will be 0
-- 0 to 1
-- blanks, underscore
begin
return cnvt_base(x,2);
end b;
function to_slv(x : natural;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : natural := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & "TO_SLV, shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
end to_slv;
function to_sl(x : natural)
return std_logic is
variable r : std_logic := '0';
begin
case x is
when 0 => null;
when 1 => r := '1';
when others =>
assert false
report lf &
"TO_SL found illegal input character: " &
to_int_str(x) & lf & "converting character to '-'"
severity warning;
return '-';
end case;
return r;
end to_sl;
function int_to_slv(x : integer;
rtn_len : positive range 1 to 32 := 32)
return std_logic_vector is
-- if rtn_len is < than sizeof(x), result will be truncated on the left
variable int : integer := x;
variable ptr : positive := 32;
variable r : std_logic_vector(1 to 32) := (others=>'0');
begin
if int >= 0 or int = 0 then
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & " shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
return r(33-rtn_len to 32);
else
int := 2**(rtn_len - 1) + int;
while int > 0 loop
case int rem 2 is
when 0 => r(ptr) := '0';
when 1 => r(ptr) := '1';
when others =>
assert false report lf & " shouldn't happen"
severity failure;
return "0";
end case;
int := int / 2;
ptr := ptr - 1;
end loop;
r(33-rtn_len) := '1';
return r(33-rtn_len to 32);
end if;
end int_to_slv;
function to_time (x: natural) return time is
begin
return x * 1 ns;
end to_time;
function to_int(x : std_logic_vector) return integer is
-- assumes x is an signed number
-- more than 32 bits are truncated on left
variable t : std_logic_vector(x'length downto 1) := x;
variable int : std_logic_vector(32 downto 1) := (others => '0');
variable sign : std_logic := '0';
variable size : integer := 0;
variable inv : boolean := false;
variable r : integer := 0;
variable place : positive := 1;
begin
if x'length < 33 then
sign := t(x'length);
for i in t'reverse_range loop
if sign = '1' then
if inv = true then
t(i) := not(t(i));
elsif t(i) = '1' then
inv := true;
end if;
end if;
size := size +1;
end loop;
inv := false;
for i in 1 to size - 1 loop
case t(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
" TO_INT found illegal value "
severity warning;
return 0;
end case;
place := place * 2;
end loop;
if sign = '1' THEN
return (- r);
else
return r;
end if;
else -- x'length >= 33
int := t(32 downto 1);
sign := t(32);
for i in 1 to 31 loop
if sign = '1' then
if inv = true then
int(i) := not(int(i));
elsif int(i) = '1' then
inv := true;
end if;
end if;
end loop;
inv := false;
for i in 1 to 31 loop
case int(i) is
when '1' | 'H' => r := r + place;
when '0' | 'L' => null;
when others =>
assert false
report lf &
" TO_INT found illegal value "
severity warning;
return 0;
end case;
place := place * 2;
end loop;
if sign = '1' THEN
return (- r);
else
return r;
end if;
end if;
end to_int;
END conversions;
modelsim_lib.vhd 0000664 0000000 0000000 00000010203 14574545710 0036101 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x010-00_src/Source -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik Nuremberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : ModelSim library for Riviera-PRO
-- Project :
--------------------------------------------------------------------------------
-- File : modelsim_lib.vhd
-- Author : M. Henze
-- Email :
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created :
--------------------------------------------------------------------------------
-- Simulator : Riviera-PRO
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- CAUTION - this file shall not be used for new designs. It is only kept
-- for compliance with old designs.
-- For new designs use VHDL2008 syntax instead.
--
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
LIBRARY aldec;
USE aldec.signal_agent_pkg.ALL;
USE aldec.aldec_tools.ALL;
----------------------------------------
-- CAUTION! Don't use for new designs!
-- Use VHDL2008 instead!
----------------------------------------
PACKAGE util IS
TYPE force_type IS (default, deposit, drive, freeze);
type del_mode is (MTI_INERTIAL, MTI_TRANSPORT);
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer);
procedure init_signal_spy(
source : in string;
dest : in string
);
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer);
PROCEDURE signal_release( destination : IN string;
verbose : IN integer);
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
);
END;
PACKAGE BODY util IS
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer) IS
BEGIN
signal_agent(source, destination ,verbose);
END PROCEDURE init_signal_spy;
procedure init_signal_spy(
source : in string;
dest : in string
) is
begin
signal_agent(source,dest,0);
end procedure init_signal_spy;
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--force(force_type'image(forcetype), destination, value);
force_signal(force_type'image(forcetype), destination, value);
END PROCEDURE signal_force;
PROCEDURE signal_release( destination : IN string;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--noforce ( destination );
noforce_signal ( destination );
END PROCEDURE signal_release;
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
) is
begin
signal_agent(src_obj, dest_obj, 0);
end procedure init_signal_driver;
END;
print_pkg.vhd 0000664 0000000 0000000 00000100047 14574545710 0035445 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x010-00_src/Source -- SPDX-FileCopyrightText: 2001 MEN Mikroelektronik Nuernberg GmbH
--
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Print Package
-- Project : none
---------------------------------------------------------------
-- File : print_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 26/08/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
-- several procedures and functions for screen printing
---------------------------------------------------------------
-- Hierarchy:
--
-- none
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.9 $
--
-- $Log: print_pkg.vhd,v $
-- Revision 1.9 2015/11/12 14:57:26 AGeissler
-- R1: Missing now procedure with one string
-- M1: Overload existing print_now_s with sting instead of integer
--
-- Revision 1.8 2015/11/12 13:56:46 AGeissler
-- R1: Missing character to std_logic_vector conversion function
-- M1: Added functions std_logic_vector_to_char and char_to_std_logic_vector
-- R2: Missing now procedures
-- M2: Added for each procedure a equivalent one, with an additional time print
--
-- Revision 1.7 2015/11/12 11:04:50 AGeissler
-- R1: The user shall decide, when and if spaces are used
-- M1: Removed spaces from print procedures
--
-- Revision 1.6 2015/03/10 10:20:34 AGeissler
-- R1: Improvement
-- M1.1: Added overloaded function for print_s_hb, print_s_hw, print_s_hl with std_logic_vector as parameter
-- M1.2: Replaced print_s_bit with print_s_std as a overloaded function with a std_logic as parameter
-- M1.3: Added short description for each function
--
-- Revision 1.5 2015/03/10 09:25:56 AGeissler
-- R1: Missing function to print an single bit
-- M1: Added function print_s_bit
--
-- Revision 1.4 2014/12/02 17:27:10 AGeissler
-- R1: Missing print functions for integer in hex with different sizes
-- M1: Added print functions print_s_hb, print_s_hw, print_s_hl
--
-- Revision 1.3 2014/11/24 11:26:00 AGeissler
-- R1: Missing function to print two strings for example text + time
-- (print_s(" it took ", time'image(tmp_time));)
-- M1: Added procedure print_s
--
-- Revision 1.2 2006/03/01 09:34:09 mmiehling
-- added print_now_s
--
-- Revision 1.1 2005/10/20 10:42:26 mmiehling
-- Initial Revision
--
-- Revision 1.1 2005/09/15 12:05:59 MMiehling
-- Initial Revision
--
-- Revision 1.2 2004/05/13 14:22:49 MMiehling
-- multifunction device support
--
-- Revision 1.1 2004/04/14 09:42:28 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_textio.all;
USE ieee.numeric_std.all;
LIBRARY std;
USE std.textio.all;
PACKAGE print_pkg IS
PROCEDURE print_mtest ( source : string;
address : std_logic_vector;
is_data : std_logic_vector;
should_data : std_logic_vector;
arg : boolean);
PROCEDURE print (s: IN string);
PROCEDURE print_s (s: IN string; s2: IN string);
PROCEDURE print_s_s (s: IN string; s2: IN string; s3: IN string);
PROCEDURE print_s_i (s: IN string; s2: IN integer);
PROCEDURE print_s_h (s: IN string; s2: IN integer);
PROCEDURE print_s_hb (s: IN string; s2: IN integer);
PROCEDURE print_s_hw (s: IN string; s2: IN integer);
PROCEDURE print_s_hl (s: IN string; s2: IN integer);
PROCEDURE print_s_hb (s: IN string; s2: IN std_logic_vector(7 DOWNTO 0));
PROCEDURE print_s_hw (s: IN string; s2: IN std_logic_vector(15 DOWNTO 0));
PROCEDURE print_s_hl (s: IN string; s2: IN std_logic_vector(31 DOWNTO 0));
PROCEDURE print_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_cycle ( header : string;
address : std_logic_vector;
data : std_logic_vector;
sel_o_int : std_logic_vector(3 DOWNTO 0);
ende : string);
PROCEDURE print_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_s_std (s: IN string; vec: IN std_logic_vector);
PROCEDURE print_time (s: IN string);
PROCEDURE print_sum (intext: IN string; mstr_err: IN integer; wb_err: IN integer);
-- now procedures
PROCEDURE print_now (s: IN string);
PROCEDURE print_now_s (s: IN string; s2: IN integer);
PROCEDURE print_now_s (s: IN string; s2: IN string);
PROCEDURE print_now_s_s (s: IN string; s2: IN string; s3: IN string);
PROCEDURE print_now_s_i (s: IN string; s2: IN integer);
PROCEDURE print_now_s_h (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hb (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hw (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hl (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hb (s: IN string; s2: IN std_logic_vector(7 DOWNTO 0));
PROCEDURE print_now_s_hw (s: IN string; s2: IN std_logic_vector(15 DOWNTO 0));
PROCEDURE print_now_s_hl (s: IN string; s2: IN std_logic_vector(31 DOWNTO 0));
PROCEDURE print_now_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_now_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_now_s_std (s: IN string; vec: IN std_logic_vector);
FUNCTION char_to_std_logic_vector(arg : character) RETURN std_logic_vector;
FUNCTION std_logic_vector_to_char(arg : std_logic_vector(7 DOWNTO 0)) RETURN character;
END print_pkg;
PACKAGE BODY print_pkg IS
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string with the current simulation time
PROCEDURE print_time(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITELINE(output,l);
END print_time;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic
PROCEDURE print_s_std(s: IN string; bit: IN std_logic) IS
VARIABLE l: line;
VARIABLE s2: string(1 TO 3);
BEGIN
WRITE(l, s);
IF bit = '1' THEN
s2 := "'1'";
ELSE
s2 := "'0'";
END IF;
WRITE(l, s2);
WRITELINE(output,l);
END print_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_s_std(s: IN string; vec: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, vec);
WRITELINE(output,l);
END print_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print wishbone information
PROCEDURE print_cycle( header : string;
address : std_logic_vector;
data : std_logic_vector;
sel_o_int: std_logic_vector(3 DOWNTO 0);
ende : string) IS
VARIABLE l : line;
BEGIN
WRITE(l,header);
WRITE(l,string'(" "));
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l,string'(" ADR: "));
HWRITE(l,address,justified=>left);
WRITE(l,string'(" DATA: "));
IF address(1) = '0' THEN
CASE sel_o_int IS
WHEN "1111" => HWRITE(l,data);
WHEN "0001" => HWRITE(l,data(7 DOWNTO 0));
WRITE(l,string'(" "));
WHEN "0010" => HWRITE(l,data(15 DOWNTO 8));
WRITE(l,string'(" "));
WHEN "0100" => HWRITE(l,data(23 DOWNTO 16));
WRITE(l,string'(" "));
WHEN "1000" => HWRITE(l,data(31 DOWNTO 24));
WRITE(l,string'(" "));
WHEN "0011" => HWRITE(l,data(15 DOWNTO 0));
WRITE(l,string'(" "));
WHEN "1100" => HWRITE(l,data(31 DOWNTO 16));
WRITE(l,string'(" "));
WHEN OTHERS => ASSERT FALSE REPORT "PRINT_PKG Error: sel_o is undefined" SEVERITY error;
END CASE;
ELSE
HWRITE(l,data);
END IF;
WRITE(l,string'(" "));
WRITE(l,ende);
WRITELINE(output,l);
END print_cycle;
----------------------------------------------------------------------------------------------------------------------------------------
-- print the result of a memory test
PROCEDURE print_mtest( source : string;
address : std_logic_vector;
is_data : std_logic_vector;
should_data : std_logic_vector;
arg : boolean) IS
VARIABLE tranx : line;
BEGIN
WRITE(tranx,source);
WRITE(tranx,now, justified=>right,field =>10, unit=> ns );
WRITE(tranx,string'(" Memory Test "));
WRITE(tranx,string'(" ADR: "));
HWRITE(tranx,address,justified=>left);
IF NOT arg THEN
WRITE(tranx,string'(" DATA should be: "));
HWRITE(tranx,should_data);
WRITE(tranx, string'(" is "));
ELSE
WRITE(tranx,string'(" DATA: "));
END IF;
HWRITE(tranx,is_data);
WRITE(tranx,string'(" "));
IF arg THEN
WRITE(tranx,string'("OK"));
ELSE
WRITE(tranx,string'("ERROR!"));
END IF;
WRITELINE(output,tranx);
END print_mtest;
----------------------------------------------------------------------------------------------------------------------------------------
-- print string
PROCEDURE print(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITELINE(output,l);
END print;
----------------------------------------------------------------------------------------------------------------------------------------
-- print two strings (for example to print string and time = print_s(" it took ", time'image(tmp_time));
PROCEDURE print_s(s: IN string;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print three strings (for example to print string, value and type = print_s(" it took ", integer, "ns");
PROCEDURE print_s_s(s: IN string; s2: IN string; s3: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITE(l, s3);
WRITELINE(output,l);
END print_s_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a integer as a decimal number
PROCEDURE print_s_i(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_s_i;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits (equal to print_s_hl but is needed to be backward compatible)
PROCEDURE print_s_h(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_s_h;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 2 digits
PROCEDURE print_s_hb(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,8)));
WRITELINE(output,l);
END print_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 4 digits
PROCEDURE print_s_hw(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,16)));
WRITELINE(output,l);
END print_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits
PROCEDURE print_s_hl(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 2 digits
PROCEDURE print_s_hb(s: IN string;s2: IN std_logic_vector(7 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 4 digits
PROCEDURE print_s_hw(s: IN string;s2: IN std_logic_vector(15 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 8 digits
PROCEDURE print_s_hl(s: IN string;s2: IN std_logic_vector(31 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a decimal number
PROCEDURE print_s_dl(s: IN string;s2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, to_integer(unsigned(s2)));
WRITELINE(output,l);
END print_s_dl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print the result of a test case
PROCEDURE print_sum(intext: IN string; mstr_err: IN integer; wb_err: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, string'(" "));
WRITELINE(output,l);
IF mstr_err = 0 AND wb_err = 0 THEN
WRITE(l, string'(" P A S S "));
WRITE(l, intext);
WRITELINE(output,l);
ELSE
WRITE(l, string'(" F A I L "));
WRITE(l, intext);
WRITELINE(output,l);
WRITE(l, string'(" Number of PCI errors: "));
WRITE(l, mstr_err);
WRITELINE(output,l);
WRITE(l, string'(" Number of WB errors: "));
WRITE(l, wb_err);
WRITELINE(output,l);
END IF;
WRITE(l, string'("*************************************************************************************************************"));
WRITELINE(output,l);
END print_sum;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string with the current simulation time
PROCEDURE print_now(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITELINE(output,l);
END print_now;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and an integer as decimal number withthe current simulation time
PROCEDURE print_now_s(s: IN string; s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print two strings (for example to print string and time = print_s(" it took ", time'image(tmp_time));
PROCEDURE print_now_s(s: IN string;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print three strings (for example to print string, value and type = print_s(" it took ", integer, "ns");
PROCEDURE print_now_s_s(s: IN string; s2: IN string; s3: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITE(l, s3);
WRITELINE(output,l);
END print_now_s_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a integer as a decimal number
PROCEDURE print_now_s_i(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_i;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits (equal to print_s_hl but is needed to be backward compatible)
PROCEDURE print_now_s_h(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_now_s_h;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 2 digits
PROCEDURE print_now_s_hb(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,8)));
WRITELINE(output,l);
END print_now_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 4 digits
PROCEDURE print_now_s_hw(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,16)));
WRITELINE(output,l);
END print_now_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits
PROCEDURE print_now_s_hl(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_now_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 2 digits
PROCEDURE print_now_s_hb(s: IN string;s2: IN std_logic_vector(7 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 4 digits
PROCEDURE print_now_s_hw(s: IN string;s2: IN std_logic_vector(15 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 8 digits
PROCEDURE print_now_s_hl(s: IN string;s2: IN std_logic_vector(31 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a decimal number
PROCEDURE print_now_s_dl(s: IN string;s2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, to_integer(unsigned(s2)));
WRITELINE(output,l);
END print_now_s_dl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic
PROCEDURE print_now_s_std(s: IN string; bit: IN std_logic) IS
VARIABLE l: line;
VARIABLE s2: string(1 TO 3);
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
IF bit = '1' THEN
s2 := "'1'";
ELSE
s2 := "'0'";
END IF;
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std(s: IN string; vec: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, vec);
WRITELINE(output,l);
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert character to std_logic_vector
FUNCTION char_to_std_logic_vector( arg : character) RETURN std_logic_vector IS
BEGIN
RETURN std_logic_vector(to_unsigned(character'POS(arg), 8));
END FUNCTION char_to_std_logic_vector;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert std_logic_vector to character
FUNCTION std_logic_vector_to_char( arg : std_logic_vector(7 DOWNTO 0) ) RETURN character IS
BEGIN
CASE arg IS
-- NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
-- BS, HT, LF, VT, FF, CR, SO, SI,
WHEN "00000000" =>
RETURN NUL;
WHEN "00000001" =>
RETURN SOH;
WHEN "00000010" =>
RETURN STX;
WHEN "00000011" =>
RETURN ETX;
WHEN "00000100" =>
RETURN EOT;
WHEN "00000101"=>
RETURN ENQ;
WHEN "00000110" =>
RETURN ACK;
WHEN "00000111" =>
RETURN BEL;
WHEN "00001000" =>
RETURN BS;
WHEN "00001001" =>
RETURN HT;
WHEN "00001010" =>
RETURN LF;
WHEN "00001011" =>
RETURN VT;
WHEN "00001100" =>
RETURN FF;
WHEN "00001101" =>
RETURN CR;
WHEN "00001110" =>
RETURN SO;
WHEN "00001111" =>
RETURN SI;
-- DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
-- CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
WHEN "00010000" =>
RETURN DLE;
WHEN "00010001" =>
RETURN DC1;
WHEN "00010010" =>
RETURN DC2;
WHEN "00010011" =>
RETURN DC3;
WHEN "00010100" =>
RETURN DC4;
WHEN "00010101" =>
RETURN NAK;
WHEN "00010110" =>
RETURN SYN;
WHEN "00010111" =>
RETURN ETB;
WHEN "00011000" =>
RETURN CAN;
WHEN "00011001" =>
RETURN EM;
WHEN "00011010" =>
RETURN SUB;
WHEN "00011011" =>
RETURN ESC;
WHEN "00011100" =>
RETURN FSP;
WHEN "00011101" =>
RETURN GSP;
WHEN "00011110" =>
RETURN RSP;
WHEN "00011111" =>
RETURN USP;
-- ' ', '!', '"', '#', '$', '%', '&', ''',
-- '(', ')', '*', '+', ',', '-', '.', '/',
WHEN "00100000" =>
RETURN ' ';
WHEN "00100001" =>
RETURN '!';
WHEN "00100010" =>
RETURN '"'; --"
WHEN "00100011" =>
RETURN '#';
WHEN "00100100" =>
RETURN '$';
WHEN "00100101" =>
RETURN '%';
WHEN "00100110" =>
RETURN '&';
WHEN "00100111" =>
RETURN ''';
WHEN "00101000" =>
RETURN '(';
WHEN "00101001" =>
RETURN ')';
WHEN "00101010" =>
RETURN '*';
WHEN "00101011" =>
RETURN '+';
WHEN "00101100" =>
RETURN ',';
WHEN "00101101" =>
RETURN '-';
WHEN "00101110" =>
RETURN '.';
WHEN "00101111" =>
RETURN '/';
-- '0', '1', '2', '3', '4', '5', '6', '7',
-- '8', '9', ':', ';', '<', '=', '>', '?',
WHEN "00110000" =>
RETURN '0';
WHEN "00110001" =>
RETURN '1';
WHEN "00110010" =>
RETURN '2';
WHEN "00110011" =>
RETURN '3';
WHEN "00110100" =>
RETURN '4';
WHEN "00110101" =>
RETURN '5';
WHEN "00110110" =>
RETURN '6';
WHEN "00110111" =>
RETURN '7';
WHEN "00111000" =>
RETURN '8';
WHEN "00111001" =>
RETURN '9';
WHEN "00111010" =>
RETURN ':';
WHEN "00111011" =>
RETURN ';';
WHEN "00111100" =>
RETURN '<';
WHEN "00111101" =>
RETURN '=';
WHEN "00111110" =>
RETURN '>';
WHEN "00111111" =>
RETURN '?';
-- '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
-- 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
WHEN "01000000" =>
RETURN '@';
WHEN "01000001" =>
RETURN 'A';
WHEN "01000010" =>
RETURN 'B';
WHEN "01000011" =>
RETURN 'C';
WHEN "01000100" =>
RETURN 'D';
WHEN "01000101" =>
RETURN 'E';
WHEN "01000110" =>
RETURN 'F';
WHEN "01000111" =>
RETURN 'G';
WHEN "01001000" =>
RETURN 'H';
WHEN "01001001" =>
RETURN 'I';
WHEN "01001010" =>
RETURN 'J';
WHEN "01001011" =>
RETURN 'K';
WHEN "01001100" =>
RETURN 'L';
WHEN "01001101" =>
RETURN 'M';
WHEN "01001110" =>
RETURN 'N';
WHEN "01001111" =>
RETURN 'O';
-- 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
-- 'X', 'Y', 'Z', '[', '\', ']', '^', '_',
WHEN "01010000" =>
RETURN 'P';
WHEN "01010001" =>
RETURN 'Q';
WHEN "01010010" =>
RETURN 'R';
WHEN "01010011" =>
RETURN 'S';
WHEN "01010100" =>
RETURN 'T';
WHEN "01010101" =>
RETURN 'U';
WHEN "01010110" =>
RETURN 'V';
WHEN "01010111" =>
RETURN 'W';
WHEN "01011000" =>
RETURN 'X';
WHEN "01011001" =>
RETURN 'Y';
WHEN "01011010" =>
RETURN 'Z';
WHEN "01011011" =>
RETURN '[';
WHEN "01011100" =>
RETURN '\';
WHEN "01011101" =>
RETURN ']';
WHEN "01011110" =>
RETURN '^';
WHEN "01011111" =>
RETURN '_';
-- '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
-- 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
WHEN "01100000" =>
RETURN '`';
WHEN "01100001" =>
RETURN 'a';
WHEN "01100010" =>
RETURN 'b';
WHEN "01100011" =>
RETURN 'c';
WHEN "01100100" =>
RETURN 'd';
WHEN "01100101" =>
RETURN 'e';
WHEN "01100110" =>
RETURN 'f';
WHEN "01100111" =>
RETURN 'g';
WHEN "01101000" =>
RETURN 'h';
WHEN "01101001" =>
RETURN 'i';
WHEN "01101010" =>
RETURN 'j';
WHEN "01101011" =>
RETURN 'k';
WHEN "01101100" =>
RETURN 'l';
WHEN "01101101" =>
RETURN 'm';
WHEN "01101110" =>
RETURN 'n';
WHEN "01101111" =>
RETURN 'o';
-- 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
-- 'x', 'y', 'z', '{', '|', '}', '~', DEL,
WHEN "01110000" =>
RETURN 'p';
WHEN "01110001" =>
RETURN 'q';
WHEN "01110010" =>
RETURN 'r';
WHEN "01110011" =>
RETURN 's';
WHEN "01110100" =>
RETURN 't';
WHEN "01110101" =>
RETURN 'u';
WHEN "01110110" =>
RETURN 'v';
WHEN "01110111" =>
RETURN 'w';
WHEN "01111000" =>
RETURN 'x';
WHEN "01111001" =>
RETURN 'y';
WHEN "01111010" =>
RETURN 'z';
WHEN "01111011" =>
RETURN '{';
WHEN "01111100" =>
RETURN '|';
WHEN "01111101" =>
RETURN '}';
WHEN "01111110" =>
RETURN '~';
WHEN "01111111" =>
RETURN DEL;
WHEN OTHERS =>
RETURN '0';
END CASE;
-- missing characters:
-- C128, C129, C130, C131, C132, C133, C134, C135,
-- C136, C137, C138, C139, C140, C141, C142, C143,
-- C144, C145, C146, C147, C148, C149, C150, C151,
-- C152, C153, C154, C155, C156, C157, C158, C159,
-- ' ', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '',
-- '', '', '', '', '', '', '', '');
END FUNCTION std_logic_vector_to_char;
END; terminal.vhd 0000664 0000000 0000000 00000012327 14574545710 0035266 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x010-00_src/Source -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Simulation Terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 10/11/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Application Layer for simulation stimuli
---------------------------------------------------------------
-- Hierarchy:
--
-- testbench
-- terminal
-- wb_test
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: terminal.vhd,v $
-- Revision 1.2 2006/03/15 14:21:54 mmiehling
-- extended tga
-- removed "use work.vme_pkg.all"
--
-- Revision 1.1 2005/08/23 15:21:05 MMiehling
-- Initial Revision
--
-- Revision 1.3 2005/03/18 15:14:18 MMiehling
-- changed
--
-- Revision 1.2 2005/01/31 16:28:56 mmiehling
-- updated
--
-- Revision 1.1 2004/11/16 12:09:06 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.print_pkg.all;
USE work.terminal_pkg.ALL;
ENTITY terminal IS
PORT (
rst : IN std_logic;
terminal_in_0 : IN terminal_in_type;
terminal_out_0 : OUT terminal_out_type;
terminal_in_1 : IN terminal_in_type;
terminal_out_1 : OUT terminal_out_type
);
END terminal;
ARCHITECTURE terminal_arch OF terminal IS
SIGNAL terminal_err_0 : integer:=0;
SIGNAL terminal_err_1 : integer:=0;
SIGNAL end_of_tests : boolean;
CONSTANT en_msg_0 : boolean:= false;
CONSTANT en_msg_1 : boolean:= false;
BEGIN
term_0: PROCESS
VARIABLE err : integer;
BEGIN
init(terminal_out_0);
IF rst /= '0' THEN
WAIT until rst = '0';
END IF;
WAIT FOR 1000 ns;
print("***************************************************");
print(" Start of Tests");
print("***************************************************");
-- wr32(terminal_in_0, terminal_out_0, x"0000_0050", x"1234_5678", 1, en_msg_0, TRUE, "000000");
-- wait_for(terminal_in_0, terminal_out_0, 5, TRUE);
-- rd32(terminal_in_0, terminal_out_0, x"0000_0050", x"1234_5678", 1, en_msg_0, TRUE, "000000", err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- wait_for(terminal_in_0, terminal_out_0, 5, TRUE);
wr32(terminal_in_0, terminal_out_0, x"0000_0000", x"0000_0000", 3000, en_msg_0, TRUE, "000000");
rd32(terminal_in_0, terminal_out_0, x"0000_0000", x"0000_0000", 3000, en_msg_0, TRUE, "000000", err);
terminal_err_0 <= terminal_err_0 + err;
wr32(terminal_in_0, terminal_out_0, x"0000_0000", x"0000_0000", 500, en_msg_0, TRUE, "000000");
rd32(terminal_in_0, terminal_out_0, x"0000_0000", x"0000_0000", 500, en_msg_0, TRUE, "000000", err);
terminal_err_0 <= terminal_err_0 + err;
sdram_burst(terminal_in_0, terminal_out_0, x"0000_0000", en_msg_0, terminal_err_0);
wr32(terminal_in_0, terminal_out_0, x"0000_0100", x"0000_0100", 500, en_msg_0, TRUE, "000000");
rd32(terminal_in_0, terminal_out_0, x"0000_0100", x"0000_0100", 500, en_msg_0, TRUE, "000000", err);
terminal_err_0 <= terminal_err_0 + err;
wr32(terminal_in_0, terminal_out_0, x"0000_0200", x"0000_0200", 500, en_msg_0, TRUE, "000000");
rd32(terminal_in_0, terminal_out_0, x"0000_0200", x"0000_0200", 500, en_msg_0, TRUE, "000000", err);
terminal_err_0 <= terminal_err_0 + err;
wr32(terminal_in_0, terminal_out_0, x"0000_0300", x"0000_0300", 500, en_msg_0, TRUE, "000000");
rd32(terminal_in_0, terminal_out_0, x"0000_0300", x"0000_0300", 500, en_msg_0, TRUE, "000000", err);
terminal_err_0 <= terminal_err_0 + err;
IF end_of_tests = FALSE THEN
WAIT on end_of_tests;
END IF;
WAIT FOR 2000 ns;
print("***************************************************");
print(" Test Summary:");
print_s_i(" Number of errors: ", terminal_err_0);
print_s_i(" Number of errors: ", terminal_err_1);
print("***************************************************");
ASSERT FALSE REPORT "--- END OF SIMULATION ---" SEVERITY failure;
END PROCESS term_0;
term_1: PROCESS
VARIABLE err : integer;
BEGIN
init(terminal_out_1);
end_of_tests <= FALSE;
IF rst /= '0' THEN
WAIT until rst = '0';
END IF;
WAIT FOR 1000 ns;
sdram_burst(terminal_in_1, terminal_out_1, x"0000_5000", en_msg_1, terminal_err_1);
wr32(terminal_in_1, terminal_out_1, x"0000_0060", x"abcd_ef01", 1, en_msg_1, TRUE, "000000");
rd32(terminal_in_1, terminal_out_1, x"0000_0060", x"abcd_ef01", 1, en_msg_1, TRUE, "000000", err);
terminal_err_1 <= terminal_err_1 + err;
wr32(terminal_in_1, terminal_out_1, x"0000_5000", x"0000_0000", 2000, en_msg_1, TRUE, "000000");
rd32(terminal_in_1, terminal_out_1, x"0000_5000", x"0000_0000", 2000, en_msg_1, TRUE, "000000", err);
terminal_err_1 <= terminal_err_1 + err;
end_of_tests <= TRUE;
WAIT;
END PROCESS term_1;
END terminal_arch;
terminal_pkg.vhd 0000664 0000000 0000000 00000052571 14574545710 0036134 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/16x010-00_src/Source -- SPDX-FileCopyrightText: 2001 MEN Mikroelektronik Nuernberg GmbH
--
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Package for simulation terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 22/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.9 $
--
-- $Log: terminal_pkg.vhd,v $
-- Revision 1.9 2010/08/16 12:57:16 FLenhardt
-- Added an overloaded MTEST which accepts a seed number as an input
--
-- Revision 1.8 2009/01/13 10:57:52 FLenhardt
-- Defined that TGA=2 means configuration access
--
-- Revision 1.7 2008/09/10 17:26:45 MSchindler
-- added flash_mtest_indirect procedure
--
-- Revision 1.6 2007/07/26 07:48:15 FLenhardt
-- Defined usage of TGA
--
-- Revision 1.5 2007/07/18 10:53:34 FLenhardt
-- Fixed bug regarding MTEST printout
--
-- Revision 1.4 2007/07/18 10:28:35 mernst
-- - Changed err to sum up errors instead of setting a specific value
-- - Added dat vector to terminal_in record
--
-- Revision 1.3 2006/08/24 08:52:02 mmiehling
-- changed txt_out to integer
--
-- Revision 1.1 2006/06/23 16:33:04 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/12 10:49:17 MMiehling
-- initialization of iram now with mem_init (back)
-- added testcase 14
--
-- Revision 1.1 2006/05/09 16:51:16 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/10/27 08:35:35 flenhardt
-- Added IRQ to TERMINAL_IN_TYPE record
--
-- Revision 1.1 2005/08/23 15:21:07 MMiehling
-- Initial Revision
--
-- Revision 1.1 2005/07/01 15:47:38 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/01/31 16:28:59 mmiehling
-- updated
--
-- Revision 1.1 2004/11/16 12:09:07 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.print_pkg.all;
USE ieee.std_logic_arith.ALL;
PACKAGE terminal_pkg IS
TYPE terminal_in_type IS record
done : boolean; -- edge indicates end of transfer
busy : std_logic; -- indicates status of master
err : natural; -- number of errors occured
irq : std_logic; -- interrupt request
dat : std_logic_vector(31 DOWNTO 0); -- Input data
END record;
TYPE terminal_out_type IS record
adr : std_logic_vector(31 DOWNTO 0); -- address
tga : std_logic_vector(5 DOWNTO 0); -- 0=mem, 1=io, 2=conf
dat : std_logic_vector(31 DOWNTO 0); -- write data
wr : natural; -- 0=read, 1=write, 2=wait for numb cycles
typ : natural; -- 0=b, w=1, l=2
numb : natural; -- number of transactions (1=single, >1=burst)
start : boolean; -- edge starts transfer
txt : integer; -- enables info messages -- 0=quiet, 1=only errors, 2=all
END record;
-- Bus Accesses
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type);
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
);
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) ;
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) ;
PROCEDURE flash_mtest_indirect( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
adr_if : std_logic_vector; -- = address of indirect interface
txt_out : integer;
tga : std_logic_vector;
err : OUT natural
) ;
END terminal_pkg;
PACKAGE BODY terminal_pkg IS
----------------------------------------------------------------------------------------------------------
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type) IS
BEGIN
terminal_out.adr <= (OTHERS => '0');
terminal_out.tga <= (OTHERS => '0');
terminal_out.dat <= (OTHERS => '0');
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.numb <= 0;
terminal_out.txt <= 0;
terminal_out.start <= TRUE;
END PROCEDURE init;
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
) IS
BEGIN
terminal_out.wr <= 2;
terminal_out.numb <= numb;
terminal_out.txt <= 0;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
-- This is the legacy MTEST (without seed)
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
mtest(terminal_in, terminal_out, adr, adr_end, typ, numb, txt_out, tga, 0, err);
END PROCEDURE;
-- This is an overloaded MTEST which accepts a seed number as an input,
-- which can be used to generate the pseudo-random data in different ways
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) IS
VARIABLE loc_err : natural;
VARIABLE loc_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE loc_dat : std_logic_vector(31 DOWNTO 0);
VARIABLE numb_cnt : natural;
BEGIN
loc_adr := adr;
numb_cnt := 0;
loc_err := 0;
loc_dat := adr;
while NOT(numb_cnt = numb) LOOP
CASE typ IS
WHEN 0 => -- long
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"4";
END LOOP;
WHEN 1 => -- word
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"2";
END LOOP;
WHEN 2 => -- byte
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"1";
END LOOP;
WHEN OTHERS =>
print("ERROR terminal_pkg: typ IS NOT defined!");
END CASE;
numb_cnt := numb_cnt + 1;
END LOOP;
IF loc_err > 0 THEN
print_s_i(" mtest FAIL errors: ", loc_err);
ELSE
print(" mtest PASS");
END IF;
err := err + loc_err;
END PROCEDURE;
PROCEDURE flash_mtest_indirect( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
adr_if : std_logic_vector; -- = address of indirect interface
txt_out : integer;
tga : std_logic_vector;
err : OUT natural
) IS
VARIABLE loc_err : natural;
VARIABLE loc_err2 : natural;
VARIABLE loc_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE loc_dat : std_logic_vector(31 DOWNTO 0);
VARIABLE numb_cnt : natural;
BEGIN
--loc_adr := adr;
numb_cnt := 0;
loc_err := 0;
loc_dat := adr;
while NOT(numb_cnt = numb) LOOP
CASE typ IS
WHEN 0 => -- long
loc_adr := conv_std_logic_vector((conv_integer(adr)/4),32);
print("Flash Address OF the address register will be autoincremented");
print("Writing 32-bit data into Data Register => 32-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/4),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", loc_dat(31 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "001" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("Reading Data Register from Memory using indirect addressing");
loc_adr := conv_std_logic_vector((conv_integer(adr)/4),32);
loc_dat := adr;
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/4),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", loc_dat(31 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isnt expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN 1 => -- word
loc_adr := conv_std_logic_vector((conv_integer(adr)/2),32);
print("Flash Address OF the address register will be autoincremented");
print("Writing 16-bit data into Data Register => 16-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/2),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", x"0000" & loc_dat(15 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "010" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("READ AND Check 16-bit-Data from Memory using indirect addressing");
loc_adr := conv_std_logic_vector((conv_integer(adr)/2),32);
loc_dat := adr;
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/2),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", x"0000" & loc_dat(15 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isnt expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN 2 => -- byte
loc_adr := adr;
print("Flash Address OF the address register will be autoincremented");
print("Writing 8-bit data into Data Register => 8-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", x"000000" & loc_dat(7 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "000" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("READ AND Check 8-bit-Data from Memory using indirect addressing");
loc_adr := adr;
loc_dat := adr;
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", x"000000" & loc_dat(7 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isnt expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN OTHERS =>
print("ERROR terminal_pkg: typ IS NOT defined!");
END CASE;
numb_cnt := numb_cnt + 1;
END LOOP;
IF loc_err > 0 THEN
print_s_i(" mtest_indirect FAIL errors: ", loc_err);
ELSE
print(" mtest_indirect PASS");
END IF;
err := loc_err;
END PROCEDURE;
--------------------------------------------------------------------------------------------
END; vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/README.rst0000664 0000000 0000000 00000021320 14574545710 0031324 0 ustar 00root root 0000000 0000000 .. SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
..
.. SPDX-License-Identifier: CC-BY-SA-4.0+
A25_VME Testbench
=================
**Important Note:** As of August 2023, this testbench is building, running but
it fails. See commit message a0dd0164 for more details and hints on what might
need fixing. The rest of this document is also likely (partially) obsolete, it
is provided for information only and it should be updated once the testbench is
restored to fully working order.
VHDL source for A25 simulation environment and test cases
Contents of this repository:
``16x001-00_src``: Simulation Model of a dynamic 32-bit wide RAM with wishbone slave
interface for single and burst accesses.
``16x004-00_src``: PCIe x1 master simulation model
``16x010-00_src``: Helper functions for simulation environment
``Testbench``: Main VHDL sources for A25 test bench
Hierarchy of the bench:
a25_tb.vhd
|- terminal main control module of the test bench
|- mt58l512l18f simulation model of external SRAM
|- SN74ABT125 simulation model of external bus driver
|- SN74LVTH245 simulation model of external bus driver
|- vmebus simulation model of VMEbus
|- vme_sim_mon VMEbus timing monitor
|- vme_sim_mstr simulation model of VMEbus master
|- vme_sim_slave simulation model of VMEbus slave
Packages:
terminal_pkg package with all test case implementations
vme_sim_pack package for vmebus internal definitions
``Simulation``: Work folder of simulator Modelsim (PE 6.6)
a25.mpf Modelsim project file
build_all_a25.do main do file to run the simulation
test_report.txt Modelsim log
wbm_x_transcript.txt Access log of Wishbone master #x
wbs_x_transcript.txt Access log of Wishbone slave #x
Folder setup:
your_root_folder
+- 16a025-00_src
+- [...]
+- 16a025-00_tb
+- [...]
+- Altera_src <- shall include BFM files
+- altpcietb_bfm_common.vhd
+- altpcietb_bfm_constants.vhd
+- altpcietb_bfm_log.vhd
+- altpcietb_bfm_shmem.vhd
+- altpcietb_bfm_req_intf.vhd
+- altpcietb_bfm_rdwr.vhd
+- altpcietb_bfm_configure.vhd
+- altpcietb_pipe_xtx2yrx.vhd
+- altpcietb_pipe_phy.vhd
+- altpcietb_ltssm_mon.vhd
+- altpcietb_bfm_rp_top_x8_pipen1b.vhd
+- altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vho
+- altpcietb_bfm_rpvar_64b_x8_gen2_pipen1b.vho
+- altpcietb_bfm_vc_intf.vhd
+- Simulation
+- build_all_a25.do <- to start simulation, only prepared for x1 - add x2/x4 sources
+- [...]
+- Testbench
+- [...]
Preliminaries to simulation
---------------------------
Prior to simulation some files must be generated and/or copied to specific locations within the working directory. Follow the steps
described below:
1. Generate all Hard_IP_xy with y being either 1, 2 or 4 and generate the
simulation model for VHDL.
2. Open the Hard_IP_xy.vhd file and add these generics::
generic(
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
IO_SPACE_BAR_0 : string := "false";
PREFETCH_BAR_0 : string := "true";
SIZE_MASK_BAR_0 : natural := 28;
IO_SPACE_BAR_1 : string := "false";
PREFETCH_BAR_1 : string := "true";
SIZE_MASK_BAR_1 : natural := 18;
IO_SPACE_BAR_2 : string := "false";
PREFETCH_BAR_2 : string := "false";
SIZE_MASK_BAR_2 : natural := 19;
IO_SPACE_BAR_3 : string := "false";
PREFETCH_BAR_3 : string := "false";
SIZE_MASK_BAR_3 : natural := 7;
IO_SPACE_BAR_4 : string := "true";
PREFETCH_BAR_4 : string := "false";
SIZE_MASK_BAR_4 : natural := 5;
IO_SPACE_BAR_5 : string := "true";
PREFETCH_BAR_5 : string := "false";
SIZE_MASK_BAR_5 : natural := 6
);
to the entity. Then add these generics::
generic(
MEN_VENDOR_ID : natural := 16#1A88#;
MEN_DEVICE_ID : natural := 16#4D45#;
MEN_REVISION_ID : natural := 16#0#;
MEN_CLASS_CODE : natural := 16#068000#;
MEN_SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
MEN_SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
MEN_IO_SPACE_BAR_0 : string := "false";
MEN_PREFETCH_BAR_0 : string := "true";
MEN_SIZE_MASK_BAR_0 : natural := 28;
MEN_IO_SPACE_BAR_1 : string := "false";
MEN_PREFETCH_BAR_1 : string := "true";
MEN_SIZE_MASK_BAR_1 : natural := 18;
MEN_IO_SPACE_BAR_2 : string := "false";
MEN_PREFETCH_BAR_2 : string := "false";
MEN_SIZE_MASK_BAR_2 : natural := 19;
MEN_IO_SPACE_BAR_3 : string := "false";
MEN_PREFETCH_BAR_3 : string := "false";
MEN_SIZE_MASK_BAR_3 : natural := 7;
MEN_IO_SPACE_BAR_4 : string := "true";
MEN_PREFETCH_BAR_4 : string := "false";
MEN_SIZE_MASK_BAR_4 : natural := 5;
MEN_IO_SPACE_BAR_5 : string := "true";
MEN_PREFETCH_BAR_5 : string := "false";
MEN_SIZE_MASK_BAR_5 : natural := 6
);
to the Hard_IP_xy_core component. Afterwards connect both generics within the generic map of the component Hard_IP_xy_core.
3. Open the file Hard_IP_xy_core.vhd and add the generics desribed above to the entity. Afterwards connect them to the appropriate
ports of the generic map of the component altpcie_hip_pipen1b.
4. Repeat step 3 for the file Hard_IP_xy_core.vho
5. Open the file Hard_IP_xy_plus.vhd and add the same generics as were added to Hard_IP_xy.vhd to the entity. Then add these
generics to the Hard_IP_xy component and connect them with the generic map.
6. Copy the Hard_IP files to ``your_root_folder/Altera_src/x1`` (see folder description)
7. Copy the BFM files to ``your_root_folder/16a025-00_tb/Altera_src``
8. Open the file
``/your_root_folder/16a025-00_tb/Altera_src/altpcietb_bfm_configure.vhd``
and add these lines after ``line 505``::
for i in 0 to 6 loop
case i is
when 0 =>
temp_bar := bars(i);
temp_bar(31 downto 20) := x"800";
temp_bar(19 downto 18) := "00";
bars(i) := temp_bar;
when 1 =>
temp_bar := bars(i);
temp_bar(31 downto 20) := x"900";
bars(i) := temp_bar;
when 2 =>
temp_bar := bars(i);
temp_bar(31 downto 25) := "1010000";
bars(i) := temp_bar;
when 3 =>
temp_bar := bars(i);
temp_bar(31 downto 29) := "111";
bars(i) := temp_bar;
when 4 =>
temp_bar := bars(i);
temp_bar(31 downto 24) := x"00";
bars(i) := temp_bar;
when 5 =>
temp_bar := bars(i);
-- don't change
when 6 =>
temp_bar := bars(i);
-- don't change
end case;
end loop;
Afterwards add the next line after ``line 392``::
variable temp_bar : std_logic_vector(63 downto 0) := (others => '0');
How to run the simulation
-------------------------
1. Start Modelsim (prepared with PE 6.6) and open project file
2. Use precompiled libraries from Altera: adopt the path to the libraries by
replacing "D:/modelsim_lib/pe66_quartus121/" in file ``build_all_a25.do``
3. due to PCIe simulation model supports just x1, the A25_top need to be
adopted at instance ip_16z091_01_top: USE_LANES => "001
4. Select one or more test cases to be executed in file terminal.vhd, below
"Start of Tests" by using comments for the others
4. run do file: do build_all_a25.do
5. each test case reports an error sum at the end of its execution => if there
are no errors, test has passed
CAUTION: be aware that the BFM does issue some error messages which is assumed as normal behavior. These messages typically look
as follows(with xy being the actual lane number)::
ERROR: TxElecIdle not asserted while reset asserted, Lane: xy, MAC: RP
ERROR: TxElecIdle not asserted in P1 state, Lane: xy, MAC: RP
Info: Duration of test bench run with all test cases is approximately 50 min on
a i7-2620M @ 2.6 GHz running Windows 7 and Modelsim PE 6.6
Simulation/ 0000775 0000000 0000000 00000000000 14574545710 0031704 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench build_all_a25.do 0000664 0000000 0000000 00000042120 14574545710 0034625 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Simulation # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
####################################################################
## Configuration of pathes for libraries and A25_VME repo clone ##
####################################################################
setenv A25_VME_PATH ../..
onerror {break}
## Altera Simulation Libraries:
##
# set path to Quartus used for library compilation
if { ![info exists ::env(QUARTUS_ROOTDIR) ]} {
setenv QUARTUS_ROOTDIR /opt/altera/16.0/quartus
}
printf $env(QUARTUS_ROOTDIR)
####################################################################
# manage paths for libraries and working directory for easy adaption
set vsimversion [regsub -all { } [vsim -version] ""]
set libdir "lib/$vsimversion"
set workdir "lib/$vsimversion/work"
# create working directory if not present yet
if {![file isdirectory $workdir]} {
puts "VSIM_COMPILE: creating working library"
file mkdir $workdir
vlib $workdir
vmap work $workdir
}
# compile libraries
if [file exists "$libdir/libs"] {
} else {file mkdir "$libdir/libs"}
if {![file isdirectory "$libdir/libs/altera"]} {
vlib "$libdir/libs/altera"
vmap altera "$libdir/libs/altera"
vcom -work altera \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/altera_europa_support_lib.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/altera_primitives_components.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/altera_primitives.vhd
}
if {![file isdirectory "$libdir/libs/altera_mf"]} {
vlib "$libdir/libs/altera_mf"
vmap altera_mf "$libdir/libs/altera_mf"
vcom -work altera_mf \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/altera_mf_components.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/altera_mf.vhd
}
if {![file isdirectory "$libdir/libs/lpm"]} {
vlib "$libdir/libs/lpm"
vmap lpm "$libdir/libs/lpm"
vcom -93 -quiet -work lpm \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/220pack.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/220model.vhd
}
if {![file isdirectory "$libdir/libs/sgate"]} {
vlib "$libdir/libs/sgate"
vmap sgate "$libdir/libs/sgate"
vcom -93 -quiet -work sgate \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/sgate_pack.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/sgate.vhd
}
if {![file isdirectory "$libdir/libs/cycloneiv"]} {
vlib "$libdir/libs/cycloneiv"
vmap cycloneiv "$libdir/libs/cycloneiv"
vcom -93 -quiet -work cycloneiv \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/cycloneiv_atoms.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/cycloneiv_components.vhd
}
if {![file isdirectory "$libdir/libs/cycloneiv_hssi"]} {
vlib "$libdir/libs/cycloneiv_hssi"
vmap cycloneiv_hssi "$libdir/libs/cycloneiv_hssi"
vcom -93 -quiet -work cycloneiv_hssi \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/cycloneiv_hssi_components.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/cycloneiv_hssi_atoms.vhd
}
if {![file isdirectory "$libdir/libs/cycloneiv_pcie_hip"]} {
vlib "$libdir/libs/cycloneiv_pcie_hip"
vmap cycloneiv_pcie_hip "$libdir/libs/cycloneiv_pcie_hip"
vcom -93 -quiet -work cycloneiv_pcie_hip \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/cycloneiv_pcie_hip_components.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/cycloneiv_pcie_hip_atoms.vhd
}
if {![file isdirectory "$libdir/libs/arriaii_hssi"]} {
vlib "$libdir/libs/arriaii_hssi"
vmap arriaii_hssi "$libdir/libs/arriaii_hssi"
vcom -93 -quiet -work arriaii_hssi \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/arriaii_hssi_components.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/arriaii_hssi_atoms.vhd
}
if {![file isdirectory "$libdir/libs/stratixiv_hssi"]} {
vlib "$libdir/libs/stratixiv_hssi"
vmap stratixiv_hssi "$libdir/libs/stratixiv_hssi"
vcom -93 -quiet -work stratixiv_hssi \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/stratixiv_hssi_components.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/stratixiv_hssi_atoms.vhd
}
if {![file isdirectory "$libdir/libs/stratixiigx_hssi"]} {
vlib "$libdir/libs/stratixiigx_hssi"
vmap stratixiigx_hssi "$libdir/libs/stratixiigx_hssi"
vcom -93 -quiet -work stratixiigx_hssi \
$env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/chaining_dma/testbench/stratixiigx_hssi_components.vhd \
$env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/chaining_dma/testbench/stratixiigx_hssi_atoms.vhd
}
## Packages and Simulation Models
##
# only recompile unchanged sources if necessary, checking one folder should be enough
# recompiling Altera BFM sources is time consuming
if {![file isdirectory "$libdir/work/fpga_pkg_2"]} {
vcom -work work -2002 $env(A25_VME_PATH)/16z000-00_src/Source/fpga_pkg_2.vhd
vcom -work work -2002 -explicit ../16x010-00_src/Source/conversions.vhd
vcom -work work -2002 -explicit ../16x010-00_src/Source/print_pkg.vhd
vcom -work work -2002 -explicit ../16x001-00_src/Source/iram32_pkg.vhd
vcom -work work -2002 -explicit ../Testbench_src/vme_sim_pack.vhd
vcom -work work -2002 -explicit ../16x001-00_src/Source/iram32_sim.vhd
# PCIe BFM
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_common.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_constants.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_log.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_shmem.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_req_intf.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_rdwr.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_configure.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_pipe_xtx2yrx.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_pipe_phy.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_ltssm_mon.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_rp_top_x8_pipen1b.vhd
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vho
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_rpvar_64b_x8_gen2_pipen1b.vho
vcom -work work -2008 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcietb_bfm_vc_intf.vhd
}
vcom -work work -2008 ../16x004-01_src/Source/utils_pkg.vhd
vcom -work work -2008 ../16x004-01_src/Source/types_pkg.vhd
vcom -work work -2008 ../16x004-01_src/Source/pcie_sim_pkg.vhd
vcom -work work -2008 -explicit ../Testbench_src/terminal_pkg.vhd
vcom -work work -2008 ../16x004-01_src/Source/pcie_sim.vhd
## DUT Source
##
# remote update
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_pkg.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_ru_ctrl.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_ru_ctrl_cyc5.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_ru/z126_01_ru_cycloneiv.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_wbmon.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_wb2pasmi.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_wb_pkg.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_wb_if_arbiter.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_top.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_indi_if_ctrl_regs.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_fifo_d1.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_clk_trans_wb2wb.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_switch_fab_2.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z126-01_src/Source/z126_01_pasmi/z126_01_pasmi_m25p32.vhd
# compile special files for simulation
#vcom -work work -2002 ../Testbench_src/m25p32/mem_util_pkg.vhd
#vcom -work work -2002 ../Testbench_src/m25p32/internal_logic.vhd
#vcom -work work -2002 ../Testbench_src/m25p32/memory_access.vhd
#vcom -work work -2002 ../Testbench_src/m25p32/ACDC_check.vhd
#vcom -work work -2002 ../Testbench_src/m25p32/M25P32.vhd
vcom -work work -2002 ../Testbench_src/z126_01_altremote_update_sim_model.vhd
# iram
vcom -work work -2002 $env(A25_VME_PATH)/16z024-01_src/Source/iram_wb.vhd
vcom -work work -2002 $env(A25_VME_PATH)/16z024-01_src/Source/iram_av.vhd
## vme
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_pkg.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_dma_arbiter.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_dma_au.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_dma_du.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_dma_fifo.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_dma_mstr.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_dma_slv.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/dma_mblt_boost.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_dma.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_arbiter.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_sys_arbiter.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_au.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_bustimer.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_ctrl.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_du.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_locmon.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_mailbox.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_master.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_requester.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_slave.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_wbm.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/vme_wbs.vhd
vcom -work work -2002 $env(A25_VME_PATH)/../dependencies/wb-vme-bridge/hdl/16z002-01_src/Source/wbb2vme_top.vhd
# pcie core simulation files
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcie_rs_serdes.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcierd_reconfig_clk_pll.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcie_pll_125_250.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcie_pll_100_125.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcie_pll_100_250.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcie_reconfig_4sgx.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/common/testbench/altpcie_reconfig_3cgx.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/chaining_dma/Hard_IP_x1_plus.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_examples/chaining_dma/Hard_IP_x1_rs_hip.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_core.vho
## pcie2wbb
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/src_utils_pkg.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/generic_dcfifo_mixedw.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/pcie_msi.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/alt_reconf/alt_reconf.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/rx_len_cntr.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/rx_get_data.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/rx_ctrl.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/rx_module.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/z091_01_wb_master.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/error.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/tx_put_data.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/tx_compl_timeout.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/tx_ctrl.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/tx_module.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/init.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/z091_01_wb_slave.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/interrupt_core.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/interrupt_wb.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/ip_16z091_01.vhd
vcom -2002 $env(A25_VME_PATH)/top/z091_01_wb_adr_dec.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1_serdes.vhd
vcom -2002 $env(A25_VME_PATH)/16z091-01_src/Source/x1/Hard_IP_x1.vhd
vcom -2008 ../Testbench_src/ip_16z091_01_top_sim.vhd
# 16z100
vcom -work work -93 $env(A25_VME_PATH)/top/wb_pkg.vhd
vcom -work work -93 $env(A25_VME_PATH)/16z100-00_src/Source/switch_fab_1.vhd
vcom -work work -93 $env(A25_VME_PATH)/16z100-00_src/Source/switch_fab_2.vhd
vcom -work work -93 $env(A25_VME_PATH)/16z100-00_src/Source/switch_fab_3.vhd
vcom -work work -93 $env(A25_VME_PATH)/16z100-00_src/Source/switch_fab_4.vhd
vcom -work work -93 $env(A25_VME_PATH)/16z100-00_src/Source/wbmon.vhd
vcom -work work -93 $env(A25_VME_PATH)/16z100-00_src/Source/fifo_d1.vhd
vcom -work work -93 $env(A25_VME_PATH)/16z100-00_src/Source/clk_trans_wb2wb.vhd
vcom -work work -93 $env(A25_VME_PATH)/top/wb_bus.vhd
## Toplevel
vcom -2008 $env(A25_VME_PATH)/top/pll_pcie/pll_pcie.vhd
vcom -2008 $env(A25_VME_PATH)/top/sram.vhd
vcom -2008 ../Testbench_src/A25_top_sim.vhd
## Testbench
vcom -2002 ../Testbench_src/SN74LVTH245.vhd
vcom -2002 ../Testbench_src/SN74ABT125.vhd
vcom -2002 ../Testbench_src/mt58l512l18f.vhd
vcom -2002 ../Testbench_src/terminal.vhd
vcom -2002 ../Testbench_src/vme_sim_mon.vhd
vcom -2002 ../Testbench_src/vme_sim_mstr.vhd
vcom -2002 ../Testbench_src/vme_sim_slave.vhd
vcom -2002 ../Testbench_src/vmebus.vhd
vcom -2008 ../Testbench_src/a25_tb.vhd
vsim -t fs \
-L altera \
-L altera_mf \
-L lpm \
-L sgate \
-L arriaii_hssi \
-L stratixiv_hssi \
-L cycloneiv_hssi \
-L stratixiigx_hssi \
-L pciebfm_lib \
-l test_report.txt \
-novopt \
work.a25_tb_conf
#add wave sim:/a25_tb/a25/*
#add wave sim:/a25_tb/a25/vme/vmedma/*
#add wave sim:/a25_tb/a25/vme/vmedma/dma_mstr/*
#add wave sim:/a25_tb/a25/vme/vmectrl/du/* add wave sim:/a25_tb/a25/vme/vmectrl/au/*
#add wave sim:/a25_tb/a25/vme/vmectrl/bustimer/*
#add wave sim:/a25_tb/a25/vme/vmectrl/master/*
#add wave sim:/a25_tb/a25/vme/vmectrl/requester/*
#add wave sim:/a25_tb/a25/vme/vmectrl/arbiter/*
#add wave sim:/a25_tb/vme_bus/*
#add wave sim:/a25_tb/vme_bus/vmesimmstr/*
do wave.do
#log -r /*
#add wave -divider {PCIe EP}
#add wave -group {all EP ports}\
#/a25_tb/a25/pcie/*
#add wave -divider {BFM}
#add wave \
# -literal -hex /a25_tb/pcie_sim_inst/bar_addr \
# /a25_tb/pcie_sim_inst/bar_limit \
# -literal -hex /a25_tb/pcie_sim_inst/main/var_bar0_addr \
# -dec /a25_tb/pcie_sim_inst/main/var_bar0_limit \
# -literal -hex /a25_tb/pcie_sim_inst/main/var_bar1_addr \
# -dec /a25_tb/pcie_sim_inst/main/var_bar1_limit \
# -literal -hex /a25_tb/pcie_sim_inst/main/var_bar2_addr \
# -dec /a25_tb/pcie_sim_inst/main/var_bar2_limit \
# -literal -hex /a25_tb/pcie_sim_inst/main/var_bar3_addr \
# -dec /a25_tb/pcie_sim_inst/main/var_bar3_limit \
# -literal -hex /a25_tb/pcie_sim_inst/main/var_bar4_addr \
# -dec /a25_tb/pcie_sim_inst/main/var_bar4_limit \
# -literal -hex /a25_tb/pcie_sim_inst/main/var_bar5_addr \
# -dec /a25_tb/pcie_sim_inst/main/var_bar5_limit
#
#add wave -group {all BFM ports} \
#/a25_tb/pcie_sim_inst/bfm_inst/crst \
#/a25_tb/pcie_sim_inst/bfm_inst/srst \
#/a25_tb/pcie_sim_inst/*
#add wave -divider {DEBUG}
# next 5 lines are for debugging only, remove later
variable NumericStdNoWarnings 1
variable StdArithNoWarnings 1
#run 50 ns
#variable NumericStdNoWarnings 0
#variable StdArithNoWarnings 0
run -all
quit
wave.do 0000664 0000000 0000000 00000021121 14574545710 0033167 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Simulation # SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /a25_tb/a25/clk_16mhz
add wave -noupdate /a25_tb/a25/led_green_n
add wave -noupdate /a25_tb/a25/led_red_n
add wave -noupdate /a25_tb/a25/hreset_n
add wave -noupdate /a25_tb/a25/v2p_rstn
add wave -noupdate /a25_tb/a25/fpga_test
add wave -noupdate /a25_tb/a25/refclk
add wave -noupdate /a25_tb/pcie_rx
add wave -noupdate /a25_tb/pcie_tx
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_rxvalid_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_rxstatus_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_rxdatak_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_rxdata_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_rxelecidle_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_phystatus_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_clk250_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_clk500_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_rate_ext_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_powerdown_ext_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_txdatak_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_txdata_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_txcompl_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_txelecidle_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_txdetectrx_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_rxpolarity_int
add wave -noupdate -group {PCIe Serdes} /a25_tb/ep_ltssm_int
add wave -noupdate -expand -group SRAM /a25_tb/a25/sr_clk
add wave -noupdate -expand -group SRAM -radix hexadecimal /a25_tb/a25/sr_a
add wave -noupdate -expand -group SRAM -radix hexadecimal /a25_tb/a25/sr_d
add wave -noupdate -expand -group SRAM /a25_tb/a25/sr_bwa_n
add wave -noupdate -expand -group SRAM /a25_tb/a25/sr_bwb_n
add wave -noupdate -expand -group SRAM /a25_tb/a25/sr_bw_n
add wave -noupdate -expand -group SRAM /a25_tb/a25/sr_cs1_n
add wave -noupdate -expand -group SRAM /a25_tb/a25/sr_adsc_n
add wave -noupdate -expand -group SRAM /a25_tb/a25/sr_oe_n
add wave -noupdate -group VME /a25_tb/a25/vme_ga
add wave -noupdate -group VME /a25_tb/a25/vme_gap
add wave -noupdate -group VME -radix hexadecimal /a25_tb/a25/vme_a
add wave -noupdate -group VME /a25_tb/a25/vme_a_dir
add wave -noupdate -group VME /a25_tb/a25/vme_a_oe_n
add wave -noupdate -group VME -radix hexadecimal /a25_tb/a25/vme_d
add wave -noupdate -group VME /a25_tb/a25/vme_d_dir
add wave -noupdate -group VME /a25_tb/a25/vme_d_oe_n
add wave -noupdate -group VME /a25_tb/a25/vme_am_dir
add wave -noupdate -group VME -radix hexadecimal /a25_tb/a25/vme_am
add wave -noupdate -group VME /a25_tb/a25/vme_am_oe_n
add wave -noupdate -group VME /a25_tb/a25/vme_write_n
add wave -noupdate -group VME /a25_tb/a25/vme_iack_n
add wave -noupdate -group VME /a25_tb/a25/vme_irq_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_irq_o
add wave -noupdate -group VME /a25_tb/a25/vme_as_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_as_o_n
add wave -noupdate -group VME /a25_tb/a25/vme_as_oe
add wave -noupdate -group VME /a25_tb/a25/vme_retry_o_n
add wave -noupdate -group VME /a25_tb/a25/vme_retry_oe
add wave -noupdate -group VME /a25_tb/a25/vme_retry_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_sysres_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_sysres_o
add wave -noupdate -group VME /a25_tb/a25/vme_ds_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_ds_o_n
add wave -noupdate -group VME /a25_tb/a25/vme_ds_oe
add wave -noupdate -group VME /a25_tb/a25/vme_berr_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_berr_o
add wave -noupdate -group VME /a25_tb/a25/vme_dtack_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_dtack_o
add wave -noupdate -group VME /a25_tb/a25/vme_scon
add wave -noupdate -group VME /a25_tb/a25/vme_sysfail_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_sysfail_o
add wave -noupdate -group VME /a25_tb/a25/vme_bbsy_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_bbsy_o
add wave -noupdate -group VME /a25_tb/a25/vme_bclr_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_bclr_o_n
add wave -noupdate -group VME /a25_tb/a25/vme_br_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_br_o
add wave -noupdate -group VME /a25_tb/a25/vme_iack_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_iack_o_n
add wave -noupdate -group VME /a25_tb/a25/vme_acfail_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_sysclk
add wave -noupdate -group VME /a25_tb/a25/vme_bg_i_n
add wave -noupdate -group VME /a25_tb/a25/vme_bg_o_n
add wave -noupdate /a25_tb/a25/vme/dma_irq
add wave -noupdate -expand -group VME_DMA_WBS /a25_tb/a25/vme/vmedma/stb_i
add wave -noupdate -expand -group VME_DMA_WBS /a25_tb/a25/vme/vmedma/ack_o
add wave -noupdate -expand -group VME_DMA_WBS /a25_tb/a25/vme/vmedma/we_i
add wave -noupdate -expand -group VME_DMA_WBS /a25_tb/a25/vme/vmedma/cyc_i
add wave -noupdate -expand -group VME_DMA_WBS /a25_tb/a25/vme/vmedma/sel_i
add wave -noupdate -expand -group VME_DMA_WBS /a25_tb/a25/vme/vmedma/adr_i
add wave -noupdate -expand -group VME_DMA_WBS /a25_tb/a25/vme/vmedma/slv_dat_i
add wave -noupdate -expand -group VME_DMA_WBS /a25_tb/a25/vme/vmedma/slv_dat_o
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/dma_mstr/mstr_state
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/cti
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/tga_o
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/err_i
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/cyc_o_sram
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/cyc_o_vme
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/cyc_o_pci
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/stb_o
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/we_o
add wave -noupdate -expand -group VME_DMA_WBM -radix hexadecimal /a25_tb/a25/vme/vmedma/sel_o
add wave -noupdate -expand -group VME_DMA_WBM -radix hexadecimal /a25_tb/a25/vme/vmedma/adr_o
add wave -noupdate -expand -group VME_DMA_WBM -radix hexadecimal /a25_tb/a25/vme/vmedma/mstr_dat_o
add wave -noupdate -expand -group VME_DMA_WBM -radix hexadecimal /a25_tb/a25/vme/vmedma/mstr_dat_i
add wave -noupdate -expand -group VME_DMA_WBM /a25_tb/a25/vme/vmedma/ack_i
add wave -noupdate -expand -group PCIE_WBM /a25_tb/a25/pcie/wbm_ack
add wave -noupdate -expand -group PCIE_WBM -radix hexadecimal /a25_tb/a25/pcie/wbm_dat_i
add wave -noupdate -expand -group PCIE_WBM /a25_tb/a25/pcie/wbm_stb
add wave -noupdate -expand -group PCIE_WBM -radix hexadecimal /a25_tb/a25/pcie/wbm_cyc_o
add wave -noupdate -expand -group PCIE_WBM /a25_tb/a25/pcie/wbm_we
add wave -noupdate -expand -group PCIE_WBM -radix hexadecimal /a25_tb/a25/pcie/wbm_sel
add wave -noupdate -expand -group PCIE_WBM -radix hexadecimal /a25_tb/a25/pcie/wbm_adr
add wave -noupdate -expand -group PCIE_WBM -radix hexadecimal /a25_tb/a25/pcie/wbm_dat_o
add wave -noupdate -expand -group PCIE_WBM /a25_tb/a25/pcie/wbm_cti
add wave -noupdate -expand -group PCIE_WBS /a25_tb/a25/pcie/wbs_cyc
add wave -noupdate -expand -group PCIE_WBS /a25_tb/a25/pcie/wbs_stb
add wave -noupdate -expand -group PCIE_WBS /a25_tb/a25/pcie/wbs_we
add wave -noupdate -expand -group PCIE_WBS -radix hexadecimal /a25_tb/a25/pcie/wbs_sel
add wave -noupdate -expand -group PCIE_WBS -radix hexadecimal /a25_tb/a25/pcie/wbs_adr
add wave -noupdate -expand -group PCIE_WBS -radix hexadecimal /a25_tb/a25/pcie/wbs_dat_i
add wave -noupdate -expand -group PCIE_WBS -radix hexadecimal /a25_tb/a25/pcie/wbs_cti
add wave -noupdate -expand -group PCIE_WBS /a25_tb/a25/pcie/wbs_tga
add wave -noupdate -expand -group PCIE_WBS /a25_tb/a25/pcie/wbs_ack
add wave -noupdate -expand -group PCIE_WBS /a25_tb/a25/pcie/wbs_err
add wave -noupdate -expand -group PCIE_WBS -radix hexadecimal /a25_tb/a25/pcie/wbs_dat_o
add wave -noupdate /a25_tb/term/terminal_in_0
add wave -noupdate /a25_tb/term/terminal_out_0
add wave -noupdate /a25_tb/term/terminal_in_1
add wave -noupdate /a25_tb/term/terminal_out_1
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {233181250000 fs} 1} {{Cursor 2} {244866250000 fs} 1} {{Cursor 3} {197526486262 fs} 1}
configure wave -namecolwidth 151
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {196477343484 fs} {200673914580 fs}
Testbench_src/ 0000775 0000000 0000000 00000000000 14574545710 0032346 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench A25_top_sim.vhd 0000664 0000000 0000000 00000155562 14574545710 0035150 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Toplevel File of A25 FPGA
-- Project : 1614_CERN_A25
--------------------------------------------------------------------------------
-- File : A25_top.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 2016-06-03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- A25_top
-- wbb2vme_top
-- sram
-- ip_16z091_01_top
-- iram_wb
-- pll_pcie
-- z126_01_top
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.wb_pkg.ALL;
USE work.fpga_pkg_2.ALL;
USE work.z126_01_pkg.ALL;
USE work.vme_pkg.ALL;
ENTITY A25_top IS
GENERIC (
SIMULATION : boolean := FALSE;
FPGA_FAMILY : family_type := CYCLONE4;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk_16mhz : IN std_logic;
led_green_n : OUT std_logic;
led_red_n : OUT std_logic;
hreset_n : IN std_logic; -- reset
v2p_rstn : OUT std_logic; -- connected to hreset_req1_n
fpga_test : INOUT std_logic_vector(5 DOWNTO 1);
-- pcie
refclk : IN std_logic; -- 100 MHz pcie clock
pcie_rx : IN std_logic_vector(3 DOWNTO 0); -- PCIe receive line
pcie_tx : OUT std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
-- sram
sr_clk : OUT std_logic;
sr_a : OUT std_logic_vector(18 DOWNTO 0);
sr_d : INOUT std_logic_vector(15 DOWNTO 0);
sr_bwa_n : OUT std_logic;
sr_bwb_n : OUT std_logic;
sr_bw_n : OUT std_logic;
sr_cs1_n : OUT std_logic;
sr_adsc_n : OUT std_logic;
sr_oe_n : OUT std_logic;
-- vmebus
vme_ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : IN std_logic; -- geographical addresses
vme_a : INOUT std_logic_vector(31 DOWNTO 0);
vme_a_dir : OUT std_logic;
vme_a_oe_n : OUT std_logic;
vme_d : INOUT std_logic_vector(31 DOWNTO 0);
vme_d_dir : OUT std_logic;
vme_d_oe_n : OUT std_logic;
vme_am_dir : OUT std_logic;
vme_am : INOUT std_logic_vector(5 DOWNTO 0);
vme_am_oe_n : OUT std_logic;
vme_write_n : INOUT std_logic;
vme_iack_n : INOUT std_logic;
vme_irq_i_n : IN std_logic_vector(7 DOWNTO 1);
vme_irq_o : OUT std_logic_vector(7 DOWNTO 1); -- high active on A25
vme_as_i_n : IN std_logic;
vme_as_o_n : OUT std_logic;
vme_as_oe : OUT std_logic; -- high active on A25
vme_retry_o_n : OUT std_logic;
vme_retry_oe : OUT std_logic; -- high active on A25
vme_retry_i_n : IN std_logic;
vme_sysres_i_n : IN std_logic;
vme_sysres_o : OUT std_logic; -- high active on A25
vme_ds_i_n : IN std_logic_vector(1 DOWNTO 0);
vme_ds_o_n : OUT std_logic_vector(1 DOWNTO 0);
vme_ds_oe : OUT std_logic; -- high active on A25
vme_berr_i_n : IN std_logic;
vme_berr_o : OUT std_logic; -- high active on A25
vme_dtack_i_n : IN std_logic;
vme_dtack_o : OUT std_logic; -- high active on A25
vme_scon : OUT std_logic; -- high active on A25
vme_sysfail_i_n : IN std_logic;
vme_sysfail_o : OUT std_logic; -- high active on A25
vme_bbsy_i_n : IN std_logic;
vme_bbsy_o : OUT std_logic; -- high active on A25
vme_bclr_i_n : IN std_logic; -- bus clear input
vme_bclr_o_n : OUT std_logic; -- bus clear output
vme_br_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_br_o : OUT std_logic_vector(3 DOWNTO 0); -- high active on A25
vme_iack_i_n : IN std_logic;
vme_iack_o_n : OUT std_logic;
vme_acfail_i_n : IN std_logic;
vme_sysclk : OUT std_logic;
vme_bg_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_bg_o_n : OUT std_logic_vector(3 DOWNTO 0);
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0)
);
END A25_top;
ARCHITECTURE A25_top_arch OF A25_top IS
CONSTANT NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 10;
COMPONENT ip_16z091_01_top
GENERIC(
SIMULATION : std_logic := '0'; -- =1 simulation,=0 synthesis
FPGA_FAMILY : family_type := NONE;
IRQ_WIDTH : integer range 32 downto 1 := 1;
-- only use one of the following 3:
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
NR_OF_BARS_USED : natural range 6 downto 1 := 5;
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
BAR_MASK_0 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_1 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_2 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_3 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_4 : std_logic_vector(31 downto 0) := x"FF000001";
BAR_MASK_5 : std_logic_vector(31 downto 0) := x"FF000001";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000010000"; -- 16DW = 64Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
GP_DEBUG_PORT_WIDTH : positive := 1
);
PORT(
-- Hard IP ports:
clk_50 : in std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
clk_125 : in std_logic; -- 125 MHz clock for fixed_clk
ref_clk : in std_logic; -- 100 MHz reference clock
clk_500 : in std_logic; -- 500 Hz clock
ext_rst_n : in std_logic;
rx_0 : in std_logic;
rx_1 : in std_logic;
rx_2 : in std_logic;
rx_3 : in std_logic;
tx_0 : out std_logic;
tx_1 : out std_logic;
tx_2 : out std_logic;
tx_3 : out std_logic;
-- Wishbone ports:
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
irq_req_i : in std_logic_vector(IRQ_WIDTH -1 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0);
-- debug port
gp_debug_port : out std_logic_vector(GP_DEBUG_PORT_WIDTH -1 downto 0); -- general purpose debug port
link_train_active : out std_logic
);
END COMPONENT;
COMPONENT wb_bus
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- Master Bus
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic_vector(3 DOWNTO 0);
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic_vector(1 DOWNTO 0);
wbmo_2 : IN wbo_type;
wbmi_2 : OUT wbi_type;
wbmo_2_cyc : IN std_logic_vector(2 DOWNTO 0);
wbmo_3 : IN wbo_type;
wbmi_3 : OUT wbi_type;
wbmo_3_cyc : IN std_logic;
-- Slave Bus
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
wbso_1 : IN wbi_type;
wbsi_1 : OUT wbo_type;
wbsi_1_cyc : OUT std_logic;
wbso_2 : IN wbi_type;
wbsi_2 : OUT wbo_type;
wbsi_2_cyc : OUT std_logic;
wbso_3 : IN wbi_type;
wbsi_3 : OUT wbo_type;
wbsi_3_cyc : OUT std_logic;
wbso_4 : IN wbi_type;
wbsi_4 : OUT wbo_type;
wbsi_4_cyc : OUT std_logic
);
END COMPONENT;
COMPONENT pll_pcie
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT iram_wb
GENERIC
(
FPGA_FAMILY: family_type := CYCLONE; -- ACEX,CYCLONE,CYCLONE2,CYCLONE3,ARRIA_GX
read_only: natural := 0; -- 0=R/W, 1=R/O
USEDW_WIDTH: positive := 6; -- 2**(USEDW_WIDTH + 2) bytes
LOCATION: string := "iram.hex" -- string shall be empty if no HEX file
);
PORT
(
clk : IN std_logic; -- Wishbone clock
rst : IN std_logic; -- global async high active reset
-- Wishbone signals
stb_i : IN std_logic; -- request
cyc_i : IN std_logic; -- chip select
ack_o : OUT std_logic; -- acknowledge
err_o : OUT std_logic; -- error
we_i : IN std_logic; -- write=1 read=0
sel_i : IN std_logic_vector(3 DOWNTO 0); -- byte enables
adr_i : IN std_logic_vector((USEDW_WIDTH + 1) DOWNTO 2);
dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END COMPONENT;
COMPONENT sram
PORT (
clk66 : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
-- local bus
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic; -- high active write enable
sel_i : IN std_logic_vector(3 DOWNTO 0); -- high active byte enables
cyc_i : IN std_logic;
dat_o : OUT std_logic_vector(31 DOWNTO 0);
dat_i : IN std_logic_vector(31 DOWNTO 0);
adr_i : IN std_logic_vector(19 DOWNTO 0);
-- pins to sram
bwn : OUT std_logic; -- global byte write enable:
bwan : OUT std_logic; -- byte a write enable:
bwbn : OUT std_logic; -- byte b write enable:
adscn : OUT std_logic; -- Synchronous Address Status Controller: .
roen : OUT std_logic; -- data port output enable: .
ra : OUT std_logic_vector(18 DOWNTO 0); -- address lines:
rd_in : IN std_logic_vector(15 DOWNTO 0); -- data lines:
rd_out : OUT std_logic_vector(15 DOWNTO 0); -- data lines:
rd_oe : OUT std_logic
);
END COMPONENT;
COMPONENT z126_01_top
GENERIC (
SIMULATION : boolean := FALSE; -- true => use the altasmi parallel of an older quartus version (11.1 SP2) the new one can not be simulated
-- (only the M25P32 is supported for simulation!!)
-- false => use the newest altasmi parallel (13.0)
FPGA_FAMILY : family_type := CYCLONE5; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
FLASH_TYPE : flash_type := M25P32; -- see SUPPORTED_DEVICES for supported serial flash device types
USE_DIRECT_INTERFACE : boolean := TRUE; -- true => the direct interfaces is included and arbitrated with the indirect interface
-- false => only the indirect interface is available (reducing resource consumption)
USE_REMOTE_UPDATE : boolean := TRUE; -- true => the remote update controller is included and more than one FPGA image can be selected
-- false => only the FPGA Fallback Image can be used for FPGA configuration (reducing resource consumption)
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT (
clk_40mhz : IN std_logic; -- serial flash clock (maximum 40 MHz)
rst_clk_40mhz : IN std_logic; -- this reset should be a power up reset to
-- reduce the reconfiguration (load FPGA Image) time when LOAD_FPGA_IMAGE = TRUE.
-- this reset must be deasserted synchronous to the clk_40mhz
clk_dir : IN std_logic; -- wishbone clock for direct interface
rst_dir : IN std_logic; -- wishbone async high active reset
-- this reset must be deasserted synchronous to the clk_dir
clk_indi : IN std_logic; -- wishbone clock for indirect interface
rst_indi : IN std_logic; -- wishbone async high active reset
-- this reset must be deasserted synchronous to the clk_indi
board_status : OUT std_logic_vector(1 DOWNTO 0);
-- wishbone signals slave interface 0 (direct addressing)
wbs_stb_dir : IN std_logic; -- request
wbs_ack_dir : OUT std_logic; -- acknoledge
wbs_we_dir : IN std_logic; -- write=1 read=0
wbs_sel_dir : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc_dir : IN std_logic; -- chip select
wbs_dat_o_dir : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i_dir : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr_dir : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_err_dir : OUT std_logic; -- error
-- wishbone signals slave interface 1 (indirect addressing)
wbs_stb_indi : IN std_logic; -- request
wbs_ack_indi : OUT std_logic; -- acknoledge
wbs_we_indi : IN std_logic; -- write=1 read=0
wbs_sel_indi : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc_indi : IN std_logic; -- chip select
wbs_dat_o_indi : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i_indi : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr_indi : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_err_indi : OUT std_logic -- error
);
END COMPONENT;
COMPONENT wbb2vme_top
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
dma_irq : OUT std_logic; -- interrupt request dma to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- vmectrl slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- vmectrl master
wbm_ctrl_stb_o : OUT std_logic;
wbm_ctrl_ack_i : IN std_logic;
wbm_ctrl_err_i : IN std_logic;
wbm_ctrl_we_o : OUT std_logic;
wbm_ctrl_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_ctrl_cyc_sram : OUT std_logic;
wbm_ctrl_cyc_pci : OUT std_logic;
wbm_ctrl_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbm_dma_stb_o : OUT std_logic;
wbm_dma_ack_i : IN std_logic;
wbm_dma_we_o : OUT std_logic;
wbm_dma_cti : OUT std_logic_vector(2 DOWNTO 0);
wbm_dma_tga_o : OUT std_logic_vector(8 DOWNTO 0);
wbm_dma_err_i : IN std_logic;
wbm_dma_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_dma_cyc_sram : OUT std_logic;
wbm_dma_cyc_vme : OUT std_logic;
wbm_dma_cyc_pci : OUT std_logic;
wbm_dma_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- dedicated PCI wb-master for DMA boost
pci_cyc_o : OUT std_logic;
pci_stb_o : OUT std_logic;
pci_we_o : OUT std_logic;
pci_sel_o : OUT std_logic_vector(3 DOWNTO 0);
pci_tga_o : OUT std_logic_vector(8 DOWNTO 0);
pci_cti_o : OUT std_logic_vector(2 DOWNTO 0);
pci_adr_o : OUT std_logic_vector(31 DOWNTO 0);
pci_dat_o : OUT std_logic_vector(31 DOWNTO 0);
pci_dat_i : IN std_logic_vector(31 DOWNTO 0);
pci_ack_i : IN std_logic;
pci_err_i : IN std_logic;
-- vmebus
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
bclr_i_n : IN std_logic; -- bus clear input
bclr_o_n : OUT std_logic; -- bus clear output
retry_i_n : IN std_logic; -- bus retry input
retry_o_n : OUT std_logic; -- bus retry output
retry_oe_n : OUT std_logic; -- bus retry output enable
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rst : OUT std_logic -- Reset from VMEbus to System on board
);
END COMPONENT;
CONSTANT CONST_500HZ : integer := 66667; -- half 500Hz clock period counter value at 66MHz
SIGNAL sys_clk : std_logic; -- system clock 66 MHz
SIGNAL sys_rst : std_logic; -- system async reset
SIGNAL rst_33 : std_logic; -- reset synchronized to clk_33
SIGNAL clk_33 : std_logic; -- 33 MHz clock for 16z066
SIGNAL clk_50 : std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
SIGNAL clk_125 : std_logic; -- 125 MHz clock for fixed_clk
SIGNAL clk_500 : std_logic; -- 500 Hz clock
SIGNAL cnt_500hz : integer;
-- MASTER SIGNALS
SIGNAL wbmo_0 : wbo_type;
SIGNAL wbmi_0 : wbi_type;
SIGNAL wbmo_0_cyc : std_logic_vector(3 DOWNTO 0);
SIGNAL wbmo_0_cyc_int : std_logic_vector(9 DOWNTO 0);
SIGNAL wbmo_1 : wbo_type;
SIGNAL wbmi_1 : wbi_type;
SIGNAL wbmo_1_cyc : std_logic_vector(1 DOWNTO 0);
SIGNAL wbmo_2 : wbo_type;
SIGNAL wbmi_2 : wbi_type;
SIGNAL wbmo_2_cyc : std_logic_vector(2 DOWNTO 0);
SIGNAL wbmo_3 : wbo_type;
SIGNAL wbmi_3 : wbi_type;
SIGNAL wbmo_3_cyc : std_logic;
-- SLAVE SIGNALS
SIGNAL wbso_0 : wbi_type;
SIGNAL wbsi_0 : wbo_type;
SIGNAL wbsi_0_cyc : std_logic;
SIGNAL wbso_1 : wbi_type;
SIGNAL wbsi_1 : wbo_type;
SIGNAL wbsi_1_cyc : std_logic;
SIGNAL wbso_2 : wbi_type;
SIGNAL wbsi_2 : wbo_type;
SIGNAL wbsi_2_cyc : std_logic;
SIGNAL wbso_3 : wbi_type;
SIGNAL wbsi_3 : wbo_type;
SIGNAL wbsi_3_cyc : std_logic;
SIGNAL wbso_4 : wbi_type;
SIGNAL wbsi_4 : wbo_type;
SIGNAL wbsi_4_cyc : std_logic;
SIGNAL pll_locked : std_logic;
SIGNAL sr_d_oe : std_logic;
SIGNAL board_status : std_logic_vector(1 DOWNTO 0);
SIGNAL sr_d_out : std_logic_vector(15 DOWNTO 0);
SIGNAL sr_d_in : std_logic_vector(15 DOWNTO 0);
SIGNAL vme_irq : std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
SIGNAL berr_irq : std_logic; -- signal berrn interrupt request
SIGNAL locmon_irq : std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
SIGNAL mailbox_irq : std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
SIGNAL mailbox_irq_i : std_logic;
SIGNAL dma_irq : std_logic;
SIGNAL slot01n : std_logic;
SIGNAL test_vec : test_vec_type;
SIGNAL pll_locked_inv : std_logic;
SIGNAL startup_rst : std_logic:='1';
SIGNAL porst : std_logic;
SIGNAL porst_n_q : std_logic:='0';
SIGNAL porst_n : std_logic:='0';
SIGNAL link_train_active : std_logic;
SIGNAL vme_berr : std_logic;
SIGNAL vme_mstr_busy : std_logic;
SIGNAL led_cnt : std_logic_vector(17 DOWNTO 0); -- 2^18 = 3.9 ms
SIGNAL v2p_rst : std_logic;
-- high active signals on A25
SIGNAL vme_irq_o_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_as_oe_n : std_logic;
SIGNAL vme_retry_oe_n : std_logic;
SIGNAL vme_sysres_o_n : std_logic;
SIGNAL vme_ds_oe_n : std_logic;
SIGNAL vme_scon_n : std_logic;
SIGNAL vme_sysfail_o_n : std_logic;
SIGNAL vme_bbsy_o_n : std_logic;
SIGNAL vme_dtack_o_n : std_logic;
SIGNAL vme_berr_o_n : std_logic;
SIGNAL vme_br_o_n : std_logic_vector(3 DOWNTO 0);
BEGIN
vme_irq_o <= NOT vme_irq_o_n ;
vme_as_oe <= NOT vme_as_oe_n ;
vme_retry_oe <= NOT vme_retry_oe_n ;
vme_sysres_o <= NOT vme_sysres_o_n ;
vme_ds_oe <= NOT vme_ds_oe_n ;
vme_scon <= NOT vme_scon_n ;
vme_sysfail_o <= NOT vme_sysfail_o_n;
vme_bbsy_o <= NOT vme_bbsy_o_n ;
vme_br_o <= NOT vme_br_o_n ;
vme_berr_o <= NOT vme_berr_o_n;
vme_dtack_o <= NOT vme_dtack_o_n;
led_red_n <= NOT vme_berr;
-- led_green_n <= slot01;
vme_sysclk <= clk_16mhz;
vme_scon_n <= slot01n;
-- counter for extending vme master active pulses to at least 3 ms
PROCESS(sys_clk, sys_rst)
BEGIN
IF sys_rst = '1' THEN
led_cnt <= (OTHERS => '0');
led_green_n <= '1';
ELSIF sys_clk'event AND sys_clk = '1' THEN
IF vme_mstr_busy = '1' THEN -- if master is active, start counter to extend pulse for 3 ms
led_cnt <= (OTHERS => '1');
led_green_n <= '0'; -- switch on LED
ELSIF led_cnt = 0 THEN -- is 3 ms over?
led_cnt <= (OTHERS => '0');
led_green_n <= '1'; -- switch off LED
ELSE
led_cnt <= led_cnt - '1'; -- count for 3 ms
led_green_n <= '0';
END IF;
END IF;
END PROCESS;
pll_locked_inv <= NOT pll_locked;
startup_rst <= pll_locked_inv;
wbso_3.err <= '0';
wbso_4.err <= '0';
wbmo_0.bte <= "00";
wbmo_1.bte <= "00";
wbmo_2.bte <= "00";
wbmo_1.cti <= "000";
fpga_test(1) <= 'Z';
fpga_test(2) <= 'Z';
fpga_test(3) <= 'Z';
fpga_test(4) <= 'Z';
fpga_test(5) <= 'Z';
-- generate power on reset in order to start application fpga load as early as possible
PROCESS (clk_16mhz)
BEGIN
IF clk_16mhz'EVENT AND clk_16mhz = '1' THEN
porst_n_q <= '1';
porst_n <= porst_n_q;
END IF;
END PROCESS;
porst <= NOT porst_n;
-- synchronize reset to 33 MHz clock
PROCESS(clk_33, pll_locked)
BEGIN
IF pll_locked = '0' THEN
rst_33 <= '1';
ELSIF clk_33'EVENT AND clk_33 = '1' THEN
rst_33 <= '0';
END IF;
END PROCESS;
PROCESS(sys_clk, hreset_n, pll_locked)
BEGIN
IF hreset_n = '0' OR pll_locked = '0' THEN
sys_rst <= '1';
ELSIF sys_clk'EVENT AND sys_clk = '1' THEN
sys_rst <= '0';
END IF;
END PROCESS;
PROCESS(sys_clk, sys_rst)
BEGIN
IF sys_rst = '1' THEN
cnt_500hz <= 0;
clk_500 <= '0';
ELSIF sys_clk'EVENT AND sys_clk = '1' THEN
IF cnt_500hz = 0 THEN
cnt_500hz <= CONST_500HZ;
clk_500 <= NOT clk_500;
ELSE
cnt_500hz <= cnt_500hz - 1;
END IF;
END IF;
END PROCESS;
pll: pll_pcie
PORT MAP (
areset => porst,
inclk0 => clk_16mhz, -- 16 MHz
c0 => clk_125, -- 125 MHz
c1 => clk_50, -- 50 MHz
c2 => sys_clk, -- 66 MHz
c3 => sr_clk, -- 66 MHz phase shifted to sys_clk
c4 => clk_33, -- 33 MHz
locked => pll_locked
);
wbmo_0_cyc <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
"0001" WHEN wbmo_0_cyc_int(0) = '1' ELSE -- | Chameleon Table | 0 | 0 | 200 | 0 |
"0010" WHEN wbmo_0_cyc_int(1) = '1' ELSE -- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
"0100" WHEN wbmo_0_cyc_int(2) = '1' ELSE -- | 16z002-01 VME | 2 | 10000 | 10000 | 0 |
"0100" WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
"0100" WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
"1000" WHEN wbmo_0_cyc_int(5) = '1' ELSE -- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
"0100" WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(8) = '1' ELSE -- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
"0100" WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CR/CSR | 9 | 0 | 01000000 | 4 |
"0000"; -- +--------------------------+-----+----------+----------+-----+
wbmo_1.tga <= (OTHERS => '0');
wbmo_0.tga(7) <= '0'; -- indicate access from PCIE
wbmo_0.tga(8) <= '0'; -- unused
wbmo_0.tga(6 DOWNTO 0) <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
CONST_VME_A24D16 WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
CONST_VME_A16D16 WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
CONST_VME_A16D32 WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
CONST_VME_IACK WHEN wbmo_0_cyc_int(2) = '1'
AND wbmo_0.adr(8) = '1' ELSE -- |16z002-01 VME IACK | 2 | 10100 | 10 | 0 |
CONST_VME_REGS WHEN wbmo_0_cyc_int(2) = '1' ELSE -- |16z002-01 VME REGS | 2 | 10000 | 10000 | 0 |
CONST_VME_A32D32 WHEN wbmo_0_cyc_int(8) = '1' ELSE -- |16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
CONST_VME_A24D32 WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
CONST_VME_CRCSR WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CRCSR | 9 | 0 | 1000000 | 4 |
(OTHERS => '0'); -- +--------------------------+-----+----------+----------+-----+
pcie: ip_16z091_01_top
GENERIC MAP (
SIMULATION => '1',
FPGA_FAMILY => CYCLONE4,
IRQ_WIDTH => 13,
USE_LANES => "001",-- x1 for simulation
--USE_LANES => "100",-- x1 for simulation
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
NR_OF_BARS_USED => 5,
VENDOR_ID => 16#1A88#,
DEVICE_ID => 16#4D45#,
REVISION_ID => 16#1#,
CLASS_CODE => 16#068000#,
SUBSYSTEM_VENDOR_ID => 16#D5#,
SUBSYSTEM_DEVICE_ID => 16#5A91#,
BAR_MASK_0 => x"FFFC0000", -- 256k
BAR_MASK_1 => x"FFF00000", -- 1M
BAR_MASK_2 => x"FE000000", -- 32M
BAR_MASK_3 => x"E0000000", -- 512M
BAR_MASK_4 => x"FF000000", -- 16M
BAR_MASK_5 => x"FFFFF000",
PCIE_REQUEST_LENGTH => "0000100000", -- 32DW = 128Byte
RX_LPM_WIDTHU => 10,
TX_HEADER_LPM_WIDTHU => 5,
TX_DATA_LPM_WIDTHU => 10,
BFM_LANE_WIDTH => BFM_LANE_WIDTH,
GP_DEBUG_PORT_WIDTH => 1
)
PORT MAP (
-- Hard IP ports:
clk_50 => clk_50,
clk_125 => clk_125,
ref_clk => refclk,
clk_500 => clk_500,
ext_rst_n => hreset_n,
rx_0 => pcie_rx(0),
rx_1 => pcie_rx(1),
rx_2 => pcie_rx(2),
rx_3 => pcie_rx(3),
tx_0 => pcie_tx(0),
tx_1 => pcie_tx(1),
tx_2 => pcie_tx(2),
tx_3 => pcie_tx(3),
wb_clk => sys_clk,
wb_rst => sys_rst,
wbm_ack => wbmi_0.ack,
wbm_dat_i => wbmi_0.dat,
wbm_stb => wbmo_0.stb,
wbm_cyc_o => wbmo_0_cyc_int,
wbm_we => wbmo_0.we ,
wbm_sel => wbmo_0.sel,
wbm_adr => wbmo_0.adr,
wbm_dat_o => wbmo_0.dat,
wbm_cti => wbmo_0.cti,
wbm_tga => open,
wbs_cyc => wbsi_4_cyc,
wbs_stb => wbsi_4.stb,
wbs_we => wbsi_4.we ,
wbs_sel => wbsi_4.sel,
wbs_adr => wbsi_4.adr,
wbs_dat_i => wbsi_4.dat,
wbs_cti => wbsi_4.cti,
wbs_tga => wbsi_4.tga(0),
wbs_ack => wbso_4.ack,
wbs_err => open,
wbs_dat_o => wbso_4.dat,
irq_req_i(0) => vme_irq(0) ,
irq_req_i(1) => vme_irq(1) ,
irq_req_i(2) => vme_irq(2) ,
irq_req_i(3) => vme_irq(3) ,
irq_req_i(4) => vme_irq(4) ,
irq_req_i(5) => vme_irq(5) ,
irq_req_i(6) => vme_irq(6) ,
irq_req_i(7) => vme_irq(7) ,
irq_req_i(8) => berr_irq ,
irq_req_i(9) => dma_irq ,
irq_req_i(10) => locmon_irq(0) ,
irq_req_i(11) => locmon_irq(1) ,
irq_req_i(12) => mailbox_irq_i ,
error_timeout => open,
error_cor_ext_rcv => open,
error_cor_ext_rpl => open,
error_rpl => open,
error_r2c0 => open,
error_msi_num => open,
-- Hard IP BFM connections
ep_rxvalid_i => ep_rxvalid_i,
ep_rxstatus_i => ep_rxstatus_i,
ep_rxdatak_i => ep_rxdatak_i,
ep_rxdata_i => ep_rxdata_i,
ep_rxelecidle_i => ep_rxelecidle_i,
ep_phystatus_i => ep_phystatus_i,
ep_clk250_o => ep_clk250_o,
ep_clk500_o => ep_clk500_o,
ep_rate_ext_o => ep_rate_ext_o,
ep_powerdown_ext_o => ep_powerdown_ext_o,
ep_txdatak_o => ep_txdatak_o,
ep_txdata_o => ep_txdata_o,
ep_txcompl_o => ep_txcompl_o,
ep_txelecidle_o => ep_txelecidle_o,
ep_txdetectrx_o => ep_txdetectrx_o,
ep_rxpolarity_o => ep_rxpolarity_o,
ep_ltssm_o => ep_ltssm_o,
gp_debug_port => open,
link_train_active => link_train_active
);
mailbox_irq_i <= mailbox_irq(0) OR mailbox_irq(1);
cham: iram_wb
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY,
read_only => 1,
USEDW_WIDTH => 9, -- 0x200 = 512
LOCATION => "../../top/chameleon.hex"
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
stb_i => wbsi_0.stb,
cyc_i => wbsi_0_cyc,
ack_o => wbso_0.ack,
err_o => wbso_0.err,
we_i => wbsi_0.we,
sel_i => wbsi_0.sel,
adr_i => wbsi_0.adr(10 DOWNTO 2),
dat_i => wbsi_0.dat,
dat_o => wbso_0.dat
);
srami: sram
PORT MAP (
clk66 => sys_clk,
rst => sys_rst,
stb_i => wbsi_3.stb,
ack_o => wbso_3.ack,
we_i => wbsi_3.we,
sel_i => wbsi_3.sel,
cyc_i => wbsi_3_cyc,
dat_o => wbso_3.dat,
dat_i => wbsi_3.dat,
adr_i => wbsi_3.adr(19 DOWNTO 0),
bwn => sr_bw_n,
bwan => sr_bwa_n,
bwbn => sr_bwb_n,
adscn => sr_adsc_n,
roen => sr_oe_n,
ra => sr_a,
rd_in => sr_d_in,
rd_out => sr_d_out,
rd_oe => sr_d_oe
);
sr_cs1_n <= '0'; --sys_rst; -- selected if FPGA reset is released
srdat: PROCESS(sr_d_oe, sr_d_out, sr_d)
BEGIN
IF sr_d_oe = '1' THEN
sr_d <= sr_d_out;
sr_d_in <= sr_d;
ELSE
sr_d <= (OTHERS => 'Z');
sr_d_in <= sr_d;
END IF;
END PROCESS;
sflash: z126_01_top
GENERIC MAP (
SIMULATION => true,
FPGA_FAMILY => CYCLONE4,
FLASH_TYPE => M25P32,
USE_DIRECT_INTERFACE => FALSE,
USE_REMOTE_UPDATE => TRUE,
LOAD_FPGA_IMAGE => TRUE,
LOAD_FPGA_IMAGE_ADR => X"200100"
)
PORT MAP (
clk_40mhz => clk_33,
rst_clk_40mhz => rst_33,
clk_dir => sys_clk,
rst_dir => sys_rst,
clk_indi => sys_clk,
rst_indi => sys_rst,
board_status => board_status,
wbs_stb_dir => '0',
wbs_ack_dir => OPEN,
wbs_we_dir => '0',
wbs_sel_dir => (OTHERS => '0'),
wbs_cyc_dir => '0',
wbs_dat_o_dir => OPEN,
wbs_dat_i_dir => (OTHERS => '0'),
wbs_adr_dir => (OTHERS => '0'),
wbs_err_dir => OPEN,
-- wishbone signals slave interface 1 (indirect addressing)
wbs_stb_indi => wbsi_1.stb,
wbs_ack_indi => wbso_1.ack,
wbs_we_indi => wbsi_1.we,
wbs_sel_indi => wbsi_1.sel,
wbs_cyc_indi => wbsi_1_cyc,
wbs_dat_o_indi => wbso_1.dat,
wbs_dat_i_indi => wbsi_1.dat,
wbs_adr_indi => wbsi_1.adr,
wbs_err_indi => wbso_1.err
);
vme: wbb2vme_top
GENERIC MAP(
A16_REG_MAPPING => true,
LONGADD_SIZE => 3,
USE_LONGADD => TRUE
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
startup_rst => startup_rst,
postwr => open,
vme_irq => vme_irq ,
berr_irq => berr_irq,
locmon_irq => locmon_irq ,
mailbox_irq => mailbox_irq,
dma_irq => dma_irq ,
prevent_sysrst => '0',
test_vec => test_vec,
-- vmectrl slave
wbs_stb_i => wbsi_2.stb,
wbs_ack_o => wbso_2.ack,
wbs_err_o => wbso_2.err,
wbs_we_i => wbsi_2.we,
wbs_sel_i => wbsi_2.sel,
wbs_cyc_i => wbsi_2_cyc,
wbs_adr_i => wbsi_2.adr,
wbs_dat_o => wbso_2.dat,
wbs_dat_i => wbsi_2.dat,
wbs_tga_i => wbsi_2.tga,
-- vmectrl master
wbm_ctrl_stb_o => wbmo_1.stb,
wbm_ctrl_ack_i => wbmi_1.ack,
wbm_ctrl_err_i => wbmi_1.err,
wbm_ctrl_we_o => wbmo_1.we,
wbm_ctrl_sel_o => wbmo_1.sel,
wbm_ctrl_cyc_sram => wbmo_1_cyc(0),
wbm_ctrl_cyc_pci => wbmo_1_cyc(1),
wbm_ctrl_adr_o => wbmo_1.adr,
wbm_ctrl_dat_o => wbmo_1.dat,
wbm_ctrl_dat_i => wbmi_1.dat,
wbm_dma_stb_o => wbmo_2.stb,
wbm_dma_ack_i => wbmi_2.ack,
wbm_dma_we_o => wbmo_2.we,
wbm_dma_cti => wbmo_2.cti,
wbm_dma_tga_o => wbmo_2.tga,
wbm_dma_err_i => wbmi_2.err,
wbm_dma_sel_o => wbmo_2.sel,
wbm_dma_cyc_vme => wbmo_2_cyc(0),
wbm_dma_cyc_sram => wbmo_2_cyc(1),
wbm_dma_cyc_pci => wbmo_2_cyc(2),
wbm_dma_adr_o => wbmo_2.adr,
wbm_dma_dat_o => wbmo_2.dat,
wbm_dma_dat_i => wbmi_2.dat,
pci_dat_i => (others => '0'),
pci_ack_i => '0',
pci_err_i => '0',
va => vme_a,
vd => vme_d,
vam => vme_am,
writen => vme_write_n,
iackn => vme_iack_n,
irq_i_n => vme_irq_i_n,
irq_o_n => vme_irq_o_n,
as_o_n => vme_as_o_n,
as_oe_n => vme_as_oe_n,
as_i_n => vme_as_i_n,
sysresn => vme_sysres_o_n,
sysresin => vme_sysres_i_n,
ds_o_n => vme_ds_o_n,
ds_i_n => vme_ds_i_n,
ds_oe_n => vme_ds_oe_n,
berrn => vme_berr_o_n,
berrin => vme_berr_i_n,
dtackn => vme_dtack_o_n,
dtackin => vme_dtack_i_n,
slot01n => slot01n,
sysfail_i_n => vme_sysfail_i_n,
sysfail_o_n => vme_sysfail_o_n,
bbsyn => vme_bbsy_o_n,
bbsyin => vme_bbsy_i_n,
bclr_i_n => vme_bclr_i_n,
bclr_o_n => vme_bclr_o_n,
retry_i_n => vme_retry_i_n ,
retry_o_n => vme_retry_o_n ,
retry_oe_n => vme_retry_oe_n ,
br_i_n => vme_br_i_n,
br_o_n => vme_br_o_n,
iackin => vme_iack_i_n,
iackoutn => vme_iack_o_n,
acfailn => vme_acfail_i_n,
bg_i_n => vme_bg_i_n,
bg_o_n => vme_bg_o_n,
ga => vme_ga,
gap => vme_gap,
vme_berr => vme_berr,
vme_mstr_busy => vme_mstr_busy,
d_dir => vme_d_dir ,
d_oe_n => vme_d_oe_n ,
am_dir => vme_am_dir ,
am_oe_n => vme_am_oe_n,
a_dir => vme_a_dir ,
a_oe_n => vme_a_oe_n ,
v2p_rst => v2p_rst
);
v2p_rstn <= '0' WHEN v2p_rst = '1' ELSE 'Z';
wbb : wb_bus
GENERIC MAP (
sets => sets,
timeout => timeout
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
wbmo_0 => wbmo_0,
wbmi_0 => wbmi_0,
wbmo_0_cyc => wbmo_0_cyc,
wbmo_1 => wbmo_1,
wbmi_1 => wbmi_1,
wbmo_1_cyc => wbmo_1_cyc,
wbmo_2 => wbmo_2,
wbmi_2 => wbmi_2,
wbmo_2_cyc => wbmo_2_cyc,
wbmo_3 => wbmo_3,
wbmi_3 => wbmi_3,
wbmo_3_cyc => wbmo_3_cyc,
wbso_0 => wbso_0,
wbsi_0 => wbsi_0,
wbsi_0_cyc => wbsi_0_cyc,
wbso_1 => wbso_1,
wbsi_1 => wbsi_1,
wbsi_1_cyc => wbsi_1_cyc,
wbso_2 => wbso_2,
wbsi_2 => wbsi_2,
wbsi_2_cyc => wbsi_2_cyc,
wbso_3 => wbso_3,
wbsi_3 => wbsi_3,
wbsi_3_cyc => wbsi_3_cyc,
wbso_4 => wbso_4,
wbsi_4 => wbsi_4,
wbsi_4_cyc => wbsi_4_cyc
);
wbmo_3.stb <= '0';
wbmo_3_cyc <= '0';
-------------------------------------------------------------------------------------------------------------
END A25_top_arch;
-- CONFIGURATION wbm_cfg OF pcies_wbm_ctrl IS
-- FOR pcies_wbm_ctrl_arch
-- FOR wb_adr_dec_inst : pcies_wb_adr_dec
-- USE ENTITY work.pcies_wb_adr_dec(wb_adr_dec_arch);
-- END FOR;
-- END FOR;
-- END CONFIGURATION wbm_cfg;
--
-- CONFIGURATION pcies_wbm_cfg OF pcies_wbm IS
-- FOR pcies_wbm_arch
-- FOR wbm : pcies_wbm_ctrl
-- USE CONFIGURATION work.wbm_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION pcies_wbm_cfg;
--
-- CONFIGURATION pcies2wbb_cfg OF pcies2wbb_top IS
-- FOR pcies2wbb_top_arch
-- FOR pcies_wbm_i : pcies_wbm
-- USE CONFIGURATION work.pcies_wbm_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION pcies2wbb_cfg;
--
-- CONFIGURATION top_cfg of A25_top IS
-- FOR A25_top_arch
-- FOR pcie : pcies2wbb_top
-- USE CONFIGURATION work.pcies2wbb_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION top_cfg;
-- Configurations for 16z091-01 address decoder
CONFIGURATION z091_01_wb_master_cfg OF z091_01_wb_master IS
FOR z091_01_wb_master_arch
FOR z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
USE ENTITY work.z091_01_wb_adr_dec(a25_arch);
END FOR;
END FOR;
END CONFIGURATION z091_01_wb_master_cfg;
CONFIGURATION ip_16z091_01_cfg OF ip_16z091_01 IS
FOR ip_16z091_01_arch
FOR wb_master_comp : z091_01_wb_master
USE CONFIGURATION work.z091_01_wb_master_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_cfg;
CONFIGURATION ip_16z091_01_top_cfg OF ip_16z091_01_top IS
FOR ip_16z091_01_top_arch
FOR ip_16z091_01_comp : ip_16z091_01
USE CONFIGURATION work.ip_16z091_01_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_top_cfg;
CONFIGURATION top_cfg OF A25_top IS
FOR A25_top_arch
FOR pcie : ip_16z091_01_top
USE CONFIGURATION work.ip_16z091_01_top_cfg;
END FOR;
END FOR;
END CONFIGURATION top_cfg;
SN74ABT125.vhd 0000664 0000000 0000000 00000011416 14574545710 0034326 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Bus Buffer Gates with 3-state outputs
-- Project :
---------------------------------------------------------------
-- File : SN74ABT125.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 09/02/12
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: SN74ABT125.vhd,v $
-- Revision 1.1 2012/03/29 10:28:41 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SN74ABT125 IS
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
oe_n : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- output enable: 0= driver is active, 1= tri-state
a : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : OUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END SN74ABT125;
ARCHITECTURE SN74ABT125_arch OF SN74ABT125 IS
CONSTANT tPLH_max : time:= 4.9 ns;
CONSTANT tPHL_max : time:= 4.9 ns;
CONSTANT tPZH_max : time:= 5.9 ns;
CONSTANT tPZL_max : time:= 6.8 ns;
CONSTANT tPHZ_max : time:= 6.2 ns;
CONSTANT tPLZ_max : time:= 6.2 ns;
CONSTANT tPLH_min : time:= 1 ns;
CONSTANT tPHL_min : time:= 1 ns;
CONSTANT tPZH_min : time:= 1 ns;
CONSTANT tPZL_min : time:= 1 ns;
CONSTANT tPHZ_min : time:= 1 ns;
CONSTANT tPLZ_min : time:= 1 ns;
CONSTANT tPLH_typ : time:= 3.2 ns;
CONSTANT tPHL_typ : time:= 2.5 ns;
CONSTANT tPZH_typ : time:= 3.6 ns;
CONSTANT tPZL_typ : time:= 2.5 ns;
CONSTANT tPHZ_typ : time:= 3.8 ns;
CONSTANT tPLZ_typ : time:= 3.3 ns;
SIGNAL b_out : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL oe_n_in : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL a_in : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL tPLH : time;
SIGNAL tPHL : time;
SIGNAL tPZH : time;
SIGNAL tPZL : time;
SIGNAL tPHZ : time;
SIGNAL tPLZ : time;
SIGNAL pwr_rst : std_logic;
BEGIN
tPLH <= tPLH_min WHEN OP_COND = 0 ELSE
tPLH_typ WHEN OP_COND = 1 ELSE
tPLH_max;
tPHL <= tPHL_min WHEN OP_COND = 0 ELSE
tPHL_typ WHEN OP_COND = 1 ELSE
tPHL_max;
tPZH <= tPZH_min WHEN OP_COND = 0 ELSE
tPZH_typ WHEN OP_COND = 1 ELSE
tPZH_max;
tPZL <= tPZL_min WHEN OP_COND = 0 ELSE
tPZL_typ WHEN OP_COND = 1 ELSE
tPZL_max;
tPHZ <= tPHZ_min WHEN OP_COND = 0 ELSE
tPHZ_typ WHEN OP_COND = 1 ELSE
tPHZ_max;
tPLZ <= tPLZ_min WHEN OP_COND = 0 ELSE
tPLZ_typ WHEN OP_COND = 1 ELSE
tPLZ_max;
oe_n_in <= to_x01(oe_n);
a_in <= to_x01(a);
pwr_rst <= '1', '0' AFTER 2 ps;
b <= b_out;
gen: FOR i IN 0 TO WIDTH-1 GENERATE
PROCESS(pwr_rst, oe_n_in(i), a_in(i), b_out(i))
BEGIN
IF pwr_rst'event AND oe_n_in(i) = '1' THEN
b_out(i) <= 'H';
ELSIF pwr_rst'event AND oe_n_in(i) = '0' THEN
b_out(i) <= a_in(i);
ELSIF (a_in(i)'event AND a_in(i) = '1' AND oe_n_in(i) = '0' ) THEN -- a 0->1
b_out(i) <= transport a_in(i) AFTER tPLH;
ELSIF (a_in(i)'event AND a_in(i) = '0' AND oe_n_in(i) = '0') THEN -- a 1->0
b_out(i) <= transport a_in(i) AFTER tPHL;
ELSIF (oe_n_in'event AND oe_n_in(i) = '0' AND a_in(i) = '1') THEN -- oe_n_in 1->0 a=1
b_out(i) <= transport a_in(i) AFTER tPZH;
ELSIF (oe_n_in'event AND oe_n_in(i) = '0' AND a(i) = '0') THEN -- oe_n_in 1->0 a=0
b_out(i) <= transport a_in(i) AFTER tPZL;
ELSIF (oe_n_in'event AND oe_n_in(i) = '1' AND b_out(i) = '1') THEN -- oe_n_in 0->1 b=1
b_out(i) <= transport 'H' AFTER tPHZ;
ELSIF (oe_n_in'event AND oe_n_in(i) = '1' AND b_out(i) = '0') THEN -- oe_n_in 0->1 b=0
b_out(i) <= transport 'H' AFTER tPLZ;
END IF;
END PROCESS;
END GENERATE gen;
END SN74ABT125_arch;
SN74LVTH245.vhd 0000664 0000000 0000000 00000015744 14574545710 0034510 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : SN74LVTH245.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 09/02/12
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: SN74LVTH245.vhd,v $
-- Revision 1.1 2012/03/29 10:28:42 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SN74LVTH245 IS
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
dir : IN std_logic; -- direction: 0= B data to A, 1= A data to B
oe_n : IN std_logic; -- output enable: 0= driver is active, 1= tri-state
a : INOUT std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : INOUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END SN74LVTH245;
ARCHITECTURE SN74LVTH245_arch OF SN74LVTH245 IS
CONSTANT tPLH_max : time:= 3.5 ns;
CONSTANT tPHL_max : time:= 3.5 ns;
CONSTANT tPZH_max : time:= 5.5 ns;
CONSTANT tPZL_max : time:= 5.5 ns;
CONSTANT tPHZ_max : time:= 5.9 ns;
CONSTANT tPLZ_max : time:= 5.0 ns;
CONSTANT tPLH_min : time:= 1.2 ns;
CONSTANT tPHL_min : time:= 1.2 ns;
CONSTANT tPZH_min : time:= 1.3 ns;
CONSTANT tPZL_min : time:= 1.7 ns;
CONSTANT tPHZ_min : time:= 2.2 ns;
CONSTANT tPLZ_min : time:= 2.2 ns;
CONSTANT tPLH_typ : time:= 2.3 ns;
CONSTANT tPHL_typ : time:= 2.1 ns;
CONSTANT tPZH_typ : time:= 3.2 ns;
CONSTANT tPZL_typ : time:= 3.4 ns;
CONSTANT tPHZ_typ : time:= 3.5 ns;
CONSTANT tPLZ_typ : time:= 3.4 ns;
SIGNAL oe_n_in : std_logic;
SIGNAL dir_in : std_logic;
SIGNAL a_out : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL b_out : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL a_int : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL b_int : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL tPLH : time;
SIGNAL tPHL : time;
SIGNAL tPZH : time;
SIGNAL tPZL : time;
SIGNAL tPHZ : time;
SIGNAL tPLZ : time;
SIGNAL pwr_rst : std_logic;
BEGIN
tPLH <= tPLH_min WHEN OP_COND = 0 ELSE
tPLH_typ WHEN OP_COND = 1 ELSE
tPLH_max;
tPHL <= tPHL_min WHEN OP_COND = 0 ELSE
tPHL_typ WHEN OP_COND = 1 ELSE
tPHL_max;
tPZH <= tPZH_min WHEN OP_COND = 0 ELSE
tPZH_typ WHEN OP_COND = 1 ELSE
tPZH_max;
tPZL <= tPZL_min WHEN OP_COND = 0 ELSE
tPZL_typ WHEN OP_COND = 1 ELSE
tPZL_max;
tPHZ <= tPHZ_min WHEN OP_COND = 0 ELSE
tPHZ_typ WHEN OP_COND = 1 ELSE
tPHZ_max;
tPLZ <= tPLZ_min WHEN OP_COND = 0 ELSE
tPLZ_typ WHEN OP_COND = 1 ELSE
tPLZ_max;
a <= a_out;
b <= b_out;
a_int <= transport to_x01(a) after 1 ps;
b_int <= transport to_x01(b) after 1 ps;
oe_n_in <= to_x01(oe_n);
dir_in <= to_x01(dir);
pwr_rst <= '1', '0' AFTER 2 ps;
gen: FOR i IN 0 TO (WIDTH-1) GENERATE
PROCESS(pwr_rst, dir_in, oe_n_in, a_int, b_int, a_out(i), b_out(i))
BEGIN
IF pwr_rst'event AND dir_in = '0' AND oe_n_in = '1' THEN
a_out(i) <= 'H';
ELSIF pwr_rst'event AND dir_in = '0' AND oe_n_in = '0' THEN
a_out(i) <= b_int(i);
ELSIF (pwr_rst'event OR dir_in'event) AND dir_in = '1' THEN
a_out(i) <= 'H';
ELSIF (b_int(i)'event AND b_int(i) = '1' AND oe_n_in = '0' AND dir_in = '0') OR -- b 0->1
(dir_in'event AND dir_in = '0' AND oe_n_in = '0' AND b_int(i) = '1') THEN -- dir_in 1->0
a_out(i) <= transport b_int(i) AFTER tPLH;
ELSIF (b_int(i)'event AND b_int(i) = '0' AND oe_n_in = '0' AND dir_in = '0') OR -- b 1->0
(dir_in'event AND dir_in = '0' AND oe_n_in = '0' AND b_int(i) = '0') THEN -- dir_in 0->1
a_out(i) <= transport b_int(i) AFTER tPHL;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND b_int(i) = '1' AND dir_in = '0') THEN -- oe_n_in 1->0 b=1
a_out(i) <= transport b_int(i) AFTER tPZH;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND b_int(i) = '0' AND dir_in = '0') THEN -- oe_n_in 1->0 b=0
a_out(i) <= transport b_int(i) AFTER tPZL;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND a_int(i) = '1' AND dir_in = '0') THEN -- oe_n_in 0->1 a=1
a_out(i) <= transport 'H' AFTER tPHZ;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND a_int(i) = '0' AND dir_in = '0') THEN -- oe_n_in 0->1 a=0
a_out(i) <= transport 'H' AFTER tPLZ;
END IF;
IF pwr_rst'event AND dir_in = '1' AND oe_n_in = '1' THEN
b_out(i) <= 'H';
ELSIF pwr_rst'event AND dir_in = '1' AND oe_n_in = '0' THEN
b_out(i) <= a_int(i);
ELSIF (pwr_rst'event OR dir_in'event) AND dir_in = '0' THEN
b_out(i) <= 'H';
ELSIF (a_int(i)'event AND a_int(i) = '1' AND oe_n_in = '0' AND dir_in = '1') OR -- a 0->1
(dir_in'event AND dir_in = '1' AND oe_n_in = '0' AND a_int(i) = '1') THEN -- dir_in 0->1
b_out(i) <= transport a_int(i) AFTER tPLH;
ELSIF (a_int(i)'event AND a_int(i) = '0' AND oe_n_in = '0' AND dir_in = '1') OR -- a 1->0
(dir_in'event AND dir_in = '1' AND oe_n_in = '0' AND a_int(i) = '0') THEN -- dir_in 1->0
b_out(i) <= transport a_int(i) AFTER tPHL;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND a_int(i) = '1' AND dir_in = '1') THEN -- oe_n_in 1->0 a=1
b_out(i) <= transport a_int(i) AFTER tPZH;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND a_int(i) = '0' AND dir_in = '1') THEN -- oe_n_in 1->0 a=0
b_out(i) <= transport a_int(i) AFTER tPZL;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND b_int(i) = '1' AND dir_in = '1') THEN -- oe_n_in 0->1 b=1
b_out(i) <= transport 'H' AFTER tPHZ;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND b_int(i) = '0' AND dir_in = '1') THEN -- oe_n_in 0->1 b=0
b_out(i) <= transport 'H' AFTER tPLZ;
END IF;
END PROCESS;
END GENERATE gen;
END SN74LVTH245_arch;
a25_tb.vhd 0000664 0000000 0000000 00000105641 14574545710 0034134 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Testbench A25
-- Project :
---------------------------------------------------------------
-- File : a25_tb.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 31/01/12
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.fpga_pkg_2.ALL;
USE work.vme_sim_pack.all;
USE work.terminal_pkg.all;
use work.pcie_sim_pkg.all;
ENTITY a25_tb IS
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
END a25_tb;
ARCHITECTURE a25_tb_arch OF a25_tb IS
COMPONENT A25_top
GENERIC (
SIMULATION : boolean := FALSE;
FPGA_FAMILY : family_type := CYCLONE4;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk_16mhz : IN std_logic;
led_green_n : OUT std_logic;
led_red_n : OUT std_logic;
hreset_n : IN std_logic; -- reset
v2p_rstn : OUT std_logic; -- connected to hreset_req1_n
fpga_test : INOUT std_logic_vector(5 DOWNTO 1);
-- pcie
refclk : IN std_logic; -- 100 MHz pcie clock
pcie_rx : IN std_logic_vector(3 DOWNTO 0); -- PCIe receive line
pcie_tx : OUT std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
-- sram bus
sr_clk : OUT std_logic;
sr_a : OUT std_logic_vector(18 DOWNTO 0);
sr_d : INOUT std_logic_vector(15 DOWNTO 0);
sr_bwa_n : OUT std_logic;
sr_bwb_n : OUT std_logic;
sr_bw_n : OUT std_logic;
sr_cs1_n : OUT std_logic;
sr_adsc_n : OUT std_logic;
sr_oe_n : OUT std_logic;
-- vmebus
vme_ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : IN std_logic; -- geographical addresses
vme_a : INOUT std_logic_vector(31 DOWNTO 0);
vme_a_dir : OUT std_logic;
vme_a_oe_n : OUT std_logic;
vme_d : INOUT std_logic_vector(31 DOWNTO 0);
vme_d_dir : OUT std_logic;
vme_d_oe_n : OUT std_logic;
vme_am_dir : OUT std_logic;
vme_am : INOUT std_logic_vector(5 DOWNTO 0);
vme_am_oe_n : OUT std_logic;
vme_write_n : INOUT std_logic;
vme_iack_n : INOUT std_logic;
vme_irq_i_n : IN std_logic_vector(7 DOWNTO 1);
vme_irq_o : OUT std_logic_vector(7 DOWNTO 1); -- high active on A25
vme_as_i_n : IN std_logic;
vme_as_o_n : OUT std_logic;
vme_as_oe : OUT std_logic; -- high active on A25
vme_retry_o_n : OUT std_logic;
vme_retry_oe : OUT std_logic; -- high active on A25
vme_retry_i_n : IN std_logic;
vme_sysres_i_n : IN std_logic;
vme_sysres_o : OUT std_logic; -- high active on A25
vme_ds_i_n : IN std_logic_vector(1 DOWNTO 0);
vme_ds_o_n : OUT std_logic_vector(1 DOWNTO 0);
vme_ds_oe : OUT std_logic; -- high active on A25
vme_berr_i_n : IN std_logic;
vme_berr_o : OUT std_logic; -- high active on A25
vme_dtack_i_n : IN std_logic;
vme_dtack_o : OUT std_logic; -- high active on A25
vme_scon : OUT std_logic; -- high active on A25
vme_sysfail_i_n : IN std_logic;
vme_sysfail_o : OUT std_logic; -- high active on A25
vme_bbsy_i_n : IN std_logic;
vme_bbsy_o : OUT std_logic; -- high active on A25
vme_bclr_i_n : IN std_logic; -- bus clear input
vme_bclr_o_n : OUT std_logic; -- bus clear output
vme_br_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_br_o : OUT std_logic_vector(3 DOWNTO 0); -- high active on A25
vme_iack_i_n : IN std_logic;
vme_iack_o_n : OUT std_logic;
vme_acfail_i_n : IN std_logic;
vme_sysclk : OUT std_logic;
vme_bg_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_bg_o_n : OUT std_logic_vector(3 DOWNTO 0);
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0)
);
END COMPONENT;
COMPONENT MT58L512L18F
GENERIC (
-- Clock
tKC : TIME := 8.0 ns; -- Timing are for -6.8
tKH : TIME := 1.8 ns;
tKL : TIME := 1.8 ns;
-- Output Times
tKQHZ : TIME := 3.8 ns;
-- Setup Times
tAS : TIME := 1.8 ns;
tADSS : TIME := 1.8 ns;
tAAS : TIME := 1.8 ns;
tWS : TIME := 1.8 ns;
tDS : TIME := 1.8 ns;
tCES : TIME := 1.8 ns;
-- Hold Times
tAH : TIME := 0.5 ns;
tADSH : TIME := 0.5 ns;
tAAH : TIME := 0.5 ns;
tWH : TIME := 0.5 ns;
tDH : TIME := 0.5 ns;
tCEH : TIME := 0.5 ns;
-- Bus Width and Data Bus
addr_bits : INTEGER := 19;
data_bits : INTEGER := 18
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Mode : IN STD_LOGIC;
Adv_n : IN STD_LOGIC;
Clk : IN STD_LOGIC;
Adsc_n : IN STD_LOGIC;
Adsp_n : IN STD_LOGIC;
Bwa_n : IN STD_LOGIC;
Bwb_n : IN STD_LOGIC;
Bwe_n : IN STD_LOGIC;
Gw_n : IN STD_LOGIC;
Ce_n : IN STD_LOGIC;
Ce2 : IN STD_LOGIC;
Ce2_n : IN STD_LOGIC;
Oe_n : IN STD_LOGIC;
Zz : IN STD_LOGIC
);
END COMPONENT;
COMPONENT vmebus
PORT (
slot1 : IN boolean:=TRUE; -- if true dut is in slot1
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type;
vme_mon_out : OUT vme_mon_out_type;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type;
-- the VME signals:
vb_am : INOUT std_logic_vector(5 DOWNTO 0);
vb_data : INOUT std_logic_vector(31 DOWNTO 0);
vb_adr : INOUT std_logic_vector(31 DOWNTO 0);
vb_writen : INOUT std_logic;
vb_iackn : INOUT std_logic;
vb_asn : INOUT std_logic;
vb_dsan : INOUT std_logic;
vb_dsbn : INOUT std_logic;
vb_bbsyn : INOUT std_logic;
vb_berrn : INOUT std_logic;
vb_brn : INOUT std_logic_vector(3 DOWNTO 0);
vb_dtackn : INOUT std_logic;
vb_sysresn : INOUT std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_bgin : OUT std_logic_vector(3 DOWNTO 0);
vb_bgout : IN std_logic_vector(3 DOWNTO 0);
vb_iackin : OUT std_logic;
vb_iackout : IN std_logic;
vb_acfailn : INOUT std_logic
);
END COMPONENT;
COMPONENT SN74LVTH245
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
dir : IN std_logic; -- direction: 0= B data to A, 1= A data to B
oe_n : IN std_logic; -- output enable: 0= driver is active, 1= tri-state
a : INOUT std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : INOUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END COMPONENT;
COMPONENT SN74ABT125
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
oe_n : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- output enable: 0= driver is active, 1= tri-state
a : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : OUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END COMPONENT;
COMPONENT terminal
PORT (
hreset_n : OUT std_logic;
slot1 : OUT boolean:=TRUE; -- if true dut is in slot1
en_clk : OUT boolean;
terminal_in_0 : IN terminal_in_type;
terminal_out_0 : OUT terminal_out_type;
terminal_in_1 : IN terminal_in_type;
terminal_out_1 : OUT terminal_out_type;
v2p_rstn : IN std_logic; -- connected to hreset_req1_n
vme_slv_in : OUT vme_slv_in_type;
vme_slv_out : IN vme_slv_out_type;
vme_mon_out : IN vme_mon_out_type;
vme_ga : OUT std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : OUT std_logic -- geographical addresses
);
END COMPONENT;
component pcie_sim
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
port(
rst_i : in std_logic;
pcie_rstn_i : in std_logic;
clk_i : in std_logic;
ep_clk250_i : in std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_i : in std_logic; -- endpoint SERDES 500MHz clk output
-- PCIe lanes
bfm_tx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
bfm_rx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i : in std_logic; -- endpoint rate_ext
ep_powerdown_ext_i : in std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_i : in std_logic_vector(4 downto 0);
ep_rxvalid_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_o : out std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
-- MEN terminal connection, in/out references are terminal view
term_out : in terminal_out_type;
term_in : out terminal_in_type
);
end component;
CONSTANT T_FPGA_TO_SRAM : time := 0 ns;
SIGNAL clk_125 : std_logic:='1';
SIGNAL clk_250 : std_logic:='0';
SIGNAL clk_16mhz_int : std_logic:='0';
SIGNAL clk_16mhz : std_logic:='0';
SIGNAL en_clk : boolean;
SIGNAL led_green_n : std_logic;
SIGNAL led_red_n : std_logic;
SIGNAL hreset_n : std_logic; -- reset
SIGNAL hreset : std_logic; -- reset
SIGNAL v2p_rstn : std_logic; -- connected to hreset_req1_n
SIGNAL refclk : std_logic:='0'; -- 100 MHz pcie clock
SIGNAL pcie_rx : std_logic_vector(3 DOWNTO 0); -- PCIe receive line
SIGNAL pcie_tx : std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
SIGNAL sr_clk : std_logic;
SIGNAL trans_sr_clk : std_logic;
SIGNAL sr_a : std_logic_vector(18 DOWNTO 0);
SIGNAL sr_d : std_logic_vector(15 DOWNTO 0);
SIGNAL sr_bwa_n : std_logic;
SIGNAL sr_bwb_n : std_logic;
SIGNAL sr_bw_n : std_logic;
SIGNAL sr_cs1_n : std_logic;
SIGNAL sr_adsc_n : std_logic;
SIGNAL sr_oe_n : std_logic;
SIGNAL vme_ga : std_logic_vector(4 DOWNTO 0);
SIGNAL vme_gap : std_logic;
SIGNAL vme_a : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_a_dir : std_logic;
SIGNAL vme_a_oe_n : std_logic;
SIGNAL vme_d : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_d_dir : std_logic;
SIGNAL vme_d_oe_n : std_logic;
SIGNAL vme_am_dir : std_logic;
SIGNAL vme_am : std_logic_vector(5 DOWNTO 0);
SIGNAL vme_am_oe_n : std_logic;
SIGNAL vme_write_n : std_logic;
SIGNAL vme_iack_n : std_logic;
SIGNAL vme_irq_i_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_irq_o_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_as_i_n : std_logic;
SIGNAL vme_as_o_n : std_logic;
SIGNAL vme_as_oe : std_logic;
SIGNAL vme_as_oe_n : std_logic;
SIGNAL vme_retry_o_n : std_logic;
SIGNAL vme_retry_oe_n : std_logic;
SIGNAL vme_retry_i_n : std_logic;
SIGNAL vme_sysres_i_n : std_logic;
SIGNAL vme_sysres_o_n : std_logic;
SIGNAL vme_ds_i_n : std_logic_vector(1 DOWNTO 0);
SIGNAL vme_ds_o_n : std_logic_vector(1 DOWNTO 0);
SIGNAL vme_ds_oe_n : std_logic;
SIGNAL vme_berr_i_n : std_logic;
SIGNAL vme_berr_o_n : std_logic;
SIGNAL vme_berr_o : std_logic;
SIGNAL vme_dtack_i_n : std_logic;
SIGNAL vme_dtack_o_n : std_logic;
SIGNAL vme_dtack_o : std_logic;
SIGNAL vme_scon_n : std_logic;
SIGNAL vme_sysfail_i_n : std_logic;
SIGNAL vme_sysfail_o_n : std_logic;
SIGNAL vme_bbsy_i_n : std_logic;
SIGNAL vme_bbsy_o_n : std_logic;
SIGNAL vme_bclr_i_n : std_logic; -- bus clear input
SIGNAL vme_bclr_o_n : std_logic; -- bus clear output
SIGNAL vme_br_i_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_br_o_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_iack_i_n : std_logic;
SIGNAL vme_iack_o_n : std_logic;
SIGNAL vme_acfail_i_n : std_logic;
SIGNAL vme_sysclk : std_logic;
SIGNAL vme_bg_i_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_bg_o_n : std_logic_vector(3 DOWNTO 0);
-- high active signals on A25
SIGNAL vme_irq_o : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_retry_oe : std_logic;
SIGNAL vme_sysres_o : std_logic;
SIGNAL vme_ds_oe : std_logic;
SIGNAL vme_scon : std_logic;
SIGNAL vme_sysfail_o : std_logic;
SIGNAL vme_bbsy_o : std_logic;
SIGNAL vme_br_o : std_logic_vector(3 DOWNTO 0);
SIGNAL terminal_in_0 : terminal_in_type;
SIGNAL terminal_out_0 : terminal_out_type;
SIGNAL terminal_in_1 : terminal_in_type;
SIGNAL terminal_out_1 : terminal_out_type;
SIGNAL vme_slv_in : vme_slv_in_type;
SIGNAL vme_slv_out : vme_slv_out_type;
SIGNAL vme_mon_out : vme_mon_out_type;
SIGNAL Addr : std_logic_vector(18 DOWNTO 0);
SIGNAL Adsc_n : std_logic;
SIGNAL Bwa_n : std_logic;
SIGNAL Bwb_n : std_logic;
SIGNAL Bwe_n : std_logic;
SIGNAL Oe_n : std_logic;
SIGNAL ce_n : std_logic;
SIGNAL vb_am : std_logic_vector(5 DOWNTO 0);
SIGNAL vb_data : std_logic_vector(31 DOWNTO 0);
SIGNAL vb_adr : std_logic_vector(31 DOWNTO 0);
SIGNAL vb_writen : std_logic;
SIGNAL vb_iackn : std_logic;
SIGNAL vb_asn : std_logic;
SIGNAL vb_dsan : std_logic;
SIGNAL vb_dsbn : std_logic;
SIGNAL vb_bbsyn : std_logic;
SIGNAL vb_berrn : std_logic;
SIGNAL vb_brn : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_dtackn : std_logic;
SIGNAL vb_sysresn : std_logic;
SIGNAL vb_irq1n : std_logic;
SIGNAL vb_irq2n : std_logic;
SIGNAL vb_irq3n : std_logic;
SIGNAL vb_irq4n : std_logic;
SIGNAL vb_irq5n : std_logic;
SIGNAL vb_irq6n : std_logic;
SIGNAL vb_irq7n : std_logic;
SIGNAL vb_bgin : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_bgout : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_iackin : std_logic;
SIGNAL vb_iackout : std_logic;
SIGNAL vb_acfailn : std_logic;
SIGNAL vb_sysclk : std_logic;
SIGNAL vb_sysfailn : std_logic;
SIGNAL dummy : std_logic:='1';
SIGNAL slot1 : boolean;
-- Hard IP BFM connections
signal ep_rxvalid_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxstatus_int : std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0);
signal ep_rxdatak_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxdata_int : std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0);
signal ep_rxelecidle_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_phystatus_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_clk250_int : std_logic;
signal ep_clk500_int : std_logic;
signal ep_rate_ext_int : std_logic;
signal ep_powerdown_ext_int : std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0);
signal ep_txdatak_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txdata_int : std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0);
signal ep_txcompl_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txelecidle_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txdetectrx_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxpolarity_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_ltssm_int : std_logic_vector(4 downto 0);
BEGIN
-- high active signals on A25
vme_irq_o_n <= NOT vme_irq_o ;
vme_retry_oe_n <= NOT vme_retry_oe ;
vme_sysres_o_n <= NOT vme_sysres_o ;
vme_ds_oe_n <= NOT vme_ds_oe ;
vme_scon_n <= NOT vme_scon ;
vme_sysfail_o_n <= NOT vme_sysfail_o ;
vme_bbsy_o_n <= NOT vme_bbsy_o ;
vme_br_o_n <= NOT vme_br_o ;
vme_as_oe_n <= NOT vme_as_oe;
vme_dtack_o_n <= NOT vme_dtack_o;
vme_berr_o_n <= NOT vme_berr_o;
a25: A25_top
GENERIC MAP (
SIMULATION => TRUE,
FPGA_FAMILY => CYCLONE4,
BFM_LANE_WIDTH => BFM_LANE_WIDTH,
sets => "1110",
timeout => 5000
)
PORT MAP (
clk_16mhz => clk_16mhz ,
led_green_n => led_green_n ,
led_red_n => led_red_n ,
hreset_n => hreset_n ,
v2p_rstn => v2p_rstn ,
fpga_test => open,
refclk => refclk ,
pcie_rx => pcie_rx ,
pcie_tx => pcie_tx ,
sr_clk => sr_clk ,
sr_a => sr_a ,
sr_d => sr_d ,
sr_bwa_n => sr_bwa_n ,
sr_bwb_n => sr_bwb_n ,
sr_bw_n => sr_bw_n ,
sr_cs1_n => sr_cs1_n ,
sr_adsc_n => sr_adsc_n ,
sr_oe_n => sr_oe_n ,
vme_ga => vme_ga,
vme_gap => vme_gap,
vme_a => vme_a ,
vme_a_dir => vme_a_dir ,
vme_a_oe_n => vme_a_oe_n ,
vme_d => vme_d ,
vme_d_dir => vme_d_dir ,
vme_d_oe_n => vme_d_oe_n ,
vme_am_dir => vme_am_dir ,
vme_am => vme_am ,
vme_am_oe_n => vme_am_oe_n ,
vme_write_n => vme_write_n ,
vme_iack_n => vme_iack_n ,
vme_irq_i_n => vme_irq_i_n ,
vme_irq_o => vme_irq_o ,
vme_as_i_n => vme_as_i_n ,
vme_as_o_n => vme_as_o_n ,
vme_as_oe => vme_as_oe ,
vme_retry_o_n => vme_retry_o_n ,
vme_retry_oe => vme_retry_oe ,
vme_retry_i_n => vme_retry_i_n ,
vme_sysres_i_n => vme_sysres_i_n ,
vme_sysres_o => vme_sysres_o ,
vme_ds_i_n => vme_ds_i_n ,
vme_ds_o_n => vme_ds_o_n ,
vme_ds_oe => vme_ds_oe ,
vme_berr_i_n => vme_berr_i_n ,
vme_berr_o => vme_berr_o ,
vme_dtack_i_n => vme_dtack_i_n ,
vme_dtack_o => vme_dtack_o ,
vme_scon => vme_scon ,
vme_sysfail_i_n => vme_sysfail_i_n ,
vme_sysfail_o => vme_sysfail_o ,
vme_bbsy_i_n => vme_bbsy_i_n ,
vme_bbsy_o => vme_bbsy_o ,
vme_bclr_i_n => vme_bclr_i_n ,
vme_bclr_o_n => vme_bclr_o_n ,
vme_br_i_n => vme_br_i_n ,
vme_br_o => vme_br_o ,
vme_iack_i_n => vme_iack_i_n ,
vme_iack_o_n => vme_iack_o_n ,
vme_acfail_i_n => vme_acfail_i_n ,
vme_sysclk => vme_sysclk ,
vme_bg_i_n => vme_bg_i_n ,
vme_bg_o_n => vme_bg_o_n,
-- Hard IP BFM connections
ep_rxvalid_i => ep_rxvalid_int,
ep_rxstatus_i => ep_rxstatus_int,
ep_rxdatak_i => ep_rxdatak_int,
ep_rxdata_i => ep_rxdata_int,
ep_rxelecidle_i => ep_rxelecidle_int,
ep_phystatus_i => ep_phystatus_int,
ep_clk250_o => ep_clk250_int,
ep_clk500_o => ep_clk500_int,
ep_rate_ext_o => ep_rate_ext_int,
ep_powerdown_ext_o => ep_powerdown_ext_int,
ep_txdatak_o => ep_txdatak_int,
ep_txdata_o => ep_txdata_int,
ep_txcompl_o => ep_txcompl_int,
ep_txelecidle_o => ep_txelecidle_int,
ep_txdetectrx_o => ep_txdetectrx_int,
ep_rxpolarity_o => ep_rxpolarity_int,
ep_ltssm_o => ep_ltssm_int
);
clk_16mhz_int <= NOT clk_16mhz_int AFTER 31.25 ns;
clk_16mhz <= clk_16mhz_int WHEN en_clk ELSE '0';
refclk <= NOT refclk AFTER 5 ns;
clk_125 <= NOT clk_125 AFTER 4 ns; -- 125 MHz
clk_250 <= NOT clk_250 AFTER 2 ns; -- 250 MHz
hreset <= NOT hreset_n;
pcie_sim_inst: pcie_sim
generic map(
BFM_LANE_WIDTH => BFM_LANE_WIDTH
)
port map(
rst_i => hreset,
pcie_rstn_i => hreset_n,
clk_i => refclk,
ep_clk250_i => ep_clk250_int,
ep_clk500_i => ep_clk500_int,
-- PCIe lanes
bfm_tx_i => pcie_tx(BFM_LANE_WIDTH -1 downto 0),
bfm_rx_o => pcie_rx(BFM_LANE_WIDTH -1 downto 0),
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i => ep_rate_ext_int,
ep_powerdown_ext_i => ep_powerdown_ext_int,
ep_txdatak_i => ep_txdatak_int,
ep_txdata_i => ep_txdata_int,
ep_txcompl_i => ep_txcompl_int,
ep_txelecidle_i => ep_txelecidle_int,
ep_txdetectrx_i => ep_txdetectrx_int,
ep_rxpolarity_i => ep_rxpolarity_int,
ep_ltssm_i => ep_ltssm_int,
ep_rxvalid_o => ep_rxvalid_int,
ep_rxstatus_o => ep_rxstatus_int,
ep_rxdatak_o => ep_rxdatak_int,
ep_rxdata_o => ep_rxdata_int,
ep_rxelecidle_o => ep_rxelecidle_int,
ep_phystatus_o => ep_phystatus_int,
-- MEN terminal connection, in/out references are terminal view
term_out => terminal_out_0,
term_in => terminal_in_0
);
trans_sr_clk <= transport sr_clk AFTER 12 ns;
Addr <= transport sr_a AFTER (T_FPGA_TO_SRAM);
Adsc_n <= transport sr_adsc_n AFTER (T_FPGA_TO_SRAM);
Bwa_n <= transport sr_bwa_n AFTER (T_FPGA_TO_SRAM);
Bwb_n <= transport sr_bwb_n AFTER (T_FPGA_TO_SRAM);
Bwe_n <= transport sr_bw_n AFTER (T_FPGA_TO_SRAM);
Oe_n <= transport sr_oe_n AFTER (T_FPGA_TO_SRAM);
ce_n <= '1', '0' AFTER 28 ns;
sram : MT58L512L18F
GENERIC MAP (
addr_bits => 19,
data_bits => 16
)
PORT MAP(
Clk => trans_sr_clk,
Dq => sr_d ,
Addr => Addr ,
Adsc_n => adsc_n,
Bwa_n => Bwa_n ,
Bwb_n => Bwb_n ,
Bwe_n => Bwe_n ,
Oe_n => Oe_n ,
Adsp_n => '1',
Mode => '0',
Adv_n => '1',
Gw_n => '1',
Ce_n => ce_n,
Ce2 => '1',
Ce2_n => '0',
Zz => '0'
);
vme_bus : vmebus
PORT MAP (
slot1 => slot1, -- if true dut is in slot1
vme_slv_in => vme_slv_in ,
vme_slv_out => vme_slv_out,
vme_mon_out => vme_mon_out,
terminal_in_x => terminal_in_1 ,
terminal_out_x => terminal_out_1 ,
vb_am => vb_am ,
vb_data => vb_data ,
vb_adr => vb_adr ,
vb_writen => vb_writen ,
vb_iackn => vb_iackn ,
vb_asn => vb_asn ,
vb_dsan => vb_dsan ,
vb_dsbn => vb_dsbn ,
vb_bbsyn => vb_bbsyn ,
vb_berrn => vb_berrn ,
vb_brn => vb_brn ,
vb_dtackn => vb_dtackn ,
vb_sysresn => vb_sysresn ,
vb_irq1n => vb_irq1n ,
vb_irq2n => vb_irq2n ,
vb_irq3n => vb_irq3n ,
vb_irq4n => vb_irq4n ,
vb_irq5n => vb_irq5n ,
vb_irq6n => vb_irq6n ,
vb_irq7n => vb_irq7n ,
vb_bgin => vb_bgin ,
vb_bgout => vb_bgout ,
vb_iackin => vb_iackin ,
vb_iackout => vb_iackout ,
vb_acfailn => vb_acfailn
);
bus_drv_ctrl_out: SN74ABT125
GENERIC MAP (
OP_COND => 2,
WIDTH => 21
)
PORT MAP (
oe_n(0) => vme_irq_o_n(1),
oe_n(1) => vme_irq_o_n(2),
oe_n(2) => vme_irq_o_n(3),
oe_n(3) => vme_irq_o_n(4),
oe_n(4) => vme_irq_o_n(5),
oe_n(5) => vme_irq_o_n(6),
oe_n(6) => vme_irq_o_n(7),
oe_n(7) => vme_as_oe_n,
oe_n(8) => vme_dtack_o_n,
oe_n(9) => vme_ds_o_n(0),
oe_n(10) => vme_ds_o_n(1),
oe_n(11) => vme_sysclk,
oe_n(12) => vme_berr_o_n,
oe_n(13) => vme_sysres_o_n,
oe_n(14) => vme_sysfail_o_n,
oe_n(15) => vme_br_o_n(0),
oe_n(16) => vme_br_o_n(1),
oe_n(17) => vme_br_o_n(2),
oe_n(18) => vme_br_o_n(3),
oe_n(19) => '1',
oe_n(20) => vme_bbsy_o_n,
a(0) => vme_irq_o_n(1),
a(1) => vme_irq_o_n(2),
a(2) => vme_irq_o_n(3),
a(3) => vme_irq_o_n(4),
a(4) => vme_irq_o_n(5),
a(5) => vme_irq_o_n(6),
a(6) => vme_irq_o_n(7),
a(7) => vme_as_o_n,
a(8) => vme_dtack_o_n,
a(9) => vme_ds_o_n(0),
a(10) => vme_ds_o_n(1),
a(11) => vme_sysclk,
a(12) => vme_berr_o_n,
a(13) => vme_sysres_o_n,
a(14) => vme_sysfail_o_n,
a(15) => vme_br_o_n(0),
a(16) => vme_br_o_n(1),
a(17) => vme_br_o_n(2),
a(18) => vme_br_o_n(3),
a(19) => '1',
a(20) => vme_bbsy_o_n,
b(0) => vb_irq1n,
b(1) => vb_irq2n,
b(2) => vb_irq3n,
b(3) => vb_irq4n,
b(4) => vb_irq5n,
b(5) => vb_irq6n,
b(6) => vb_irq7n,
b(7) => vb_asn,
b(8) => vb_dtackn,
b(9) => vb_dsan,
b(10) => vb_dsbn,
b(11) => vb_sysclk,
b(12) => vb_berrn,
b(13) => vb_sysresn,
b(14) => vb_sysfailn,
b(15) => vb_brn(0),
b(16) => vb_brn(1),
b(17) => vb_brn(2),
b(18) => vb_brn(3),
b(19) => vb_acfailn,
b(20) => vb_bbsyn
);
vb_irq1n <= 'H';
bus_drv_ctrl_in: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 29
)
PORT MAP(
dir => '1', -- a->b
oe_n => '0',
a(0) => vb_irq1n,
a(1) => vb_irq2n,
a(2) => vb_irq3n,
a(3) => vb_irq4n,
a(4) => vb_irq5n,
a(5) => vb_irq6n,
a(6) => vb_irq7n,
a(7) => vb_iackin,
a(8) => vme_iack_o_n,
a(9) => vb_asn,
a(10) => vb_dtackn,
a(11) => vb_dsan,
a(12) => vb_dsbn,
a(13) => vb_berrn,
a(14) => vb_sysresn,
a(15) => dummy,
a(16) => vme_bg_o_n(0),
a(17) => vme_bg_o_n(1),
a(18) => vme_bg_o_n(2),
a(19) => vme_bg_o_n(3),
a(20) => vb_bgin(0),
a(21) => vb_bgin(1),
a(22) => vb_bgin(2),
a(23) => vb_bgin(3),
a(24) => vb_bbsyn,
a(25) => vb_brn(0),
a(26) => vb_brn(1),
a(27) => vb_brn(2),
a(28) => vb_brn(3),
b(0) => vme_irq_i_n(1),
b(1) => vme_irq_i_n(2),
b(2) => vme_irq_i_n(3),
b(3) => vme_irq_i_n(4),
b(4) => vme_irq_i_n(5),
b(5) => vme_irq_i_n(6),
b(6) => vme_irq_i_n(7),
b(7) => vme_iack_i_n,
b(8) => vb_iackout,
b(9) => vme_as_i_n,
b(10) => vme_dtack_i_n,
b(11) => vme_ds_i_n(0),
b(12) => vme_ds_i_n(1),
b(13) => vme_berr_i_n,
b(14) => vme_sysres_i_n,
b(15) => vme_sysfail_i_n,
b(16) => vb_bgout(0),
b(17) => vb_bgout(1),
b(18) => vb_bgout(2),
b(19) => vb_bgout(3),
b(20) => vme_bg_i_n(0),
b(21) => vme_bg_i_n(1),
b(22) => vme_bg_i_n(2),
b(23) => vme_bg_i_n(3),
b(24) => vme_bbsy_i_n,
b(25) => vme_br_i_n(0),
b(26) => vme_br_i_n(1),
b(27) => vme_br_i_n(2),
b(28) => vme_br_i_n(3)
);
bus_drv_am: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 8
)
PORT MAP(
dir => vme_am_dir,
oe_n => vme_am_oe_n,
a(0) => vme_am(0),
a(1) => vme_am(1),
a(2) => vme_am(2),
a(3) => vme_am(3),
a(4) => vme_am(4),
a(5) => vme_am(5),
a(6) => vme_iack_n,
a(7) => vme_write_n,
b(0) => vb_am(0),
b(1) => vb_am(1),
b(2) => vb_am(2),
b(3) => vb_am(3),
b(4) => vb_am(4),
b(5) => vb_am(5),
b(6) => vb_iackn,
b(7) => vb_writen
);
bus_drv_adr: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 32
)
PORT MAP(
dir => vme_a_dir,
oe_n => vme_a_oe_n,
a => vme_a,
b => vb_adr
);
bus_drv_dat: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 32
)
PORT MAP(
dir => vme_d_dir,
oe_n => vme_d_oe_n,
a => vme_d,
b => vb_data
);
term: terminal
PORT MAP (
hreset_n => hreset_n ,
slot1 => slot1,
en_clk => en_clk,
terminal_in_0 => terminal_in_0 ,
terminal_out_0 => terminal_out_0,
terminal_in_1 => terminal_in_1 ,
terminal_out_1 => terminal_out_1,
vme_slv_in => vme_slv_in ,
vme_slv_out => vme_slv_out,
vme_mon_out => vme_mon_out,
v2p_rstn => v2p_rstn ,
vme_ga => vme_ga,
vme_gap => vme_gap
);
END a25_tb_arch;
CONFIGURATION a25_tb_conf of a25_tb IS
FOR a25_tb_arch
FOR a25 : A25_top
USE CONFIGURATION work.top_cfg;
END FOR;
END FOR;
END CONFIGURATION a25_tb_conf;
ip_16z091_01_top_sim.vhd 0000664 0000000 0000000 00000211707 14574545710 0036455 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : top level module for 16z091-01 design
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : ip_16z091_01_top
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 23.02.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a
-- Synthesis : Quartus II 10.0
--------------------------------------------------------------------------------
-- Description :
-- Toplevel module that combines the 16z091-01 IP core with the Altera hard
-- makro PCIe IP core
--------------------------------------------------------------------------------
-- Hierarchy :
-- * ip_16z091_01_top_core
-- ip_16z091_01
-- Hard_IP
-- z091_01_wb_adr_dec
-- pcie_msi
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.fpga_pkg_2.all;
entity ip_16z091_01_top is
generic(
SIMULATION : std_logic := '0'; -- =1 simulation,=0 synthesis
FPGA_FAMILY : family_type := NONE;
IRQ_WIDTH : integer range 32 downto 1 := 1;
-- only use one of the following 3:
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
NR_OF_BARS_USED : natural range 6 downto 1 := 5;
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
BAR_MASK_0 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_1 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_2 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_3 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_4 : std_logic_vector(31 downto 0) := x"FF000001";
BAR_MASK_5 : std_logic_vector(31 downto 0) := x"FF000001";
ROM_MASK : std_logic_vector(31 downto 0) := x"FFFF0000";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000010000"; -- 16DW = 64Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
GP_DEBUG_PORT_WIDTH : positive := 1
);
port(
-- Hard IP ports:
clk_50 : in std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
clk_125 : in std_logic; -- 125 MHz clock for fixed_clk, CycloneIV only
ref_clk : in std_logic; -- 100 MHz reference clock
clk_500 : in std_logic; -- 500 Hz clock
ext_rst_n : in std_logic; -- for CycloneV this MUST be connected to
-- nPERSTL0 for top left HardIP
-- nPERSTL1 for bottom left Hard IP <- use this one first (recommended by Altera)
rx_0 : in std_logic;
rx_1 : in std_logic;
rx_2 : in std_logic;
rx_3 : in std_logic;
tx_0 : out std_logic;
tx_1 : out std_logic;
tx_2 : out std_logic;
tx_3 : out std_logic;
-- Wishbone ports:
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
irq_req_i : in std_logic_vector(IRQ_WIDTH -1 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0);
-- debug port
gp_debug_port : out std_logic_vector(GP_DEBUG_PORT_WIDTH -1 downto 0); -- general purpose debug port
link_train_active : out std_logic
);
end entity ip_16z091_01_top;
-- ****************************************************************************
-- +----------------------------------------------------------------------------
-- | Architecture for Cyclone IV
-- +----------------------------------------------------------------------------
architecture ip_16z091_01_top_arch of ip_16z091_01_top is
constant MAX_ADDR_VAL : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- := 2^32 - 1
function conv_std_to_string(
in_bit : std_logic
) return string is
begin
if(in_bit = '0') then
return "false";
else
return "true";
end if;
end function conv_std_to_string;
function calc_mask_size(
in_BAR_mask : std_logic_vector;
BAR_No : integer range 5 downto 0
) return integer is
variable in_val : std_logic_vector(31 downto 0) := (others => '0');
variable int_temp : integer := 0;
variable addr_line : integer range 32 downto 1 := 1;
begin
if(BAR_No > NR_OF_BARS_USED - 1) then
return 0;
else
---------------------------------------------------------
-- memory thus unmask I/O, type and prefetch bit values
---------------------------------------------------------
if(in_BAR_mask(0) = '0') then
in_val := in_BAR_mask(31 downto 4) & "0000";
-----------------------------------------
-- I/O thus unmask I/O and reserved bit
-----------------------------------------
else
in_val := in_BAR_mask(31 downto 2) & "00";
end if;
in_val := MAX_ADDR_VAL - in_val;
int_temp := conv_integer(unsigned(in_val));
while int_temp >= 2 loop
addr_line := addr_line + 1;
int_temp := int_temp / 2;
end loop;
return addr_line;
end if;
end function calc_mask_size;
constant IO_SPACE_0 : string := conv_std_to_string(BAR_MASK_0(0));
constant PREFETCH_0 : string := conv_std_to_string(BAR_MASK_0(3));
constant SIZE_MASK_0 : integer := calc_mask_size(BAR_MASK_0, 0);
constant IO_SPACE_1 : string := conv_std_to_string(BAR_MASK_1(0));
constant PREFETCH_1 : string := conv_std_to_string(BAR_MASK_1(3));
constant SIZE_MASK_1 : integer := calc_mask_size(BAR_MASK_1, 1);
constant IO_SPACE_2 : string := conv_std_to_string(BAR_MASK_2(0));
constant PREFETCH_2 : string := conv_std_to_string(BAR_MASK_2(3));
constant SIZE_MASK_2 : integer := calc_mask_size(BAR_MASK_2, 2);
constant IO_SPACE_3 : string := conv_std_to_string(BAR_MASK_3(0));
constant PREFETCH_3 : string := conv_std_to_string(BAR_MASK_3(3));
constant SIZE_MASK_3 : integer := calc_mask_size(BAR_MASK_3, 3);
constant IO_SPACE_4 : string := conv_std_to_string(BAR_MASK_4(0));
constant PREFETCH_4 : string := conv_std_to_string(BAR_MASK_4(3));
constant SIZE_MASK_4 : integer := calc_mask_size(BAR_MASK_4, 4);
constant IO_SPACE_5 : string := conv_std_to_string(BAR_MASK_5(0));
constant PREFETCH_5 : string := conv_std_to_string(BAR_MASK_5(3));
constant SIZE_MASK_5 : integer := calc_mask_size(BAR_MASK_5, 5);
--TODO_ITEM FIX THIS!
--constant SIZE_MASK_ROM : integer := calc_mask_size(ROM_MASK, 6);
constant SIZE_MASK_ROM : integer := calc_mask_size(ROM_MASK, 5);
constant SUPPORTED_DEVICES : supported_family_types := (CYCLONE4, ARRIA2_GX);
-- internal signals -----------------------------------------------------------
signal rst_int : std_logic;
signal core_clk_int : std_logic;
signal crst_int : std_logic;
signal srst_int : std_logic;
signal srstn_int : std_logic;
signal npor_int : std_logic;
signal clk250_int : std_logic;
signal clk250_int_1delta_delay : std_logic;
signal clk250_int_2delta_delay : std_logic;
signal clk250_int_3delta_delay : std_logic;
signal rx_st_data0_int : std_logic_vector(63 downto 0);
signal rx_st_err0_int : std_logic;
signal rx_st_valid0_int : std_logic;
signal rx_st_sop0_int : std_logic;
signal rx_st_eop0_int : std_logic;
signal rx_st_be0_int : std_logic_vector(7 downto 0);
signal rx_st_bardec0_int : std_logic_vector(7 downto 0);
signal tx_st_ready0_int : std_logic;
signal tx_fifo_full0_int : std_logic;
signal tx_fifo_empty0_int : std_logic;
signal tx_fifo_rdptr0_int : std_logic_vector(3 downto 0);
signal tx_fifo_wrptr0_int : std_logic_vector(3 downto 0);
signal pme_to_sr_int : std_logic;
signal tl_cfg_add_int : std_logic_vector(3 downto 0);
signal tl_cfg_ctl_int : std_logic_vector(31 downto 0);
signal tl_cfg_ctl_wr_int : std_logic;
signal tl_cfg_sts_int : std_logic_vector(52 downto 0);
signal tl_cfg_sts_wr_int : std_logic;
signal app_int_ack_int : std_logic;
signal app_msi_ack_int : std_logic;
signal rx_st_mask0_int : std_logic;
signal rx_st_ready0_int : std_logic;
signal tx_st_err0_int : std_logic;
signal tx_st_valid0_int : std_logic;
signal tx_st_sop0_int : std_logic;
signal tx_st_eop0_int : std_logic;
signal tx_st_data0_int : std_logic_vector(63 downto 0);
signal pme_to_cr_int : std_logic;
signal app_int_sts_int : std_logic;
signal app_msi_req_int : std_logic;
signal app_msi_tc_int : std_logic_vector(2 downto 0);
signal app_msi_num_int : std_logic_vector(4 downto 0);
signal pex_msi_num_int : std_logic_vector(4 downto 0);
signal derr_cor_ext_rcv_int : std_logic_vector(1 downto 0) := "00";
signal derr_cor_ext_rpl_int : std_logic;
signal derr_rpl_int : std_logic;
signal r2c_err0_int : std_logic;
signal cpl_err_int : std_logic_vector(6 downto 0);
signal cpl_pending_int : std_logic;
--signal int_bar_hit : std_logic_vector(6 downto 0);
--signal wbm_adr_int : std_logic_vector(31 downto 0);
signal reconfig_fromgxb_int : std_logic_vector (4 downto 0);
signal reconfig_togxb_int : std_logic_vector (3 downto 0);
SIGNAL reconf_busy : std_logic;
signal pll_powerdown_int : std_logic;
signal l2_exit : std_logic;
signal hotrst_exit : std_logic;
signal dlup_exit : std_logic;
signal rst_cwh : std_logic;
signal rst_cwh_cnt : std_logic_vector (1 downto 0);
--signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
--signal wbm_cyc_o_int_d : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0); --mwawrik: delayed cycle causes problems
signal test_in_int : std_logic_vector(39 downto 0);
signal pipe_mode_int : std_logic;
signal txdetectrx_int : std_logic;
signal powerdown_int : std_logic_vector(1 downto 0);
-- signals to connect pcie_msi
signal int_wb_int : std_logic;
signal int_wb_pwr_enable : std_logic;
signal int_wb_int_num : std_logic_vector(4 downto 0);
signal int_wb_int_ack : std_logic;
signal int_wb_int_num_allowed : std_logic_vector(5 downto 0);
signal int_ltssm : std_logic_vector(4 downto 0);
signal reconfig_clk_locked_int : std_logic;
signal reconfig_clk_int : std_logic;
signal fixedclk_serdes_int : std_logic;
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component ip_16z091_01
generic(
FPGA_FAMILY : family_type := NONE;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
READY_LATENCY : natural := 2;
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001";
WBM_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011";
WBM_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
WBS_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100";
WBS_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000";
RX_FIFO_DEPTH : natural := 1024;
RX_LPM_WIDTHU : natural := 10;
TX_HEADER_FIFO_DEPTH : natural := 32;
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024;
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
wb_rst : in std_logic;
-- IP Core
core_clk : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
--wb_bar_dec : out std_logic_vector(6 downto 0);
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
wb_int : in std_logic;
wb_pwr_enable : in std_logic;
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end component;
component Hard_IP_x1
port (
-- inputs:
signal app_int_sts : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal app_msi_req : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC;
signal crst : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal lmi_wren : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pclk_in : IN STD_LOGIC;
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pm_event : IN STD_LOGIC;
signal pme_to_cr : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal rx_st_ready0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
-- outputs:
signal app_clk : OUT STD_LOGIC;
signal app_int_ack : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal core_clk_out : OUT STD_LOGIC;
signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
signal derr_cor_ext_rpl : OUT STD_LOGIC;
signal derr_rpl : OUT STD_LOGIC;
signal dlup_exit : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal l2_exit : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal lmi_ack : OUT STD_LOGIC;
signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal r2c_err0 : OUT STD_LOGIC;
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal rx_st_err0 : OUT STD_LOGIC;
signal rx_st_sop0 : OUT STD_LOGIC;
signal rx_st_valid0 : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_out0 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC
);
end component;
COMPONENT Hard_IP_x4 is
port (
-- inputs:
signal app_int_sts : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal app_msi_req : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC;
signal crst : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal lmi_wren : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pclk_in : IN STD_LOGIC;
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pm_event : IN STD_LOGIC;
signal pme_to_cr : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rx_in1 : IN STD_LOGIC;
signal rx_in2 : IN STD_LOGIC;
signal rx_in3 : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal rx_st_ready0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata1_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata2_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata3_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxdatak1_ext : IN STD_LOGIC;
signal rxdatak2_ext : IN STD_LOGIC;
signal rxdatak3_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxelecidle1_ext : IN STD_LOGIC;
signal rxelecidle2_ext : IN STD_LOGIC;
signal rxelecidle3_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus1_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus2_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus3_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal rxvalid1_ext : IN STD_LOGIC;
signal rxvalid2_ext : IN STD_LOGIC;
signal rxvalid3_ext : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
-- outputs:
signal app_int_ack : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal core_clk_out : OUT STD_LOGIC;
signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
signal derr_cor_ext_rpl : OUT STD_LOGIC;
signal derr_rpl : OUT STD_LOGIC;
signal dlup_exit : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal l2_exit : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal lmi_ack : OUT STD_LOGIC;
signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal r2c_err0 : OUT STD_LOGIC;
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal rx_st_err0 : OUT STD_LOGIC;
signal rx_st_sop0 : OUT STD_LOGIC;
signal rx_st_valid0 : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal rxpolarity1_ext : OUT STD_LOGIC;
signal rxpolarity2_ext : OUT STD_LOGIC;
signal rxpolarity3_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_out0 : OUT STD_LOGIC;
signal tx_out1 : OUT STD_LOGIC;
signal tx_out2 : OUT STD_LOGIC;
signal tx_out3 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txcompl1_ext : OUT STD_LOGIC;
signal txcompl2_ext : OUT STD_LOGIC;
signal txcompl3_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata1_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata2_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata3_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdatak1_ext : OUT STD_LOGIC;
signal txdatak2_ext : OUT STD_LOGIC;
signal txdatak3_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC;
signal txelecidle1_ext : OUT STD_LOGIC;
signal txelecidle2_ext : OUT STD_LOGIC;
signal txelecidle3_ext : OUT STD_LOGIC
);
end component hard_ip_x4;
component Hard_IP_x1_plus is
port (
-- inputs:
signal app_int_sts : in std_logic;
signal app_msi_num : in std_logic_vector (4 downto 0);
signal app_msi_req : in std_logic;
signal app_msi_tc : in std_logic_vector (2 downto 0);
signal cpl_err : in std_logic_vector (6 downto 0);
signal cpl_pending : in std_logic;
signal fixedclk_serdes : in std_logic;
signal lmi_addr : in std_logic_vector (11 downto 0);
signal lmi_din : in std_logic_vector (31 downto 0);
signal lmi_rden : in std_logic;
signal lmi_wren : in std_logic;
signal local_rstn : in std_logic;
signal pcie_rstn : in std_logic;
signal pclk_in : in std_logic;
signal pex_msi_num : in std_logic_vector (4 downto 0);
signal phystatus_ext : in std_logic;
signal pipe_mode : in std_logic := std_logic'('0');
signal pld_clk : in std_logic;
signal pm_auxpwr : in std_logic;
signal pm_data : in std_logic_vector (9 downto 0);
signal pm_event : in std_logic;
signal pme_to_cr : in std_logic;
signal reconfig_clk : in std_logic;
signal reconfig_clk_locked : in std_logic;
signal refclk : in std_logic;
signal rx_in0 : in std_logic := std_logic'('0');
signal rx_st_mask0 : in std_logic;
signal rx_st_ready0 : in std_logic;
signal rxdata0_ext : in std_logic_vector (7 downto 0);
signal rxdatak0_ext : in std_logic;
signal rxelecidle0_ext : in std_logic;
signal rxstatus0_ext : in std_logic_vector (2 downto 0);
signal rxvalid0_ext : in std_logic;
signal test_in : in std_logic_vector (39 downto 0);
signal tx_st_data0 : in std_logic_vector (63 downto 0);
signal tx_st_eop0 : in std_logic;
signal tx_st_err0 : in std_logic;
signal tx_st_sop0 : in std_logic;
signal tx_st_valid0 : in std_logic;
-- outputs:
signal app_clk : out std_logic;
signal app_int_ack : out std_logic;
signal app_msi_ack : out std_logic;
signal clk250_out : out std_logic;
signal clk500_out : out std_logic;
signal core_clk_out : out std_logic;
signal lane_act : out std_logic_vector (3 downto 0);
signal lmi_ack : out std_logic;
signal lmi_dout : out std_logic_vector (31 downto 0);
signal ltssm : out std_logic_vector (4 downto 0);
signal pme_to_sr : out std_logic;
signal powerdown_ext : out std_logic_vector (1 downto 0);
signal rate_ext : out std_logic;
signal rc_pll_locked : out std_logic;
signal rx_st_bardec0 : out std_logic_vector (7 downto 0);
signal rx_st_be0 : out std_logic_vector (7 downto 0);
signal rx_st_data0 : out std_logic_vector (63 downto 0);
signal rx_st_eop0 : out std_logic;
signal rx_st_err0 : out std_logic;
signal rx_st_sop0 : out std_logic;
signal rx_st_valid0 : out std_logic;
signal rxpolarity0_ext : out std_logic;
signal srstn : out std_logic;
signal test_out : out std_logic_vector (8 downto 0);
signal tl_cfg_add : out std_logic_vector (3 downto 0);
signal tl_cfg_ctl : out std_logic_vector (31 downto 0);
signal tl_cfg_ctl_wr : out std_logic;
signal tl_cfg_sts : out std_logic_vector (52 downto 0);
signal tl_cfg_sts_wr : out std_logic;
signal tx_cred0 : out std_logic_vector (35 downto 0);
signal tx_fifo_empty0 : out std_logic;
signal tx_out0 : out std_logic;
signal tx_st_ready0 : out std_logic;
signal txcompl0_ext : out std_logic;
signal txdata0_ext : out std_logic_vector (7 downto 0);
signal txdatak0_ext : out std_logic;
signal txdetectrx_ext : out std_logic;
signal txelecidle0_ext : OUT STD_LOGIC
);
end component Hard_IP_x1_plus;
component altpcierd_reconfig_clk_pll is
port (
signal inclk0 : in std_logic;
signal locked : out std_logic;
signal c0 : out std_logic;
signal c1 : out std_logic
);
end component altpcierd_reconfig_clk_pll;
--component z091_01_wb_adr_dec
-- generic(
-- NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
-- );
-- port (
-- pci_cyc_i : in std_logic_vector(6 downto 0);
-- wbm_adr_o_q : in std_logic_vector(31 downto 2);
--
-- wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
-- );
--end component;
component alt_reconf
port(
reconfig_clk : in std_logic;
reconfig_fromgxb : in std_logic_vector (4 downto 0);
busy : out std_logic;
reconfig_togxb : out std_logic_vector (3 downto 0)
);
end component;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
component pcie_msi
generic (
WIDTH : integer range 32 downto 1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
irq_req_i : in std_logic_vector(WIDTH -1 downto 0);
wb_int_o : out std_logic;
wb_pwr_enable_o : out std_logic;
wb_int_num_o : OUT std_logic_vector(4 downto 0);
wb_int_ack_i : in std_logic;
wb_int_num_allowed_i : in std_logic_vector(5 downto 0)
);
end component;
-------------------------------------------------------------------------------
begin
-- coverage off
assert not no_valid_device(supported_devices => SUPPORTED_DEVICES, device => FPGA_FAMILY) report "16z091-01: no valid FPGA device selected" severity failure;
-- coverage on
--wbm_cyc_o <= wbm_cyc_o_int;
npor_int <= ext_rst_n and '1';
pll_powerdown_int <= not npor_int;
--core_clk_int <= clk250_int;
ep_clk250_o <= clk250_int;
clk250_int_1delta_delay <= clk250_int;
clk250_int_2delta_delay <= clk250_int_1delta_delay;
clk250_int_3delta_delay <= clk250_int_2delta_delay;
----------------------------------
-- assign debug port if ltssm is
-- in link training mode
----------------------------------
link_train_active <= '0' when int_ltssm = "01111" else
'1';
ep_ltssm_o <= int_ltssm;
-- -------------------------------------------------
-- -- work around for Altera receiver detect issue
-- -------------------------------------------------
-- --pipe_mode_int <= '0'; -- use serial mode
-- test_in_int(39 downto 4) <= (others => '0');
-- test_in_int(3) <= not pipe_mode_int;
-- test_in_int(2 downto 1) <= (others => '0');
-- --------------------------------------------
-- -- speed up initialization for simulation:
-- --------------------------------------------
-- test_in_int(0) <= SIMULATION;
pipe_mode_int <= '1';
test_in_int(39 downto 10) <= (others => '0');
test_in_int(9) <= '1'; -- disable polling.compliance
test_in_int(8 downto 4) <= (others => '0');
test_in_int(3) <= not pipe_mode_int; -- forces all lanes to detect the receiver
test_in_int(2 downto 1) <= (others => '0');
test_in_int(0) <= '1'; -- speed up simulation by making counters faster than normal
-- instanciate components
ip_16z091_01_comp : ip_16z091_01
generic map(
FPGA_FAMILY => FPGA_FAMILY,
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
READY_LATENCY => 2,
FIFO_MAX_USEDW => conv_std_logic_vector((2**RX_LPM_WIDTHU - 8),10),
WBM_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 5),10),
WBM_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
WBS_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 4),10),
WBS_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
PCIE_REQUEST_LENGTH => PCIE_REQUEST_LENGTH,
RX_FIFO_DEPTH => 2**RX_LPM_WIDTHU,
RX_LPM_WIDTHU => RX_LPM_WIDTHU,
TX_HEADER_FIFO_DEPTH => 2**TX_HEADER_LPM_WIDTHU,
TX_HEADER_LPM_WIDTHU => TX_HEADER_LPM_WIDTHU,
TX_DATA_FIFO_DEPTH => 2**TX_DATA_LPM_WIDTHU,
TX_DATA_LPM_WIDTHU => TX_DATA_LPM_WIDTHU
)
port map(
clk => core_clk_int,
rst => srst_int, --rst_int,
clk_500 => clk_500,
wb_clk => wb_clk,
wb_rst => wb_rst,
-- IP Core
core_clk => core_clk_int,
rx_st_data0 => rx_st_data0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_valid0 => rx_st_valid0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_bardec0 => rx_st_bardec0_int,
tx_st_ready0 => tx_st_ready0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
pme_to_sr => pme_to_sr_int,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_valid0 => tx_st_valid0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_data0 => tx_st_data0_int,
pme_to_cr => pme_to_cr_int,
app_int_sts => app_int_sts_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
app_msi_num => app_msi_num_int,
pex_msi_num => pex_msi_num_int,
derr_cor_ext_rcv => derr_cor_ext_rcv_int,
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
r2c_err0 => r2c_err0_int,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
-- Wishbone master
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
--wbm_cyc => OPEN,
wbm_cyc_o => wbm_cyc_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
--wb_bar_dec => int_bar_hit,
-- Wishbone slave
wbs_cyc => wbs_cyc,
wbs_stb => wbs_stb,
wbs_we => wbs_we,
wbs_sel => wbs_sel,
wbs_adr => wbs_adr,
wbs_dat_i => wbs_dat_i,
wbs_cti => wbs_cti,
wbs_tga => wbs_tga,
wbs_ack => wbs_ack,
wbs_err => wbs_err,
wbs_dat_o => wbs_dat_o,
-- interrupt
wb_int => int_wb_int,
wb_pwr_enable => int_wb_pwr_enable,
wb_int_num => int_wb_int_num,
wb_int_ack => int_wb_int_ack,
wb_int_num_allowed => int_wb_int_num_allowed,
-- error
error_timeout => error_timeout,
error_cor_ext_rcv => error_cor_ext_rcv,
error_cor_ext_rpl => error_cor_ext_rpl,
error_rpl => error_rpl,
error_r2c0 => error_r2c0,
error_msi_num => error_msi_num,
-- debug port
rx_debug_out => open
);
-- gen_x4: if USE_LANES = "100" generate
-- Hard_IP_x4_comp : entity work.Hard_IP_x4
-- port map(
-- -- inputs:
-- app_int_sts => app_int_sts_int,
-- app_msi_num => app_msi_num_int,
-- app_msi_req => app_msi_req_int,
-- app_msi_tc => app_msi_tc_int,
-- busy_altgxb_reconfig => reconf_busy,
-- cal_blk_clk => clk_50,
-- cpl_err => cpl_err_int,
-- cpl_pending => cpl_pending_int,
-- crst => crst_int,
-- fixedclk_serdes => clk_125,
-- gxb_powerdown => '0',
-- hpg_ctrler => (others => '0'),
-- lmi_addr => (others => '0'),
-- lmi_din => (others => '0'),
-- lmi_rden => '0',
-- lmi_wren => '0',
-- npor => npor_int,
-- pclk_in => core_clk_int,
-- pex_msi_num => pex_msi_num_int,
-- phystatus_ext => ep_phystatus_i(0),
-- pipe_mode => pipe_mode_int,
-- pld_clk => core_clk_int,
-- pll_powerdown => pll_powerdown_int,
-- pm_auxpwr => '0',
-- pm_data => (others => '0'),
-- pm_event => '0',
-- pme_to_cr => pme_to_cr_int,
-- reconfig_clk => clk_50,
-- reconfig_togxb => reconfig_togxb_int,
-- refclk => ref_clk,
-- rx_in0 => rx_0,
-- rx_in1 => rx_1,
-- rx_in2 => rx_2,
-- rx_in3 => rx_3,
-- rx_st_mask0 => rx_st_mask0_int,
-- rx_st_ready0 => rx_st_ready0_int,
-- rxdata0_ext => ep_rxdata_i(7 downto 0),
-- rxdata1_ext => ep_rxdata_i(15 downto 8),
-- rxdata2_ext => ep_rxdata_i(23 downto 16),
-- rxdata3_ext => ep_rxdata_i(31 downto 24),
-- rxdatak0_ext => ep_rxdatak_i(0),
-- rxdatak1_ext => ep_rxdatak_i(1),
-- rxdatak2_ext => ep_rxdatak_i(2),
-- rxdatak3_ext => ep_rxdatak_i(3),
-- rxelecidle0_ext => ep_rxelecidle_i(0),
-- rxelecidle1_ext => ep_rxelecidle_i(1),
-- rxelecidle2_ext => ep_rxelecidle_i(2),
-- rxelecidle3_ext => ep_rxelecidle_i(3),
-- rxstatus0_ext => ep_rxstatus_i(2 downto 0),
-- rxstatus1_ext => ep_rxstatus_i(5 downto 3),
-- rxstatus2_ext => ep_rxstatus_i(8 downto 6),
-- rxstatus3_ext => ep_rxstatus_i(11 downto 9),
-- rxvalid0_ext => ep_rxvalid_i(0),
-- rxvalid1_ext => ep_rxvalid_i(1),
-- rxvalid2_ext => ep_rxvalid_i(2),
-- rxvalid3_ext => ep_rxvalid_i(3),
-- srst => srst_int,
-- test_in => test_in_int,
-- tx_st_data0 => tx_st_data0_int,
-- tx_st_eop0 => tx_st_eop0_int,
-- tx_st_err0 => tx_st_err0_int,
-- tx_st_sop0 => tx_st_sop0_int,
-- tx_st_valid0 => tx_st_valid0_int,
--
-- -- outputs:
-- app_int_ack => app_int_ack_int,
-- app_msi_ack => app_msi_ack_int,
-- clk250_out => ep_clk250_o,
-- clk500_out => ep_clk500_o,
-- core_clk_out => core_clk_int,
-- derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
-- derr_cor_ext_rpl => derr_cor_ext_rpl_int,
-- derr_rpl => derr_rpl_int,
-- dlup_exit => dlup_exit,
-- hotrst_exit => hotrst_exit,
-- ko_cpl_spc_vc0 => open,
-- l2_exit => l2_exit,
-- lane_act => open,
-- lmi_ack => open,
-- lmi_dout => open,
-- ltssm => int_ltssm,
-- pme_to_sr => pme_to_sr_int,
-- powerdown_ext => powerdown_int, --ep_powerdown_ext_o,
-- r2c_err0 => r2c_err0_int,
-- rate_ext => ep_rate_ext_o,
-- rc_pll_locked => open,
-- reconfig_fromgxb => reconfig_fromgxb_int,
-- reset_status => open,
-- rx_fifo_empty0 => open,
-- rx_fifo_full0 => open,
-- rx_st_bardec0 => rx_st_bardec0_int,
-- rx_st_be0 => rx_st_be0_int,
-- rx_st_data0 => rx_st_data0_int,
-- rx_st_eop0 => rx_st_eop0_int,
-- rx_st_err0 => rx_st_err0_int,
-- rx_st_sop0 => rx_st_sop0_int,
-- rx_st_valid0 => rx_st_valid0_int,
-- rxpolarity0_ext => ep_rxpolarity_o(0),
-- rxpolarity1_ext => ep_rxpolarity_o(1),
-- rxpolarity2_ext => ep_rxpolarity_o(2),
-- rxpolarity3_ext => ep_rxpolarity_o(3),
-- suc_spd_neg => open,
-- test_out => open,
-- tl_cfg_add => tl_cfg_add_int,
-- tl_cfg_ctl => tl_cfg_ctl_int,
-- tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
-- tl_cfg_sts => tl_cfg_sts_int,
-- tl_cfg_sts_wr => tl_cfg_sts_wr_int,
-- tx_cred0 => open,
-- tx_fifo_empty0 => tx_fifo_empty0_int,
-- tx_fifo_full0 => tx_fifo_full0_int,
-- tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
-- tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
-- tx_out0 => tx_0,
-- tx_out1 => tx_1,
-- tx_out2 => tx_2,
-- tx_out3 => tx_3,
-- tx_st_ready0 => tx_st_ready0_int,
-- txcompl0_ext => ep_txcompl_o(0),
-- txcompl1_ext => ep_txcompl_o(1),
-- txcompl2_ext => ep_txcompl_o(2),
-- txcompl3_ext => ep_txcompl_o(3),
-- txdata0_ext => ep_txdata_o(7 downto 0),
-- txdata1_ext => ep_txdata_o(15 downto 8),
-- txdata2_ext => ep_txdata_o(23 downto 16),
-- txdata3_ext => ep_txdata_o(31 downto 24),
-- txdatak0_ext => ep_txdatak_o(0),
-- txdatak1_ext => ep_txdatak_o(1),
-- txdatak2_ext => ep_txdatak_o(2),
-- txdatak3_ext => ep_txdatak_o(3),
-- txdetectrx_ext => txdetectrx_int, --ep_txdetectrx_o(0),
-- txelecidle0_ext => ep_txelecidle_o(0),
-- txelecidle1_ext => ep_txelecidle_o(1),
-- txelecidle2_ext => ep_txelecidle_o(2),
-- txelecidle3_ext => ep_txelecidle_o(3)
-- );
--
-----------------------------------------------------------------------
-- Hard IP has only one bit for txdetectrx and 2 bits for powerdown
-- thus map these to the other ports
-----------------------------------------------------------------------
-- ep_txdetectrx_o(0) <= txdetectrx_int;
-- ep_txdetectrx_o(1) <= txdetectrx_int;
-- ep_txdetectrx_o(2) <= txdetectrx_int;
-- ep_txdetectrx_o(3) <= txdetectrx_int;
-- ep_powerdown_ext_o(1 downto 0) <= powerdown_int;
-- ep_powerdown_ext_o(3 downto 2) <= powerdown_int;
-- ep_powerdown_ext_o(5 downto 4) <= powerdown_int;
-- ep_powerdown_ext_o(7 downto 6) <= powerdown_int;
-- end generate gen_x4;
-- gen_x2: if USE_LANES = "010" generate
-- Hard_IP_x2_comp : entity work.Hard_IP_x2
-- generic map(
-- VENDOR_ID => VENDOR_ID,
-- DEVICE_ID => DEVICE_ID,
-- REVISION_ID => REVISION_ID,
-- CLASS_CODE => CLASS_CODE,
-- SUBSYSTEM_VENDOR_ID => SUBSYSTEM_VENDOR_ID,
-- SUBSYSTEM_DEVICE_ID => SUBSYSTEM_DEVICE_ID,
--
-- IO_SPACE_BAR_0 => IO_SPACE_0, -- IO_SPACE_BAR_0,
-- PREFETCH_BAR_0 => PREFETCH_0, -- PREFETCH_BAR_0,
-- SIZE_MASK_BAR_0 => SIZE_MASK_0, -- SIZE_MASK_BAR_0,
--
-- IO_SPACE_BAR_1 => IO_SPACE_1, -- IO_SPACE_BAR_1,
-- PREFETCH_BAR_1 => PREFETCH_1, -- PREFETCH_BAR_1,
-- SIZE_MASK_BAR_1 => SIZE_MASK_1, -- SIZE_MASK_BAR_1,
--
-- IO_SPACE_BAR_2 => IO_SPACE_2, -- IO_SPACE_BAR_2,
-- PREFETCH_BAR_2 => PREFETCH_2, -- PREFETCH_BAR_2,
-- SIZE_MASK_BAR_2 => SIZE_MASK_2, -- SIZE_MASK_BAR_2,
--
-- IO_SPACE_BAR_3 => IO_SPACE_3, -- IO_SPACE_BAR_3,
-- PREFETCH_BAR_3 => PREFETCH_3, -- PREFETCH_BAR_3,
-- SIZE_MASK_BAR_3 => SIZE_MASK_3, -- SIZE_MASK_BAR_3,
--
-- IO_SPACE_BAR_4 => IO_SPACE_4, -- IO_SPACE_BAR_4,
-- PREFETCH_BAR_4 => PREFETCH_4, -- PREFETCH_BAR_4,
-- SIZE_MASK_BAR_4 => SIZE_MASK_4, -- SIZE_MASK_BAR_4,
--
-- IO_SPACE_BAR_5 => IO_SPACE_5, -- IO_SPACE_BAR_5,
-- PREFETCH_BAR_5 => PREFETCH_5, -- PREFETCH_BAR_5,
-- SIZE_MASK_BAR_5 => SIZE_MASK_5 -- SIZE_MASK_BAR_5
-- )
-- port map(
-- -- inputs:
-- app_int_sts => app_int_sts_int,
-- app_msi_num => app_msi_num_int,
-- app_msi_req => app_msi_req_int,
-- app_msi_tc => app_msi_tc_int,
-- cal_blk_clk => clk_50,
-- cpl_err => cpl_err_int,
-- cpl_pending => cpl_pending_int,
-- crst => crst_int,
-- gxb_powerdown => '0',
-- hpg_ctrler => (others => '0'),
-- lmi_addr => (others => '0'),
-- lmi_din => (others => '0'),
-- lmi_rden => '0',
-- lmi_wren => '0',
-- npor => '1', --ext_rst_n, --'0',
-- pclk_in => core_clk_int,
-- pex_msi_num => pex_msi_num_int,
-- phystatus_ext => '0',
-- pipe_mode => '0',
-- pld_clk => core_clk_int,
-- pll_powerdown => '0',
-- pm_auxpwr => '0',
-- pm_data => (others => '0'),
-- pm_event => '0',
-- pme_to_cr => pme_to_cr_int,
-- reconfig_clk => clk_50,
-- reconfig_togxb => reconfig_togxb_int,
-- refclk => ref_clk,
-- rx_in0 => rx_0,
-- rx_in1 => rx_1,
-- rx_st_mask0 => rx_st_mask0_int,
-- rx_st_ready0 => rx_st_ready0_int,
-- rxdata0_ext => (others => '0'),
-- rxdata1_ext => (others => '0'),
-- rxdatak0_ext => '0',
-- rxdatak1_ext => '0',
-- rxelecidle0_ext => '0',
-- rxelecidle1_ext => '0',
-- rxstatus0_ext => (others => '0'),
-- rxstatus1_ext => (others => '0'),
-- rxvalid0_ext => '0',
-- rxvalid1_ext => '0',
-- srst => srst_int,
-- test_in => (others => '0'),
-- tx_st_data0 => tx_st_data0_int,
-- tx_st_eop0 => tx_st_eop0_int,
-- tx_st_err0 => tx_st_err0_int,
-- tx_st_sop0 => tx_st_sop0_int,
-- tx_st_valid0 => tx_st_valid0_int,
--
-- -- outputs:
-- app_int_ack => app_int_ack_int,
-- app_msi_ack => app_msi_ack_int,
-- clk250_out => open,
-- clk500_out => open,
-- core_clk_out => core_clk_int,
-- derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
-- derr_cor_ext_rpl => derr_cor_ext_rpl_int,
-- derr_rpl => derr_rpl_int,
-- dlup_exit => open,
-- hotrst_exit => open,
-- ko_cpl_spc_vc0 => open,
-- l2_exit => open,
-- lane_act => open,
-- lmi_ack => open,
-- lmi_dout => open,
-- ltssm => open,
-- pme_to_sr => pme_to_sr_int,
-- powerdown_ext => open,
-- r2c_err0 => r2c_err0_int,
-- rate_ext => open,
-- rc_pll_locked => open,
-- reconfig_fromgxb => reconfig_fromgxb_int,
-- reset_status => open,
-- rx_fifo_empty0 => open,
-- rx_fifo_full0 => open,
-- rx_st_bardec0 => rx_st_bardec0_int,
-- rx_st_be0 => rx_st_be0_int,
-- rx_st_data0 => rx_st_data0_int,
-- rx_st_eop0 => rx_st_eop0_int,
-- rx_st_err0 => rx_st_err0_int,
-- rx_st_sop0 => rx_st_sop0_int,
-- rx_st_valid0 => rx_st_valid0_int,
-- rxpolarity0_ext => open,
-- rxpolarity1_ext => open,
-- suc_spd_neg => open,
-- test_out => open,
-- tl_cfg_add => tl_cfg_add_int,
-- tl_cfg_ctl => tl_cfg_ctl_int,
-- tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
-- tl_cfg_sts => tl_cfg_sts_int,
-- tl_cfg_sts_wr => tl_cfg_sts_wr_int,
-- tx_cred0 => open,
-- tx_fifo_empty0 => tx_fifo_empty0_int,
-- tx_fifo_full0 => tx_fifo_full0_int,
-- tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
-- tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
-- tx_out0 => tx_0,
-- tx_out1 => tx_1,
-- tx_st_ready0 => tx_st_ready0_int,
-- txcompl0_ext => open,
-- txcompl1_ext => open,
-- txdata0_ext => open,
-- txdata1_ext => open,
-- txdatak0_ext => open,
-- txdatak1_ext => open,
-- txdetectrx_ext => open,
-- txelecidle0_ext => open,
-- txelecidle1_ext => open
-- );
-- tx_2 <= '1';
-- tx_3 <= '1';
-- end generate gen_x2;
gen_x1: if USE_LANES = "001" generate
Hard_IP_x1_comp : Hard_IP_x1_plus
port map(
app_int_sts => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
--busy_altgxb_reconfig => reconf_busy,
--cal_blk_clk => clk_50,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
--crst => crst_int,
fixedclk_serdes => clk_125, --fixedclk_serdes_int, --clk_125,
--gxb_powerdown => '0',
--hpg_ctrler => (others => '0'),
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
local_rstn => '1',
--npor => npor_int,
pcie_rstn => ext_rst_n,
pclk_in => clk250_int, --clk250_int_3delta_delay, --clk250_int, --core_clk_int,
pex_msi_num => pex_msi_num_int,
phystatus_ext => ep_phystatus_i(0),
pipe_mode => pipe_mode_int,
pld_clk => core_clk_int,
--pll_powerdown => pll_powerdown_int,
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_clk => reconfig_clk_int, --clk_50,
reconfig_clk_locked => reconfig_clk_locked_int,
--reconfig_togxb => reconfig_togxb_int,
refclk => ref_clk,
rx_in0 => rx_0,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
rxdata0_ext => ep_rxdata_i(7 downto 0),
rxdatak0_ext => ep_rxdatak_i(0),
rxelecidle0_ext => ep_rxelecidle_i(0),
rxstatus0_ext => ep_rxstatus_i(2 downto 0),
rxvalid0_ext => ep_rxvalid_i(0),
--srst => srst_int,
test_in => test_in_int,
tx_st_data0 => tx_st_data0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_valid0 => tx_st_valid0_int,
-- outputs:
app_clk => open,
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
clk250_out => clk250_int, --ep_clk250_o,
clk500_out => ep_clk500_o,
core_clk_out => core_clk_int,
--derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
--derr_cor_ext_rpl => derr_cor_ext_rpl_int,
--derr_rpl => derr_rpl_int,
--dlup_exit => dlup_exit,
--hotrst_exit => hotrst_exit,
--ko_cpl_spc_vc0 => open,
--l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
ltssm => int_ltssm,
pme_to_sr => pme_to_sr_int,
powerdown_ext => powerdown_int, --ep_powerdown_ext_o(1 downto 0),
--r2c_err0 => r2c_err0_int,
rate_ext => ep_rate_ext_o,
rc_pll_locked => open,
--rc_rx_digitalreset => open,
--reconfig_fromgxb => reconfig_fromgxb_int,
--reset_status => open,
--rx_fifo_empty0 => open,
--rx_fifo_full0 => open,
rx_st_bardec0 => rx_st_bardec0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_data0 => rx_st_data0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_valid0 => rx_st_valid0_int,
rxpolarity0_ext => ep_rxpolarity_o(0),
srstn => srstn_int,
--suc_spd_neg => open,
test_out => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred0 => open,
tx_fifo_empty0 => tx_fifo_empty0_int,
--tx_fifo_full0 => tx_fifo_full0_int,
--tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
--tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
tx_out0 => tx_0,
tx_st_ready0 => tx_st_ready0_int,
txcompl0_ext => ep_txcompl_o(0),
txdata0_ext => ep_txdata_o(7 downto 0),
txdatak0_ext => ep_txdatak_o(0),
txdetectrx_ext => txdetectrx_int, --ep_txdetectrx_o(0),
txelecidle0_ext => ep_txelecidle_o(0)
);
ep_txdetectrx_o(0) <= txdetectrx_int;
ep_powerdown_ext_o(1 downto 0) <= powerdown_int;
-- manage removed signals
tx_fifo_full0_int <= '0';
tx_fifo_rdptr0_int <= (others => '0');
tx_fifo_wrptr0_int <= (others => '0');
r2c_err0_int <= '0';
derr_cor_ext_rcv_int(0) <= '0';
derr_cor_ext_rpl_int <= '0';
derr_rpl_int <= '0';
dlup_exit <= '0';
hotrst_exit <= '0';
l2_exit <= '0';
tx_1 <= '1';
tx_2 <= '1';
tx_3 <= '1';
end generate gen_x1;
reconfig_pll : altpcierd_reconfig_clk_pll
port map(
inclk0 => ref_clk,
locked => reconfig_clk_locked_int,
c0 => reconfig_clk_int,
c1 => fixedclk_serdes_int
);
--z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
-- generic map(
-- NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
-- )
-- port map(
-- pci_cyc_i => int_bar_hit,
-- wbm_adr_o_q => wbm_adr_int(31 downto 2),
--
-- wbm_cyc_o => wbm_cyc_o_int
-- );
--mwawrik: this process is responsible for the problem, that the cycle is longer active than acknowledge
--cyc_o : process(wb_rst, wb_clk)
--begin
-- if wb_rst = '1' then
-- wbm_cyc_o_int_d <= (others => '0');
-- elsif wb_clk'event and wb_clk = '1' then
-- if wbm_ack = '1' then
-- wbm_cyc_o_int_d <= (others=>'0');
-- else
-- wbm_cyc_o_int_d <= wbm_cyc_o_int;
-- end if;
-- end if;
--end process cyc_o;
------------------------------------------------------------------------------
alt_reconf_comp : alt_reconf
port map(
reconfig_clk => clk_50,
reconfig_fromgxb => reconfig_fromgxb_int,
busy => reconf_busy,
reconfig_togxb => reconfig_togxb_int
);
gen_srst_crst_for_cold_warm_hot: process(rst_int,core_clk_int)
begin
if(rst_int = '1') then -- deactivate rst_cwh during ext_rst
rst_cwh <= '0';
rst_cwh_cnt <= (others => '0');
elsif(core_clk_int'event and core_clk_int = '1') then
if(l2_exit = '0' or hotrst_exit = '0' or dlup_exit = '0') then -- start reset
rst_cwh_cnt <= (others => '1');
elsif(rst_cwh_cnt > 0) then -- count condition
rst_cwh_cnt <= rst_cwh_cnt - 1;
else -- stop condition
rst_cwh_cnt <= (others => '0');
end if;
if(rst_cwh_cnt = 0) then -- reset if cnt > 0
rst_cwh <= '0';
else
rst_cwh <= '1';
end if;
end if;
end process;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
pcie_msi_i0 : pcie_msi
generic map(
WIDTH => IRQ_WIDTH
)
port map(
clk_i => wb_clk,
rst_i => wb_rst,
irq_req_i => irq_req_i,
wb_int_o => int_wb_int,
wb_pwr_enable_o => int_wb_pwr_enable,
wb_int_num_o => int_wb_int_num,
wb_int_ack_i => int_wb_int_ack,
wb_int_num_allowed_i => int_wb_int_num_allowed
);
-------------------------------------------------------------------------------
-- port assignement
--wbm_adr <= wbm_adr_int;
-- reset and clock logic
rst_int <= not ext_rst_n;
crst_int <= rst_int or rst_cwh;
--srst_int <= rst_int or rst_cwh;
srst_int <= not srstn_int;
-------------------------------------------------------------------------------
end architecture ip_16z091_01_top_arch;
mt58l512l18f.vhd 0000664 0000000 0000000 00000027666 14574545710 0034766 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-License-Identifier: CERN-OHL-S-2.0+
-------------------------------------------------------------------------------
--
-- File Name: MT58L512L18F.VHD
-- Revision: 2.0
-- Date: April 3rd, 2002
-- Model: Bus Functional
-- Simulator: Aldec, ModemSim, NCDesktop
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: sphuynh@micron.com
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part #: MT58L512L18F
--
-- Description: Micron 8 Meg SyncBurst SRAM (Flow-through)
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1997 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- --- -------------- ------------ ---------- -----------------------------
-- 2.0 Son P. Huynh 208-368-3825 04/03/2002 - Fix Burst counter
-- Micron Technology, Inc.
--
-------------------------------------------------------------------------------
LIBRARY ieee, std, work;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.standard.ALL;
USE std.textio.all;
ENTITY MT58L512L18F IS
GENERIC (
-- Clock
tKC : TIME := 8.0 ns; -- Timing are for -6.8
tKH : TIME := 1.8 ns;
tKL : TIME := 1.8 ns;
-- Output Times
tKQHZ : TIME := 3.8 ns;
-- Setup Times
tAS : TIME := 1.8 ns;
tADSS : TIME := 1.8 ns;
tAAS : TIME := 1.8 ns;
tWS : TIME := 1.8 ns;
tDS : TIME := 1.8 ns;
tCES : TIME := 1.8 ns;
-- Hold Times
tAH : TIME := 0.5 ns;
tADSH : TIME := 0.5 ns;
tAAH : TIME := 0.5 ns;
tWH : TIME := 0.5 ns;
tDH : TIME := 0.5 ns;
tCEH : TIME := 0.5 ns;
-- Bus Width and Data Bus
addr_bits : INTEGER := 19;
data_bits : INTEGER := 16
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Mode : IN STD_LOGIC;
Adv_n : IN STD_LOGIC;
Clk : IN STD_LOGIC;
Adsc_n : IN STD_LOGIC;
Adsp_n : IN STD_LOGIC;
Bwa_n : IN STD_LOGIC;
Bwb_n : IN STD_LOGIC;
Bwe_n : IN STD_LOGIC;
Gw_n : IN STD_LOGIC;
Ce_n : IN STD_LOGIC;
Ce2 : IN STD_LOGIC;
Ce2_n : IN STD_LOGIC;
Oe_n : IN STD_LOGIC;
Zz : IN STD_LOGIC
);
END MT58L512L18F;
ARCHITECTURE behave OF MT58L512L18F IS
TYPE memory IS ARRAY (2 ** addr_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits / 2 - 1 DOWNTO 0);
SIGNAL doe : STD_LOGIC;
SIGNAL dout : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
SIGNAL bwan, bwbn, ce, clr : STD_LOGIC;
--FILE outfile: TEXT IS OUT "sram_outfile.txt";
BEGIN
bwan <= ((Bwa_n OR Bwe_n) AND Gw_n) OR (NOT(Ce_n) AND NOT(Adsp_n));
bwbn <= ((Bwb_n OR Bwe_n) AND Gw_n) OR (NOT(Ce_n) AND NOT(Adsp_n));
ce <= NOT(Ce_n) AND Ce2 AND NOT(Ce2_n);
clr <= NOT(Adsc_n) OR (NOT(Adsp_n) AND NOT(Ce_n));
main : PROCESS
-- Memory Array
VARIABLE bank0, bank1 : memory;
-- Address Registers
VARIABLE addr_reg_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE addr_reg_out : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-- Burst Counter
VARIABLE bcount : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE baddr0 : STD_LOGIC;
VARIABLE baddr1 : STD_LOGIC;
-- Other Registers
VARIABLE din : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
VARIABLE ce_reg : STD_LOGIC;
VARIABLE bwa_reg : STD_LOGIC;
VARIABLE bwb_reg : STD_LOGIC;
VARIABLE write_line : line;
VARIABLE i,j : integer;
VARIABLE dat : STD_LOGIC_VECTOR (data_bits*2 - 1 DOWNTO 0);
BEGIN
i := 0;
j := 0;
LOOP
dat := conv_std_logic_vector(j,data_bits*2);
bank0(i) := dat(data_bits/2 -1 DOWNTO 0);
bank1(i) := dat(data_bits-1 DOWNTO data_bits/2);
bank0(i+1) := dat(3*data_bits/2 -1 DOWNTO data_bits);
bank1(i+1) := dat(2*data_bits-1 DOWNTO 3*data_bits/2);
i := i + 2;
j := j + 1;
IF i = 2 ** addr_bits THEN
exit;
END IF;
END LOOP;
LOOP
WAIT ON Clk;
IF Clk'EVENT AND Clk = '1' AND Zz = '0' THEN
-- Address Register
IF clr = '1' THEN
addr_reg_in := Addr;
END IF;
-- Binary Counter and Logic
IF Mode = '1' AND clr = '1' THEN
bcount := "00";
ELSIF Mode = '0' AND clr = '1' THEN
bcount := Addr(1 DOWNTO 0);
ELSIF Adv_n = '0' AND clr = '0' THEN
bcount(1) := bcount(0) XOR bcount(1);
bcount(0) := NOT(bcount(0));
END IF;
-- Burst Address Decode
IF Mode = '1' THEN
baddr0 := bcount(0) XOR addr_reg_in(0);
baddr1 := bcount(1) XOR addr_reg_in(1);
ELSE
baddr0 := bcount(0);
baddr1 := bcount(1);
END IF;
-- Output Address
addr_reg_out (addr_bits - 1 DOWNTO 2) := addr_reg_in (addr_bits - 1 DOWNTO 2);
addr_reg_out (1) := baddr1;
addr_reg_out (0) := baddr0;
-- Byte Write Register
bwa_reg := NOT(bwan);
bwb_reg := NOT(bwbn);
-- Enable Register
IF clr = '1' THEN
ce_reg := ce;
END IF;
-- Input Register
IF (ce_reg = '1' AND (bwa_reg = '1' OR bwb_reg = '1')) THEN
din := Dq;
ELSE
din := (OTHERS => 'Z');
END IF;
-- Byte Write Driver
IF ce_reg = '1' AND bwa_reg = '1' THEN
bank0 (CONV_INTEGER(addr_reg_out)) := din ( 7 DOWNTO 0);
-- WRITE(write_line, 'W');
-- WRITE(write_line, 'L');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(din(7 DOWNTO 0)));
-- WRITELINE(outfile, write_line);
END IF;
IF ce_reg = '1' AND bwb_reg = '1' THEN
bank1 (CONV_INTEGER(addr_reg_out)) := din (15 DOWNTO 8);
-- WRITE(write_line, 'W');
-- WRITE(write_line, 'H');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(din(15 DOWNTO 8)));
-- WRITELINE(outfile, write_line);
END IF;
-- Output Register
IF (NOT(bwa_reg = '1' OR bwb_reg = '1')) THEN
dout ( 7 DOWNTO 0) <= bank0 (CONV_INTEGER(addr_reg_out));
dout (15 DOWNTO 8) <= bank1 (CONV_INTEGER(addr_reg_out));
-- WRITE(write_line, 'R');
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(addr_reg_out));
-- WRITE(write_line, ' ');
-- WRITE(write_line, TO_HEX_STRING(bank1 (CONV_INTEGER(addr_reg_out))));
-- WRITE(write_line, TO_HEX_STRING(bank0 (CONV_INTEGER(addr_reg_out))));
-- WRITELINE(outfile, write_line);
END IF;
-- Data Out Enable
doe <= ce_reg AND (NOT(bwa_reg OR bwb_reg));
END IF;
END LOOP;
END PROCESS main;
-- Output buffer
WITH (NOT(Oe_n) AND NOT(Zz) AND doe) SELECT
Dq <= TRANSPORT dout AFTER tKQHZ WHEN '1',
(OTHERS => 'Z') AFTER tKQHZ WHEN '0',
(OTHERS => 'Z') AFTER tKQHZ WHEN OTHERS;
-- Checking for setup time violation
Setup_check : PROCESS
BEGIN
WAIT ON Clk;
IF Clk'EVENT AND Clk = '1' THEN
ASSERT(Addr'LAST_EVENT >= tAS)
REPORT "Addr Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Adsc_n'LAST_EVENT >= tADSS)
REPORT "Adsc_n Setup time violation -- tADSS"
SEVERITY WARNING;
ASSERT(Adsp_n'LAST_EVENT >= tADSS)
REPORT "Adsp_n Setup time violation -- tADSS"
SEVERITY WARNING;
ASSERT(Adv_n'LAST_EVENT >= tAAS)
REPORT "Adv_n Setup time violation -- tAAS"
SEVERITY WARNING;
ASSERT(Bwa_n'LAST_EVENT >= tWS)
REPORT "Bwa_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Bwb_n'LAST_EVENT >= tWS)
REPORT "Bwb_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Bwe_n'LAST_EVENT >= tWS)
REPORT "Bwe_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Gw_n'LAST_EVENT >= tWS)
REPORT "Gw_n Setup time violation -- tWS"
SEVERITY WARNING;
ASSERT(Ce_n'LAST_EVENT >= tCES)
REPORT "Ce_n Setup time violation -- tCES"
SEVERITY WARNING;
ASSERT(Ce2_n'LAST_EVENT >= tCES)
REPORT "Ce2_n Setup time violation -- tCES"
SEVERITY WARNING;
ASSERT(Ce2'LAST_EVENT >= tCES)
REPORT "Ce2 Setup time violation -- tCES"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Checking for hold time violation
Hold_check : PROCESS
BEGIN
WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tADSH), Clk'DELAYED(tAAH), Clk'DELAYED(tWH), Clk'DELAYED(tCEH);
IF Clk'DELAYED(tAH)'EVENT AND Clk'DELAYED(tAH) = '1' THEN
ASSERT(Addr'LAST_EVENT > tAH)
REPORT "Addr Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tADSH)'EVENT AND Clk'DELAYED(tADSH) = '1' THEN
ASSERT(Adsc_n'LAST_EVENT > tADSH)
REPORT "Adsc_n Hold time violation -- tADSH"
SEVERITY WARNING;
ASSERT(Adsp_n'LAST_EVENT > tADSH)
REPORT "Adsp_n Hold time violation -- tADSH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tAAH)'EVENT AND Clk'DELAYED(tAAH) = '1' THEN
ASSERT(Adv_n'LAST_EVENT > tAAH)
REPORT "Adv_n Hold time violation -- tAAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tWH)'EVENT AND Clk'DELAYED(tWH) = '1' THEN
ASSERT(Bwa_n'LAST_EVENT > tWH)
REPORT "Bwa_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Bwb_n'LAST_EVENT > tWH)
REPORT "Bwb_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Bwe_n'LAST_EVENT > tWH)
REPORT "Bwe_n Hold time violation -- tWH"
SEVERITY WARNING;
ASSERT(Gw_n'LAST_EVENT > tWH)
REPORT "Gw_n Hold time violation -- tWH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED(tCEH)'EVENT AND Clk'DELAYED(tCEH) = '1' THEN
ASSERT(Ce_n'LAST_EVENT > tCEH)
REPORT "Ce_n Hold time violation -- tCEH"
SEVERITY WARNING;
ASSERT(Ce2_n'LAST_EVENT > tCEH)
REPORT "Ce2_n Hold time violation -- tCEH"
SEVERITY WARNING;
ASSERT(Ce2'LAST_EVENT > tCEH)
REPORT "Ce2 Hold time violation -- tCEH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
terminal.vhd 0000664 0000000 0000000 00000024171 14574545710 0034671 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Simulation Terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 10/11/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Application Layer for simulation stimuli
---------------------------------------------------------------
-- Hierarchy:
--
-- testbench
-- terminal
-- wb_test
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: terminal.vhd,v $
-- Revision 1.3 2013/07/15 13:14:20 mmiehling
-- adopted testcases
--
-- Revision 1.2 2013/04/18 15:11:08 MMiehling
-- support of pcie model
--
-- Revision 1.1 2012/03/29 10:28:43 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/03/15 14:21:54 mmiehling
-- extended tga
-- removed "use work.vme_pkg.all"
--
-- Revision 1.1 2005/08/23 15:21:05 MMiehling
-- Initial Revision
--
-- Revision 1.3 2005/03/18 15:14:18 MMiehling
-- changed
--
-- Revision 1.2 2005/01/31 16:28:56 mmiehling
-- updated
--
-- Revision 1.1 2004/11/16 12:09:06 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.print_pkg.all;
USE work.terminal_pkg.ALL;
USE work.vme_sim_pack.all;
USE work.pcie_sim_pkg.ALL;
LIBRARY modelsim_lib;
USE modelsim_lib.util.all;
USE std.textio.all;
library std;
use std.env.all;
ENTITY terminal IS
PORT (
hreset_n : OUT std_logic;
slot1 : OUT boolean:=TRUE; -- if true dut is in slot1
en_clk : OUT boolean:=TRUE; -- if true dut is supplied with 16 mhz clk
terminal_in_0 : IN terminal_in_type; -- PCIe Master Model
terminal_out_0 : OUT terminal_out_type;
terminal_in_1 : IN terminal_in_type; -- VMEbus Master Model
terminal_out_1 : OUT terminal_out_type;
vme_slv_in : OUT vme_slv_in_type;
vme_slv_out : IN vme_slv_out_type;
vme_mon_out : IN vme_mon_out_type;
v2p_rstn : IN std_logic; -- connected to hreset_req1_n
vme_ga : OUT std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : OUT std_logic -- geographical addresses
);
END terminal;
ARCHITECTURE terminal_arch OF terminal IS
SIGNAL terminal_err_0 : integer:=0;
SIGNAL end_of_tests : boolean;
SIGNAL vb_sysresn : std_logic;
SIGNAL irq_req : std_logic_vector(16 DOWNTO 0);
CONSTANT en_msg_0 : integer:= 2;
BEGIN
term_0: PROCESS
VARIABLE err : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
hreset_n <= '0';
en_clk <= TRUE;
vme_ga <= (OTHERS => '0');
vme_gap <= '0';
--init_signal_spy("/a25_tb/a25/pcie/irq_req","irq_req",1,1);
init_signal_spy("/a25_tb/vb_sysresn","vb_sysresn",1,1);
init(terminal_out_0);
init(terminal_out_1);
init_vme_slv(vme_slv_in);
-- powerup board
-- shorten reset time on vme bus
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/pre_cnt_max_sig", "0000001000", 0 ns, freeze, -1 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/main_cnt_max_sig", "000000000000011", 0 ns, freeze, -1 ns, 1);
--signal_force("/a25_tb/a25/pcie/test_pcie_core", "0000000000000001", 0 ns, freeze, -1 ns, 1);
--signal_force("/a25_tb/a25/pcie/test_rs_serdes", "1", 0 ns, freeze, -1 ns, 1);
slot1 <= TRUE;
WAIT FOR 100 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
print("***************************************************");
print(" Start of Tests");
print("***************************************************");
-- Reset:
vme_reset(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, slot1, hreset_n, v2p_rstn, vb_sysresn, en_msg_0, err);
terminal_err_0 <= terminal_err_0 + err;
-- -- VME Buserror:
-- vme_buserror(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- -- chameleon
-- cham_test(terminal_in_0, terminal_out_0, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- -- geographical address test
-- vme_ga_test(terminal_in_0, terminal_out_0, vme_ga, vme_gap, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- -- VME Slave:
-- vme_slave_a242sram(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_slave_a242pci(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_slave_a322sram(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_slave_a322pci(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_slave_a162regs(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- -- VME Master:
-- vme_master_windows(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- -- VME Interrupt Handler:
-- vme_irq_rcv(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, vme_slv_in, vme_slv_out, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- -- VME Interrupter:
-- vme_irq_trans(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, vme_slv_in, vme_slv_out, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- -- VME DMA:
-- vme_dma_boundaries(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_dma_fifo(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
-- vme_dma_sram2a24d32(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
-- vme_dma_am(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, vme_slv_in, vme_slv_out, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
-- vme_dma_sram2sram(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
-- vme_dma_sram2a32d32(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_dma_sram2a32d64(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_dma_sram2pci(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_arbitration(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, hreset_n, slot1, en_clk, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_dma_pci2sram(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_dma_pci2a32d32_zc(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
--
-- vme_dma_pci2a32d64_zc(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, err);
-- terminal_err_0 <= terminal_err_0 + err;
vme_dma_a32d64_pci_zc(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, 0, 1, err);
terminal_err_0 <= terminal_err_0 + err;
vme_dma_a32d64_pci_zc(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, irq_req, en_msg_0, 1, 1, err);
terminal_err_0 <= terminal_err_0 + err;
WAIT FOR 1 us;
print("***************************************************");
print(" Test Summary:");
print_s_i(" Number of errors: ", terminal_err_0);
print("***************************************************");
finish(0);
WAIT;
END PROCESS term_0;
END terminal_arch;
terminal_pkg.vhd 0000664 0000000 0000000 00001251275 14574545710 0035542 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Package for simulation terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 22/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- Revision 1.4 2017/06/13 07:00:00 mmiehling
-- reworked comments in vme_dma_sram2a32d64
--
-- Revision 1.3 2013/07/15 13:14:22 mmiehling
-- adopted testcases
--
-- Revision 1.2 2013/04/18 15:11:10 MMiehling
-- rework
--
-- Revision 1.1 2012/03/29 10:28:45 MMiehling
-- Initial Revision
--
-- Revision 1.9 2010/08/16 12:57:16 FLenhardt
-- Added an overloaded MTEST which accepts a seed number as an input
--
-- Revision 1.8 2009/01/13 10:57:52 FLenhardt
-- Defined that TGA=2 means configuration access
--
-- Revision 1.7 2008/09/10 17:26:45 MSchindler
-- added flash_mtest_indirect procedure
--
-- Revision 1.6 2007/07/26 07:48:15 FLenhardt
-- Defined usage of TGA
--
-- Revision 1.5 2007/07/18 10:53:34 FLenhardt
-- Fixed bug regarding MTEST printout
--
-- Revision 1.4 2007/07/18 10:28:35 mernst
-- - Changed err to sum up errors instead of setting a specific value
-- - Added dat vector to terminal_in record
--
-- Revision 1.3 2006/08/24 08:52:02 mmiehling
-- changed txt_out to integer
--
-- Revision 1.1 2006/06/23 16:33:04 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/12 10:49:17 MMiehling
-- initialization of iram now with mem_init (back)
-- added testcase 14
--
-- Revision 1.1 2006/05/09 16:51:16 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/10/27 08:35:35 flenhardt
-- Added IRQ to TERMINAL_IN_TYPE record
--
-- Revision 1.1 2005/08/23 15:21:07 MMiehling
-- Initial Revision
--
-- Revision 1.1 2005/07/01 15:47:38 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/01/31 16:28:59 mmiehling
-- updated
--
-- Revision 1.1 2004/11/16 12:09:07 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.all;
USE ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
USE work.print_pkg.all;
USE work.vme_sim_pack.all;
USE work.iram32_pkg.all;
USE work.pcie_sim_pkg.ALL;
LIBRARY modelsim_lib;
USE modelsim_lib.util.all;
USE std.textio.all;
PACKAGE terminal_pkg IS
CONSTANT SIM_BAR0 : std_logic_vector(31 DOWNTO 0):= x"0000_0000";
CONSTANT BAR0 : std_logic_vector(31 DOWNTO 0):=x"8000_0000";
CONSTANT BAR1 : std_logic_vector(31 DOWNTO 0):=x"9000_0000";
CONSTANT BAR2 : std_logic_vector(31 DOWNTO 0):= x"a000_0000";
CONSTANT BAR3 : std_logic_vector(31 DOWNTO 0):= x"e000_0000";
CONSTANT BAR4 : std_logic_vector(31 DOWNTO 0):= x"0000_0000";
CONSTANT BAR5 : std_logic_vector(31 DOWNTO 0):= x"0000_0000";
-- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
-- | Chameleon Table | 0 | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
-- | 16z002-01 VME | 2 | 10000 | 10000 | 0 |
-- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
-- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
-- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
-- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
-- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
-- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
-- +--------------------------+-----+----------+----------+-----+
CONSTANT VME_REGS : std_logic_vector(31 DOWNTO 0):=x"0001_0000" + BAR0;
CONSTANT VME_IACK : std_logic_vector(31 DOWNTO 0):=x"0001_0100" + BAR0;
CONSTANT VME_A16D16 : std_logic_vector(31 DOWNTO 0):=x"0002_0000" + BAR0;
CONSTANT VME_A16D32 : std_logic_vector(31 DOWNTO 0):=x"0003_0000" + BAR0;
CONSTANT VME_A24D16 : std_logic_vector(31 DOWNTO 0):=x"0000_0000" + BAR2;
CONSTANT VME_A24D32 : std_logic_vector(31 DOWNTO 0):=x"0100_0000" + BAR2;
CONSTANT VME_CRCSR : std_logic_vector(31 DOWNTO 0):=x"0000_0000" + BAR4;
CONSTANT VME_A32D32 : std_logic_vector(31 DOWNTO 0):=x"0000_0000" + BAR3;
CONSTANT SRAM : std_logic_vector(31 DOWNTO 0):=x"0000_0000" + BAR1;
CONSTANT DMA_VME_AM_A16D16_non : std_logic_vector(4 downto 0):="00001";
CONSTANT DMA_VME_AM_A16D16_priv : std_logic_vector(4 downto 0):="10001";
CONSTANT DMA_VME_AM_A16D32_non : std_logic_vector(4 downto 0):="00101";
CONSTANT DMA_VME_AM_A16D32_priv : std_logic_vector(4 downto 0):="10101";
CONSTANT DMA_VME_AM_A24D16_non : std_logic_vector(4 downto 0):="00000";
CONSTANT DMA_VME_AM_A24D16_priv : std_logic_vector(4 downto 0):="10000";
CONSTANT DMA_VME_AM_A24D32_non : std_logic_vector(4 downto 0):="00100";
CONSTANT DMA_VME_AM_A24D32_priv : std_logic_vector(4 downto 0):="10100";
CONSTANT DMA_VME_AM_A24D64_non : std_logic_vector(4 downto 0):="01100";
CONSTANT DMA_VME_AM_A24D64_priv : std_logic_vector(4 downto 0):="11100";
CONSTANT DMA_VME_AM_A32D32_non : std_logic_vector(4 downto 0):="00110";
CONSTANT DMA_VME_AM_A32D32_priv : std_logic_vector(4 downto 0):="10110";
CONSTANT DMA_VME_AM_A32D64_non : std_logic_vector(4 downto 0):="01110";
CONSTANT DMA_VME_AM_A32D64_priv : std_logic_vector(4 downto 0):="11110";
CONSTANT DMA_BLK : std_logic:='0';
CONSTANT DMA_SGL : std_logic:='1';
CONSTANT DMA_DEVICE_SRAM : std_logic_vector(2 downto 0):="001";
CONSTANT DMA_DEVICE_VME : std_logic_vector(2 downto 0):="010";
CONSTANT DMA_DEVICE_PCI : std_logic_vector(2 downto 0):="100";
TYPE terminal_in_type IS record
done : boolean; -- edge indicates end of transfer
busy : std_logic; -- indicates status of master
err : natural; -- number of errors occured
irq : std_logic; -- interrupt request
dat : std_logic_vector(31 DOWNTO 0); -- Input data
END record;
TYPE terminal_out_type IS record
adr : std_logic_vector(31 DOWNTO 0); -- address
tga : std_logic_vector(5 DOWNTO 0); --
dat : std_logic_vector(31 DOWNTO 0); -- write data
wr : natural; -- 0=read, 1=write, 2=wait for numb cycles
typ : natural; -- 0=b, w=1, l=2, dl=3
numb : natural; -- number of transactions (1=single, >1=burst)
start : boolean; -- edge starts transfer
txt : integer; -- enables info messages -- 0=quiet, 1=only errors, 2=all
END record;
-- Bus Accesses
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type);
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
);
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd64( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd8_iack( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr64( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) ;
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) ;
PROCEDURE vme_ga_test(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL vme_ga : OUT std_logic_vector(4 DOWNTO 0);
SIGNAL vme_gap : OUT std_logic;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2a24d32(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_am(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_boundaries(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_fifo(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
size : integer; -- number of longwords to be transmitted by DMA
src_adr : std_logic_vector(31 downto 0); -- DMA source address
dest_adr : std_logic_vector(31 downto 0); -- DMA destination address
vme_am : std_logic_vector(4 downto 0); -- address modifier bits of buffer descriptor
src_dev : std_logic_vector(2 downto 0); -- source device bits of buffer descriptor
dest_dev : std_logic_vector(2 downto 0); -- destination device bits of buffer descriptor
blk : std_logic; -- block or single access
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_pci2sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_pci2a32d32_zc(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_a32d32_pci_zc(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
inc_src : in integer;
init_data : in integer;
err : OUT natural
);
PROCEDURE vme_dma_a24d64_pci_zc(
signal terminal_in_0 : in terminal_in_type;
signal terminal_out_0 : out terminal_out_type;
signal terminal_in_1 : in terminal_in_type;
signal terminal_out_1 : out terminal_out_type;
signal irq_req : in std_logic_vector(16 downto 0);
en_msg_0 : in integer;
inc_src : in integer;
init_data : in integer;
err : out natural
);
PROCEDURE vme_dma_pci2a32d64_zc(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_a32d64_pci_zc(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
inc_src : in integer;
init_data : in integer;
err : OUT natural
);
PROCEDURE vme_slave_a242sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a242pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_reset(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL slot1 : OUT boolean;
SIGNAL hreset_n : OUT std_logic;
SIGNAL v2p_rstn : IN std_logic;
SIGNAL vb_sysresn : IN std_logic;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a322sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a322pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE cham_test(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a162regs(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2a32d32(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2a32d64(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_buserror(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_master_windows(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_arbitration(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL hreset_n : OUT std_logic;
SIGNAL slot1 : OUT boolean;
SIGNAL en_clk : OUT boolean;
en_msg_0 : integer;
err : OUT natural
) ;
PROCEDURE vme_arbiter(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_irq_rcv(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_irq_trans(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE rd_iram_bfm(
adr : std_logic_vector(31 DOWNTO 0); -- address
exp_dat : std_logic_vector(31 DOWNTO 0); -- expected data
txt_out : integer; -- 0= no message, 1=only errors, 2=all
err : OUT integer -- 1 if exp_dat /= read data
);
PROCEDURE wr_iram_bfm(
adr : std_logic_vector(31 DOWNTO 0); -- address
dat : std_logic_vector(31 DOWNTO 0); -- data
txt_out : integer; -- 0= no message, 1=only errors, 2=all
err : OUT integer
);
PROCEDURE print_err(s: in string; err: in integer);
procedure configure_bfm(
signal terminal_in : in terminal_in_type;
signal terminal_out : out terminal_out_type;
bar0_addr : std_logic_vector(31 downto 0);
bar1_addr : std_logic_vector(31 downto 0);
bar2_addr : std_logic_vector(31 downto 0);
bar3_addr : std_logic_vector(31 downto 0);
bar4_addr : std_logic_vector(31 downto 0);
bar5_addr : std_logic_vector(31 downto 0);
txt_out : integer
);
END terminal_pkg;
PACKAGE BODY terminal_pkg IS
----------------------------------------------------------------------------------------------------------
PROCEDURE print_err(s: in string; err: in integer) is
variable l: line;
BEGIN
write(l, ' ');
WRITELINE(output,l);
WRITE(l, string'(" Testcase: "));
write(l, s);
WRITE(l, string'(" Error Sum: "));
write(l, err);
writeline(output,l);
write(l, ' ');
WRITELINE(output,l);
END print_err;
PROCEDURE wr_iram_bfm(
adr : std_logic_vector(31 DOWNTO 0); -- address
dat : std_logic_vector(31 DOWNTO 0); -- data
txt_out : integer; -- 0= no message, 1=only errors, 2=all
err : OUT integer
) IS
BEGIN
--! procedure to write values to the BFM internal memory
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param nbr_of_dw number of DWORDS that will be written
--! @param io_space set to true is I/O space is targeted
--! @param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
--! @param mem_addr offset for internal memory space, start at x"0000_0000"
--! @param start_data_val first data value to write, other values are defined by data_inc
--! @param data_inc defines the data increment added to start_data_val for DW 2 to nbr_of_dw
--set_bfm_memory(0, 1, FALSE, TRUE, adr, dat, 1);
set_bfm_memory(nbr_of_dw => 1, mem_addr => adr, start_data_val => dat, data_inc => 1);
IF txt_out > 1 THEN
print_cycle("BFM SET: ", adr, dat, "1111", "");
END IF;
err := 0;
END PROCEDURE;
PROCEDURE rd_iram_bfm(
adr : std_logic_vector(31 DOWNTO 0); -- address
exp_dat : std_logic_vector(31 DOWNTO 0); -- expected data
txt_out : integer; -- 0= no message, 1=only errors, 2=all
err : OUT integer -- 1 if exp_dat /= read data
) IS
VARIABLE databuf_out : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
BEGIN
--! procedure to read from BFM internal memory
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param nbr_of_dw number of DWORDS that will be written
--! @param io_space set to true is I/O space is targeted
--! @param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
--! @param mem_addr offset for internal memory space, start at x"0000_0000"
--! @return databuf_out returns a dword_vector that contains all data read from BFM internal memory
--get_bfm_memory(0, 1, FALSE, TRUE, adr, databuf_out);
get_bfm_memory(nbr_of_dw => 1, mem_addr => adr, databuf_out => databuf_out);
IF databuf_out(0) /= exp_dat THEN
IF txt_out > 0 THEN
print_mtest("ERROR: ", adr, databuf_out(0), exp_dat, FALSE);
END IF;
err := 1;
ELSIF txt_out > 1 THEN
print_mtest("RD_IRAM_BFM: ", adr, databuf_out(0), exp_dat, TRUE);
err := 0;
END IF;
END PROCEDURE;
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type) IS
BEGIN
terminal_out.adr <= (OTHERS => '0');
terminal_out.tga <= (OTHERS => '0');
terminal_out.dat <= (OTHERS => '0');
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.numb <= 0;
terminal_out.txt <= 0;
terminal_out.start <= TRUE;
END PROCEDURE init;
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
) IS
BEGIN
terminal_out.wr <= 2;
terminal_out.numb <= numb;
terminal_out.txt <= 0;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd64( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 3;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd8_iack(
SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 4; -- indicate iack
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr64( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 3;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
-- This is the legacy MTEST (without seed)
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
mtest(terminal_in, terminal_out, adr, adr_end, typ, numb, txt_out, tga, 0, err);
END PROCEDURE;
-- This is an overloaded MTEST which accepts a seed number as an input,
-- which can be used to generate the pseudo-random data in different ways
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) IS
VARIABLE loc_err : natural;
VARIABLE loc_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE loc_dat : std_logic_vector(31 DOWNTO 0);
VARIABLE numb_cnt : natural;
BEGIN
loc_adr := adr;
numb_cnt := 0;
loc_err := 0;
loc_dat := adr;
while NOT(numb_cnt = numb) LOOP
CASE typ IS
WHEN 0 => -- long
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"4";
END LOOP;
WHEN 1 => -- word
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"2";
END LOOP;
WHEN 2 => -- byte
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"1";
END LOOP;
WHEN OTHERS =>
print("ERROR terminal_pkg: typ IS NOT defined!");
END CASE;
numb_cnt := numb_cnt + 1;
END LOOP;
IF loc_err > 0 THEN
print_s_i(" mtest FAIL errors: ", loc_err);
ELSE
print(" mtest PASS");
END IF;
err := err + loc_err;
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_ga_test(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL vme_ga : OUT std_logic_vector(4 DOWNTO 0);
SIGNAL vme_gap : OUT std_logic;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE vme_ga_int : std_logic_vector(4 DOWNTO 0);
VARIABLE vme_gap_int : std_logic;
BEGIN
print("Test vme_ga_test: VME graphical address test");
-- reset value shall be 0x0
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0050", x"0000_1e00", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time("Check Slot Number detection by using corresponding VME_GA/VME_GAP settings");
FOR i IN 1 TO 21 LOOP
print_s_i("Slot Number ",i);
vme_ga_int := NOT (conv_std_logic_vector(i,5)); -- inverted number
vme_gap_int := NOT (vme_ga_int(4) XOR vme_ga_int(3) XOR vme_ga_int(2) XOR vme_ga_int(1) XOR vme_ga_int(0));
vme_ga <= vme_ga_int;
vme_gap <= vme_gap_int;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0050", x"0000" & conv_std_logic_vector(i,8) & "00" & vme_gap_int & vme_ga_int, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
WAIT FOR 1 us;
print_time("Check Slot Number detection by using incorrect VME_GAP settings => Slot Number shall be always 30");
FOR i IN 1 TO 21 LOOP
print_s_i("Slot Number ",i);
vme_ga_int := NOT (conv_std_logic_vector(i,5)); -- inverted number
vme_gap_int := (vme_ga_int(4) XOR vme_ga_int(3) XOR vme_ga_int(2) XOR vme_ga_int(1) XOR vme_ga_int(0));
vme_ga <= vme_ga_int;
vme_gap <= vme_gap_int;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0050", x"0000" & x"1e" & "00" & vme_gap_int & vme_ga_int, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
WAIT FOR 1 us;
print_time("Check Slot Number detection by using incorrect VME_GA/VME_GAP settings => Slot Number shall be always 30");
FOR i IN 22 TO 31 LOOP
vme_ga_int := NOT (conv_std_logic_vector(i,5)); -- inverted number
vme_gap_int := NOT (vme_ga_int(4) XOR vme_ga_int(3) XOR vme_ga_int(2) XOR vme_ga_int(1) XOR vme_ga_int(0));
print_s_std("VME_GAP & VME_GA setting = ", "00" & vme_gap_int & vme_ga_int);
vme_ga <= vme_ga_int;
vme_gap <= vme_gap_int;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0050", x"0000" & x"1e" & "00" & vme_gap_int & vme_ga_int, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
err := err_sum;
print_err("vme_ga_test", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2a24d32(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0110: VME DMA: SRAM TO VME A24D32 AND back");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2a24d32): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- test data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"1111_1111", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_000c", x"2222_2222", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_000c", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0010", x"3333_3333", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0010", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0014", x"4444_4444", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0014", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear destination in VME_A24D32
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0004", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- clear destination in SRAM
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0100", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_010c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0110", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0114", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_00fc", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- config buffer descriptor #1 SRAM => VME_A24D32
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0020_0004", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0020_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0008", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_2040", 1, en_msg_0, TRUE, "000001"); -- source=sram dest=A24D32 inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_2040", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- config buffer descriptor #2 VME_A24D32 => SRAM
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0100", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0100", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"0020_0004", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"0020_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_1041", 1, en_msg_0, TRUE, "000001"); -- source=A24D32 dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_1041", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2a24d32): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a24d32: dma irq NOT asserted");
END IF;
-- check control reg for irq asserted
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0006", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0004", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000c", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0010", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check destination SRAM
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_00fc", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0100", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_010c", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0110", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check irq
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a24d32: dma irq NOT asserted");
END IF;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2a24d32: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma_sram2a24d32", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_pci2sram(
signal terminal_in_0 : in terminal_in_type;
signal terminal_out_0 : out terminal_out_type;
signal terminal_in_1 : in terminal_in_type;
signal terminal_out_1 : out terminal_out_type;
signal irq_req : in std_logic_vector(16 downto 0);
en_msg_0 : in integer;
err : out natural
) is
variable loc_err : integer :=0;
variable err_sum : integer :=0;
variable adr : std_logic_vector(31 downto 0);
variable dat : std_logic_vector(31 downto 0);
variable dma_dst : std_logic_vector(31 downto 0); -- DMA dest address for the current buffer descriptor
variable dma_src : std_logic_vector(31 downto 0); -- DMA src address for the current buffer descriptor
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
-- Test parameters:
constant c_TEST_SIZE : integer := 256; -- number of words to be transmitted by DMA in the whole test
constant c_DMA_TRANSFER_SZ : natural := 16; -- DMA single transfer size
constant c_DMA_SRC : std_logic_vector(31 downto 0) := x"0000_0010"; -- PCIe source address
constant c_DMA_DST : std_logic_vector(31 downto 0) := x"0000_0000"; -- SRAM destination address
begin
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_pci2sram): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- first, copy test data to SHM
dma_src := c_DMA_SRC;
for i in 0 to c_TEST_SIZE-1 loop
adr := dma_src + 4*i;
bfm_wr_shm(addr => to_integer(unsigned(adr)), len=>4, dat => std_logic_vector(to_unsigned(4*i, 32)));
end loop;
-- program DMA
adr := x"000f_f900";
dma_dst := c_DMA_DST;
dma_src := c_DMA_SRC;
for i in 0 to (c_TEST_SIZE/c_DMA_TRANSFER_SZ-1) loop
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", dma_dst, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dma_src, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", std_logic_vector(to_unsigned(c_DMA_TRANSFER_SZ - 1, 32)), 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"00041000", 1, en_msg_0, TRUE, "000001");
dma_dst := dma_dst + x"40";
dma_src := dma_src + x"40";
adr := adr + x"10";
end loop;
-- overwrite last buffer descriptor to set DMA_NULL=1 (last element of the list
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"00041001", 1, en_msg_0, TRUE, "000001");
-- Write to DMA Status Register (DMASTA): DMA_IEN | DMA_EN
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
-- WE'VE JUST ENABLED DMA, NOW IT PERFORMS THE TRANSFER
-- and we wait for the MSI when DMA is done
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_pci2sram): error while executing bfm_poll_msi()"); end if;
end if;
if irq_req(13) = '0' then
print_time("ERROR vme_dma_pci2sram: dma irq NOT asserted");
end if;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
if irq_req(13) = '1' then
print_time("ERROR vme_dma_pci2sram: dma irq asserted");
end if;
if var_success then
print_now("Got and cleared MSI");
end if;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
if var_success then
-- here the DMA is over, we should verify data
print_now("Reading data for verification...");
for i in 0 to c_TEST_SIZE-1 loop
rd32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end loop;
end if;
err := err_sum;
print_err("vme_dma_pci2sram", err_sum);
end if;
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_pci2a32d32_zc( -- zero-copy variant of the test
signal terminal_in_0 : in terminal_in_type;
signal terminal_out_0 : out terminal_out_type;
signal terminal_in_1 : in terminal_in_type;
signal terminal_out_1 : out terminal_out_type;
signal irq_req : in std_logic_vector(16 downto 0);
en_msg_0 : in integer;
err : out natural
) is
variable loc_err : integer:=0;
variable err_sum : integer:=0;
variable adr : std_logic_vector(31 DOWNTO 0);
variable dat : std_logic_vector(31 DOWNTO 0);
variable dma_dst : std_logic_vector(31 DOWNTO 0);
variable dma_src : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
-- Test parameters:
constant c_TEST_SIZE : integer := 256; -- number of words to be transmitted by DMA in the whole test
constant c_DMA_TRANSFER_SZ : natural := 16; -- DMA single transfer size (words)
constant c_DMA_SRC : std_logic_vector(31 downto 0) := x"0000_0010"; -- PCIe source address
constant c_DMA_DST : std_logic_vector(31 downto 0) := x"3000_0000"; -- VME dest address
BEGIN
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_pci2sram): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- set A32 address extension
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- first, copy test data to SHM
dma_src := c_DMA_SRC;
for i in 0 to c_TEST_SIZE-1 loop
adr := dma_src + 4*i;
bfm_wr_shm(addr => to_integer(unsigned(adr)), len=>4, dat => std_logic_vector(to_unsigned(4*i, 32)));
end loop;
-- program DMA
adr := x"000f_f900";
dma_dst := c_DMA_DST;
dma_src := c_DMA_SRC;
for i in 0 to (c_TEST_SIZE/c_DMA_TRANSFER_SZ-1) loop
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", dma_dst, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dma_src, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", std_logic_vector(to_unsigned(c_DMA_TRANSFER_SZ - 1, 32)), 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"00042060", 1, en_msg_0, TRUE, "000001");
dma_dst := dma_dst + (c_DMA_TRANSFER_SZ*4);
dma_src := dma_src + (c_DMA_TRANSFER_SZ*4);
adr := adr + x"10";
end loop;
-- overwrite last buffer descriptor to set DMA_NULL=1 (last element of the list
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"00042061", 1, en_msg_0, TRUE, "000001");
-- Write to DMA Status Register (DMASTA): DMA_IEN | DMA_EN
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
-- WE'VE JUST ENABLED DMA, NOW IT PERFORMS THE TRANSFER
-- and we wait for the MSI when DMA is done
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
-- single MSI poll has too short timeout for the transfer tested here.
-- Thus the loop.
for i in 0 to 10 loop
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => 0,
success => var_success
);
if var_success then
exit;
end if;
end loop;
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_pci2sram): error while executing bfm_poll_msi()"); end if;
end if;
if irq_req(13) = '0' then
print_time("ERROR vme_dma_pci2sram: dma irq NOT asserted");
end if;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
if irq_req(13) = '1' then
print_time("ERROR vme_dma_pci2sram: dma irq asserted");
end if;
if var_success then
print_now("Got and cleared MSI");
end if;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
if var_success then
-- here the DMA is over, we should verify data
print_now("Reading data for verification...");
for i in 0 to c_TEST_SIZE-1 loop
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end loop;
end if;
err := err_sum;
print_err("vme_dma_pci2a32d32_zc", err_sum);
end if;
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_a32d32_pci_zc( -- zero-copy variant of the test
signal terminal_in_0 : in terminal_in_type;
signal terminal_out_0 : out terminal_out_type;
signal terminal_in_1 : in terminal_in_type;
signal terminal_out_1 : out terminal_out_type;
signal irq_req : in std_logic_vector(16 downto 0);
en_msg_0 : in integer;
inc_src : in integer;
init_data : in integer;
err : out natural
) is
variable loc_err : integer:=0;
variable err_sum : integer:=0;
variable adr : std_logic_vector(31 DOWNTO 0);
variable dat : std_logic_vector(31 DOWNTO 0);
variable dma_dst : std_logic_vector(31 DOWNTO 0);
variable dma_src : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
-- Test parameters:
constant c_TEST_SIZE : integer := 256; -- number of words to be transmitted by DMA in the whole test
constant c_DMA_TRANSFER_SZ : natural := 16; -- DMA single transfer size (words)
constant c_DMA_DST : std_logic_vector(31 downto 0) := x"0000_0010"; -- PCIe dest address
constant c_DMA_SRC : std_logic_vector(31 downto 0) := x"3000_0000"; -- VME source address
BEGIN
if inc_src = 0 then
print_now("DMA no inc_src");
else
print_now("DMA WITH inc_src");
end if;
print("Test DMA ZC: A32D32 to PCIe");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_a32d32_pci_zc): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- set A32 address extension
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
if init_data = 1 then
-- first, write test data to VME
dma_src := c_DMA_SRC;
for i in 0 to c_TEST_SIZE-1 loop
adr := dma_src + 4*i;
-- A32D32 single accesses
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000" + (4*i), std_logic_vector(to_unsigned(4*i, 32)), 1, en_msg_0, TRUE, "000001");
err_sum := err_sum + loc_err;
end loop;
end if;
-- program DMA
adr := x"000f_f900";
dma_dst := c_DMA_DST;
dma_src := c_DMA_SRC;
for i in 0 to (c_TEST_SIZE/c_DMA_TRANSFER_SZ-1) loop
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", dma_dst, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dma_src, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", std_logic_vector(to_unsigned(c_DMA_TRANSFER_SZ - 1, 32)), 1, en_msg_0, TRUE, "000001");
if inc_src = 0 then
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"00024060", 1, en_msg_0, TRUE, "000001");
else
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"00024064", 1, en_msg_0, TRUE, "000001");
end if;
dma_dst := dma_dst + (c_DMA_TRANSFER_SZ*4);
dma_src := dma_src + (c_DMA_TRANSFER_SZ*4);
adr := adr + x"10";
end loop;
-- overwrite last buffer descriptor to set DMA_NULL=1 (last element of the list
if inc_src = 0 then
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"00024061", 1, en_msg_0, TRUE, "000001");
else
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"00024065", 1, en_msg_0, TRUE, "000001");
end if;
-- Write to DMA Status Register (DMASTA): DMA_IEN | DMA_EN
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
-- WE'VE JUST ENABLED DMA, NOW IT PERFORMS THE TRANSFER
-- and we wait for the MSI when DMA is done
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
-- single MSI poll has too short timeout for the transfer tested here.
-- Thus the loop.
for i in 0 to 10 loop
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => 0,
success => var_success
);
if var_success then
exit;
end if;
end loop;
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_a32d32_pci_zc): error while executing bfm_poll_msi()"); end if;
end if;
if irq_req(13) = '0' then
print_time("ERROR vme_dma_a32d32_pci_zc: dma irq NOT asserted");
end if;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
if irq_req(13) = '1' then
print_time("ERROR vme_dma_a32d32_pci_zc: dma irq asserted");
end if;
if var_success then
print_now("Got and cleared MSI");
end if;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dma_dst := c_DMA_DST;
if var_success then
-- here the DMA is over, we should verify data
print_now("Reading data for verification...");
for i in 0 to c_TEST_SIZE-1 loop
adr := dma_dst + 4*i;
bfm_rd_shm(addr => to_integer(unsigned(adr)), len => 4, dat => dat);
if dat /= std_logic_vector(to_unsigned(4*i, dat'length)) then
print_s_hl("Error at ", i);
print_s_hl("read word bfm:", dat);
err_sum := err_sum + 1;
end if;
end loop;
end if;
err := err_sum;
print_err("vme_dma_a32d32_pci_zc", err_sum);
end if;
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_pci2a32d64_zc( -- zero-copy variant of the test
signal terminal_in_0 : in terminal_in_type;
signal terminal_out_0 : out terminal_out_type;
signal terminal_in_1 : in terminal_in_type;
signal terminal_out_1 : out terminal_out_type;
signal irq_req : in std_logic_vector(16 downto 0);
en_msg_0 : in integer;
err : out natural
) is
variable loc_err : integer:=0;
variable err_sum : integer:=0;
variable adr : std_logic_vector(31 DOWNTO 0);
variable dat : std_logic_vector(31 DOWNTO 0);
variable dma_dst : std_logic_vector(31 DOWNTO 0);
variable dma_src : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
-- Test parameters:
constant c_TEST_SIZE : integer := 256; -- number of words to be transmitted by DMA in the whole test
constant c_DMA_TRANSFER_SZ : natural := 16; -- DMA single transfer size (words)
constant c_DMA_SRC : std_logic_vector(31 downto 0) := x"0000_0010"; -- PCIe source address
constant c_DMA_DST : std_logic_vector(31 downto 0) := x"3000_0000"; -- VME dest address
BEGIN
print("Test DMA ZC: PCIe to A32D64");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_pci2a32d64_zc): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- set A32 address extension
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- first, copy test data to SHM
dma_src := c_DMA_SRC;
for i in 0 to 2*c_TEST_SIZE-1 loop
adr := dma_src + 4*i;
bfm_wr_shm(addr => to_integer(unsigned(adr)), len=>4, dat => std_logic_vector(to_unsigned(4*i, 32)));
end loop;
-- program DMA
adr := x"000f_f900";
dma_dst := c_DMA_DST;
dma_src := c_DMA_SRC;
for i in 0 to (c_TEST_SIZE/c_DMA_TRANSFER_SZ-1) loop
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", dma_dst, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dma_src, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", std_logic_vector(to_unsigned(c_DMA_TRANSFER_SZ - 1, 32)), 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"000420e0", 1, en_msg_0, TRUE, "000001");
dma_dst := dma_dst + (c_DMA_TRANSFER_SZ*4);
dma_src := dma_src + (c_DMA_TRANSFER_SZ*4);
adr := adr + x"10";
end loop;
-- overwrite last buffer descriptor to set DMA_NULL=1 (last element of the list
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"000420e1", 1, en_msg_0, TRUE, "000001");
-- Write to DMA Status Register (DMASTA): DMA_IEN | DMA_EN
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
-- WE'VE JUST ENABLED DMA, NOW IT PERFORMS THE TRANSFER
-- and we wait for the MSI when DMA is done
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
-- single MSI poll has too short timeout for the transfer tested here.
-- Thus the loop.
for i in 0 to 10 loop
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => 0,
success => var_success
);
if var_success then
exit;
end if;
end loop;
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_pci2a32d64_zc): error while executing bfm_poll_msi()"); end if;
end if;
if irq_req(13) = '0' then
print_time("ERROR vme_dma_pci2a32d64_zc: dma irq NOT asserted");
end if;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
if irq_req(13) = '1' then
print_time("ERROR vme_dma_pci2a32d64_zc: dma irq asserted");
end if;
if var_success then
print_now("Got and cleared MSI");
end if;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
if var_success then
-- here the DMA is over, we should verify data
print_now("Reading data for verification...");
for i in 0 to c_TEST_SIZE-1 loop
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end loop;
end if;
err := err_sum;
print_err("vme_dma_pci2a32d64_zc", err_sum);
end if;
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_a24d64_pci_zc( -- zero-copy variant of the test
signal terminal_in_0 : in terminal_in_type;
signal terminal_out_0 : out terminal_out_type;
signal terminal_in_1 : in terminal_in_type;
signal terminal_out_1 : out terminal_out_type;
signal irq_req : in std_logic_vector(16 downto 0);
en_msg_0 : in integer;
inc_src : in integer;
init_data : in integer;
err : out natural
) is
variable loc_err : integer:=0;
variable err_sum : integer:=0;
variable adr : std_logic_vector(31 DOWNTO 0);
variable dat : std_logic_vector(31 DOWNTO 0);
variable dma_dst : std_logic_vector(31 DOWNTO 0);
variable dma_src : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
-- Test parameters:
constant c_TEST_SIZE : integer := 256; -- number of words to be transmitted by DMA in the whole test
constant c_DMA_TRANSFER_SZ : natural := 16; -- DMA single transfer size (words)
constant c_DMA_DST : std_logic_vector(31 downto 0) := x"0000_0010"; -- PCIe dest address
constant c_DMA_SRC : std_logic_vector(31 downto 0) := x"0020_0000"; -- VME source address
BEGIN
if inc_src = 0 then
print_now("DMA no inc_src");
else
print_now("DMA WITH inc_src");
end if;
print("Test DMA ZC: A32D64 to PCIe");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_a24d64_pci_zc): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
if init_data = 1 then
-- first, write test data to VME
dma_src := c_DMA_SRC;
for i in 0 to c_TEST_SIZE-1 loop
adr := dma_src + 4*i;
-- A32D32 single accesses
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"20_0000" + (4*i), std_logic_vector(to_unsigned(4*i, 32)), 1, en_msg_0, TRUE, "000001");
err_sum := err_sum + loc_err;
end loop;
end if;
-- program DMA
adr := x"000f_f900";
dma_dst := c_DMA_DST;
dma_src := c_DMA_SRC;
for i in 0 to (c_TEST_SIZE/c_DMA_TRANSFER_SZ-1) loop
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", dma_dst, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dma_src, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", std_logic_vector(to_unsigned(c_DMA_TRANSFER_SZ - 1, 32)), 1, en_msg_0, TRUE, "000001");
if inc_src = 0 then
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"000240c0", 1, en_msg_0, TRUE, "000001");
else
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"000240c4", 1, en_msg_0, TRUE, "000001");
end if;
dma_dst := dma_dst + (c_DMA_TRANSFER_SZ*4);
dma_src := dma_src + (c_DMA_TRANSFER_SZ*4);
adr := adr + x"10";
end loop;
-- overwrite last buffer descriptor to set DMA_NULL=1 (last element of the list
if inc_src = 0 then
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"000240c1", 1, en_msg_0, TRUE, "000001");
else
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"000240c5", 1, en_msg_0, TRUE, "000001");
end if;
-- Write to DMA Status Register (DMASTA): DMA_IEN | DMA_EN
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
-- WE'VE JUST ENABLED DMA, NOW IT PERFORMS THE TRANSFER
-- and we wait for the MSI when DMA is done
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
-- single MSI poll has too short timeout for the transfer tested here.
-- Thus the loop.
for i in 0 to 10 loop
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => 0,
success => var_success
);
if var_success then
exit;
end if;
end loop;
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_a24d64_pci_zc): error while executing bfm_poll_msi()"); end if;
end if;
if irq_req(13) = '0' then
print_time("ERROR vme_dma_a24d64_pci_zc: dma irq NOT asserted");
end if;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
if irq_req(13) = '1' then
print_time("ERROR vme_dma_a24d64_pci_zc: dma irq asserted");
end if;
if var_success then
print_now("Got and cleared MSI");
end if;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dma_dst := c_DMA_DST;
if var_success then
-- here the DMA is over, we should verify data
print_now("Reading data for verification...");
for i in 0 to c_TEST_SIZE-1 loop
adr := dma_dst + 4*i;
bfm_rd_shm(addr => to_integer(unsigned(adr)), len => 4, dat => dat);
if dat /= std_logic_vector(to_unsigned(4*i, dat'length)) then
print_s_hl("Error at ", i);
print_s_hl("read word bfm:", dat);
err_sum := err_sum + 1;
end if;
end loop;
end if;
err := err_sum;
print_err("vme_dma_a24d64_pci_zc", err_sum);
end if;
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_a32d64_pci_zc( -- zero-copy variant of the test
signal terminal_in_0 : in terminal_in_type;
signal terminal_out_0 : out terminal_out_type;
signal terminal_in_1 : in terminal_in_type;
signal terminal_out_1 : out terminal_out_type;
signal irq_req : in std_logic_vector(16 downto 0);
en_msg_0 : in integer;
inc_src : in integer;
init_data : in integer;
err : out natural
) is
variable loc_err : integer:=0;
variable err_sum : integer:=0;
variable adr : std_logic_vector(31 DOWNTO 0);
variable dat : std_logic_vector(31 DOWNTO 0);
variable dma_dst : std_logic_vector(31 DOWNTO 0);
variable dma_src : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
-- Test parameters:
constant c_TEST_SIZE : integer := 256; -- number of words to be transmitted by DMA in the whole test
constant c_DMA_TRANSFER_SZ : natural := 16; -- DMA single transfer size (words)
constant c_DMA_DST : std_logic_vector(31 downto 0) := x"0000_0010"; -- PCIe dest address
constant c_DMA_SRC : std_logic_vector(31 downto 0) := x"3000_0000"; -- VME source address
BEGIN
if inc_src = 0 then
print_now("DMA no inc_src");
else
print_now("DMA WITH inc_src");
end if;
print("Test DMA ZC: A32D64 to PCIe");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_a32d64_pci_zc): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- set A32 address extension
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
if init_data = 1 then
-- first, write test data to VME
dma_src := c_DMA_SRC;
for i in 0 to c_TEST_SIZE-1 loop
adr := dma_src + 4*i;
-- A32D32 single accesses
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000" + (4*i), std_logic_vector(to_unsigned(4*i, 32)), 1, en_msg_0, TRUE, "000001");
err_sum := err_sum + loc_err;
end loop;
end if;
-- program DMA
adr := x"000f_f900";
dma_dst := c_DMA_DST;
dma_src := c_DMA_SRC;
for i in 0 to (c_TEST_SIZE/c_DMA_TRANSFER_SZ-1) loop
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", dma_dst, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dma_src, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", std_logic_vector(to_unsigned(c_DMA_TRANSFER_SZ - 1, 32)), 1, en_msg_0, TRUE, "000001");
if inc_src = 0 then
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"000240e0", 1, en_msg_0, TRUE, "000001");
else
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"000240e4", 1, en_msg_0, TRUE, "000001");
end if;
dma_dst := dma_dst + (c_DMA_TRANSFER_SZ*4);
dma_src := dma_src + (c_DMA_TRANSFER_SZ*4);
adr := adr + x"10";
end loop;
-- overwrite last buffer descriptor to set DMA_NULL=1 (last element of the list
if inc_src = 0 then
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"000240e1", 1, en_msg_0, TRUE, "000001");
else
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"000240e5", 1, en_msg_0, TRUE, "000001");
end if;
-- Write to DMA Status Register (DMASTA): DMA_IEN | DMA_EN
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
-- WE'VE JUST ENABLED DMA, NOW IT PERFORMS THE TRANSFER
-- and we wait for the MSI when DMA is done
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
-- single MSI poll has too short timeout for the transfer tested here.
-- Thus the loop.
for i in 0 to 10 loop
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => 0,
success => var_success
);
if var_success then
exit;
end if;
end loop;
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_a32d64_pci_zc): error while executing bfm_poll_msi()"); end if;
end if;
if irq_req(13) = '0' then
print_time("ERROR vme_dma_a32d64_pci_zc: dma irq NOT asserted");
end if;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
if irq_req(13) = '1' then
print_time("ERROR vme_dma_a32d64_pci_zc: dma irq asserted");
end if;
if var_success then
print_now("Got and cleared MSI");
end if;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dma_dst := c_DMA_DST;
if var_success then
-- here the DMA is over, we should verify data
print_now("Reading data for verification...");
for i in 0 to c_TEST_SIZE-1 loop
adr := dma_dst + 4*i;
bfm_rd_shm(addr => to_integer(unsigned(adr)), len => 4, dat => dat);
if dat /= std_logic_vector(to_unsigned(4*i, dat'length)) then
print_s_hl("Error at ", i);
print_s_hl("read word bfm:", dat);
err_sum := err_sum + 1;
end if;
end loop;
end if;
err := err_sum;
print_err("vme_dma_a32d64_pci_zc", err_sum);
end if;
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_am(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable offset : std_logic_vector(11 downto 0);
variable size : integer; -- number of longwords to be transmitted by DMA
variable am : std_logic_vector(5 downto 0);
BEGIN
-- checks all address modifiers possible by DMA transfer: A16, A24, A32, D16, D32, D64, supervisory, non-privilegded
size := 14;
-- set longadd
-- wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001"); -- if generic USE_LONGADD=false
-- rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001", loc_err);
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- test data in sram
FOR i IN 0 TO size*4+1 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001");
END LOOP;
print_time("Test vme_dma_am: A24 Accesses");
-- A24_D16 supervisory BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D16 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0000", -- destination address
DMA_VME_AM_A24D16_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D16 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0000", -- source address
x"0000_2000", -- destination address
DMA_VME_AM_A24D16_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D32 supervisory BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D32 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0100", -- destination address
DMA_VME_AM_A24D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0100", -- source address
x"0000_2100", -- destination address
DMA_VME_AM_A24D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D16 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D16 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0200", -- destination address
DMA_VME_AM_A24D16_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D16 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0200", -- source address
x"0000_2200", -- destination address
DMA_VME_AM_A24D16_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D32 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0300", -- destination address
DMA_VME_AM_A24D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0300", -- source address
x"0000_2300", -- destination address
DMA_VME_AM_A24D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D64 supervisory MBLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D64 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0400", -- destination address
DMA_VME_AM_A24D64_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0400", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D64 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0400", -- source address
x"0000_2400", -- destination address
DMA_VME_AM_A24D64_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2400", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D16 non-priviledged BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D64 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0500", -- destination address
DMA_VME_AM_A24D16_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0500", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D64 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0500", -- source address
x"0000_2500", -- destination address
DMA_VME_AM_A24D16_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2500", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D32 non-priviledged BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D32 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0600", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0600", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0600", -- source address
x"0000_2600", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2600", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D16 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D16 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0700", -- destination address
DMA_VME_AM_A24D16_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0700", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D16 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0700", -- source address
x"0000_2700", -- destination address
DMA_VME_AM_A24D16_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2700", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D32 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D32 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0800", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0800", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0800", -- source address
x"0000_2800", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2800", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D64 non-priviledged MBLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D64 non-privileged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0900", -- destination address
DMA_VME_AM_A24D64_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0900", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 non-privileged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0900", -- source address
x"0000_2900", -- destination address
DMA_VME_AM_A24D64_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2900", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time("Test vme_dma_am: A16 Accesses");
-- A16_D16 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A16D16 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0000_1000", -- destination address
DMA_VME_AM_A16D16_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_SUPER THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A16D16 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_1000", -- source address
x"0000_2a00", -- destination address
DMA_VME_AM_A16D16_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_SUPER THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2a00", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16_D32 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A16D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0000_1100", -- destination address
DMA_VME_AM_A16D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_SUPER THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A16D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_1100", -- source address
x"0000_2b00", -- destination address
DMA_VME_AM_A16D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_SUPER THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2b00", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16_D16 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A16D16 non-priviledged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0000_1200", -- destination address
DMA_VME_AM_A16D16_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_NONPRIV THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A16D16 non-priviledged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_1200", -- source address
x"0000_2c00", -- destination address
DMA_VME_AM_A16D16_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_NONPRIV THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2c00", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16_D32 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A16D32 non-priviledged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0000_1300", -- destination address
DMA_VME_AM_A16D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_NONPRIV THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A16D32 non-priviledged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_1300", -- source address
x"0000_2d00", -- destination address
DMA_VME_AM_A16D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_NONPRIV THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2d00", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time("Test vme_dma_am: A32 Accesses");
-- A32_D32 supervisory BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D32 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0000", -- destination address
DMA_VME_AM_A32D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0000", -- source address
x"0000_3000", -- destination address
DMA_VME_AM_A32D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D32 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0100", -- destination address
DMA_VME_AM_A32D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0100", -- source address
x"0000_3100", -- destination address
DMA_VME_AM_A32D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D64 supervisory MBLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D64 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0200", -- destination address
DMA_VME_AM_A32D64_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D64 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0200", -- source address
x"0000_3200", -- destination address
DMA_VME_AM_A32D64_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D32 non-priviledged BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D32 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0300", -- destination address
DMA_VME_AM_A32D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0300", -- source address
x"0000_3300", -- destination address
DMA_VME_AM_A32D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D32 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D32 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0400", -- destination address
DMA_VME_AM_A32D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0400", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0400", -- source address
x"0000_3400", -- destination address
DMA_VME_AM_A32D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3400", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D64 non-priviledged MBLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D64 non-privileged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0600", -- destination address
DMA_VME_AM_A32D64_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0600", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D64 non-privileged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0600", -- source address
x"0000_3600", -- destination address
DMA_VME_AM_A32D64_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3600", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_dma_am", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_boundaries(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable offset : std_logic_vector(11 downto 0);
variable size : integer; -- number of longwords to be transmitted by DMA
BEGIN
size := 64; --257
-- test data in sram
FOR i IN 0 TO size*4+1 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001");
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME with size of 4 bytes ");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
1, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
print("Test vme_dma_boundaries: VME DMA: VME to SRAM with size of 4 bytes ");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
1, -- data block size = 1 longword
x"0020_0000", -- source address
x"0000_2000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_000c", 1, en_msg_0, TRUE, "000001"); -- clear dma err
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME with size of 0x404 longwords at offset 0x4");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_0004", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_0004", -- source address
x"0000_1000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0004" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0004" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with size of 256 bytes (exactly as large as boundary)");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_0000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_0000", -- source address
x"0000_1000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing boundary by one access");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0e0";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_1" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_1" & offset, -- source address
x"0000_2" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_1" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_1" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_2" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_2" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing boundary by two access");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0e4";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_2" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_2" & offset, -- source address
x"0000_3" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_2" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_2" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_3" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_3" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing boundary by three access");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0e8";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_3" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_3" & offset, -- source address
x"0000_4" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_3" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_3" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_4" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_4" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing after one access");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0fc";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_4" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_4" & offset, -- source address
x"0000_5" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_4" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_4" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_5" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_5" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing after two accesses");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0f8";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_5" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_5" & offset, -- source address
x"0000_6" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_5" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_5" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_6" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_6" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing after three accesses");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0f4";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_6" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_6" & offset, -- source address
x"0000_7" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_6" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_6" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_7" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_7" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
err := err_sum;
print_err("vme_dma_boundaries", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_fifo(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable offset : std_logic_vector(11 downto 0);
variable size : integer; -- number of longwords to be transmitted by DMA
constant CONST_FIFO_SIZE : integer := 256;
BEGIN
size := CONST_FIFO_SIZE;
-- test data in sram
FOR i IN 0 TO size*4+1 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001");
END LOOP;
print("Test vme_dma_fifo: SRAM TO VME AND back with size of fifo depth");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_0000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_0000", -- source address
x"0000_1000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_fifo: SRAM TO VME AND back with size of fifo depth +1");
size := CONST_FIFO_SIZE+1;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_1000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_1000", -- source address
x"0000_2000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_fifo: SRAM TO VME AND back with size of fifo depth +2");
size := CONST_FIFO_SIZE+2;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_2000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_2000", -- source address
x"0000_3000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_2000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_2000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
err := err_sum;
print_err("vme_dma_fifo", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma (
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
size : integer; -- number of longwords to be transmitted by DMA
src_adr : std_logic_vector(31 downto 0); -- DMA source address
dest_adr : std_logic_vector(31 downto 0); -- DMA destination address
vme_am : std_logic_vector(4 downto 0); -- address modifier bits of buffer descriptor
src_dev : std_logic_vector(2 downto 0); -- source device bits of buffer descriptor
dest_dev : std_logic_vector(2 downto 0); -- destination device bits of buffer descriptor
blk : std_logic; -- block(0) or single(1) access
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable bd_0xc : std_logic_vector(31 downto 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2a24d32): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
if en_msg_0 > 0 then
print_now ("VME DMA access");
print_s_std(" Source Address = ", src_adr);
if src_dev = "001" then
print (" Source Device = SRAM");
elsif src_dev = "010" then
print (" Source Device = VME");
elsif src_dev = "100" then
print (" Source Device = PCI");
else
print (" Source Device = unknown");
end if;
print_s_std(" Destination Address = ", dest_adr);
if dest_dev = "001" then
print (" Destination Device = SRAM");
elsif dest_dev = "010" then
print (" Destination Device = VME");
elsif dest_dev = "100" then
print (" Destination Device = PCI");
else
print (" Destination Device = unknown");
end if;
print_s_i (" Size in Byte = ", size*4);
end if;
bd_0xc := "0000000000000" & src_dev & '0' & dest_dev & "000" & vme_am & blk & "001";
-- config buffer descriptor
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", dest_adr, 1, 0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", dest_adr, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", src_adr, 1, 0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", src_adr, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0000" + size-1, 1, 0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0000" + size-1, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", bd_0xc, 1, 0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", bd_0xc, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, 0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2a24d32): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma: dma irq NOT asserted");
END IF;
-- clear irq request
print_now("!!!!!!");
print_now("clearing IRQ");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, 0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma: dma irq asserted");
END IF;
print_now("now IRQ should be cleared");
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_reset(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL slot1 : OUT boolean;
SIGNAL hreset_n : OUT std_logic;
SIGNAL v2p_rstn : IN std_logic;
SIGNAL vb_sysresn : IN std_logic;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0010: VME Reset (there might be WBB bus errors indicated");
print("NOT Slot1");
-- powerup board
-- shorten reset time on vme bus
hreset_n <= '0';
signal_force("/a25_tb/a25/pll/areset", "1", 0 ns, freeze, 100 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/pre_cnt_max_sig", "0000001000", 0 ns, freeze, -1 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/main_cnt_max_sig", "000000000000011", 0 ns, freeze, -1 ns, 1);
-- signal_force("/a25_tb/a25/pcie/test_pcie_core", "0000000000000001", 0 ns, freeze, -1 ns, 1);
-- signal_force("/a25_tb/a25/pcie/test_rs_serdes", "1", 0 ns, freeze, -1 ns, 1);
slot1 <= FALSE;
WAIT FOR 100 ns;
IF vb_sysresn /= '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be active");
err_sum := err_sum + 1;
END IF;
hreset_n <= '1';
WAIT FOR 1 us;
IF vb_sysresn = '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be inactive");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
print_time("check result of slot1 detection");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0018", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time(" vb_sysresn inactive?");
IF vb_sysresn = '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be inactive");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
print_time(" force vb_sysresn TO 0");
signal_force("/a25_tb/vb_sysresn", "0", 0 ns, freeze, 1000 ns, 1);
WAIT FOR 200 ns;
print_time(" v2p_rstn active?");
IF v2p_rstn /= '0' THEN
print_time(" ERROR: SIGNAL v2p_rstn should be active");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
print_time(" v2p_rstn inactive?");
IF v2p_rstn = '0' THEN
print_time(" ERROR: SIGNAL v2p_rstn should be inactive");
err_sum := err_sum + 1;
END IF;
hreset_n <= '1';
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0018", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
----------------------------
print("Slot1");
-- powerup board
-- shorten reset time on vme bus
hreset_n <= '0';
signal_force("/a25_tb/a25/pll/areset", "1", 0 ns, freeze, 100 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/pre_cnt_max_sig", "0000001000", 0 ns, freeze, -1 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/main_cnt_max_sig", "000000000000011", 0 ns, freeze, -1 ns, 1);
-- signal_force("/a25_tb/a25/pcie/test_pcie_core", "0000000000000001", 0 ns, freeze, -1 ns, 1);
-- signal_force("/a25_tb/a25/pcie/test_rs_serdes", "1", 0 ns, freeze, -1 ns, 1);
slot1 <= TRUE;
WAIT FOR 100 ns;
IF vb_sysresn /= '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be active");
err_sum := err_sum + 1;
END IF;
hreset_n <= '1';
WAIT FOR 1 us;
IF vb_sysresn = '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be inactive");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
print_time("check result of slot1 detection");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0018", x"00000001", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time(" vb_sysresn inactive?");
IF vb_sysresn = '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be inactive");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
print_time(" force vb_sysresn TO 0");
signal_force("/a25_tb/vb_sysresn", "0", 0 ns, freeze, 1000 ns, 1);
WAIT FOR 200 ns;
print_time(" v2p_rstn active?");
IF v2p_rstn /= '0' THEN
print_time(" ERROR: SIGNAL v2p_rstn should be active");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
print_time(" v2p_rstn inactive?");
IF v2p_rstn = '0' THEN
print_time(" ERROR: SIGNAL v2p_rstn should be inactive");
err_sum := err_sum + 1;
END IF;
hreset_n <= '1';
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0018", x"00000001", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_reset", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a242sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0030: VME A24 TO SRAM WRITE");
-- write to a24 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0013", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0030_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0030_0104", x"cafe_affe", 1, en_msg_0, TRUE, "111101");
wr32(terminal_in_1, terminal_out_1, x"0030_0108", x"1111_2222", 1, en_msg_0, TRUE, "111101");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"0030_0130", x"1112_1314", 1, en_msg_0, TRUE, "111101");
wr16(terminal_in_1, terminal_out_1, x"0030_0132", x"1516_1718", 1, en_msg_0, TRUE, "111101");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"0030_0140", x"1111_11aa", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0141", x"1111_bb11", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0142", x"11cc_1111", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0143", x"dd11_1111", 1, en_msg_0, TRUE, "111101");
-- write to a24 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0040_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0040_0304", x"cafe_affe", 1, en_msg_0, TRUE, "111001");
wr32(terminal_in_1, terminal_out_1, x"0040_0308", x"1111_2222", 1, en_msg_0, TRUE, "111001");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"0040_0330", x"1112_1314", 1, en_msg_0, TRUE, "111001");
wr16(terminal_in_1, terminal_out_1, x"0040_0332", x"1516_1718", 1, en_msg_0, TRUE, "111001");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"0040_0340", x"1111_11aa", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0341", x"1111_bb11", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0342", x"11cc_1111", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0343", x"dd11_1111", 1, en_msg_0, TRUE, "111001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0050_0000
WAIT FOR 1 us;
-- non privileged block transfer
wr32(terminal_in_1, terminal_out_1, x"0050_0410", x"3333_4444", 2, en_msg_0, TRUE, "111011");
WAIT FOR 100 ns;
-- supervisory block transfer
wr32(terminal_in_1, terminal_out_1, x"0050_0420", x"5555_5555", 3, en_msg_0, TRUE, "111111");
WAIT FOR 100 ns;
-- non privileged 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"0050_0450", x"1234_5678", 2, en_msg_0, TRUE, "111000");
WAIT FOR 100 ns;
-- supervisory 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"0050_0470", x"cafe_affe", 3, en_msg_0, TRUE, "111100");
WAIT FOR 100 ns;
-- read from sram
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"1111_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0132", x"1516_1314", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0140", x"ddcc_bbaa", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"1111_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0332", x"1516_1314", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0340", x"ddcc_bbaa", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0410", x"3333_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0414", x"3433_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0420", x"5555_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0424", x"5655_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0428", x"5755_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := x"1234_5678";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0454", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0450", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_045c", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0458", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := x"cafe_affe";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0474", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0470", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_047c", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0478", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0484", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0480", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test: VME A24 TO SRAM READ");
-- prepare data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"1111_2222", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0030", x"1516_1314", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0034", x"1234_5678", 1, en_msg_0, TRUE, "000001");
dat := x"1234_5678";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0044", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0040", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_004c", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0048", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0054", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0050", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_005c", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0080", x"abcd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0084", x"accd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0088", x"adcd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_008c", x"aecd_ef01", 1, en_msg_0, TRUE, "000001");
-- read from a24 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0070_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0070_0008", x"1111_2222", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"0070_0030", x"1112_1314", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"0070_0032", x"1516_1718", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"0070_0034", x"1111_1178", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0035", x"1111_5611", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0036", x"1134_1111", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0037", x"1211_1111", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0070_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0050_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0050_0008", x"1111_2222", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"0050_0030", x"1112_1314", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"0050_0032", x"1516_1718", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"0050_0034", x"1111_1178", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0035", x"1111_5611", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0036", x"1134_1111", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0037", x"1211_1111", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0050_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0080_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0080_0080", x"abcd_ef01", 2, en_msg_0, TRUE, "111111", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (non privileged block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0090_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0090_0080", x"abcd_ef01", 3, en_msg_0, TRUE, "111011", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x00a0_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"00a0_0040", x"1234_5678", 2, en_msg_0, TRUE, "111100", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x00b0_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"00b0_0040", x"1234_5678", 3, en_msg_0, TRUE, "111000", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_slave_a242sram", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a242pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
VARIABLE ex_dat : std_logic_vector(31 DOWNTO 0);
CONSTANT OFFSET : std_logic_vector(31 DOWNTO 0):=x"1000_0000";
BEGIN
print("Test MEN_01A021_00_IT_0040: VME A24 TO PCI WRITE");
-- set pci offset
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0028", x"0000_0100", 1, en_msg_0, TRUE, "000001"); -- set pci offset to 0x1000_0000
-- write to a24 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0013", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0030_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0030_0104", x"cafe_affe", 1, en_msg_0, TRUE, "111101");
wr32(terminal_in_1, terminal_out_1, x"0030_0108", x"1111_2222", 1, en_msg_0, TRUE, "111101");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"0030_0130", x"1112_1314", 1, en_msg_0, TRUE, "111101");
wr16(terminal_in_1, terminal_out_1, x"0030_0132", x"1516_1718", 1, en_msg_0, TRUE, "111101");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"0030_0140", x"1111_11aa", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0141", x"1111_bb11", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0142", x"11cc_1111", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0143", x"dd11_1111", 1, en_msg_0, TRUE, "111101");
-- write to a24 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0040_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0040_0304", x"cafe_affe", 1, en_msg_0, TRUE, "111001");
wr32(terminal_in_1, terminal_out_1, x"0040_0308", x"1111_2222", 1, en_msg_0, TRUE, "111001");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"0040_0330", x"1112_1314", 1, en_msg_0, TRUE, "111001");
wr16(terminal_in_1, terminal_out_1, x"0040_0332", x"1516_1718", 1, en_msg_0, TRUE, "111001");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"0040_0340", x"1111_11aa", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0341", x"1111_bb11", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0342", x"11cc_1111", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0343", x"dd11_1111", 1, en_msg_0, TRUE, "111001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0050_0000
WAIT FOR 1 us;
-- non privileged block transfer
wr32(terminal_in_1, terminal_out_1, x"0050_0410", x"3333_4444", 2, en_msg_0, TRUE, "111011");
WAIT FOR 100 ns;
-- supervisory block transfer
wr32(terminal_in_1, terminal_out_1, x"0050_0420", x"5555_5555", 3, en_msg_0, TRUE, "111111");
WAIT FOR 100 ns;
-- non privileged 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"0050_0450", x"1234_5678", 2, en_msg_0, TRUE, "111000");
WAIT FOR 100 ns;
-- supervisory 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"0050_0470", x"cafe_affe", 3, en_msg_0, TRUE, "111100");
WAIT FOR 2 us;
-- read from sram
rd_iram_bfm(x"0000_0104", x"cafe_affe", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0108", x"1111_2222", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0130", x"1516_1314", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0140", x"ddcc_bbaa", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0304", x"cafe_affe", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0308", x"1111_2222", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0330", x"1516_1314", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0340", x"ddcc_bbaa", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0410", x"3333_4444", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0414", x"3433_4444", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0420", x"5555_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0424", x"5655_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0428", x"5755_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := x"1234_5678";
rd_iram_bfm(x"0000_0454", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0450", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_045c", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0458", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := x"cafe_affe";
rd_iram_bfm(x"0000_0474", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0470", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_047c", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0478", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_0484", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0480", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
print("Test: VME A24 TO PCI READ");
-- prepare data in sram
wr_iram_bfm(x"0000_0004", x"cafe_affe", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0008", x"1111_2222", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0030", x"1516_1314", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0034", x"1234_5678", en_msg_0, loc_err);
dat := x"1234_5678";
wr_iram_bfm(x"0000_0044", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0040", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_004c", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0048", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_0054", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0050", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_005c", dat, en_msg_0, loc_err);
wr_iram_bfm(x"0000_0080", x"abcd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0084", x"accd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0088", x"adcd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_008c", x"aecd_ef01", en_msg_0, loc_err);
-- read from a24 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0070_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0070_0008", x"1111_2222", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"0070_0030", x"1112_1314", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"0070_0032", x"1516_1718", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"0070_0034", x"1111_1178", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0035", x"1111_5611", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0036", x"1134_1111", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0037", x"1211_1111", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0070_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0050_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0050_0008", x"1111_2222", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"0050_0030", x"1112_1314", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"0050_0032", x"1516_1718", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"0050_0034", x"1111_1178", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0035", x"1111_5611", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0036", x"1134_1111", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0037", x"1211_1111", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0050_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0080_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0080_0080", x"abcd_ef01", 2, en_msg_0, TRUE, "111111", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (non privileged block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0090_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0090_0080", x"abcd_ef01", 3, en_msg_0, TRUE, "111011", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x00a0_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"00a0_0040", x"1234_5678", 2, en_msg_0, TRUE, "111100", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x00b0_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"00b0_0040", x"1234_5678", 3, en_msg_0, TRUE, "111000", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_slave_a242pci", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE cham_test(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
CONSTANT c_REF_MODEL : std_logic_vector(7 downto 0) := x"41"; -- "A"
CONSTANT c_REF_MAJOR : std_logic_vector(7 downto 0) := x"03";
CONSTANT c_REF_MINOR : std_logic_vector(7 downto 0) := x"0A";
BEGIN
dat := x"00" & c_REF_MINOR & c_REF_MODEL & c_REF_MAJOR;
print("Test MEN_01A021_00_IT_0210: Chameleon Table");
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0000", dat, 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0004", x"0000abce", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0008", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_000c", x"32304100", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0010", x"30302d35", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0014", x"006013ff", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0018", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_001c", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0020", x"00000200", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("cham_test", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a322sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0020: VME A32 TO SRAM WRITE");
-- write to a32 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0012", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x2000_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"2000_0104", x"cafe_affe", 1, en_msg_0, TRUE, "001101");
wr32(terminal_in_1, terminal_out_1, x"2000_0108", x"1111_2222", 1, en_msg_0, TRUE, "001101");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"2000_0130", x"1112_1314", 1, en_msg_0, TRUE, "001101");
wr16(terminal_in_1, terminal_out_1, x"2000_0132", x"1516_1718", 1, en_msg_0, TRUE, "001101");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"2000_0140", x"1111_11aa", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0141", x"1111_bb11", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0142", x"11cc_1111", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0143", x"dd11_1111", 1, en_msg_0, TRUE, "001101");
-- write to a32 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x4000_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"4000_0304", x"cafe_affe", 1, en_msg_0, TRUE, "001001");
wr32(terminal_in_1, terminal_out_1, x"4000_0308", x"1111_2222", 1, en_msg_0, TRUE, "001001");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"4000_0330", x"1112_1314", 1, en_msg_0, TRUE, "001001");
wr16(terminal_in_1, terminal_out_1, x"4000_0332", x"1516_1718", 1, en_msg_0, TRUE, "001001");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"4000_0340", x"1111_11aa", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0341", x"1111_bb11", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0342", x"11cc_1111", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0343", x"dd11_1111", 1, en_msg_0, TRUE, "001001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x5000_0000
WAIT FOR 1 us;
-- non privileged block transfer
wr32(terminal_in_1, terminal_out_1, x"5000_0410", x"3333_4444", 2, en_msg_0, TRUE, "001011");
WAIT FOR 100 ns;
-- supervisory block transfer
wr32(terminal_in_1, terminal_out_1, x"5000_0420", x"5555_5555", 3, en_msg_0, TRUE, "001111");
WAIT FOR 100 ns;
-- non privileged 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"5000_0450", x"1234_5678", 2, en_msg_0, TRUE, "001000");
WAIT FOR 100 ns;
-- supervisory 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"5000_0470", x"cafe_affe", 3, en_msg_0, TRUE, "001100");
WAIT FOR 100 ns;
-- read from sram
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"1111_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0132", x"1516_1314", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0140", x"ddcc_bbaa", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"1111_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0332", x"1516_1314", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0340", x"ddcc_bbaa", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0410", x"3333_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0414", x"3433_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0420", x"5555_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0424", x"5655_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0428", x"5755_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := x"1234_5678";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0454", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0450", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_045c", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0458", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := x"cafe_affe";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0474", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0470", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_047c", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0478", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0484", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0480", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test: VME A32 TO SRAM READ");
-- prepare data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"1111_2222", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0030", x"1516_1314", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0034", x"1234_5678", 1, en_msg_0, TRUE, "000001");
dat := x"1234_5678";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0044", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0040", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_004c", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0048", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0054", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0050", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_005c", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0080", x"abcd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0084", x"accd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0088", x"adcd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_008c", x"aecd_ef01", 1, en_msg_0, TRUE, "000001");
-- read from a32 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x7000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"7000_0008", x"1111_2222", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"7000_0030", x"1112_1314", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"7000_0032", x"1516_1718", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"7000_0034", x"1111_1178", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0035", x"1111_5611", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0036", x"1134_1111", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0037", x"1211_1111", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"7000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x5000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"5000_0008", x"1111_2222", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"5000_0030", x"1112_1314", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"5000_0032", x"1516_1718", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"5000_0034", x"1111_1178", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0035", x"1111_5611", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0036", x"1134_1111", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0037", x"1211_1111", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"5000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x8000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"8000_0080", x"abcd_ef01", 2, en_msg_0, TRUE, "001111", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (non privileged block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x9000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"9000_0080", x"abcd_ef01", 3, en_msg_0, TRUE, "001011", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0xa000_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"a000_0040", x"1234_5678", 2, en_msg_0, TRUE, "001100", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0xb000_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"b000_0040", x"1234_5678", 3, en_msg_0, TRUE, "001000", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_slave_a322sram", err_sum);
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a322pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
VARIABLE ex_dat : std_logic_vector(31 DOWNTO 0);
CONSTANT OFFSET : std_logic_vector(31 DOWNTO 0):=x"2000_0000";
BEGIN
print("Test MEN_01A021_00_IT_0050: VME A32 TO PCI WRITE");
-- set bar0 offset of bfm to 0x2000_0000
init_bfm(0, x"0000_0000", x"0000_0000", x"0000_0000_0000_0000", x"0000", 256);
-- set pci offset
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0028", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- set pci offset to 0x0000_0000
-- write to a32 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0012", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x2000_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"2000_0104", x"cafe_affe", 1, en_msg_0, TRUE, "001101");
wr32(terminal_in_1, terminal_out_1, x"2000_0108", x"1111_2222", 1, en_msg_0, TRUE, "001101");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"2000_0130", x"1112_1314", 1, en_msg_0, TRUE, "001101");
wr16(terminal_in_1, terminal_out_1, x"2000_0132", x"1516_1718", 1, en_msg_0, TRUE, "001101");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"2000_0140", x"1111_11aa", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0141", x"1111_bb11", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0142", x"11cc_1111", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0143", x"dd11_1111", 1, en_msg_0, TRUE, "001101");
-- write to a32 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x4000_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"4000_0304", x"cafe_affe", 1, en_msg_0, TRUE, "001001");
wr32(terminal_in_1, terminal_out_1, x"4000_0308", x"1111_2222", 1, en_msg_0, TRUE, "001001");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"4000_0330", x"1112_1314", 1, en_msg_0, TRUE, "001001");
wr16(terminal_in_1, terminal_out_1, x"4000_0332", x"1516_1718", 1, en_msg_0, TRUE, "001001");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"4000_0340", x"1111_11aa", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0341", x"1111_bb11", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0342", x"11cc_1111", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0343", x"dd11_1111", 1, en_msg_0, TRUE, "001001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x5000_0000
WAIT FOR 1 us;
-- non privileged block transfer
wr32(terminal_in_1, terminal_out_1, x"5000_0410", x"3333_4444", 2, en_msg_0, TRUE, "001011");
WAIT FOR 100 ns;
-- supervisory block transfer
wr32(terminal_in_1, terminal_out_1, x"5000_0420", x"5555_5555", 3, en_msg_0, TRUE, "001111");
WAIT FOR 100 ns;
-- non privileged 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"5000_0450", x"1234_5678", 2, en_msg_0, TRUE, "001000");
WAIT FOR 100 ns;
-- supervisory 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"5000_0470", x"cafe_affe", 3, en_msg_0, TRUE, "001100");
WAIT FOR 1 us;
-- read from sram
rd_iram_bfm(x"0000_0104", x"cafe_affe", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0108", x"1111_2222", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
--rd_iram_bfm(x"0000_0132", x"1516_1314", en_msg_0, loc_err);
rd_iram_bfm(x"0000_0130", x"1516_1314", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0140", x"ddcc_bbaa", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0304", x"cafe_affe", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0308", x"1111_2222", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
--rd_iram_bfm(x"0000_0332", x"1516_1314", en_msg_0, loc_err);
rd_iram_bfm(x"0000_0330", x"1516_1314", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0340", x"ddcc_bbaa", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0410", x"3333_4444", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0414", x"3433_4444", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0420", x"5555_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0424", x"5655_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0428", x"5755_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := x"1234_5678";
rd_iram_bfm(x"0000_0454", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0450", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_045c", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0458", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := x"cafe_affe";
rd_iram_bfm(x"0000_0474", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0470", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_047c", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0478", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_0484", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0480", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
print("Test: VME A32 TO PCI READ");
-- prepare data in sram
wr_iram_bfm(x"0000_0004", x"cafe_affe", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0008", x"1111_2222", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0030", x"1516_1314", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0034", x"1234_5678", en_msg_0, loc_err);
dat := x"1234_5678";
wr_iram_bfm(x"0000_0044", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0040", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_004c", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0048", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_0054", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0050", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_005c", dat, en_msg_0, loc_err);
wr_iram_bfm(x"0000_0080", x"abcd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0084", x"accd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0088", x"adcd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_008c", x"aecd_ef01", en_msg_0, loc_err);
-- read from a32 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x7000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"7000_0008", x"1111_2222", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"7000_0030", x"1112_1314", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"7000_0032", x"1516_1718", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"7000_0034", x"1111_1178", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0035", x"1111_5611", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0036", x"1134_1111", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0037", x"1211_1111", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"7000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x5000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"5000_0008", x"1111_2222", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"5000_0030", x"1112_1314", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"5000_0032", x"1516_1718", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"5000_0034", x"1111_1178", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0035", x"1111_5611", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0036", x"1134_1111", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0037", x"1211_1111", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"5000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x8000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"8000_0080", x"abcd_ef01", 2, en_msg_0, TRUE, "001111", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (non privileged block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x9000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"9000_0080", x"abcd_ef01", 3, en_msg_0, TRUE, "001011", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0xa000_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"a000_0040", x"1234_5678", 2, en_msg_0, TRUE, "001100", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0xb000_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"b000_0040", x"1234_5678", 3, en_msg_0, TRUE, "001000", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_slave_a322pcie", err_sum);
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a162regs(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
VARIABLE am : std_logic_vector(5 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0060: VME A16 TO REGS");
-- A16 supervisory access
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0012", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_2000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_2014", x"0000_3412", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0013", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_3000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_3034", x"00ab_cd1f", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_4000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_4048", x"0000_7914", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_5000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_500c", x"0000_005a", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0016", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_6000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_6004", x"0000_00ab", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_7000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_701c", x"0000_0007", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_8000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_8028", x"ffff_f000", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_9000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_9000", x"0000_0007", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_a000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_a020", x"0000_0056", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_b000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_b038", x"0000_0037", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001c", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_c000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_c03c", x"0000_0037", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001d", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_d000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_d040", x"1234_5678", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001e", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_e000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_e044", x"9abc_def0", 1, en_msg_0, TRUE, "101101");
-- read back
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001e", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_3412", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"00ab_cd1f", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_7914", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_005a", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0004", x"0000_00ab", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0007", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0028", x"ffff_f000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0000", x"0000_0007", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0020", x"0000_0056", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0038", x"0000_0037", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_003c", x"0000_0037", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0040", x"1234_5678", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0044", x"9abc_def0", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16 non-privileged access
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001f", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_f000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_f014", x"0000_1214", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_f030", x"0000_0010", 1, en_msg_0, TRUE, "101001");-- set base address to 0x0000_0000
wr32(terminal_in_1, terminal_out_1, x"0000_0034", x"00ab_ab0d", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0048", x"0000_6508", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_000c", x"0000_004b", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0004", x"0000_003c", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_001c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0028", x"5678_9000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0000", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0020", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0038", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_003c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0040", x"8765_4321", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0044", x"0fed_cba9", 1, en_msg_0, TRUE, "101001");
-- read back
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0010", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_1214", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"00ab_ab0d", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_6508", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_004b", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0004", x"0000_003c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0028", x"5678_9000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0020", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0038", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_003c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0040", x"8765_4321", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0044", x"0fed_cba9", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16 non-privileged access
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0012", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_2000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_2014", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2034", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2048", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_200c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2004", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_201c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2028", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2000", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2020", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2038", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_203c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2040", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2044", x"0000_0000", 1, en_msg_0, TRUE, "101001");
err := err_sum;
print_err("vme_slave_a162regs", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0140: VME DMA: SRAM TO SRAM ");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2sram): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- test data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0004", x"1111_1111", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0004", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"2222_2222", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_000c", x"3333_3333", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_000c", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0010", x"4444_4444", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0010", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear destination in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0100", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_010c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0110", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0114", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0118", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- config buffer descriptor
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0000_0108", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0000_0108", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0004", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_1001", 1, en_msg_0, TRUE, "000001"); -- source=sram dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_1001", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2sram): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2sram: dma irq NOT asserted");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0100", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_010c", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0110", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0114", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0118", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check control reg for irq asserted
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0006", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2sram: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma_sram2sram", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0150: DMA: SRAM TO PCIe AND back");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2pci): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- test data in sram
FOR i IN 0 TO 255 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001");
END LOOP;
-- program dma: sram2pci
-- writing list of buffer descriptors to DMA_BDx registers
adr := x"000f_f900";
dat := x"00000000";
FOR i IN 0 TO 15 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", x"0000000f", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"00014000", 1, en_msg_0, TRUE, "000001");
dat := dat + x"40";
adr := adr + x"10";
END LOOP;
-- overwrite last buffer descriptor to set DMA_NULL=1 (last element of the list
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"00014001", 1, en_msg_0, TRUE, "000001");
-- Write to DMA Status Register (DMASTA): DMA_IEN | DMA_EN
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
-- WE'VE JUST ENABLED DMA, NOW IT PERFORMS THE TRANSFER
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2pci): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- here the DMA is over, we should verify data
FOR i IN 0 TO 255 LOOP
bfm_rd_shm(addr => (4*i), len => 4, dat => dat);
if dat /= std_logic_vector(to_unsigned(4*i, dat'length)) then
print_s_hl("Error at ", i);
print_s_hl("read word bfm:", dat);
err_sum := err_sum + 1;
end if;
END LOOP;
-----------------------------------------------------
-- program dma: sram2pci
adr := x"000f_f900";
dat := x"00000000";
FOR i IN 0 TO 15 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", x"0000_0100" + dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", x"0000000f", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"00041000", 1, en_msg_0, TRUE, "000001");
dat := dat + x"40";
adr := adr + x"10";
END LOOP;
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"00041001", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2pci): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
err := err_sum;
print_err("vme_dma_sram2pci", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2a32d32(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0120: VME DMA: SRAM TO VME A32D32 AND back");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2a32d32): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- test data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0208", x"3121_1101", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0208", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_020c", x"3222_1202", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_020c", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0210", x"3323_1303", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0210", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0214", x"3424_1404", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0214", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- set A32 address extension
-- wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001"); -- if generic USE_LONGADD=false
-- rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001", loc_err);
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear destination in VME_A24D32
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0004", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- clear destination in SRAM
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0300", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_030c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0310", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0314", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_02fc", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- config buffer descriptor #1 SRAM => VME_A24D32
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"3000_0004", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"3000_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0208", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0208", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_2060", 1, en_msg_0, TRUE, "000001"); -- source=sram dest=A24D32 inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_2060", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- config buffer descriptor #2 VME_A24D32 => SRAM
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0300", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0300", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"3000_0004", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"3000_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_1061", 1, en_msg_0, TRUE, "000001"); -- source=A24D32 dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_1061", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2a32d32): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a32d32: dma irq NOT asserted");
END IF;
-- check control reg for irq asserted
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0006", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0004", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000c", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0010", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check destination SRAM
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_02fc", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0300", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_030c", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0310", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2a32d32: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma_sram2a32d32", err_sum);
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2a32d64(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0130: VME DMA: SRAM TO VME A32D64 AND back");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2a32d64): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
print(" test data in sram");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0208", x"3121_1101", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0208", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_020c", x"3222_1202", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_020c", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0210", x"3323_1303", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0210", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0214", x"3424_1404", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0214", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" set A32 address extension");
-- wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001"); -- if generic USE_LONGADD=false
-- rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001", loc_err);
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" clear destination in VME_A32D32");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0004", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001");
print(" clear destination in SRAM");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0300", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_030c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0310", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0314", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_02fc", x"0000_0000", 1, en_msg_0, TRUE, "000001");
print(" config buffer descriptor #1 SRAM => VME_A32D64");
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"3000_0008", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"3000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0208", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0208", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_20e0", 1, en_msg_0, TRUE, "000001"); -- source=sram dest=A32D64 inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_20e0", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" config buffer descriptor #2 VME_A32D64 => SRAM");
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0300", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0300", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"3000_0008", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"3000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_10e1", 1, en_msg_0, TRUE, "000001"); -- source=A32D64 dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_10e1", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" start DMA transfer");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
--wait_on_irq_assert(0);
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2a32d64): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a32d64: dma irq NOT asserted");
END IF;
print(" check control reg for irq asserted");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0006", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" check destination VME_A32D32");
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0004", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000c", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0010", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0014", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" check destination SRAM");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_02fc", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0300", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_030c", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0310", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" clear irq request");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a32d64: dma irq asserted");
END IF;
print(" check control reg for end of dma");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma_sram2a32d64", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_buserror(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE irq_req_berr : integer;
VARIABLE irq_req_dma : integer;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0160: VME Bus Error");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_buserror): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
irq_req_berr := 8;
irq_req_dma := 9;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print (" VME A16/D16 single read access");
rd32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_0000", x"0000_ffff", 1, en_msg_0, FALSE, "000001", loc_err);
--wait_on_irq_assert(0);
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_berr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_berr) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001");
--wait_on_irq_deassert(0);
IF irq_req(irq_req_berr) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print (" VME A24/D16 single read access");
rd32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0000_0000", x"0000_ffff", 1, en_msg_0, FALSE, "000001", loc_err);
--wait_on_irq_assert(0);
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_berr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_berr) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001");
--wait_on_irq_deassert(0);
IF irq_req(irq_req_berr) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print (" VME A32/D32 single read access");
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"0000_0000", x"ffff_ffff", 1, en_msg_0, FALSE, "000001", loc_err);
--wait_on_irq_assert(0);
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_berr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_berr) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001");
--wait_on_irq_deassert(0);
IF irq_req(irq_req_berr) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print (" VME DMA A24/D32 read access");
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0002_10e1", 1, en_msg_0, TRUE, "000001"); -- source=A24D32 dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0002_10e1", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" start DMA transfer");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
-- check for buserror interrupt
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_berr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_berr) = '0' THEN
print_time("ERROR vme_dma_sram2pci: buserror irq NOT asserted");
END IF;
-- check for DMA interrupt
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_dma,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_dma) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_001e", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_000c", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001");
--wait_on_irq_deassert(0);
IF irq_req(irq_req_dma) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
IF irq_req(irq_req_berr) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
err := err_sum;
print_err("vme_buserror", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_master_windows(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
BEGIN
print("Test MEN_01A021_00_IT_0070: VME A16D16");
wr16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1000", x"0000_1111", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1002", x"2222_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1010", x"aa88_11ff", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1100", x"1234_5678", 10, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1010", x"aa88_11ff", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1100", x"1234_5678", 10, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1002", x"2222_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1000", x"0000_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A16D32");
wr16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1004", x"0000_1131", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1006", x"2232_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1020", x"cafe_affe", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1020", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1200", x"cafe_affe", 12, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1200", x"cafe_affe", 12, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1006", x"2232_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1004", x"0000_1131", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A24D16");
wr16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0008", x"0000_4455", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_000a", x"6677_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0030", x"1234_5678", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0030", x"1234_5678", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0040", x"1234_5678", 14, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0040", x"1234_5678", 14, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_000a", x"6677_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0008", x"0000_4455", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A24D32");
wr16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A32D32");
-- access to vme slave simmodel offset 0x3000_0000
-- depending on the generic settings, register LONGADD will be used differently:
-- -- Generic USE_LONGADD=false
-- wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001");
-- Generic USE_LONGADD=true and LONGADD_SIZE=3
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME CR/CSR");
wr16(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001");
wr8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0100", x"4433_2211", 1, en_msg_0, TRUE, "000001");
wr8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0101", x"0000_2200", 1, en_msg_0, TRUE, "000001");
wr8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0102", x"0033_0000", 1, en_msg_0, TRUE, "000001");
wr8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0103", x"4400_0000", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0100", x"0000_0011", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0101", x"0000_2200", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0102", x"0033_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0103", x"4400_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
err := err_sum;
print_err("vme_master_windows", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_arbitration(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL hreset_n : OUT std_logic;
SIGNAL slot1 : OUT boolean;
SIGNAL en_clk : OUT boolean;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
BEGIN
print("Test MEN_01A021_00_IT_0100: VME vme_arbitration ");
-- VME Arbitration:
-- powerup board
slot1 <= TRUE;
hreset_n <= '0';
en_clk <= FALSE; -- switch off clk in order to let the PLL relock => startup reset will be generated which clears sysc bit
WAIT FOR 500 ns;
en_clk <= TRUE;
WAIT FOR 50 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0002", 1, en_msg_0, TRUE, "000001"); -- set RWD
vme_arbiter(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- powerup board
slot1 <= FALSE;
hreset_n <= '0';
en_clk <= FALSE; -- switch off clk in order to let the PLL relock => startup reset will be generated which clears sysc bit
WAIT FOR 500 ns;
en_clk <= TRUE;
WAIT FOR 50 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0002", 1, en_msg_0, TRUE, "000001"); -- set RWD
vme_arbiter(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
--
-- VME Arbitration:
-- powerup board
slot1 <= TRUE;
hreset_n <= '0';
en_clk <= FALSE; -- switch off clk in order to let the PLL relock => startup reset will be generated which clears sysc bit
WAIT FOR 500 ns;
en_clk <= TRUE;
WAIT FOR 50 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- clear RWD
vme_arbiter(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- powerup board
slot1 <= FALSE;
hreset_n <= '0';
en_clk <= FALSE; -- switch off clk in order to let the PLL relock => startup reset will be generated which clears sysc bit
WAIT FOR 500 ns;
en_clk <= TRUE;
WAIT FOR 50 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- set RWD
vme_arbiter(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_arbitration", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_arbiter(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
BEGIN
print("Test MEN_01A021_00_IT_0100: VME Arbitration ");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_1010", 1, en_msg_0, TRUE, "000001"); -- activate A24 vme slave
WAIT FOR 1 us;
print("Test: VME A16D16");
wr16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1000", x"0000_1111", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_1, terminal_out_1, x"0100_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1002", x"2222_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_1, terminal_out_1, x"0100_0008", x"1111_1111", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1010", x"aa88_11ff", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_1, terminal_out_1, x"0100_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111001", loc_err); -- read from a24 vme slave
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1010", x"aa88_11ff", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1002", x"2222_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0100_0008", x"1111_1111", 1, en_msg_0, TRUE, "111001", loc_err); -- read from a24 vme slave
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1000", x"0000_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A16D32");
wr16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1004", x"0000_1131", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_1, terminal_out_1, x"0100_0014", x"2222_2222", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1006", x"2232_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_1, terminal_out_1, x"0100_0018", x"3333_3333", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1020", x"cafe_affe", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1020", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_1, terminal_out_1, x"0100_001c", x"4444_4444", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
rd16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1006", x"2232_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_1, terminal_out_1, x"0100_0020", x"5555_5555", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
rd16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1004", x"0000_1131", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_1, terminal_out_1, x"0100_0024", x"6666_6666", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr32(terminal_in_1, terminal_out_1, x"0100_0028", x"7777_7777", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A24D16");
wr16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0008", x"0000_4455", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_1, terminal_out_1, x"0100_0014", x"2222_2222", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
wr16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_000a", x"6677_0000", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_1, terminal_out_1, x"0100_0018", x"3333_3333", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0030", x"1234_5678", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_1, terminal_out_1, x"0100_001c", x"4444_4444", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0030", x"1234_5678", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0100_0020", x"5555_5555", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_000a", x"6677_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0100_0024", x"6666_6666", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0008", x"0000_4455", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0100_0028", x"7777_7777", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A24D32");
wr16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
err := err_sum;
print_err("vme_arbiter", err_sum);
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE vme_irq_rcv(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0090: Interrupt Handler");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_irq_rcv): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- enable receiving interrupts
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_00ff", 1, en_msg_0, TRUE, "000001");
rd8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_00ff", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 150 ns;
FOR i IN 1 TO 7 LOOP
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => i,
msi_expected => var_msi_expected
);
irq_vme_slv (vme_slv_in, vme_slv_out, i, x"00"+i);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_irq_rcv): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(i+4) = '0' THEN -- acfail + vme_irq is irq_req(11:5)
print_time("ERROR vme_irq_rcv: wrong irq asserted");
END IF;
dat:=x"00"+i & x"00"+i & x"00"+i & x"00"+i;
rd8(terminal_in_0, terminal_out_0, VME_IACK + (2*i) + 1, dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 300 ns;
END LOOP;
-- disable receiving interrupts
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
rd8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
err := err_sum;
print_err("vme_irq_rcv", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_irq_trans(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0080: Interrupter");
FOR i IN 1 TO 7 LOOP
IF vme_slv_out.irq(i) = '0' THEN
print_time("ERROR: VME irqs should NOT be active!");
END IF;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0000", x"0000_0008" + i, 1, en_msg_0, TRUE, "000001"); -- set interrupt request on line x
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0004", x"0000_0000" + i, 1, en_msg_0, TRUE, "000001"); -- set interrupt id
wl: FOR j IN 0 TO 1000 LOOP
IF vme_slv_out.irq(i) = '0' THEN
print_time("exit");
exit wl;
END IF;
WAIT FOR 10 ns;
END LOOP;
dat:=x"00"+i & x"00"+i & x"00"+i & x"00"+i;
rd8_iack(terminal_in_1, terminal_out_1, VME_IACK + (2*i), dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
END LOOP;
err := err_sum;
print_err("vme_irq_trans", err_sum);
END PROCEDURE;
procedure configure_bfm(
signal terminal_in : in terminal_in_type;
signal terminal_out : out terminal_out_type;
bar0_addr : std_logic_vector(31 downto 0);
bar1_addr : std_logic_vector(31 downto 0);
bar2_addr : std_logic_vector(31 downto 0);
bar3_addr : std_logic_vector(31 downto 0);
bar4_addr : std_logic_vector(31 downto 0);
bar5_addr : std_logic_vector(31 downto 0);
txt_out : integer
) is
begin
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR0");
end if;
wr32(terminal_in, terminal_out, x"0000_0000", bar0_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR1");
end if;
wr32(terminal_in, terminal_out, x"0000_0001", bar1_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR2");
end if;
wr32(terminal_in, terminal_out, x"0000_0002", bar2_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR3");
end if;
wr32(terminal_in, terminal_out, x"0000_0003", bar3_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR4");
end if;
wr32(terminal_in, terminal_out, x"0000_0004", bar4_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR5");
end if;
wr32(terminal_in, terminal_out, x"0000_0005", bar5_addr, 1, txt_out, TRUE, "000011");
end procedure configure_bfm;
END;
vme_sim_mon.vhd 0000664 0000000 0000000 00000023243 14574545710 0035365 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : VME bus monitor
-- Project : A15
---------------------------------------------------------------
-- File : vme_sim_mon.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 02/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: vme_sim_mon.vhd,v $
-- Revision 1.1 2012/03/29 10:28:46 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/18 14:31:24 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:14 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:28:12 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee,work;
USE ieee.std_logic_1164.ALL;
USE work.vme_sim_pack.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.print_pkg.all;
ENTITY vme_sim_mon IS
PORT (
rstn : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
dtackn_in : IN std_logic;
berrn_in : IN std_logic;
addr_in : IN std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn : IN std_logic;
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
bbsyn_in : IN std_logic;
vme_mon_out : OUT vme_mon_out_type
);
END vme_sim_mon;
ARCHITECTURE vme_sim_mon_arch OF vme_sim_mon IS
BEGIN
vme_mon_out.err <= 0;
irq_1 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq1n);
print_time("vme_sim_mon: IRQ1 was asserted");
WAIT until rising_edge(vb_irq1n);
print_time("vme_sim_mon: IRQ1 was deasserted");
END PROCESS irq_1;
irq_2 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq2n);
print_time("vme_sim_mon: IRQ2 was asserted");
WAIT until rising_edge(vb_irq2n);
print_time("vme_sim_mon: IRQ2 was deasserted");
END PROCESS irq_2;
irq_3 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq3n);
print_time("vme_sim_mon: IRQ3 was asserted");
WAIT until rising_edge(vb_irq3n);
print_time("vme_sim_mon: IRQ3 was deasserted");
END PROCESS irq_3;
irq_4 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq4n);
print_time("vme_sim_mon: IRQ4 was asserted");
WAIT until rising_edge(vb_irq4n);
print_time("vme_sim_mon: IRQ4 was deasserted");
END PROCESS irq_4;
irq_5 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq5n);
print_time("vme_sim_mon: IRQ5 was asserted");
WAIT until rising_edge(vb_irq5n);
print_time("vme_sim_mon: IRQ5 was deasserted");
END PROCESS irq_5;
irq_6 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq6n);
print_time("vme_sim_mon: IRQ6 was asserted");
WAIT until rising_edge(vb_irq6n);
print_time("vme_sim_mon: IRQ6 was deasserted");
END PROCESS irq_6;
irq_7 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq7n);
print_time("vme_sim_mon: IRQ7 was asserted");
WAIT until rising_edge(vb_irq7n);
print_time("vme_sim_mon: IRQ7 was deasserted");
END PROCESS irq_7;
d_timing : PROCESS
VARIABLE zeit : time;
BEGIN
WAIT until rstn = '1';
LOOP
WAIT until falling_edge(dtackn_in);
IF writen_in = '1' THEN -- read
IF NOT data_in'stable(time_27) THEN
print_time("vme_sim_mon: Data[31:0] was not stable for time(27)!");
END IF;
zeit:=now;
WAIT until rising_edge(dsan_in) OR rising_edge(dsbn_in);
IF data_in'last_active > (now-zeit) THEN
print_time("vme_sim_mon: Data[31:0] was not stable for time(20)!");
END IF;
WAIT until rising_edge(dtackn_in);
IF NOT is_x(data_in)THEN
print_time("vme_sim_mon: Data[31:0] was not 'Z' (time(31))!");
END IF;
ELSE
IF NOT data_in'stable(time_28) THEN
print_time("vme_sim_mon: Data[31:0] was not stable for time(28)!");
END IF;
IF NOT dsan_in'stable(time_28) THEN
print_time("vme_sim_mon: dsan was not stable for time(28)!");
END IF;
IF NOT dsbn_in'stable(time_28) THEN
print_time("vme_sim_mon: dsbn was not stable for time(28)!");
END IF;
IF NOT data_in'stable(time_28 + time_8) THEN
print_time("vme_sim_mon: dsbn was not stable for time(28)!");
END IF;
IF NOT (dsan_in = '0' OR dsbn_in = '0') THEN
print_time("vme_sim_mon: dsan or dsbn must be asserted!");
END IF;
END IF;
END LOOP;
END PROCESS d_timing;
adr_timing : PROCESS
VARIABLE zeit : time;
BEGIN
WAIT until rstn = '1';
LOOP
WAIT until falling_edge(asn_in);
zeit := now;
WAIT until falling_edge(dtackn_in);
IF addr_in'last_active > (now-zeit + time_4) THEN
print_time("vme_sim_mon: addr_in was not stable for time(4) or time(14)!");
END IF;
WAIT until rising_edge(asn_in);
END LOOP;
END PROCESS adr_timing;
--adr_x : PROCESS
-- BEGIN
-- LOOP
-- WAIT on addr_in;
-- IF is_x(addr_in)THEN
-- print_time("vme_sim_mon: addr_in[31:0] was 'X'!");
-- END IF;
-- END LOOP;
-- END PROCESS adr_x;
--
--dat_x : PROCESS
-- BEGIN
-- LOOP
-- WAIT on data_in;
-- IF is_x(data_in)THEN
-- print_time("vme_sim_mon: data_in[31:0] was 'X'!");
-- END IF;
-- END LOOP;
-- END PROCESS dat_x;
asn_timing : PROCESS
BEGIN
WAIT until rstn = '1';
LOOP
IF asn_in /= '0' THEN
WAIT until asn_in = '0';
END IF;
WAIT FOR time_19;
IF NOT asn_in'stable(time_19) then
print_time("vme_sim_mon: ASn was not long enough asserted (time(19))!");
END IF;
IF asn_in = '0' THEN
WAIT until asn_in /= '0';
END IF;
END LOOP;
END PROCESS asn_timing;
am_timing : PROCESS
VARIABLE am_time : time;
BEGIN
WAIT until rstn = '1';
LOOP
IF asn_in /= '0' THEN
WAIT until asn_in = '0';
END IF;
am_time := now;
IF is_x(am_in) THEN
print_time("vme_sim_mon: AM[5:0] is not a real value ('0' or '1')!");
END IF;
IF NOT am_in'stable(time_4) then
print_time("vme_sim_mon: AM[5:0] was not stable for time(4)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
IF is_x(addr_in) THEN
print_time("vme_sim_mon: AM[5:0] is not a real value ('0' or '1')!");
END IF;
IF NOT addr_in'stable(time_4) then
print_time("vme_sim_mon: ADDR[31:0] was not stable for time(4)!");
END IF;
IF dtackn_in /= '0' THEN
WAIT until dtackn_in = '0';
END IF;
IF am_in'last_active < (time_4 + (now - am_time)) then
print_time("vme_sim_mon: AM[5:0] was not stable during access (time(4), time(16))!");
END IF;
IF addr_in'last_active < (time_4 + (now - am_time)) then
print_time("vme_sim_mon: ADDR[31:0] was not stable during access (time(4), time(16))!");
END IF;
IF asn_in = '0' THEN
WAIT until asn_in /= '0';
END IF;
-- WAIT FOR 5 ns; -- this time is not allowed!!!
IF NOT is_x(addr_in) THEN
print("vme_sim_mon: Adr[31:0] is not 'Z' after asn goes high (time(24a))!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY warning;
END IF;
IF NOT is_x(am_in) THEN
print("vme_sim_mon: AM[5:0] is not 'Z' after asn goes high (time(24a))!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY warning;
END IF;
IF NOT is_x(data_in) THEN
print("vme_sim_mon: Data_in[31:0] is not 'Z' after asn goes high (time(24a))!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY warning;
END IF;
END LOOP;
END PROCESS am_timing;
--write_timing : PROCESS
-- VARIABLE write_time : time;
-- BEGIN
-- IF arst_sig = '1' THEN
-- IF dsan_in = '1' THEN
-- WAIT until dsan_in = '0';
-- write_time := now;
-- IF NOT writen_in'stable(time_12) then
-- print("vme_sim_mon: WRITEN was not stable for time(12)!");
-- ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
-- END IF;
-- IF dsan_in = '0' THEN
-- WAIT until dsan_in = '1';
-- END IF;
-- IF dsbn_in = '0' THEN
-- WAIT until dsbn_in = '1';
-- END IF;
-- WAIT FOR time_23;
-- IF writen_in'last_active > (time_12 + (now - write_time)) then
-- print("vme_sim_mon: WRITEN was not stable during access (time(12), time(23))!");
-- ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
-- END IF;
-- END IF;
-- end if;
-- END PROCESS write_timing;
END vme_sim_mon_arch;
vme_sim_mstr.vhd 0000664 0000000 0000000 00000016736 14574545710 0035572 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : VME Simulation Master Model
-- Project : 16z002-
---------------------------------------------------------------
-- File : vme_sim_mstr.vhd
-- Author : Michael Miehling
-- Email : michael.miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 14/02/12
---------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
---------------------------------------------------------------
-- Description :
--
-- Design consists of VME Master behavioral model and an arbiter.
-- The arbiter gets active if after startup the bg3n line is '0'.
-- The master model can read or write up to 32bit and 64bit
-- data width.
-- The control of the model is via terminal connection.
---------------------------------------------------------------
-- Hierarchy:
--
-- vme_sim_pack.vhd
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_sim_mstr.vhd,v $
-- Revision 1.2 2013/04/18 15:11:12 MMiehling
-- rework
--
-- Revision 1.1 2012/03/29 10:28:47 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.terminal_pkg.all;
USE work.vme_sim_pack.all;
USE work.print_pkg.all;
ENTITY vme_sim_mstr IS
PORT (
sysresn : INOUT std_logic;
asn : INOUT std_logic;
dsan : INOUT std_logic;
dsbn : INOUT std_logic;
writen : INOUT std_logic;
dtackn : IN std_logic;
berrn : INOUT std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data : INOUT std_logic_vector(31 DOWNTO 0);
am : INOUT std_logic_vector(5 DOWNTO 0);
iackn : INOUT std_logic;
iackout : OUT std_logic;
iackin : IN std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_acfailn : INOUT std_logic;
bg3n_in : IN std_logic;
bg3n_out : OUT std_logic;
brn : INOUT std_logic_vector(3 DOWNTO 0);
bbsyn : INOUT std_logic;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type
);
END vme_sim_mstr;
ARCHITECTURE vme_sim_mstr_arch OF vme_sim_mstr IS
SIGNAL mstr_in : mstr_in_type;
SIGNAL mstr_out : mstr_out_type;
SIGNAL sim_slot1 : boolean;
SIGNAL bg3n_int : std_logic;
SIGNAL bg3n_sim : std_logic;
SIGNAL busy : std_logic;
BEGIN
vb_irq1n <= 'H';
vb_irq2n <= 'H';
vb_irq3n <= 'H';
vb_irq4n <= 'H';
vb_irq5n <= 'H';
vb_irq6n <= 'H';
vb_irq7n <= 'H';
vb_acfailn <= 'H';
mstr_in.data <= data;
mstr_in.addr <= addr;
mstr_in.dtackn <= dtackn ;
mstr_in.berrn <= berrn ;
mstr_in.iackin <= iackin ;
mstr_in.bg3n_in <= bg3n_sim;
mstr_in.bbsyn <= bbsyn ;
mstr_in.asn <= asn ;
sysresn <= mstr_out.sysresn ;
asn <= mstr_out.asn ;
dsan <= mstr_out.dsan ;
dsbn <= mstr_out.dsbn ;
writen <= mstr_out.writen ;
addr <= mstr_out.addr ;
data <= mstr_out.data ;
am <= mstr_out.am ;
iackn <= mstr_out.iackn ;
iackout <= mstr_out.iackout ;
brn <= mstr_out.brn ;
bbsyn <= mstr_out.bbsyn ;
berrn <= mstr_out.berrn ;
sl1_det: PROCESS(sysresn)
BEGIN
IF rising_edge(sysresn) AND bg3n_in = '0' THEN
sim_slot1 <= TRUE;
ELSIF rising_edge(sysresn) AND bg3n_in = '1' THEN
sim_slot1 <= FALSE;
END IF;
END PROCESS sl1_det;
sim_arbiter: PROCESS(bg3n_in, sysresn, bbsyn, brn, sim_slot1)
BEGIN
IF sysresn = '0' THEN
bg3n_int <= '1';
bg3n_sim <= '0';
ELSIF sim_slot1 = TRUE THEN -- sim model is in slot1
-- IF brn(3) = '0' AND bbsyn /= '0' THEN -- there is a request
-- bg3n_int <= '0';
-- ELSE
-- bg3n_int <= '1';
-- END IF;
IF mstr_out.brn(3) = '0' AND bbsyn /= '0' AND bg3n_int /= '0' THEN -- there is a request from simmaster and no grant to dut
bg3n_int <= '1';
bg3n_sim <= '0'; -- grant TO simmaster
ELSIF brn(3) = '0' AND bbsyn /= '0' THEN -- there is a request from dut
bg3n_int <= '0'; -- grant to dut
bg3n_sim <= '1';
ELSE
bg3n_int <= '1';
bg3n_sim <= '1';
END IF;
ELSE
bg3n_int <= '1';
bg3n_sim <= bg3n_in;
END IF;
END PROCESS sim_arbiter;
bg3n_out <= bg3n_int;
main: PROCESS
VARIABLE ind_err : integer;
VARIABLE err : integer;
VARIABLE vme_typ : character;
VARIABLE in_data : std_logic_vector(31 DOWNTO 0);
BEGIN
-- reset phase
err := 0;
vme_mstr_init(mstr_out);
terminal_in_x.done <= TRUE;
terminal_in_x.busy <= '0';
busy <= '0';
LOOP
WAIT on terminal_out_x.start;
busy <= '1';
terminal_in_x.busy <= '1';
IF terminal_out_x.typ = 0 THEN
vme_typ := 'b';
ELSIF terminal_out_x.typ = 1 THEN
vme_typ := 'w';
ELSIF terminal_out_x.typ = 2 THEN
vme_typ := 'l';
ELSIF terminal_out_x.typ = 3 THEN
vme_typ := 'd';
ELSIF terminal_out_x.typ = 4 THEN
vme_typ := 'i';
ELSE
print("vme_sim_mstr: wrong terminal.typ coding!");
END IF;
IF vme_typ = 'd' AND terminal_out_x.wr = 0 AND terminal_out_x.numb > 1 THEN -- 64 bit read
vme_mstr_read64(mstr_out, mstr_in, terminal_out_x.adr, terminal_out_x.dat, in_data, vme_typ, terminal_out_x.txt, terminal_out_x.numb, terminal_out_x.tga, err);
ELSIF vme_typ = 'd' AND terminal_out_x.wr = 1 AND terminal_out_x.numb > 1 THEN -- 64 bit write
vme_mstr_write64(mstr_out, mstr_in, terminal_out_x.adr, terminal_out_x.dat, vme_typ, terminal_out_x.txt, terminal_out_x.numb, terminal_out_x.tga);
ELSIF terminal_out_x.wr = 0 THEN -- 32 or 16 or 8 bit read
vme_mstr_read(mstr_out, mstr_in, terminal_out_x.adr, terminal_out_x.dat, in_data, vme_typ, terminal_out_x.txt, terminal_out_x.numb, terminal_out_x.tga, err);
ELSIF terminal_out_x.wr = 1 THEN -- 32 or 16 or 8 bit write
vme_mstr_write(mstr_out, mstr_in, terminal_out_x.adr, terminal_out_x.dat, vme_typ, terminal_out_x.txt, terminal_out_x.numb, terminal_out_x.tga);
ELSIF terminal_out_x.wr = 2 THEN -- wait
WAIT FOR terminal_out_x.numb * 10 ns;
ELSE
print("vme_sim_mstr: wrong terminal.wr coding!");
END IF;
terminal_in_x.dat <= in_data;
terminal_in_x.err <= err;
terminal_in_x.busy <= '0';
busy <= '0';
terminal_in_x.done <= terminal_out_x.start;
END LOOP;
END PROCESS;
END vme_sim_mstr_arch;
vme_sim_pack.vhd 0000664 0000000 0000000 00000146641 14574545710 0035522 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : vme Simulation Model Package
-- Project : none
---------------------------------------------------------------
-- File : vme_sim_pack.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 03/02/03
---------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : no
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_sim_pack.vhd,v $
-- Revision 1.2 2013/04/18 15:11:14 MMiehling
-- added vme_mstr_read64
--
-- Revision 1.1 2012/03/29 10:28:48 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.standard.ALL;
USE std.textio.all;
USE ieee.std_logic_textio.all;
USE work.print_pkg.all;
PACKAGE vme_sim_pack IS
--------------------------------TYPES-------------------------------------------
CONSTANT time_4 : time:= 35 ns;
CONSTANT time_5 : time:= 40 ns;
CONSTANT time_28 : time:= 30 ns;
CONSTANT time_27 : time:= 25 ns;
CONSTANT time_26 : time:= 5 ns; -- usually 0ns
CONSTANT time_19 : time:= 40 ns;
CONSTANT time_8 : time:= 35 ns;
CONSTANT time_12 : time:= 35 ns;
CONSTANT time_23 : time:= 10 ns;
CONSTANT time_11 : time:= 40 ns;
CONSTANT sl_base_A16 : std_logic_vector(3 DOWNTO 0):= "0001"; -- vme base address for A16 slave = 0x1000
CONSTANT sl_base_A24 : std_logic_vector(3 DOWNTO 0):= "0010"; -- vme base address for A24 slave = 0x20_0000
CONSTANT sl_base_CRCSR : std_logic_vector(3 DOWNTO 0):= "0100"; -- vme base address for CR/CSR slave = 0x40_0000
CONSTANT sl_base_A32 : std_logic_vector(3 DOWNTO 0):= "0011"; -- vme base address for A32 slave = 0x3000_0000
-- Address Modifiers
CONSTANT AM_A24_SUPER_BLT : std_logic_vector(5 DOWNTO 0):="111111";
CONSTANT AM_A24_SUPER_PROG : std_logic_vector(5 DOWNTO 0):="111110";
CONSTANT AM_A24_SUPER_DAT : std_logic_vector(5 DOWNTO 0):="111101";
CONSTANT AM_A24_SUPER_MBLT : std_logic_vector(5 DOWNTO 0):="111100";
CONSTANT AM_A24_NONPRIV_BLT : std_logic_vector(5 DOWNTO 0):="111011";
CONSTANT AM_A24_NONPRIV_PROG : std_logic_vector(5 DOWNTO 0):="111010";
CONSTANT AM_A24_NONPRIV_DAT : std_logic_vector(5 DOWNTO 0):="111001";
CONSTANT AM_A24_NONPRIV_MBLT : std_logic_vector(5 DOWNTO 0):="111000";
CONSTANT AM_CRCSR : std_logic_vector(5 DOWNTO 0):="101111";
CONSTANT AM_A16_SUPER : std_logic_vector(5 DOWNTO 0):="101101";
CONSTANT AM_A16_NONPRIV : std_logic_vector(5 DOWNTO 0):="101001";
CONSTANT AM_A32_SUPER_BLT : std_logic_vector(5 DOWNTO 0):="001111";
CONSTANT AM_A32_SUPER_PROG : std_logic_vector(5 DOWNTO 0):="001110";
CONSTANT AM_A32_SUPER_DAT : std_logic_vector(5 DOWNTO 0):="001101";
CONSTANT AM_A32_SUPER_MBLT : std_logic_vector(5 DOWNTO 0):="001100";
CONSTANT AM_A32_NONPRIV_BLT : std_logic_vector(5 DOWNTO 0):="001011";
CONSTANT AM_A32_NONPRIV_PROG : std_logic_vector(5 DOWNTO 0):="001010";
CONSTANT AM_A32_NONPRIV_DAT : std_logic_vector(5 DOWNTO 0):="001001";
CONSTANT AM_A32_NONPRIV_MBLT : std_logic_vector(5 DOWNTO 0):="001000";
SUBTYPE adr_type2 IS string(8 DOWNTO 1);
SUBTYPE adr_type IS std_logic_vector(31 DOWNTO 0);
SUBTYPE vec4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE am_type IS std_logic_vector(5 DOWNTO 0);
SUBTYPE data_type IS std_logic_vector(31 DOWNTO 0);
SUBTYPE data_type8 IS string(8 DOWNTO 1);
SUBTYPE data_type4 IS string(4 DOWNTO 1);
SUBTYPE data_type2 IS string(2 DOWNTO 1);
TYPE vme_mon_out_type IS record
err : integer;
END record;
------------------------------------------------------------------------------------------------------------------
-- vme_sim_mstr
------------------------------------------------------------------------------------------------------------------
TYPE mstr_in_type IS record
data : std_logic_vector(31 DOWNTO 0);
addr : std_logic_vector(31 DOWNTO 0);
dtackn : std_logic;
berrn : std_logic;
iackin : std_logic;
bg3n_in : std_logic;
bbsyn : std_logic;
asn : std_logic;
END record;
TYPE mstr_out_type IS record
sysresn : std_logic;
asn : std_logic;
dsan : std_logic;
dsbn : std_logic;
writen : std_logic;
addr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
am : std_logic_vector(5 DOWNTO 0);
iackn : std_logic;
iackout : std_logic;
brn : std_logic_vector(3 DOWNTO 0);
bbsyn : std_logic;
berrn : std_logic;
END record;
PROCEDURE vme_mstr_init (
SIGNAL mstr_out : OUT mstr_out_type
);
PROCEDURE vme_mstr_write (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0)
);
PROCEDURE vme_mstr_read (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
ex_data : std_logic_vector(31 DOWNTO 0);
in_data : OUT std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0);
err : OUT integer
) ;
PROCEDURE vme_mstr_write64 (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0)
);
PROCEDURE vme_mstr_read64 (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
ex_data : std_logic_vector(31 DOWNTO 0);
in_data : OUT std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0);
err : OUT integer
) ;
------------------------------------------------------------------------------------------------------------------
-- vme_sim_slv
------------------------------------------------------------------------------------------------------------------
TYPE vme_slv_in_type IS record
conf_req : boolean; -- changes on signal will call vme_sim_slv subfunctions
req_type : integer; -- if set to 0 during conf_req state changes, write request to iram is requested
-- if set to 1 during conf_req state changes, read request from iram is requested
-- if set to 2 during conf_req state changes, interrupt request will be set to active
-- if set to 3 during conf_req state changes, address modifier of last access to slave is requested
adr : std_logic_vector(31 DOWNTO 0); -- address for config read write access
wr_dat : std_logic_vector(31 DOWNTO 0); -- write data to iram
irq : integer range 7 DOWNTO 0;
END record;
TYPE vme_slv_out_type IS record
conf_ack : boolean; -- if conf_req has changed state, subfunction end will result in conf_ack state change
rd_dat : std_logic_vector(31 DOWNTO 0); -- read data to iram
irq : std_logic_vector(7 DOWNTO 1);
rd_am : std_logic_vector(5 downto 0); -- address modifier of last access
END record;
TYPE mem_entry;
TYPE entry_ptr IS access mem_entry;
TYPE mem_entry IS record
address : integer;
data : std_logic_vector(31 DOWNTO 0);
nxt : entry_ptr;
END record;
TYPE head IS record
num_entries : integer;
list_ptr : entry_ptr;
END record;
TYPE head_ptr IS access head;
PROCEDURE wr_data (
CONSTANT location : IN integer;
CONSTANT data : IN std_logic_vector;
CONSTANT byte : IN std_logic_vector(3 DOWNTO 0);
VARIABLE first : INOUT head_ptr
);
PROCEDURE rd_data (
CONSTANT location : IN integer;
VARIABLE data : OUT std_logic_vector;
VARIABLE allocated : OUT boolean;
VARIABLE first : INOUT head_ptr
);
PROCEDURE rd_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
adr : IN std_logic_vector(31 DOWNTO 0);
dat : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE wr_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
adr : IN std_logic_vector(31 DOWNTO 0);
dat : IN std_logic_vector(31 DOWNTO 0)
) ;
PROCEDURE am_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
am : OUT std_logic_vector(5 DOWNTO 0)
) ;
PROCEDURE init_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type
) ;
PROCEDURE irq_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
irq : IN integer range 7 DOWNTO 0;
dat : IN std_logic_vector(7 DOWNTO 0)
) ;
------------------------------------CONSTANTS----------------------------
FUNCTION hex_to_bit_vect (char_code : character) RETURN vec4;
FUNCTION conv_addr (addr : adr_type2) RETURN adr_type;
FUNCTION conv_data2 (data : data_type2; adr : adr_type) RETURN data_type;
FUNCTION conv_data4 (data : data_type4; adr : adr_type) RETURN data_type;
FUNCTION conv_data8 (data : data_type8) RETURN data_type;
FUNCTION conv_am (data : data_type2) RETURN am_type;
FUNCTION TO_HEX_STRING(val : std_logic_vector) RETURN string;
FUNCTION hex_to_character (hex_value : std_logic_vector(3 downto 0)) RETURN character;
PROCEDURE print(txt_out: IN integer; s: in string);
END vme_sim_pack;
-----------------------------------------------------------------------------------------------
PACKAGE BODY vme_sim_pack IS
PROCEDURE print(txt_out: IN integer; s: in string) is
variable l: line;
BEGIN
IF txt_out > 2 THEN
write(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
write(l, s);
writeline(output,l);
END IF;
END print;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_init (
SIGNAL mstr_out : OUT mstr_out_type
) IS
BEGIN
mstr_out.sysresn <= '0';
mstr_out.asn <= 'H';
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
mstr_out.writen <= 'H';
mstr_out.addr <= (OTHERS => 'H');
mstr_out.data <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.iackn <= 'H';
mstr_out.iackout <= 'H';
mstr_out.brn <= (OTHERS => 'H');
mstr_out.bbsyn <= 'H';
mstr_out.berrn <= 'H';
WAIT FOR 10 ns;
mstr_out.sysresn <= 'H';
END PROCEDURE vme_mstr_init;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_write (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0)
) IS
VARIABLE dsan : std_logic;
VARIABLE dsbn : std_logic;
VARIABLE vme_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat_out : std_logic_vector(31 DOWNTO 0);
VARIABLE cnt : integer;
VARIABLE time_dat_changed : time;
BEGIN
print(txt_out, "VME_SIM_MSTR: do we have bus arbitration?");
IF mstr_in.bg3n_in /= '0' THEN
mstr_out.brn <= "0HHH"; -- request bus
WAIT until falling_edge(mstr_in.bg3n_in); -- wait until bus grant
END IF;
print(txt_out, "VME_SIM_MSTR: wait until prior access has finished");
IF mstr_in.bbsyn = '0' THEN
WAIT until rising_edge(mstr_in.bbsyn);
END IF;
-- occupy bus
mstr_out.bbsyn <= '0', 'H' AFTER 90 ns;
-- prepare
cnt := 0;
vme_adr := adress;
dat_out := (OTHERS => '0');
IF mode = 'b' THEN -- byte access
CASE adress(1 DOWNTO 0) IS
WHEN "00" => dsan := '1'; -- B0
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(7 DOWNTO 0);
WHEN "01" => dsan := '0'; -- B1
dsbn := '1';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
dat_out(7 DOWNTO 0) := data(15 DOWNTO 8);
WHEN "10" => dsan := '1'; -- B2
dsbn := '0';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(23 DOWNTO 16);
WHEN "11" => dsan := '0'; -- B3
dsbn := '1';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
dat_out(7 DOWNTO 0) := data(31 DOWNTO 24);
WHEN OTHERS => dsan := '1';
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(7 DOWNTO 0);
END CASE;
ELSIF mode = 'w' THEN -- word access
IF adress(1) = '0' THEN
dsan := '0'; -- B0,B1
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(7 DOWNTO 0);
dat_out(7 DOWNTO 0) := data(15 DOWNTO 8);
ELSE
dsan := '0'; -- B2, B3
dsbn := '0';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
dat_out(15 DOWNTO 8) := data(23 DOWNTO 16);
dat_out(7 DOWNTO 0) := data(31 DOWNTO 24);
END IF;
ELSE -- long access (mode='l')
dsan := '0'; -- B0, B1, B2, B3
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '0'; --lwordn
dat_out(31 DOWNTO 24) := data(7 DOWNTO 0);
dat_out(23 DOWNTO 16) := data(15 DOWNTO 8);
dat_out(15 DOWNTO 8) := data(23 DOWNTO 16);
dat_out(7 DOWNTO 0) := data(31 DOWNTO 24);
END IF;
print(txt_out, "VME_SIM_MSTR: start of vme access");
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.addr <= vme_adr;
mstr_out.am <= tga;
mstr_out.writen <= '0';
WAIT FOR 40 ns;
mstr_out.asn <= '0';
WAIT FOR 5 ns;
mstr_out.brn <= "HHHH"; -- release bus arbitration
print(txt_out, "VME_SIM_MSTR: data phase");
dat_phase: LOOP
mstr_out.data <= dat_out;
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn");
IF txt_out > 1 THEN
print_mtest("VME_MSTR: WRITE ", adress, dat_out, dat_out, TRUE);
END IF;
WAIT FOR 1 ns;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
cnt := cnt + 1;
IF cnt < number THEN -- burst
dat_out := dat_out + 1;
mstr_out.data <= dat_out;
ELSE
mstr_out.data <= (OTHERS => 'H');
mstr_out.asn <= 'H';
END IF;
time_dat_changed := now;
-- WAIT until rising_edge(mstr_in.dtackn);
-- WAIT FOR 1 ns;
-- mstr_out.asn <= 'H';
IF cnt = number THEN
exit dat_phase;
END IF;
IF time_dat_changed > 35 ns THEN
next dat_phase;
ELSE
WAIT FOR (35 ns - time_dat_changed);
next dat_phase;
END IF;
END LOOP;
END PROCEDURE vme_mstr_write;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_write64 (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0)
) IS
VARIABLE dsan : std_logic;
VARIABLE dsbn : std_logic;
VARIABLE vme_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat_out : std_logic_vector(31 DOWNTO 0);
VARIABLE cnt : integer;
VARIABLE time_dat_changed : time;
BEGIN
print(txt_out, "VME_SIM_MSTR: do we have bus arbitration?");
IF mstr_in.bg3n_in /= '0' THEN
mstr_out.brn <= "0HHH"; -- request bus
WAIT until falling_edge(mstr_in.bg3n_in); -- wait until bus grant
END IF;
print(txt_out, "VME_SIM_MSTR: wait until prior access has finished");
IF mstr_in.bbsyn = '0' THEN
WAIT until rising_edge(mstr_in.bbsyn);
END IF;
-- occupy bus
mstr_out.bbsyn <= '0', 'H' AFTER 90 ns;
-- prepare
cnt := 0;
vme_adr := adress;
dat_out := (OTHERS => '0');
-- mode = 'd'
dsan := '0'; -- B0, B1, B2, B3
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '0'; --lwordn
dat_out(31 DOWNTO 24) := data(7 DOWNTO 0);
dat_out(23 DOWNTO 16) := data(15 DOWNTO 8);
dat_out(15 DOWNTO 8) := data(23 DOWNTO 16);
dat_out(7 DOWNTO 0) := data(31 DOWNTO 24);
print(txt_out, "VME_SIM_MSTR: start of vme access");
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.addr <= vme_adr;
mstr_out.am <= tga;
mstr_out.writen <= '0';
WAIT FOR 40 ns;
mstr_out.asn <= '0';
WAIT FOR 5 ns;
mstr_out.brn <= "HHHH"; -- release bus arbitration
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.data <= (OTHERS => '0'); -- no data in first d64 phase: address phase
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn FOR address phase");
WAIT FOR 1 ns;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
WAIT until rising_edge(mstr_in.dtackn);
WAIT FOR 1 ns;
print(txt_out, "VME_SIM_MSTR: data phase");
dat_phase: LOOP
vme_adr:= NOT dat_out;
mstr_out.data <= dat_out;
mstr_out.addr <= vme_adr;
WAIT FOR 35 ns;
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn");
IF txt_out > 1 THEN
print_mtest("VME_MSTR: WRITE ", adress, (vme_adr & dat_out), (vme_adr & dat_out), TRUE);
END IF;
WAIT FOR 1 ns;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
cnt := cnt + 1;
IF cnt < number THEN -- burst
dat_out := dat_out + 1;
mstr_out.data <= dat_out;
mstr_out.addr <= vme_adr;
ELSE
mstr_out.data <= (OTHERS => 'H');
mstr_out.addr <= (OTHERS => 'H');
mstr_out.asn <= 'H';
END IF;
time_dat_changed := now;
-- WAIT until rising_edge(mstr_in.dtackn);
-- WAIT FOR 1 ns;
-- mstr_out.asn <= 'H';
IF cnt = number THEN
exit dat_phase;
END IF;
IF time_dat_changed > 35 ns THEN
next dat_phase;
ELSE
WAIT FOR (35 ns - time_dat_changed);
next dat_phase;
END IF;
END LOOP;
END PROCEDURE vme_mstr_write64;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_read (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
ex_data : std_logic_vector(31 DOWNTO 0);
in_data : OUT std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0);
err : OUT integer
) IS
VARIABLE dsan : std_logic;
VARIABLE dsbn : std_logic;
VARIABLE vme_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat_in : std_logic_vector(31 DOWNTO 0);
VARIABLE cnt : integer;
VARIABLE time_dat_changed : time;
VARIABLE dat_phase_err : integer;
VARIABLE loc_err : integer;
VARIABLE expected : std_logic_vector(31 DOWNTO 0);
BEGIN
dat_phase_err := 0;
loc_err := 0;
expected := ex_data;
print(txt_out, "VME_SIM_MSTR: do we have bus arbitration?");
IF mstr_in.bg3n_in /= '0' THEN
mstr_out.brn <= "0HHH"; -- request bus
WAIT until falling_edge(mstr_in.bg3n_in); -- wait until bus grant
END IF;
print(txt_out, "VME_SIM_MSTR: wait until prior access has finished");
-- IF mstr_in.bbsyn = '0' THEN
-- WAIT until rising_edge(mstr_in.bbsyn);
-- END IF;
IF mstr_in.asn = '0' THEN
WAIT until rising_edge(mstr_in.asn);
END IF;
IF mstr_in.asn'LAST_EVENT < 40 ns AND mstr_in.asn /= '0' THEN
WAIT FOR (40 ns - mstr_in.asn'LAST_EVENT);
END IF;
-- occupy bus
mstr_out.bbsyn <= '0', 'H' AFTER 90 ns;
-- prepare
cnt := 0;
vme_adr := adress;
expected := (OTHERS => '0');
mstr_out.iackn <= 'H';
IF mode = 'b' OR mode = 'i' THEN -- byte access
IF mode = 'i' THEN
mstr_out.iackn <= '0'; -- indicate iack cycle
END IF;
CASE adress(1 DOWNTO 0) IS
WHEN "00" => dsan := '1'; -- B0
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(7 DOWNTO 0);
WHEN "01" => dsan := '0'; -- B1
dsbn := '1';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
expected(7 DOWNTO 0) := ex_data(15 DOWNTO 8);
WHEN "10" => dsan := '1'; -- B2
dsbn := '0';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(23 DOWNTO 16);
WHEN "11" => dsan := '0'; -- B3
dsbn := '1';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
expected(7 DOWNTO 0) := ex_data(31 DOWNTO 24);
WHEN OTHERS => dsan := '1';
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(7 DOWNTO 0);
END CASE;
ELSIF mode = 'w' THEN -- word access
IF adress(1) = '0' THEN
dsan := '0'; -- B0,B1
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(7 DOWNTO 0);
expected(7 DOWNTO 0) := ex_data(15 DOWNTO 8);
ELSE
dsan := '0'; -- B2, B3
dsbn := '0';
vme_adr(1) := '1';
vme_adr(0) := '1'; --lwordn
expected(15 DOWNTO 8) := ex_data(23 DOWNTO 16);
expected(7 DOWNTO 0) := ex_data(31 DOWNTO 24);
END IF;
ELSE -- long access (mode='l')
dsan := '0'; -- B0, B1, B2, B3
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '0'; --lwordn
expected(31 DOWNTO 24) := ex_data(7 DOWNTO 0);
expected(23 DOWNTO 16) := ex_data(15 DOWNTO 8);
expected(15 DOWNTO 8) := ex_data(23 DOWNTO 16);
expected(7 DOWNTO 0) := ex_data(31 DOWNTO 24);
END IF;
print(txt_out, "VME_SIM_MSTR: start of vme access");
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.addr <= vme_adr;
mstr_out.am <= tga;
mstr_out.writen <= '1';
WAIT FOR 40 ns;
mstr_out.asn <= '0';
WAIT FOR 5 ns;
mstr_out.brn <= "HHHH"; -- release bus arbitration
print(txt_out, "VME_SIM_MSTR: data phase");
dat_phase: LOOP
dat_phase_err := 0;
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn");
WAIT FOR 1 ns;
dat_in := mstr_in.data;
IF mode = 'b' OR mode = 'i' THEN
IF adress(1 DOWNTO 0) = "01" AND dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) THEN
dat_phase_err := dat_phase_err + 1;
ELSIF adress(1 DOWNTO 0) = "00" AND dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) THEN
dat_phase_err := dat_phase_err + 1;
ELSIF adress(1 DOWNTO 0) = "11" AND dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) THEN
dat_phase_err := dat_phase_err + 1;
ELSIF adress(1 DOWNTO 0) = "10" AND dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) THEN
dat_phase_err := dat_phase_err + 1;
END IF;
ELSIF mode = 'w' THEN
IF adress(1) = '0' AND
(dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8)) THEN
dat_phase_err := dat_phase_err + 1;
ELSIF adress(1) = '1' AND
(dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8)) THEN
dat_phase_err := dat_phase_err + 1;
END IF;
-- ELSIF mode = 'y' THEN -- d64
-- IF dat_in2(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
-- dat_in2(15 DOWNTO 8) /= expected(15 DOWNTO 8) OR
-- dat_in2(23 DOWNTO 16) /= expected(23 DOWNTO 16) OR
-- dat_in2(31 DOWNTO 24) /= expected(31 DOWNTO 24) THEN
-- dat_phase_err := dat_phase_err + 1;
-- END IF;
-- expected := expected + 1;
-- IF dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
-- dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) OR
-- dat_in(23 DOWNTO 16) /= expected(23 DOWNTO 16) OR
-- dat_in(31 DOWNTO 24) /= expected(31 DOWNTO 24) THEN
-- dat_phase_err := dat_phase_err + 1;
-- END IF;
ELSE -- mode = 'l'
IF dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) OR
dat_in(23 DOWNTO 16) /= expected(23 DOWNTO 16) OR
dat_in(31 DOWNTO 24) /= expected(31 DOWNTO 24) THEN
dat_phase_err := dat_phase_err + 1;
END IF;
END IF;
IF txt_out > 0 AND dat_phase_err > 0 THEN
print_mtest("VME_MSTR: READ ", adress, dat_in, expected, FALSE);
END IF;
IF txt_out > 1 AND dat_phase_err = 0 THEN
print_mtest("VME_MSTR: READ ", adress, dat_in, expected, TRUE);
END IF;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
mstr_out.iackn <= 'H';
cnt := cnt + 1;
IF cnt < number THEN -- burst
expected := expected + 1;
ELSE
mstr_out.asn <= 'H';
END IF;
time_dat_changed := now;
WAIT until rising_edge(mstr_in.dtackn);
WAIT FOR 1 ns;
loc_err := loc_err + dat_phase_err;
err := loc_err;
IF cnt = number THEN
mstr_out.asn <= 'H';
exit dat_phase;
END IF;
IF time_dat_changed > 35 ns THEN
next dat_phase;
ELSE
WAIT FOR (35 ns - time_dat_changed);
next dat_phase;
END IF;
END LOOP;
END PROCEDURE vme_mstr_read;
--------------------------------------------------------------------------------------------
PROCEDURE vme_mstr_read64 (
SIGNAL mstr_out : OUT mstr_out_type;
SIGNAL mstr_in : IN mstr_in_type;
adress : std_logic_vector(31 DOWNTO 0);
ex_data : std_logic_vector(31 DOWNTO 0);
in_data : OUT std_logic_vector(31 DOWNTO 0);
mode : character;
txt_out : integer; -- 0=quiet, 1=only errors, 2=all
number : integer;
tga : std_logic_vector(5 DOWNTO 0);
err : OUT integer
) IS
VARIABLE dsan : std_logic;
VARIABLE dsbn : std_logic;
VARIABLE vme_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat_in : std_logic_vector(63 DOWNTO 0);
VARIABLE cnt : integer;
VARIABLE time_dat_changed : time;
VARIABLE dat_phase_err : integer;
VARIABLE loc_err : integer;
VARIABLE expected : std_logic_vector(63 DOWNTO 0);
BEGIN
dat_phase_err := 0;
loc_err := 0;
expected(31 DOWNTO 0) := ex_data;
print(txt_out, "VME_SIM_MSTR: do we have bus arbitration?");
IF mstr_in.bg3n_in /= '0' THEN
mstr_out.brn <= "0HHH"; -- request bus
WAIT until falling_edge(mstr_in.bg3n_in); -- wait until bus grant
END IF;
print(txt_out, "VME_SIM_MSTR: wait until prior access has finished");
IF mstr_in.bbsyn = '0' THEN
WAIT until rising_edge(mstr_in.bbsyn);
END IF;
-- occupy bus
mstr_out.bbsyn <= '0', 'H' AFTER 90 ns;
-- prepare
cnt := 0;
vme_adr := adress;
expected := (OTHERS => '0');
-- 64-bit access
dsan := '0'; -- B0, B1, B2, B3, B4, B5, B6
dsbn := '0';
vme_adr(1) := '0';
vme_adr(0) := '0'; --lwordn
expected(31 DOWNTO 24) := ex_data(7 DOWNTO 0);
expected(23 DOWNTO 16) := ex_data(15 DOWNTO 8);
expected(15 DOWNTO 8) := ex_data(23 DOWNTO 16);
expected(7 DOWNTO 0) := ex_data(31 DOWNTO 24);
expected(63 DOWNTO 32) := NOT expected(31 DOWNTO 0);
print(txt_out, "VME_SIM_MSTR: start of vme access");
print(txt_out, "VME_SIM_MSTR: address phase");
mstr_out.addr <= vme_adr;
mstr_out.am <= tga;
mstr_out.writen <= '1';
WAIT FOR 40 ns;
mstr_out.asn <= '0';
WAIT FOR 5 ns;
mstr_out.brn <= "HHHH"; -- release bus arbitration
print(txt_out, "VME_SIM_MSTR: address phase");
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn FOR address phase");
WAIT FOR 1 ns;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
WAIT until rising_edge(mstr_in.dtackn);
WAIT FOR 1 ns;
print(txt_out, "VME_SIM_MSTR: data phase");
dat_phase: LOOP
dat_phase_err := 0;
WAIT FOR 35 ns;
mstr_out.addr <= (OTHERS => 'H');
mstr_out.am <= (OTHERS => 'H');
mstr_out.writen <= 'H';
mstr_out.dsan <= dsan;
mstr_out.dsbn <= dsbn;
WAIT until falling_edge(mstr_in.dtackn);
print(txt_out, "VME_SIM_MSTR: got dtackn");
WAIT FOR 1 ns;
dat_in := mstr_in.addr & mstr_in.data;
IF dat_in(7 DOWNTO 0) /= expected(7 DOWNTO 0) OR
dat_in(15 DOWNTO 8) /= expected(15 DOWNTO 8) OR
dat_in(23 DOWNTO 16) /= expected(23 DOWNTO 16) OR
dat_in(31 DOWNTO 24) /= expected(31 DOWNTO 24) OR
dat_in(39 DOWNTO 32) /= expected(39 DOWNTO 32) OR
dat_in(47 DOWNTO 40) /= expected(47 DOWNTO 40) OR
dat_in(55 DOWNTO 48) /= expected(55 DOWNTO 48) OR
dat_in(63 DOWNTO 56) /= expected(63 DOWNTO 56) THEN
dat_phase_err := dat_phase_err + 1;
END IF;
IF txt_out > 0 AND dat_phase_err > 0 THEN
print_mtest("VME_MSTR: READ ", adress, dat_in, expected, FALSE);
END IF;
IF txt_out > 1 AND dat_phase_err = 0 THEN
print_mtest("VME_MSTR: READ ", adress, dat_in, expected, TRUE);
END IF;
mstr_out.dsan <= 'H';
mstr_out.dsbn <= 'H';
cnt := cnt + 1;
IF cnt < number THEN -- burst
expected(31 DOWNTO 0) := expected(31 DOWNTO 0) + 1;
expected(63 DOWNTO 32) := NOT expected(31 DOWNTO 0);
ELSE
mstr_out.asn <= 'H';
END IF;
time_dat_changed := now;
WAIT until rising_edge(mstr_in.dtackn);
WAIT FOR 1 ns;
loc_err := loc_err + dat_phase_err;
err := loc_err;
IF cnt = number THEN
mstr_out.asn <= 'H';
exit dat_phase;
END IF;
IF time_dat_changed > 35 ns THEN
next dat_phase;
ELSE
WAIT FOR (35 ns - time_dat_changed);
next dat_phase;
END IF;
END LOOP;
END PROCEDURE vme_mstr_read64;
--------------------------------------------------------------------------------------------
PROCEDURE init_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type
) IS
BEGIN
vme_slv_in.req_type <= 0;
vme_slv_in.wr_dat <= (OTHERS => '0');
vme_slv_in.adr <= (OTHERS => '0');
vme_slv_in.conf_req <= FALSE;
vme_slv_in.irq <= 0;
END PROCEDURE init_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE irq_vme_slv ( SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
irq : IN integer range 7 DOWNTO 0;
dat : IN std_logic_vector(7 DOWNTO 0)
) IS
BEGIN
vme_slv_in.req_type <= 2;
vme_slv_in.irq <= irq;
vme_slv_in.wr_dat(7 DOWNTO 0) <= dat;
vme_slv_in.conf_req <= NOT vme_slv_out.conf_ack;
WAIT on vme_slv_out.conf_ack;
END PROCEDURE irq_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE wr_vme_slv ( SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
adr : IN std_logic_vector(31 DOWNTO 0);
dat : IN std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
vme_slv_in.req_type <= 0;
vme_slv_in.wr_dat <= dat;
vme_slv_in.adr <= adr;
vme_slv_in.conf_req <= NOT vme_slv_out.conf_ack;
WAIT on vme_slv_out.conf_ack;
END PROCEDURE wr_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE am_vme_slv (
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
am : OUT std_logic_vector(5 DOWNTO 0)
) is
BEGIN
vme_slv_in.req_type <= 3;
vme_slv_in.conf_req <= NOT vme_slv_out.conf_ack;
WAIT on vme_slv_out.conf_ack;
am := vme_slv_out.rd_am;
END PROCEDURE am_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE rd_vme_slv ( SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
adr : IN std_logic_vector(31 DOWNTO 0);
dat : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
vme_slv_in.req_type <= 1;
vme_slv_in.adr <= adr;
vme_slv_in.conf_req <= NOT vme_slv_out.conf_ack;
WAIT on vme_slv_out.conf_ack;
dat := vme_slv_out.rd_dat;
END PROCEDURE rd_vme_slv;
--------------------------------------------------------------------------------------------
PROCEDURE wr_data (
CONSTANT location : IN integer;
CONSTANT data : IN std_logic_vector;
CONSTANT byte : IN std_logic_vector(3 DOWNTO 0);
VARIABLE first : INOUT head_ptr
) IS
VARIABLE temp_ptr : entry_ptr;
VARIABLE new_ptr : entry_ptr;
VARIABLE prev_ptr : entry_ptr;
VARIABLE done : boolean:=FALSE;
BEGIN
done:= FALSE; -- set done to true when allocation occurs
IF first.num_entries = 0 THEN -- first access to memory
first.list_ptr := new mem_entry;
first.num_entries := 1;
first.list_ptr.address := location;
IF byte(0) = '1' THEN
first.list_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
first.list_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
first.list_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
first.list_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
first.list_ptr.nxt := null;
done := TRUE;
ELSIF location < first.list_ptr.address THEN -- address is lowest value so far in allocation to put at head of list
new_ptr := new mem_entry;
IF byte(0) = '1' THEN
new_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
new_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
new_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
new_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
new_ptr.nxt := first.list_ptr;
new_ptr.address := location;
first.list_ptr := new_ptr;
first.num_entries := first.num_entries + 1;
done := TRUE;
ELSE -- location must be >= first.list_ptr.address
temp_ptr := first.list_ptr;
while temp_ptr /= null AND NOT done LOOP
IF temp_ptr.address = location THEN -- address already allocated
IF byte(0) = '1' THEN
temp_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
temp_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
temp_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
temp_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
done := TRUE;
ELSIF temp_ptr.address > location THEN
new_ptr := new mem_entry;
new_ptr.address := location;
IF byte(0) = '1' THEN
new_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
new_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
new_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
new_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
new_ptr.nxt := temp_ptr;
prev_ptr.nxt := new_ptr; -- break pointer chain and insert new_ptr
first.num_entries := first.num_entries + 1;
done := TRUE;
ELSE
prev_ptr := temp_ptr;
temp_ptr := temp_ptr.nxt;
END IF;
END LOOP;
IF NOT done THEN
new_ptr := new mem_entry;
new_ptr.address := location;
IF byte(0) = '1' THEN
new_ptr.data(7 DOWNTO 0) := data(7 DOWNTO 0);
END IF;
IF byte(1) = '1' THEN
new_ptr.data(15 DOWNTO 8) := data(15 DOWNTO 8);
END IF;
IF byte(2) = '1' THEN
new_ptr.data(23 DOWNTO 16) := data(23 DOWNTO 16);
END IF;
IF byte(3) = '1' THEN
new_ptr.data(31 DOWNTO 24) := data(31 DOWNTO 24);
END IF;
new_ptr.nxt := null; -- add new_ptr TO END OF chain
prev_ptr.nxt := new_ptr;
first.num_entries := first.num_entries + 1;
done := TRUE;
END IF;
END IF;
WAIT FOR 0 ns;
END wr_data;
--------------------------------------------------------------------------------------------
PROCEDURE rd_data (
CONSTANT location : IN integer;
VARIABLE data : OUT std_logic_vector;
VARIABLE allocated : OUT boolean;
VARIABLE first : INOUT head_ptr
) IS
VARIABLE temp_ptr : entry_ptr;
VARIABLE is_allocated : boolean;
BEGIN
-- set allocated to true when read hits already allocated spot
is_allocated := FALSE;
IF (first.list_ptr /= null AND first.num_entries /= 0 AND location >= first.list_ptr.address) THEN
temp_ptr := first.list_ptr;
while (temp_ptr /= null AND NOT is_allocated AND location >= temp_ptr.address) LOOP
IF temp_ptr.address = location THEN -- address has been allocated
data := temp_ptr.data;
is_allocated := TRUE;
ELSE
temp_ptr := temp_ptr.nxt;
END IF;
END LOOP;
END IF;
IF NOT is_allocated THEN
data := (data'range => '1');
END IF;
allocated := is_allocated;
WAIT FOR 0 ns;
END rd_data;
FUNCTION hex_to_character (hex_value : std_logic_vector(3 downto 0))
return character is
begin
case hex_value is
when "0000" => return '0';
when "0001" => return '1';
when "0010" => return '2';
when "0011" => return '3';
when "0100" => return '4';
when "0101" => return '5';
when "0110" => return '6';
when "0111" => return '7';
when "1000" => return '8';
when "1001" => return '9';
when "1010" => return 'A';
when "1011" => return 'B';
when "1100" => return 'C';
when "1101" => return 'D';
when "1110" => return 'E';
when "1111" => return 'F';
when "ZZZZ" => return 'Z';
when others => return 'U';
end case;
end hex_to_character;
--------------------------------------------------------------------------------
-- the function can take multiple of 4 bits, upto 32 bits as input
function TO_HEX_STRING(val : std_logic_vector) return string is
variable temp : string(VAL'length / 4 downto 1);
alias valalias : std_logic_vector(VAL'length-1 downto 0) is val;
variable val32 : std_logic_vector(31 downto 0);
variable num : integer;
begin
-- temp := " ";
val32 := (others => '0');
val32(val'length-1 downto 0) := valalias;
for i in 1 to VAL'length / 4 loop
temp(i) := ' ';
temp(i) := hex_to_character(val32(i*4-1 downto i*4-4));
end loop;
return temp;
end TO_HEX_STRING;
--------------------------------------------------------------------------------
FUNCTION hex_to_bit_vect (char_code : character) RETURN vec4 IS
VARIABLE result : std_logic_vector(3 DOWNTO 0);
BEGIN
CASE char_code IS
WHEN '0' => result := "0000";
WHEN '1' => result := "0001";
WHEN '2' => result := "0010";
WHEN '3' => result := "0011";
WHEN '4' => result := "0100";
WHEN '5' => result := "0101";
WHEN '6' => result := "0110";
WHEN '7' => result := "0111";
WHEN '8' => result := "1000";
WHEN '9' => result := "1001";
WHEN 'a' => result := "1010";
WHEN 'b' => result := "1011";
WHEN 'c' => result := "1100";
WHEN 'd' => result := "1101";
WHEN 'e' => result := "1110";
WHEN 'f' => result := "1111";
WHEN OTHERS => result := "0000";
END CASE;
RETURN result;
END hex_to_bit_vect;
FUNCTION conv_addr (addr : adr_type2) RETURN adr_type IS
VARIABLE result : std_logic_vector(31 DOWNTO 0);
BEGIN
result(3 DOWNTO 0) := hex_to_bit_vect(addr(1));
result(7 DOWNTO 4) := hex_to_bit_vect(addr(2));
result(11 DOWNTO 8) := hex_to_bit_vect(addr(3));
result(15 DOWNTO 12) := hex_to_bit_vect(addr(4));
result(19 DOWNTO 16) := hex_to_bit_vect(addr(5));
result(23 DOWNTO 20) := hex_to_bit_vect(addr(6));
result(27 DOWNTO 24) := hex_to_bit_vect(addr(7));
result(31 DOWNTO 28) := hex_to_bit_vect(addr(8));
RETURN result;
END conv_addr;
FUNCTION conv_data2 (data : data_type2; adr : adr_type) RETURN data_type IS
VARIABLE result : std_logic_vector(31 DOWNTO 0);
BEGIN
result := (OTHERS => '0');
CASE adr(1 DOWNTO 0) IS
WHEN "00" => result(3 DOWNTO 0) := hex_to_bit_vect(data(1));
result(7 DOWNTO 4) := hex_to_bit_vect(data(2));
WHEN "01" => result(11 DOWNTO 8) := hex_to_bit_vect(data(1));
result(15 DOWNTO 12) := hex_to_bit_vect(data(2));
WHEN "10" => result(19 DOWNTO 16) := hex_to_bit_vect(data(1));
result(23 DOWNTO 20) := hex_to_bit_vect(data(2));
WHEN OTHERS => result(27 DOWNTO 24) := hex_to_bit_vect(data(1));
result(31 DOWNTO 28) := hex_to_bit_vect(data(2));
END CASE;
RETURN result;
END conv_data2;
FUNCTION conv_am (data : data_type2) RETURN am_type IS
VARIABLE result : std_logic_vector(7 DOWNTO 0);
BEGIN
result(3 DOWNTO 0) := hex_to_bit_vect(data(1));
result(7 DOWNTO 4) := hex_to_bit_vect(data(2));
RETURN result(5 DOWNTO 0);
END conv_am;
FUNCTION conv_data4 (data : data_type4; adr : adr_type) RETURN data_type IS
VARIABLE result : std_logic_vector(31 DOWNTO 0);
BEGIN
result := (OTHERS => '0');
CASE adr(1) IS
WHEN '0' =>
result(3 DOWNTO 0) := hex_to_bit_vect(data(1));
result(7 DOWNTO 4) := hex_to_bit_vect(data(2));
result(11 DOWNTO 8) := hex_to_bit_vect(data(3));
result(15 DOWNTO 12) := hex_to_bit_vect(data(4));
WHEN OTHERS =>
result(19 DOWNTO 16) := hex_to_bit_vect(data(1));
result(23 DOWNTO 20) := hex_to_bit_vect(data(2));
result(27 DOWNTO 24) := hex_to_bit_vect(data(3));
result(31 DOWNTO 28) := hex_to_bit_vect(data(4));
END CASE;
RETURN result;
END conv_data4;
FUNCTION conv_data8 (data : data_type8) RETURN data_type IS
VARIABLE result : std_logic_vector(31 DOWNTO 0);
BEGIN
result(3 DOWNTO 0) := hex_to_bit_vect(data(1));
result(7 DOWNTO 4) := hex_to_bit_vect(data(2));
result(11 DOWNTO 8) := hex_to_bit_vect(data(3));
result(15 DOWNTO 12) := hex_to_bit_vect(data(4));
result(19 DOWNTO 16) := hex_to_bit_vect(data(5));
result(23 DOWNTO 20) := hex_to_bit_vect(data(6));
result(27 DOWNTO 24) := hex_to_bit_vect(data(7));
result(31 DOWNTO 28) := hex_to_bit_vect(data(8));
RETURN result;
END conv_data8;
END vme_sim_pack;
vme_sim_slave.vhd 0000664 0000000 0000000 00000044040 14574545710 0035704 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : VME bus slave simmodel
-- Project : A15
---------------------------------------------------------------
-- File : vme_sim_slave.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 02/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_sim_slave.vhd,v $
-- Revision 1.2 2013/04/18 15:11:16 MMiehling
-- added irq
--
-- Revision 1.1 2012/03/29 10:28:50 MMiehling
-- Initial Revision
--
-- Revision 1.3 2006/05/18 14:31:30 MMiehling
-- correct behaviour of iack
--
-- Revision 1.2 2006/05/15 10:36:23 MMiehling
-- now support of 0x0B, 0x0F, 0x3B, 0x3F => 32Bit Block Transfer
--
-- Revision 1.1 2005/10/28 17:52:18 mmiehling
-- Initial Revision
--
-- Revision 1.2 2004/08/13 15:36:06 mmiehling
-- updated
--
-- Revision 1.1 2004/07/27 17:28:15 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee,work;
USE ieee.std_logic_1164.ALL;
USE work.vme_sim_pack.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.print_pkg.all;
ENTITY vme_sim_slave IS
PORT (
sysresin : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
berrn_in : IN std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn_in : IN std_logic; -- daisy-chain
iackn : IN std_logic; -- bussignal
irq_out : OUT std_logic_vector(7 DOWNTO 1);
dtackn_out : OUT std_logic;
data_out : OUT std_logic_vector(31 DOWNTO 0);
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type
);
END vme_sim_slave;
ARCHITECTURE vme_sim_slave_arch OF vme_sim_slave IS
SUBTYPE irq_vec IS std_logic_vector(7 DOWNTO 0);
TYPE irq_id_type IS array (7 DOWNTO 1) OF irq_vec;
SIGNAL sim_slave_active : std_logic;
SIGNAL iackn_in_int : std_logic;
SIGNAL conf_ack : boolean;
BEGIN
iackn_in_int <= '0' WHEN iackn_in = '0' AND (dsan_in = '0' OR dsbn_in = '0') ELSE '1';
vme_slv_out.conf_ack <= conf_ack;
vme_slv_out.irq(1) <= vb_irq1n;
vme_slv_out.irq(2) <= vb_irq2n;
vme_slv_out.irq(3) <= vb_irq3n;
vme_slv_out.irq(4) <= vb_irq4n;
vme_slv_out.irq(5) <= vb_irq5n;
vme_slv_out.irq(6) <= vb_irq6n;
vme_slv_out.irq(7) <= vb_irq7n;
slave : PROCESS
VARIABLE asn_time : time;
VARIABLE zeit : time;
VARIABLE addr_int : std_logic_vector(31 DOWNTO 0);
VARIABLE first_d64_cycle : boolean;
VARIABLE am_int : std_logic_vector(5 DOWNTO 0);
VARIABLE i : integer;
VARIABLE ws, sd : integer;
VARIABLE lin:line;
VARIABLE data : std_logic_vector(31 DOWNTO 0);
VARIABLE check:boolean;
VARIABLE adr_int : std_logic_vector(31 DOWNTO 3);
VARIABLE end_of_acc : std_logic;
VARIABLE mem_head : head_ptr;
VARIABLE allocated : boolean;
VARIABLE irq_id : irq_id_type;
VARIABLE irq : integer;
BEGIN
mem_head := new head'(0,null);
sim_slave_active <= '0';
data_out <= (OTHERS => 'Z');
am_int := (others => '0');
first_d64_cycle := TRUE;
conf_ack <= vme_slv_in.conf_req;
addr <= (OTHERS => 'H');
dtackn_out <= 'H';
irq_out <= (OTHERS => 'H');
irq := 0;
WAIT UNTIL sysresin /= '0'; --ohne EVENT
gen_loop: LOOP -- main loop
data_out <= (OTHERS => 'Z');
IF asn_in /= '0' OR (vme_slv_in.conf_req/= conf_ack) THEN
WAIT until falling_edge(asn_in) OR vme_slv_in.conf_req'event;
END IF;
----------------------------------------------------------------------------------------
-- config access
----------------------------------------------------------------------------------------
IF vme_slv_in.conf_req /= conf_ack THEN
IF vme_slv_in.req_type = 1 THEN
--WRITE
adr_int:=vme_slv_in.adr(31 DOWNTO 3);
wr_data(conv_integer(adr_int), vme_slv_in.wr_dat, "1111", mem_head);
ELSIF vme_slv_in.req_type = 0 THEN
-- read from iram
rd_data(conv_integer(vme_slv_in.adr(31 DOWNTO 3)), data, allocated, mem_head);
vme_slv_out.rd_dat <= data;
ELSIF vme_slv_in.req_type = 2 THEN
-- set irq request
irq_out(vme_slv_in.irq) <= '0';
irq := vme_slv_in.irq;
irq_id(irq) := vme_slv_in.wr_dat(7 DOWNTO 0);
ELSIF vme_slv_in.req_type = 3 THEN
-- request of last address modifier used
vme_slv_out.rd_am <= am_int;
END IF;
conf_ack <= vme_slv_in.conf_req; -- handshake acknowledge
next gen_loop;
END IF;
----------------------------------------------------------------------------------------
-- vme access
----------------------------------------------------------------------------------------
addr_int := addr;
am_int := am_in;
first_d64_cycle := TRUE;
LOOP
asn_time := now;
IF NOT (dsan_in = '0' OR dsbn_in = '0') AND asn_in = '0' THEN
WAIT until (dsan_in = '0' OR dsbn_in = '0' OR asn_in /= '0');
END IF;
IF asn_in /= '0' THEN
exit;
END IF;
-- D64 burst
IF iackn /= '0' AND (
(addr_int(31 DOWNTO 28) = sl_base_A32 AND (am_int(5 DOWNTO 0) = AM_A32_NONPRIV_MBLT OR am_int(5 DOWNTO 0) = AM_A32_SUPER_MBLT)) or
(addr_int(23 DOWNTO 20) = sl_base_A24 AND (am_int(5 DOWNTO 0) = AM_A24_NONPRIV_MBLT OR am_int(5 DOWNTO 0) = AM_A24_SUPER_MBLT))) THEN
sim_slave_active <= '1';
IF writen_in = '1' THEN -- READ
WAIT FOR time_26;
IF first_d64_cycle = FALSE THEN
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
addr(31 DOWNTO 24) <= data(31 DOWNTO 24);
addr(23 DOWNTO 16) <= data(23 DOWNTO 16);
addr(15 DOWNTO 8) <= data(15 DOWNTO 8);
addr(7 DOWNTO 0) <= data(7 DOWNTO 0);
rd_data(conv_integer(addr_int(11 DOWNTO 2)+1), data, allocated, mem_head);
data_out(31 DOWNTO 24) <= data(31 DOWNTO 24);
data_out(23 DOWNTO 16) <= data(23 DOWNTO 16);
data_out(15 DOWNTO 8) <= data(15 DOWNTO 8);
data_out(7 DOWNTO 0) <= data(7 DOWNTO 0);
addr_int := addr_int + 8;
END IF;
WAIT FOR time_27;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
data_out <= (OTHERS => 'H');
addr <= (OTHERS => 'H');
WAIT FOR 10 ns;
-- WAIT FOR 120 ns; -- extended to simulate slow slave with long dtackn active
dtackn_out <= 'H';
ELSE -- WRITE
IF first_d64_cycle = FALSE THEN
IF NOT (data_in'stable(time_8)) then
print("vme_sim: Data[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
IF NOT (addr'stable(time_8)) then
print("vme_sim: Addr[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
WAIT FOR time_28;
wr_data(conv_integer(addr_int(11 DOWNTO 2)), addr, "1111", mem_head);
wr_data(conv_integer(addr_int(11 DOWNTO 2)+1), data_in, "1111", mem_head);
addr_int := addr_int + 8;
ELSE
WAIT FOR time_28;
END IF;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
WAIT FOR 10 ns;
-- WAIT FOR 120 ns; -- extended to simulate slow slave with long dtackn active
dtackn_out <= 'H';
END IF;
first_d64_cycle := FALSE;
-- all normal accesses
ELSIF iackn /= '0' AND ( (addr_int(15 DOWNTO 12) = sl_base_A16 AND am_int(5 DOWNTO 4) = "10") OR
(addr_int(23 DOWNTO 20) = sl_base_A24 AND am_int(5 DOWNTO 4) = "11") OR
(addr_int(23 DOWNTO 20) = sl_base_CRCSR AND am_int(5 DOWNTO 0) = AM_CRCSR) OR
(addr_int(31 DOWNTO 28) = sl_base_A32 AND am_int(5 DOWNTO 4) = "00") )THEN
sim_slave_active <= '1';
IF writen_in = '1' THEN -- READ
WAIT FOR (time_28 - time_27);
dtackn_out <= '0';
IF (dsbn_in = '0' AND dsan_in = '0' AND addr_int(1 DOWNTO 0) = "01") OR
(dsbn_in = '0' AND dsan_in /= '0' AND addr_int(1 DOWNTO 0) = "01") OR
(dsbn_in /= '0' AND dsan_in = '0' AND addr_int(1 DOWNTO 0) = "01") THEN
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
data_out(15 DOWNTO 0) <= data(31 DOWNTO 16);
data_out(31 DOWNTO 16) <= data(15 DOWNTO 0);
ELSE
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
data_out <= data;
END IF;
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE -- WRITE
IF NOT (data_in'stable(time_8)) then
print("vme_sim: Data[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
WAIT FOR time_28;
IF addr_int(0) = '1' THEN -- lwordn = '1' => D16
data := data_in(15 DOWNTO 8) & data_in(7 DOWNTO 0) & data_in(15 DOWNTO 8) & data_in(7 DOWNTO 0);
IF dsan_in /= '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1000", mem_head);
ELSIF dsan_in = '0' AND dsbn_in /= '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0100", mem_head);
ELSIF dsan_in /= '0' AND dsbn_in = '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0010", mem_head);
ELSIF dsan_in = '0' AND dsbn_in /= '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0001", mem_head);
ELSIF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1100", mem_head);
ELSIF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0011", mem_head);
END IF;
ELSE
data := data_in;
IF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1111", mem_head);
END IF;
END IF;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
WAIT FOR 10 ns;
dtackn_out <= 'H';
END IF;
-- 0x0B, 0x0F, 0x3B, 0x3F => 32Bit Block Transfer
IF am_int = AM_A32_NONPRIV_BLT OR am_int = AM_A32_SUPER_BLT OR am_int = AM_A24_NONPRIV_BLT OR am_int = AM_A24_SUPER_BLT THEN
IF addr_int(0) = '0' THEN
addr_int := addr_int + 4;
ELSE
addr_int := addr_int + 2;
END IF;
END IF;
-- IACK-Cycle
ELSIF iackn = '0' THEN
IF iackn_in_int = '1' THEN
WAIT until (falling_edge(iackn_in_int) OR rising_edge(asn_in));
IF asn_in /= '0' THEN
exit;
END IF;
END IF;
sim_slave_active <= '1';
IF writen_in = '1' AND dsan_in = '0' AND dsbn_in /= '0' AND addr_int(0) = '1' THEN -- read iack D08
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 8) <= (OTHERS => '0');
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSIF writen_in = '1' AND dsan_in = '0' AND dsbn_in = '0' AND addr_int(0) = '1' THEN -- read iack D16
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(15 DOWNTO 8) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 16) <= (OTHERS => '0');
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSIF writen_in = '1' AND dsan_in = '0' AND dsbn_in = '0' AND addr_int(0) = '1' THEN -- read iack D32
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(15 DOWNTO 8) <= irq_id(irq); -- B(0)
data_out(23 DOWNTO 16) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 24) <= irq_id(irq); -- B(0)
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSE
print("vme_sim: For IRQH D08(O) dsan=0, dsbn=1, writen=1, lwordn=1!");
ASSERT FALSE REPORT " Funktionsfehler! " SEVERITY error;
END IF;
ELSE -- if this slave is not addressed
WAIT until rising_edge(asn_in);
END IF;
sim_slave_active <= '0';
END LOOP;
END LOOP;
END PROCESS slave;
END vme_sim_slave_arch;
vmebus.vhd 0000664 0000000 0000000 00000026323 14574545710 0034360 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2001, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : External driver simulation model
-- Project : A15
---------------------------------------------------------------
-- File : vmebus.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 03/02/03
---------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : -
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
-- tb_vme_ctrl
-- vmebus
-- vme_sim_mstr
-- vme_sim_slave
-- vme_sim_mon
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vmebus.vhd,v $
-- Revision 1.2 2013/04/18 15:11:19 MMiehling
-- added slot 1/x support
--
-- Revision 1.1 2012/03/29 10:28:51 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/18 14:30:46 MMiehling
-- changed iack connection
--
-- Revision 1.1 2005/10/28 17:52:09 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:27:56 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vme_sim_pack.ALL;
USE work.terminal_pkg.all;
ENTITY vmebus IS
PORT (
slot1 : boolean:=TRUE; -- if true dut is in slot1
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type;
vme_mon_out : OUT vme_mon_out_type;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type;
-- the VME signals:
vb_am : INOUT std_logic_vector(5 DOWNTO 0);
vb_data : INOUT std_logic_vector(31 DOWNTO 0);
vb_adr : INOUT std_logic_vector(31 DOWNTO 0);
vb_writen : INOUT std_logic;
vb_iackn : INOUT std_logic;
vb_asn : INOUT std_logic;
vb_dsan : INOUT std_logic;
vb_dsbn : INOUT std_logic;
vb_bbsyn : INOUT std_logic;
vb_berrn : INOUT std_logic;
vb_brn : INOUT std_logic_vector(3 DOWNTO 0);
vb_dtackn : INOUT std_logic;
vb_sysresn : INOUT std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_bgin : OUT std_logic_vector(3 DOWNTO 0);
vb_bgout : IN std_logic_vector(3 DOWNTO 0);
vb_iackin : OUT std_logic;
vb_iackout : IN std_logic;
vb_acfailn : INOUT std_logic
);
END vmebus;
ARCHITECTURE vmebus_arch OF vmebus IS
COMPONENT vme_sim_mstr
PORT (
sysresn : INOUT std_logic;
asn : INOUT std_logic;
dsan : INOUT std_logic;
dsbn : INOUT std_logic;
writen : INOUT std_logic;
dtackn : IN std_logic;
berrn : INOUT std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data : INOUT std_logic_vector(31 DOWNTO 0);
am : INOUT std_logic_vector(5 DOWNTO 0);
iackn : INOUT std_logic;
iackout : OUT std_logic;
iackin : IN std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_acfailn : INOUT std_logic;
bg3n_in : IN std_logic;
bg3n_out : OUT std_logic;
brn : INOUT std_logic_vector(3 DOWNTO 0);
bbsyn : INOUT std_logic;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type
);
END COMPONENT;
COMPONENT vme_sim_slave
PORT (
sysresin : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
berrn_in : IN std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn_in : IN std_logic; -- daisy-chain
iackn : IN std_logic; -- bussignal
irq_out : OUT std_logic_vector(7 DOWNTO 1);
dtackn_out : OUT std_logic;
data_out : OUT std_logic_vector(31 DOWNTO 0);
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type
);
END COMPONENT;
COMPONENT vme_sim_mon
PORT (
rstn : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
dtackn_in : IN std_logic;
berrn_in : IN std_logic;
addr_in : IN std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn : IN std_logic;
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
bbsyn_in : IN std_logic;
vme_mon_out : OUT vme_mon_out_type
);
END COMPONENT;
SIGNAL bg3n_out : std_logic;
SIGNAL sim_iackout: std_logic;
SIGNAL sim_iackin : std_logic;
SIGNAL sim_bgout : std_logic;
SIGNAL sim_bgin : std_logic;
BEGIN
vb_am <= (OTHERS => 'H');
vb_data <= (OTHERS => 'H');
vb_adr <= (OTHERS => 'H');
vb_brn <= (OTHERS => 'H');
vb_bgin <= (OTHERS => 'H');
vb_writen <= 'H';
vb_iackn <= 'H';
vb_asn <= 'H';
vb_dsan <= 'H';
vb_dsbn <= 'H';
vb_bbsyn <= 'H';
vb_berrn <= 'H';
vb_dtackn <= 'H';
vb_sysresn <= 'H';
-- vb_irq1n <= 'H';
-- vb_irq2n <= 'H';
-- vb_irq3n <= 'H';
-- vb_irq4n <= 'H';
-- vb_irq5n <= 'H';
-- vb_irq6n <= 'H';
-- vb_irq7n <= 'H';
vb_acfailn <= 'H';
vmesimmstr : vme_sim_mstr
PORT MAP (
sysresn => vb_sysresn,
asn => vb_asn,
dsan => vb_dsan,
dsbn => vb_dsbn,
writen => vb_writen,
dtackn => vb_dtackn,
berrn => vb_berrn,
addr => vb_adr,
data => vb_data,
am => vb_am,
iackn => vb_iackn,
iackout => sim_iackout,
iackin => sim_iackin,
vb_irq1n => vb_irq1n,
vb_irq2n => vb_irq2n,
vb_irq3n => vb_irq3n,
vb_irq4n => vb_irq4n,
vb_irq5n => vb_irq5n,
vb_irq6n => vb_irq6n,
vb_irq7n => vb_irq7n,
vb_acfailn => vb_acfailn,
bg3n_in => sim_bgin,
bg3n_out => sim_bgout,
brn => vb_brn,
bbsyn => vb_bbsyn,
terminal_in_x => terminal_in_x ,
terminal_out_x => terminal_out_x
);
vmesimmon: vme_sim_mon
PORT MAP(
rstn => vb_sysresn,
asn_in => vb_asn,
dsan_in => vb_dsan,
dsbn_in => vb_dsbn,
writen_in => vb_writen,
dtackn_in => vb_dtackn,
berrn_in => vb_berrn,
addr_in => vb_adr,
data_in => vb_data,
am_in => vb_am,
iackn => vb_iackn,
vb_irq1n => vb_irq1n,
vb_irq2n => vb_irq2n,
vb_irq3n => vb_irq3n,
vb_irq4n => vb_irq4n,
vb_irq5n => vb_irq5n,
vb_irq6n => vb_irq6n,
vb_irq7n => vb_irq7n,
bbsyn_in => vb_bbsyn,
vme_mon_out => vme_mon_out
);
vb_slave : vme_sim_slave
PORT MAP(
sysresin => vb_sysresn,
asn_in => vb_asn,
dsan_in => vb_dsan,
dsbn_in => vb_dsbn,
writen_in => vb_writen,
berrn_in => vb_berrn,
addr => vb_adr,
data_in => vb_data,
am_in => vb_am,
iackn_in => sim_iackin,
iackn => vb_iackn,
dtackn_out => vb_dtackn,
data_out => vb_data,
irq_out(1) => vb_irq1n,
irq_out(2) => vb_irq2n,
irq_out(3) => vb_irq3n,
irq_out(4) => vb_irq4n,
irq_out(5) => vb_irq5n,
irq_out(6) => vb_irq6n,
irq_out(7) => vb_irq7n,
vb_irq1n => vb_irq1n,
vb_irq2n => vb_irq2n,
vb_irq3n => vb_irq3n,
vb_irq4n => vb_irq4n,
vb_irq5n => vb_irq5n,
vb_irq6n => vb_irq6n,
vb_irq7n => vb_irq7n,
vme_slv_in => vme_slv_in ,
vme_slv_out => vme_slv_out
);
sl1: PROCESS(slot1, vb_iackn, vb_iackout, vb_bgout, sim_iackout, sim_bgout)
BEGIN
IF slot1 THEN
----------------------------------------------------------------
-- slot 1 2
-- dut sim
----------------------------------------------------------------
IF vb_iackn = '0' THEN
vb_iackin <= '0'; -- connect vb_iackn bussignal to daisy chain slot1
ELSE
vb_iackin <= 'H';
END IF;
sim_iackin <= vb_iackout; -- connect iack daisy chain of dut(slot1) to sim
vb_bgin(3) <= '0'; -- dut is in slot1
sim_bgin <= vb_bgout(3); -- connect bg daisy chain of dut(slot1) to sim
ELSE
----------------------------------------------------------------
-- slot 1 2
-- sim dut
----------------------------------------------------------------
vb_iackin <= sim_iackout;
IF vb_iackn = '0' THEN
sim_iackin <= '0'; -- connect vb_iackn bussignal to daisy chain slot1
ELSE
sim_iackin <= 'H';
END IF;
vb_bgin(3) <= sim_bgout; -- connect bg daisy chain of sim(slot1) to dut
sim_bgin <= '0'; -- sim is in slot1
END IF;
END PROCESS sl1;
END vmebus_arch;
z126_01_altremote_update_sim_model.vhd 0000664 0000000 0000000 00000004412 14574545710 0041522 0 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/testbench/Testbench_src -- SPDX-FileCopyrightText: 2014, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Altera remote update controller model
-- Project : -
---------------------------------------------------------------
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 05/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: $
--
-- $Log: $
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY z126_01_ru_cycloneiii IS
PORT (
clock : IN std_logic ;
data_in : IN std_logic_vector (23 DOWNTO 0);
param : IN std_logic_vector (2 DOWNTO 0);
read_param : IN std_logic ;
read_source : IN std_logic_vector (1 DOWNTO 0);
reconfig : IN std_logic ;
reset : IN std_logic ;
reset_timer : IN std_logic ;
write_param : IN std_logic ;
busy : OUT std_logic ;
data_out : OUT std_logic_vector (28 DOWNTO 0)
);
END z126_01_ru_cycloneiii;
ARCHITECTURE z126_01_ru_cycloneiii_arch OF z126_01_ru_cycloneiii IS
BEGIN
busy_p: PROCESS
BEGIN
WAIT UNTIL rising_edge(clock) OR reset = '1';
IF reset = '1' THEN
busy <= '0';
ELSIF read_param = '1' OR read_param = '1' THEN
WAIT FOR 100 ns;
WAIT UNTIL rising_edge(clock);
busy <= '1';
WAIT FOR 600 ns;
WAIT UNTIL rising_edge(clock);
busy <= '0';
END IF;
END PROCESS;
data_out <= (OTHERS => '0');
END z126_01_ru_cycloneiii_arch;
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/top/ 0000775 0000000 0000000 00000000000 14574545710 0026462 5 ustar 00root root 0000000 0000000 vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/top/.gitignore 0000664 0000000 0000000 00000000157 14574545710 0030455 0 ustar 00root root 0000000 0000000 # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
chameleon_V2.bak
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/top/A25_top.vhd 0000664 0000000 0000000 00000066023 14574545710 0030405 0 ustar 00root root 0000000 0000000 -- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : Toplevel File of A25 FPGA
-- Project : 1614_CERN_A25
--------------------------------------------------------------------------------
-- File : A25_top.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 2016-06-03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- A25_top
-- wbb2vme_top
-- sram
-- ip_16z091_01_top
-- iram_wb
-- pll_pcie
-- z126_01_top
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
USE work.wb_pkg.ALL;
USE work.fpga_pkg_2.ALL;
USE work.z126_01_pkg.ALL;
USE work.vme_pkg.ALL;
ENTITY A25_top IS
GENERIC (
SIMULATION : boolean := FALSE;
FPGA_FAMILY : family_type := CYCLONE4;
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk_16mhz : IN std_logic;
led_green_n : OUT std_logic;
led_red_n : OUT std_logic;
hreset_n : IN std_logic; -- reset
v2p_rstn : OUT std_logic; -- connected to hreset_req1_n
fpga_test : INOUT std_logic_vector(5 DOWNTO 1);
-- pcie
refclk : IN std_logic; -- 100 MHz pcie clock
pcie_rx : IN std_logic_vector(3 DOWNTO 0); -- PCIe receive line
pcie_tx : OUT std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
-- sram
sr_clk : OUT std_logic;
sr_a : OUT std_logic_vector(18 DOWNTO 0);
sr_d : INOUT std_logic_vector(15 DOWNTO 0);
sr_bwa_n : OUT std_logic;
sr_bwb_n : OUT std_logic;
sr_bw_n : OUT std_logic;
sr_cs1_n : OUT std_logic;
sr_adsc_n : OUT std_logic;
sr_oe_n : OUT std_logic;
-- vmebus
vme_ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : IN std_logic; -- geographical addresses
vme_a : INOUT std_logic_vector(31 DOWNTO 0);
vme_a_dir : OUT std_logic;
vme_a_oe_n : OUT std_logic;
vme_d : INOUT std_logic_vector(31 DOWNTO 0);
vme_d_dir : OUT std_logic;
vme_d_oe_n : OUT std_logic;
vme_am_dir : OUT std_logic;
vme_am : INOUT std_logic_vector(5 DOWNTO 0);
vme_am_oe_n : OUT std_logic;
vme_write_n : INOUT std_logic;
vme_iack_n : INOUT std_logic;
vme_irq_i_n : IN std_logic_vector(7 DOWNTO 1);
vme_irq_o : OUT std_logic_vector(7 DOWNTO 1); -- high active on A25
vme_as_i_n : IN std_logic;
vme_as_o_n : OUT std_logic;
vme_as_oe : OUT std_logic; -- high active on A25
vme_retry_o_n : OUT std_logic;
vme_retry_oe : OUT std_logic; -- high active on A25
vme_retry_i_n : IN std_logic;
vme_sysres_i_n : IN std_logic;
vme_sysres_o : OUT std_logic; -- high active on A25
vme_ds_i_n : IN std_logic_vector(1 DOWNTO 0);
vme_ds_o_n : OUT std_logic_vector(1 DOWNTO 0);
vme_ds_oe : OUT std_logic; -- high active on A25
vme_berr_i_n : IN std_logic;
vme_berr_o : OUT std_logic; -- high active on A25
vme_dtack_i_n : IN std_logic;
vme_dtack_o : OUT std_logic; -- high active on A25
vme_scon : OUT std_logic; -- high active on A25
vme_sysfail_i_n : IN std_logic;
vme_sysfail_o : OUT std_logic; -- high active on A25
vme_bbsy_i_n : IN std_logic;
vme_bbsy_o : OUT std_logic; -- high active on A25
vme_bclr_i_n : IN std_logic; -- bus clear input
vme_bclr_o_n : OUT std_logic; -- bus clear output
vme_br_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_br_o : OUT std_logic_vector(3 DOWNTO 0); -- high active on A25
vme_iack_i_n : IN std_logic;
vme_iack_o_n : OUT std_logic;
vme_acfail_i_n : IN std_logic;
vme_sysclk : OUT std_logic;
vme_bg_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_bg_o_n : OUT std_logic_vector(3 DOWNTO 0)
);
END A25_top;
ARCHITECTURE A25_top_arch OF A25_top IS
COMPONENT pll_pcie
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END COMPONENT;
function f_sel_pcie_lanes(simulation : boolean)
return std_logic_vector is
begin
if (simulation) then
return "001"; -- x1 for simulation
else
return "100"; -- x4 for synthesis
end if;
end function;
function f_sel_cham_hex(simulation : boolean)
return string is
begin
if (simulation) then
return "../../A25_VME/Source/chameleon.hex";
else
return "../top/chameleon.hex";
end if;
end function;
function f_sel_sim_bool(simulation : boolean)
return std_logic is
begin
if (simulation) then
return '1';
else
return '0';
end if;
end function;
CONSTANT CONST_500HZ : integer := 66667; -- half 500Hz clock period counter value at 66MHz
SIGNAL sys_clk : std_logic; -- system clock 66 MHz
SIGNAL sys_rst : std_logic; -- system async reset
SIGNAL rst_33 : std_logic; -- reset synchronized to clk_33
SIGNAL clk_33 : std_logic; -- 33 MHz clock for 16z066
SIGNAL clk_50 : std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
SIGNAL clk_125 : std_logic; -- 125 MHz clock for fixed_clk
SIGNAL clk_500 : std_logic; -- 500 Hz clock
SIGNAL cnt_500hz : unsigned(16 downto 0);
-- MASTER SIGNALS
SIGNAL wbmo_0 : wbo_type;
SIGNAL wbmi_0 : wbi_type;
SIGNAL wbmo_0_cyc : std_logic_vector(3 DOWNTO 0);
SIGNAL wbmo_0_cyc_bar : std_logic_vector(6 downto 0);
signal wbmo_0_adr : std_logic_vector(31 downto 0);
SIGNAL wbmo_2 : wbo_type;
SIGNAL wbmi_2 : wbi_type;
SIGNAL wbmo_2_cyc : std_logic_vector(1 DOWNTO 0);
signal wbmo_3 : wbo_type;
signal wbmo_3_cyc : std_logic;
signal wbmi_3 : wbi_type;
-- SLAVE SIGNALS
SIGNAL wbso_0 : wbi_type;
SIGNAL wbsi_0 : wbo_type;
SIGNAL wbsi_0_cyc : std_logic;
SIGNAL wbso_1 : wbi_type;
SIGNAL wbsi_1 : wbo_type;
SIGNAL wbsi_1_cyc : std_logic;
SIGNAL wbso_2 : wbi_type;
SIGNAL wbsi_2 : wbo_type;
SIGNAL wbsi_2_cyc : std_logic;
SIGNAL wbso_3 : wbi_type;
SIGNAL wbsi_3 : wbo_type;
SIGNAL wbsi_3_cyc : std_logic;
SIGNAL wbso_4 : wbi_type;
SIGNAL wbsi_4 : wbo_type;
SIGNAL wbsi_4_cyc : std_logic;
SIGNAL pll_locked : std_logic;
SIGNAL vme_a_out : std_logic_vector(31 downto 0);
SIGNAL vme_a_oe_n_int : std_logic;
SIGNAL vme_a_dir_int : std_logic;
SIGNAL vme_d_out : std_logic_vector(31 downto 0);
SIGNAL vme_d_oe_n_int : std_logic;
SIGNAL vme_d_dir_int : std_logic;
SIGNAL vme_write_n_out : std_logic;
SIGNAL vme_am_out : std_logic_vector(5 downto 0);
SIGNAL vme_iack_n_out : std_logic;
SIGNAL vme_am_oe_n_int : std_logic;
SIGNAL vme_am_dir_int : std_logic;
SIGNAL vme_irq : std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
SIGNAL berr_irq : std_logic; -- signal berrn interrupt request
SIGNAL locmon_irq : std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
SIGNAL mailbox_irq : std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
SIGNAL mailbox_irq_i : std_logic;
SIGNAL dma_irq : std_logic;
SIGNAL slot01n : std_logic;
SIGNAL pll_locked_inv : std_logic;
SIGNAL startup_rst : std_logic:='1';
SIGNAL porst : std_logic;
SIGNAL porst_n_q : std_logic:='0';
SIGNAL porst_n : std_logic:='0';
SIGNAL vme_berr : std_logic;
SIGNAL vme_mstr_busy : std_logic;
SIGNAL led_cnt : std_logic_vector(17 DOWNTO 0); -- 2^18 = 3.9 ms
SIGNAL v2p_rst : std_logic;
-- high active signals on A25
SIGNAL vme_irq_o_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_as_oe_n : std_logic;
SIGNAL vme_retry_oe_n : std_logic;
SIGNAL vme_sysres_o_n : std_logic;
SIGNAL vme_ds_oe_n : std_logic;
SIGNAL vme_scon_n : std_logic;
SIGNAL vme_sysfail_o_n : std_logic;
SIGNAL vme_bbsy_o_n : std_logic;
SIGNAL vme_dtack_o_n : std_logic;
SIGNAL vme_berr_o_n : std_logic;
SIGNAL vme_br_o_n : std_logic_vector(3 DOWNTO 0);
BEGIN
vme_irq_o <= NOT vme_irq_o_n ;
vme_as_oe <= NOT vme_as_oe_n ;
vme_retry_oe <= NOT vme_retry_oe_n ;
vme_sysres_o <= NOT vme_sysres_o_n ;
vme_ds_oe <= NOT vme_ds_oe_n ;
vme_scon <= NOT vme_scon_n ;
vme_sysfail_o <= NOT vme_sysfail_o_n;
vme_bbsy_o <= NOT vme_bbsy_o_n ;
vme_br_o <= NOT vme_br_o_n ;
vme_berr_o <= NOT vme_berr_o_n;
vme_dtack_o <= NOT vme_dtack_o_n;
led_red_n <= NOT vme_berr;
-- led_green_n <= slot01;
vme_sysclk <= clk_16mhz;
vme_scon_n <= slot01n;
v2p_rstn <= '0' WHEN v2p_rst = '1' ELSE 'Z';
-- counter for extending vme master active pulses to at least 3 ms
PROCESS(sys_clk, sys_rst)
BEGIN
IF sys_rst = '1' THEN
led_cnt <= (OTHERS => '0');
led_green_n <= '1';
ELSIF sys_clk'event AND sys_clk = '1' THEN
IF vme_mstr_busy = '1' THEN -- if master is active, start counter to extend pulse for 3 ms
led_cnt <= (OTHERS => '1');
led_green_n <= '0'; -- switch on LED
ELSIF led_cnt = 0 THEN -- is 3 ms over?
led_cnt <= (OTHERS => '0');
led_green_n <= '1'; -- switch off LED
ELSE
led_cnt <= led_cnt - '1'; -- count for 3 ms
led_green_n <= '0';
END IF;
END IF;
END PROCESS;
pll_locked_inv <= NOT pll_locked;
startup_rst <= pll_locked_inv;
wbso_4.err <= '0';
fpga_test(1) <= 'Z';
fpga_test(2) <= 'Z';
fpga_test(3) <= 'Z';
fpga_test(4) <= 'Z';
fpga_test(5) <= 'Z';
-- generate power on reset in order to start application fpga load as early as possible
PROCESS (clk_16mhz)
BEGIN
IF clk_16mhz'EVENT AND clk_16mhz = '1' THEN
porst_n_q <= '1';
porst_n <= porst_n_q;
END IF;
END PROCESS;
porst <= NOT porst_n;
-- synchronize reset to 33 MHz clock
PROCESS(clk_33, pll_locked)
BEGIN
IF pll_locked = '0' THEN
rst_33 <= '1';
ELSIF clk_33'EVENT AND clk_33 = '1' THEN
rst_33 <= '0';
END IF;
END PROCESS;
PROCESS(sys_clk, hreset_n, pll_locked)
BEGIN
IF hreset_n = '0' OR pll_locked = '0' THEN
sys_rst <= '1';
ELSIF sys_clk'EVENT AND sys_clk = '1' THEN
sys_rst <= '0';
END IF;
END PROCESS;
PROCESS(sys_clk, sys_rst)
BEGIN
IF sys_rst = '1' THEN
cnt_500hz <= (others => '0');
clk_500 <= '0';
ELSIF sys_clk'EVENT AND sys_clk = '1' THEN
IF cnt_500hz = to_unsigned(0, cnt_500hz'length) THEN
cnt_500hz <= to_unsigned(CONST_500HZ, cnt_500hz'length);
clk_500 <= NOT clk_500;
ELSE
cnt_500hz <= cnt_500hz - 1;
END IF;
END IF;
END PROCESS;
pll: pll_pcie
PORT MAP (
areset => porst,
inclk0 => clk_16mhz, -- 16 MHz
c0 => clk_125, -- 125 MHz
c1 => clk_50, -- 50 MHz
c2 => sys_clk, -- 66 MHz
c3 => sr_clk, -- 66 MHz phase shifted to sys_clk
c4 => clk_33, -- 33 MHz
locked => pll_locked
);
-- +-Module Name--------------+-dst-+---offset-+------size-+-bar-+
-- | Chameleon Table | cam | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | flh | 200 | 20 | 0 |
-- |16z002-01 VME REGS | vme | 10000 | 200 | 0 |
-- |16z002-01 VME IACK | vme | 10200 | 200 | 0 |
-- |16z002-01 VME A16D16 | vme | 20000 | 1_0000 | 0 |
-- |16z002-01 VME A16D32 | vme | 30000 | 1_0000 | 0 |
-- | 16z002-01 VME SRAM | ram | 0 | 10_0000 | 1 |
-- |16z002-01 VME A24D16 | vme | 0 | 100_0000 | 2 |
-- |16z002-01 VME A24D32 | vme | 1000000 | 100_0000 | 2 |
-- | 16z002-01 VME A32 | vme | 0 | 2000_0000 | 3 |
-- |16z002-01 VME CR/CSR | vme | 0 | 100_0000 | 4 |
-- +--------------------------+-----+----------+-----------+-----+
process (wbmo_0_cyc_bar, wbmo_0_adr, wbmo_0)
begin
wbmo_0_cyc <= "0000";
wbmo_0.tga(6 DOWNTO 0) <= (others => 'X');
wbmo_0.adr <= wbmo_0_adr;
if wbmo_0_cyc_bar(0) = '1' then
case wbmo_0_adr(17 DOWNTO 16) is
when "00" =>
if wbmo_0_adr(15 DOWNTO 9) = "0000000" then
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
wbmo_0_cyc <= "0001";
elsif wbmo_0_adr(15 DOWNTO 5) = "00000010000" then
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 20 --
wbmo_0_cyc <= "0010";
end if;
when "01" =>
if wbmo_0_adr(8) = '1' then
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_IACK;
else
-- 16z002-01 VME regs - cycle 2 - offset 10000 - size 10000 --
wbmo_0_cyc <= "1000";
wbmo_0.adr(31 downto 10) <= (others => '0');
wbmo_0.adr(9) <= '0';
end if;
when "10" =>
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A16D16;
when "11" =>
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A16D32;
when others =>
null;
end case;
elsif wbmo_0_cyc_bar (1) = '1' then
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
wbmo_0_cyc <= "1000";
wbmo_0.adr(31 downto 10) <= (others => '0');
wbmo_0.adr(9) <= '1';
elsif wbmo_0_cyc_bar (2) = '1' then
wbmo_0_cyc <= "0100";
if wbmo_0_adr(24) = '0' then
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A24D16;
else
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A24D32;
end if;
elsif wbmo_0_cyc_bar (3) = '1' then
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A32D32;
elsif wbmo_0_cyc_bar (4) = '1' then
-- 16z002-01 VME CRCSR - cycle 9 - offset 0 - size 1000000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_CRCSR;
end if;
end process;
wbmo_0.tga(7) <= '0'; -- indicate access from PCIE
wbmo_0.tga(8) <= '0'; -- unused
pcie: entity work.ip_16z091_01_top
GENERIC MAP (
SIMULATION => f_sel_sim_bool(SIMULATION),
FPGA_FAMILY => CYCLONE4,
IRQ_WIDTH => 13,
USE_LANES => f_sel_pcie_lanes(SIMULATION),
PCIE_REQUEST_LENGTH => "0001000000", -- 64DW = 256Byte
RX_LPM_WIDTHU => 10,
TX_HEADER_LPM_WIDTHU => 5,
TX_DATA_LPM_WIDTHU => 7
)
PORT MAP (
-- Hard IP ports:
clk_50 => clk_50,
clk_125 => clk_125,
ref_clk => refclk,
clk_500 => clk_500,
ext_rst_n => hreset_n,
rx_0 => pcie_rx(0),
rx_1 => pcie_rx(1),
rx_2 => pcie_rx(2),
rx_3 => pcie_rx(3),
tx_0 => pcie_tx(0),
tx_1 => pcie_tx(1),
tx_2 => pcie_tx(2),
tx_3 => pcie_tx(3),
wb_clk => sys_clk,
wb_rst => sys_rst,
wbm_ack => wbmi_0.ack,
wbm_dat_i => wbmi_0.dat,
wbm_stb => wbmo_0.stb,
wbm_cyc_bar_o => wbmo_0_cyc_bar,
wbm_we => wbmo_0.we ,
wbm_sel => wbmo_0.sel,
wbm_adr => wbmo_0_adr,
wbm_dat_o => wbmo_0.dat,
wbm_cti => wbmo_0.cti,
wbm_tga => open,
wbs_cyc => wbsi_4_cyc,
wbs_stb => wbsi_4.stb,
wbs_we => wbsi_4.we ,
wbs_sel => wbsi_4.sel,
wbs_adr => wbsi_4.adr,
wbs_dat_i => wbsi_4.dat,
wbs_cti => wbsi_4.cti,
wbs_tga => wbsi_4.tga(0),
wbs_ack => wbso_4.ack,
wbs_err => open,
wbs_dat_o => wbso_4.dat,
irq_req_i(7 downto 0) => vme_irq,
irq_req_i(8) => berr_irq,
irq_req_i(9) => dma_irq,
irq_req_i(10) => locmon_irq(0),
irq_req_i(11) => locmon_irq(1),
irq_req_i(12) => mailbox_irq_i,
error_timeout => open,
error_cor_ext_rcv => open,
error_cor_ext_rpl => open,
error_rpl => open,
error_r2c0 => open,
error_msi_num => open,
link_train_active => open
);
mailbox_irq_i <= mailbox_irq(0) OR mailbox_irq(1);
cham: entity work.iram_wb
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY,
read_only => 1,
USEDW_WIDTH => 9, -- 0x200 = 512
LOCATION => f_sel_cham_hex(SIMULATION)
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
stb_i => wbsi_0.stb,
cyc_i => wbsi_0_cyc,
ack_o => wbso_0.ack,
err_o => wbso_0.err,
we_i => wbsi_0.we,
sel_i => wbsi_0.sel,
adr_i => wbsi_0.adr(10 DOWNTO 2),
dat_i => wbsi_0.dat,
dat_o => wbso_0.dat
);
sr_oe_n <= '1';
sr_cs1_n <= '1'; --sys_rst; -- selected if FPGA reset is released
sflash: entity work.z126_01_top
GENERIC MAP (
SIMULATION => SIMULATION,
FPGA_FAMILY => CYCLONE4,
FLASH_TYPE => M25P32,
USE_DIRECT_INTERFACE => FALSE,
USE_REMOTE_UPDATE => TRUE,
LOAD_FPGA_IMAGE => TRUE,
LOAD_FPGA_IMAGE_ADR => X"200100"
)
PORT MAP (
clk_40mhz => clk_33,
rst_clk_40mhz => rst_33,
clk_dir => sys_clk,
rst_dir => sys_rst,
clk_indi => sys_clk,
rst_indi => sys_rst,
board_status => open,
wbs_stb_dir => '0',
wbs_ack_dir => OPEN,
wbs_we_dir => '0',
wbs_sel_dir => (OTHERS => '0'),
wbs_cyc_dir => '0',
wbs_dat_o_dir => OPEN,
wbs_dat_i_dir => (OTHERS => '0'),
wbs_adr_dir => (OTHERS => '0'),
wbs_err_dir => OPEN,
-- wishbone signals slave interface 1 (indirect addressing)
wbs_stb_indi => wbsi_1.stb,
wbs_ack_indi => wbso_1.ack,
wbs_we_indi => wbsi_1.we,
wbs_sel_indi => wbsi_1.sel,
wbs_cyc_indi => wbsi_1_cyc,
wbs_dat_o_indi => wbso_1.dat,
wbs_dat_i_indi => wbsi_1.dat,
wbs_adr_indi => wbsi_1.adr,
wbs_err_indi => wbso_1.err
);
vme: entity work.wbb2vme_top
GENERIC MAP(
A16_REG_MAPPING => true,
LONGADD_SIZE => 3,
USE_LONGADD => TRUE
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
startup_rst => startup_rst,
postwr => open,
vme_irq => vme_irq ,
berr_irq => berr_irq,
locmon_irq => locmon_irq ,
mailbox_irq => mailbox_irq,
dma_irq => dma_irq ,
prevent_sysrst => '0',
-- Registers
wbr_stb_i => wbsi_3.stb,
wbr_cyc_i => wbsi_3_cyc,
wbr_ack_o => wbso_3.ack,
wbr_err_o => wbso_3.err,
wbr_we_i => wbsi_3.we,
wbr_sel_i => wbsi_3.sel,
wbr_adr_i => wbsi_3.adr,
wbr_dat_i => wbsi_3.dat,
wbr_dat_o => wbso_3.dat,
-- vmectrl slave
wbs_stb_i => wbsi_2.stb,
wbs_ack_o => wbso_2.ack,
wbs_err_o => wbso_2.err,
wbs_we_i => wbsi_2.we,
wbs_sel_i => wbsi_2.sel,
wbs_cyc_i => wbsi_2_cyc,
wbs_adr_i => wbsi_2.adr,
wbs_dat_o => wbso_2.dat,
wbs_dat_i => wbsi_2.dat,
wbs_tga_i => wbsi_2.tga,
wbm_dma_stb_o => wbmo_2.stb,
wbm_dma_ack_i => wbmi_2.ack,
wbm_dma_we_o => wbmo_2.we,
wbm_dma_cti => wbmo_2.cti,
wbm_dma_tga_o => wbmo_2.tga,
wbm_dma_err_i => wbmi_2.err,
wbm_dma_sel_o => wbmo_2.sel,
wbm_dma_cyc_vme => wbmo_2_cyc(0),
wbm_dma_cyc_pci => wbmo_2_cyc(1),
wbm_dma_adr_o => wbmo_2.adr,
wbm_dma_dat_o => wbmo_2.dat,
wbm_dma_dat_i => wbmi_2.dat,
pci_cyc_o => wbmo_3_cyc,
pci_stb_o => wbmo_3.stb,
pci_we_o => wbmo_3.we,
pci_sel_o => wbmo_3.sel,
pci_tga_o => wbmo_3.tga,
pci_cti_o => wbmo_3.cti,
pci_adr_o => wbmo_3.adr,
pci_dat_o => wbmo_3.dat,
pci_dat_i => wbmi_3.dat,
pci_ack_i => wbmi_3.ack,
pci_err_i => wbmi_3.err,
va_o => vme_a_out,
va_i => vme_a,
vd_o => vme_d_out,
vd_i => vme_d,
vam_o => vme_am_out,
vam_i => vme_am,
writen_o => vme_write_n_out,
writen_i => vme_write_n,
iackn_o => vme_iack_n_out,
iackn_i => vme_iack_n,
irq_i_n => vme_irq_i_n,
irq_o_n => vme_irq_o_n,
as_o_n => vme_as_o_n,
as_oe_n => vme_as_oe_n,
as_i_n => vme_as_i_n,
sysresn => vme_sysres_o_n,
sysresin => vme_sysres_i_n,
ds_o_n => vme_ds_o_n,
ds_i_n => vme_ds_i_n,
ds_oe_n => vme_ds_oe_n,
berrn => vme_berr_o_n,
berrin => vme_berr_i_n,
dtackn => vme_dtack_o_n,
dtackin => vme_dtack_i_n,
slot01n => slot01n,
sysfail_i_n => vme_sysfail_i_n,
sysfail_o_n => vme_sysfail_o_n,
bbsyn => vme_bbsy_o_n,
bbsyin => vme_bbsy_i_n,
bclr_i_n => vme_bclr_i_n,
bclr_o_n => vme_bclr_o_n,
retry_i_n => vme_retry_i_n ,
retry_o_n => vme_retry_o_n ,
retry_oe_n => vme_retry_oe_n ,
br_i_n => vme_br_i_n,
br_o_n => vme_br_o_n,
iackin => vme_iack_i_n,
iackoutn => vme_iack_o_n,
acfailn => vme_acfail_i_n,
bg_i_n => vme_bg_i_n,
bg_o_n => vme_bg_o_n,
ga => vme_ga,
gap => vme_gap,
vme_berr => vme_berr,
vme_mstr_busy => vme_mstr_busy,
d_dir => vme_d_dir_int,
d_oe_n => vme_d_oe_n_int,
am_dir => vme_am_dir_int,
am_oe_n => vme_am_oe_n_int,
a_dir => vme_a_dir_int,
a_oe_n => vme_a_oe_n_int,
v2p_rst => v2p_rst
);
vme_a_oe_n <= vme_a_oe_n_int;
vme_a_dir <= vme_a_dir_int;
vme_a <= vme_a_out when vme_a_oe_n_int = '0' and vme_a_dir_int = '1' else (others => 'Z');
vme_d_oe_n <= vme_d_oe_n_int;
vme_d_dir <= vme_d_dir_int;
vme_d <= vme_d_out when vme_d_oe_n_int = '0' and vme_d_dir_int = '1' else (others => 'Z');
vme_am_oe_n <= vme_am_oe_n_int;
vme_am_dir <= vme_am_dir_int;
vme_write_n <= vme_write_n_out when vme_am_oe_n_int = '0' and vme_am_dir_int = '1' else 'Z';
vme_am <= vme_am_out when vme_am_oe_n_int = '0' and vme_am_dir_int = '1' else (others => 'Z');
vme_iack_n <= vme_iack_n_out when vme_am_oe_n_int = '0' and vme_am_dir_int = '1' else 'Z';
wbb : entity work.wb_bus
GENERIC MAP (
sets => sets,
timeout => timeout
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
wbmo_0 => wbmo_0,
wbmi_0 => wbmi_0,
wbmo_0_cyc => wbmo_0_cyc,
wbmo_2 => wbmo_2,
wbmi_2 => wbmi_2,
wbmo_2_cyc => wbmo_2_cyc,
wbmo_3 => wbmo_3,
wbmi_3 => wbmi_3,
wbmo_3_cyc => wbmo_3_cyc,
wbso_0 => wbso_0,
wbsi_0 => wbsi_0,
wbsi_0_cyc => wbsi_0_cyc,
wbso_1 => wbso_1,
wbsi_1 => wbsi_1,
wbsi_1_cyc => wbsi_1_cyc,
wbso_2 => wbso_2,
wbsi_2 => wbsi_2,
wbsi_2_cyc => wbsi_2_cyc,
wbso_3 => wbso_3,
wbsi_3 => wbsi_3,
wbsi_3_cyc => wbsi_3_cyc,
wbso_4 => wbso_4,
wbsi_4 => wbsi_4,
wbsi_4_cyc => wbsi_4_cyc
);
-------------------------------------------------------------------------------------------------------------
END A25_top_arch;
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/top/Manifest.py 0000664 0000000 0000000 00000001214 14574545710 0030600 0 ustar 00root root 0000000 0000000 # SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../dependencies"
modules = {
"local" : [
"../16z000-00_src/",
"../16z024-01_src/",
"../16z091-01_src/",
"../16z100-00_src/",
"../16z126-01_src/",
],
"git" : [
"https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/vme-bridge.git",
"https://ohwr.org/project/general-cores.git",
],
}
files = [
"A25_top.vhd",
"wb_bus.vhd",
"wb_pkg.vhd",
]
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/top/cham2.bat 0000664 0000000 0000000 00000000563 14574545710 0030150 0 ustar 00root root 0000000 0000000 REM SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
REM
REM SPDX-License-Identifier: GPL-3.0-or-later
set OLDDIR=%CD%
cd ..\..\software\tools\16t001-00_bin\Bin
chameleon_v2.exe -i=..\..\..\..\hdl\top\chameleon_V2.xls -a=wb
copy chameleon.hex ..\..\..\..\hdl\top\chameleon.hex
copy wb_adr_dec.vhd ..\..\..\..\hdl\top\wb_adr_dec.vhd
chdir /d %OLDDIR%
pause 1
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/top/cham2.sh 0000775 0000000 0000000 00000000514 14574545710 0030013 0 ustar 00root root 0000000 0000000 #!/bin/bash
# SPDX-FileCopyrightText: 2016 MEN Mikro Elektronik GmbH
#
# SPDX-License-Identifier: GPL-3.0-or-later
# This script does the same as cham2.bat for Linux synthesis environment
../../software/tools/16t001-00_bin/Bin/Chameleon_V2 -i chameleon_V2.xls -a=wb -x ../../software/tools/16t001-00_src/Source/device_config.xml
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/top/chameleon.hex 0000664 0000000 0000000 00000002414 14574545710 0031124 0 ustar 00root root 0000000 0000000 :0400000000104103a8
:040001000000abce82
:0400020000000000fa
:040003003230410056
:0400040030302d3536
:04000500006013ff85
:0400060000000000f6
:0400070000000000f5
:0400080000000200f2
:0400090001f8037f78
:04000a0000000000f2
:04000b0000000200ef
:04000c0000000010e0
:04000d0000082401c2
:04000e0000000200ec
:04000f0000010000ec
:0400100000000200ea
:040011000008303f74
:0400120000000200e8
:0400130000020000e7
:0400140000010000e7
:040015000008403f60
:0400160000000200e4
:0400170000030000e2
:0400180000010000e3
:040019000008503f4c
:04001a0000000201df
:04001b0000000000e1
:04001c0000100000d0
:04001d000008603f38
:04001e0000000202da
:04001f0000000000dd
:0400200001000000db
:040021000008703f24
:0400220000000202d6
:0400230001000000d8
:0400240001000000d7
:040025000008803f10
:0400260000000203d1
:0400270000000000d5
:0400280020000000b4
:040029000008903ffc
:04002a0000000204cc
:04002b0000000000d1
:04002c0001000000cf
:04002d00ffffffffd3
:04002e00ffffffffd2
:04002f00ffffffffd1
:04003000ffffffffd0
:04003100ffffffffcf
:04003200ffffffffce
:04003300ffffffffcd
:04003400ffffffffcc
:04003500ffffffffcb
:04003600ffffffffca
:04003700ffffffffc9
:04003800ffffffffc8
:04003900ffffffffc7
:04003a00ffffffffc6
:04003b00ffffffffc5
:04003c00ffffffffc4
:04003d00ffffffffc3
:04003e00ffffffffc2
:04003f00ffffffffc1
:00000001ff
vme-sbc-a25-pcie-vme-bridge-master-7b3abf92979dfd14bcad792d3bb31dbd51332e07/hdl/top/chameleon_V2.xls0000664 0000000 0000000 00000045000 14574545710 0031513 0 ustar 00root root 0000000 0000000 ࡱ > " #
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Type0-General 1 Type1-Bridge : Type2-CPU r@ Type3-BAR b Z
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< K Chameleon V2 Bus Type Model (Char) Revision MinRevision Filename ArchName AdrDec Device ID Vendor ID SubSysID
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Interrupt Pin Interrupt Line
Class Code Lat Timer General Descriptors Name Device Variant Interrupt Group Instance BAR Offset Size Bridge Descriptors DBAR Cham Offset CPU Descriptors Boot Address BAR Descriptors Base Address Bar Size A A025-00
wb_adr_dec wb 4d45 1a88 5a91 00D5 Chameleon Table 24 1 F 3F 0 200 16Z126_SERFLASH 126 D 10
16z002-01 VME 2 10000 16z002-01 VME A16D16 3 20000 16z002-01 VME A16D32 4 30000 16z002-01 VME SRAM 5 100000 16z002-01 VME A24D16 6 1000000 16z002-01 VME A24D32 7 16z002-01 VME A32 8 20000000 16z002-01 VME CR/CSR 9 R Z m , G Z
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