Resolve "HDL: use fifo from general-cores (part 2)"

Closes #14

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!10

Resolve "HDL: update vme-bridge and use dedicated WB bus for regs"

Closes #17

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!13

And minor cleanup

Remove internal sram (now a dpram in the registers)

Resolve "HDL: simplify address decoder from PCIe"

Closes #16

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!12

Remove z091_01_wb_adr_dec.vhd

simply export selected BAR as cyc signals,
move address decoding in A25_top.vhd

Resolve "HDL: adjust after inout port removal"

Closes #15

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!11

Add the tri-state in A25_top.vhd

Resolve "HDL: simplify"

Closes #13

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!9

Remove components, add comments, fix sensitivity

Resolve "HDL: use fifos from general cores (part 1)"

Closes #12

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!8

Resolve "HDL: simplify"

Closes #11

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!7

to the Manifest.py which needs it

And remove useless component declarations

unused

Remove unused components, and some blanks.

Remove a useless sensitivity

Resolve "Get rid of external sram"

Closes #8

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!5

Resolve "README: explain how to flash using ht-flasher"

Closes #9

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!6

Resolve "Fix synthesis failures"

Closes #7

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!4