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PPSi
Commit 8240a87d authored by Jean-Claude BAU's avatar Jean-Claude BAU
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Export LEDs control logic in PPSi 

The logic used to control WR switch leds is removed from HAL and
imported into PPSi. It prevents HAL from reading PPSi shared memory.
parent 9ef24075
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Showing with 127 additions and 20 deletions
arch-wrs/Makefile
View file @ 8240a87d
......@@ -14,6 +14,7 @@ OBJ-y += $A/wrs-startup.o \
$A/wrs-io.o \
$A/wrs-conf.o \
$A/wrs-calibration.o \
$A/wrs-port.o \
$A/wrs-ipcserver.o \
$A/shmem.o \
$A/util.o \
......
arch-wrs/hal_minirpc.c
View file @ 8240a87d
......@@ -60,10 +60,12 @@ struct minipc_pd __rpcdef_pps_cmd = {
},
};
struct minipc_pd __rpcdef_get_timing_state = {
.name = "get_timing_state",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_timing_state_t),
//int halexp_info_cmd(hexp_info_params_t *params);
struct minipc_pd __rpcdef_port_update_cmd = {
.name = "info_cmd",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_port_info_params_t),
MINIPC_ARG_END,
},
};
......
arch-wrs/include/hal_exports.h
View file @ 8240a87d
......@@ -83,6 +83,22 @@ typedef struct {
uint32_t timing_mode;
} hexp_pps_params_t;
#define PORT_MODE_OTHER 0
#define PORT_MODE_SLAVE 1
#define PORT_MODE_MASTER 2
typedef struct {
char name[16]; // Interface name
int synchronized; // <>0 : Master/Slave are synchronized
int mode; // PORT_MODE_XXXX
}hexp_port_info_t;
typedef struct {
int numberPortInterfaces;
hexp_port_info_t hIFace[HAL_MAX_PORTS];
} hexp_port_info_params_t;
/* Port modes (hal_port_state.mode) */
#define HEXP_PORT_MODE_WR_MASTER 1
#define HEXP_PORT_MODE_WR_SLAVE 2
......@@ -96,11 +112,9 @@ typedef struct {
#define HEXP_PORT_TSC_FALLING 2
*/
typedef struct {
int timing_mode; /* Free-running Master/GM/BC */
int locked_port;
} hexp_timing_state_t;
extern struct minipc_pd __rpcdef_lock_cmd;
extern struct minipc_pd __rpcdef_pps_cmd;
extern struct minipc_pd __rpcdef_port_update_cmd;
/* Prototypes of functions that call on rpc */
extern int halexp_check_running(void);
......@@ -108,6 +122,5 @@ extern int halexp_reset_port(const char *port_name);
extern int halexp_calibration_cmd(const char *port_name, int command, int on_off);
extern int halexp_lock_cmd(const char *port_name, int command, int priority);
extern int halexp_pps_cmd(int cmd, hexp_pps_params_t *params);
extern int halexp_get_timing_state(hexp_timing_state_t *state);
#endif
arch-wrs/include/libwr/hal_shmem.h
View file @ 8240a87d
......@@ -17,6 +17,10 @@
#define READ_SFP_DIAG_ENABLE 1
#define READ_SFP_DIAG_DISABLE 0
/* Monitor port in SNMP */
#define HAL_PORT_MONITOR_ENABLE 1
#define HAL_PORT_MONITOR_DISABLE 2
#define DEFAULT_T2_PHASE_TRANS 0
#define DEFAULT_T4_PHASE_TRANS 0
......@@ -113,6 +117,11 @@ struct hal_port_state {
/* whether the port shall be monitored by SNMP */
int monitor;
/* PPSi instance information */
int portMode; // Instance state
int synchronized; // <>0 if port is synchronized
int portInfoUpdated; // Set to 1 when updated
};
struct hal_temp_sensors {
......
arch-wrs/include/ppsi-wrs.h
View file @ 8240a87d
......@@ -66,4 +66,5 @@ timing_mode_t wrs_get_timing_mode(struct pp_globals *);
timing_mode_state_t wrs_get_timing_mode_state(struct pp_globals *);
int wrs_set_timing_mode(struct pp_globals *,timing_mode_t tm);
timing_mode_t wrs_get_timing_mode(struct pp_globals *ppg);
int wrs_update_port_info(struct pp_globals *ppg);
arch-wrs/main-loop.c
View file @ 8240a87d
......@@ -22,13 +22,22 @@
#include <hal_exports.h>
#include <common-fun.h>
#define UPDATE_PORT_INFO_COUNT 2 // Update the port info every X time of the BMCA trigger
/* Call pp_state_machine for each instance. To be called periodically,
* when no packets are incoming */
static unsigned int run_all_state_machines(struct pp_globals *ppg)
{
static int portInfoTmoIdx=-1;
int j;
int delay_ms = 0, delay_ms_j;
if ( portInfoTmoIdx==-1) {
portInfoTmoIdx=pp_gtimeout_get_timer(ppg, "SEND_PORT_INFO", TO_RAND_NONE, 0);
pp_gtimeout_set(ppg,portInfoTmoIdx,2000); // Update interface info every 2 seconds
}
for (j = 0; j < ppg->nlinks; j++) {
struct pp_instance *ppi = INST(ppg, j);
int old_lu = ppi->link_up;
......@@ -91,10 +100,9 @@ static unsigned int run_all_state_machines(struct pp_globals *ppg)
}
/* Do not call state machine if link is down */
if (ppi->link_up)
delay_ms_j = pp_state_machine(ppi, NULL, 0);
else
delay_ms_j = PP_DEFAULT_NEXT_DELAY_MS;
delay_ms_j = ppi->link_up ?
pp_state_machine(ppi, NULL, 0) :
PP_DEFAULT_NEXT_DELAY_MS;
/* delay_ms is the least delay_ms among all instances */
if (j == 0)
......@@ -115,6 +123,11 @@ static unsigned int run_all_state_machines(struct pp_globals *ppg)
delay_ms=delay_bmca;
}
if ( pp_gtimeout(ppg, portInfoTmoIdx) ) {
wrs_update_port_info(ppg);
pp_gtimeout_reset(ppg,portInfoTmoIdx);
}
return delay_ms;
}
......
arch-wrs/wrs-port.c 0 → 100644
View file @ 8240a87d
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Jean-Claude BAU
*
* Released according to GNU LGPL, version 2.1 or any later
*/
#include <ppsi/ppsi.h>
#define HAL_EXPORT_STRUCTURES
#include <ppsi-wrs.h>
#include <hal_exports.h>
static hexp_port_info_t *getPortSlot (hexp_port_info_params_t * infos,struct pp_instance *ppi) {
int i;
hexp_port_info_t *pinfo;
for (i = 0; i < infos->numberPortInterfaces; i++) {
pinfo=&infos->hIFace[i];
if ( !strcmp(pinfo->name,ppi->iface_name) )
return pinfo;
}
pinfo=&infos->hIFace[infos->numberPortInterfaces];
strcpy(pinfo->name,ppi->iface_name);
pinfo->mode=PORT_MODE_OTHER;
pinfo->synchronized=0;
infos->numberPortInterfaces++;
return pinfo;
}
/* Send information about the port for a given instance
* As many instances can be on the same port, only information on the most
* interesting port will be sent.
* Priority :
* 1/ Slave instance
* 2/ Master instance
* 3/ Other
*/
int wrs_update_port_info(struct pp_globals *ppg) {
int i;
int ret, rval;
hexp_port_info_params_t infos={.numberPortInterfaces = 0};
int nbLinks=ppg->nlinks;
for (i = 0; i < nbLinks; i++) {
struct pp_instance *ppi=INST(ppg, i);
if (ppi->link_up) {
hexp_port_info_t *pSlot=getPortSlot(&infos,ppi);
if ( ppi->state==PPS_SLAVE ) {
pSlot->mode=PORT_MODE_SLAVE;
if (!pSlot->synchronized )
pSlot->synchronized=
SRV(ppi)->servo_locked &&
(ppi->protocol_extension==PPSI_EXT_WR || ppi->protocol_extension==PPSI_EXT_L1S) &&
ppi->ext_enabled;
} else {
if ( ppi->state==PPS_MASTER && pSlot->mode!=PORT_MODE_SLAVE ) {
pSlot->mode=PORT_MODE_MASTER;
}
}
}
}
ret = minipc_call(hal_ch, DEFAULT_TO, &__rpcdef_port_update_cmd,
&rval, &infos);
if (ret < 0)
return -1;
return rval;
}
proto-ext-l1sync/l1e-hooks.c
View file @ 8240a87d
......@@ -178,6 +178,9 @@ static int l1e_ready_for_slave(struct pp_instance *ppi)
}
static void l1e_state_change(struct pp_instance *ppi) {
pp_diag(ppi, ext, 2, "hook: %s\n", __func__);
if ( !ppi->ext_enabled)
return;
switch (ppi->next_state) {
......
time-wrs/wrs-time.c
View file @ 8240a87d
......@@ -17,13 +17,6 @@
#include <hal_exports.h>
#include "../include/hw-specific/wrh.h"
/* FIXME: these externs are needed here because we can not include
* hal_exports.h with HAL_EXPORT_STRUCTURES twice (the first is by
* arch-wrs/wrs-calibration.c): structs are declared and
* defined in .h file, so this would lead to a multiple definition. */
extern struct minipc_pd __rpcdef_pps_cmd;
extern struct minipc_pd __rpcdef_lock_cmd;
int wrs_adjust_counters(int64_t adjust_sec, int32_t adjust_nsec)
{
hexp_pps_params_t p;
......
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