pax_global_header 0000666 0000000 0000000 00000000064 12165512365 0014520 g ustar 00root root 0000000 0000000 52 comment=64a2c3acda6831551673e417e5bc0e9cf0274a40
pts-base-fmc-delay/ 0000775 0000000 0000000 00000000000 12165512365 0014441 5 ustar 00root root 0000000 0000000 pts-base-fmc-delay/.gitignore 0000664 0000000 0000000 00000000012 12165512365 0016422 0 ustar 00root root 0000000 0000000 *.pyc
*.so pts-base-fmc-delay/LICENSE 0000664 0000000 0000000 00000001327 12165512365 0015451 0 ustar 00root root 0000000 0000000 Production Test Suite, automatized tests for OHWR boards.
Copyright (C) 2011 CERN
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
pts-base-fmc-delay/README 0000664 0000000 0000000 00000000215 12165512365 0015317 0 ustar 00root root 0000000 0000000 This is Production Test Suite project.
Supporting automated hardware testing at BE/CO/HT
since 2011 or even less
License: GPL v2 or later
pts-base-fmc-delay/common/ 0000775 0000000 0000000 00000000000 12165512365 0015731 5 ustar 00root root 0000000 0000000 pts-base-fmc-delay/common/csr.py 0000664 0000000 0000000 00000001331 12165512365 0017070 0 ustar 00root root 0000000 0000000 #!/usr/bin/python
import sys
import rr
import time
class CCSR:
def __init__(self, bus, base_addr):
self.base_addr = base_addr;
self.bus = bus;
def wr_reg(self, addr, val):
#print(" wr:%.8X reg:%.8X")%(val,(self.base_addr+addr))
self.bus.iwrite(0, self.base_addr + addr, 4, val)
def rd_reg(self, addr):
reg = self.bus.iread(0, self.base_addr + addr, 4)
#print(" reg:%.8X value:%.8X")%((self.base_addr+addr), reg)
return reg
def wr_bit(self, addr, bit, value):
reg = self.rd_reg(addr)
if(0==value):
reg &= ~(1<