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Production Test Suite - base
Commit 988ffd32 authored by Matthieu Cattin's avatar Matthieu Cattin
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common:gn4124: Allow dma items to pages 0 to 254 (was only page 0).

parent 2ff9a8c4
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Showing with 5 additions and 4 deletions
common/gn4124.py
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......@@ -191,17 +191,18 @@ class CGN4124:
self.dma_csr.wr_reg(self.R_DMA_ATTRIB, attrib)
else:
# write nexy DMA item(s) in host memory
# uses page 0 to store DMA items
# uses 255 pages (out of 256) to store DMA items
# current and next item addresses are automatically set
if (self.dma_item_cnt*0x20) > self.PAGE_SIZE:
if (self.dma_item_cnt*0x20) > self.PAGE_SIZE * 255:
raise GN4124OperationError('Maximum number of DMA items exceeded!')
current_item_addr = (self.dma_item_cnt-1)*0x20
next_item_addr = (self.dma_item_cnt)*0x20
next_item_page = ((self.dma_item_cnt)*0x20)/0x1000
self.wr_reg(self.HOST_BAR, self.HOST_DMA_CARRIER_START_ADDR + current_item_addr, carrier_addr)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_HOST_START_ADDR_L + current_item_addr, host_addr)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_HOST_START_ADDR_H + current_item_addr, 0x0)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_LENGTH + current_item_addr, length)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_L + current_item_addr, self.pages[0] + next_item_addr)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_L + current_item_addr, self.pages[next_item_page] + (next_item_addr & 0xFFF))
self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_H + current_item_addr, 0x0)
attrib = (dma_dir << self.DMA_ATTRIB_DIR) + (last_item << self.DMA_ATTRIB_LAST)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_ATTRIB + current_item_addr, attrib)
......@@ -218,7 +219,7 @@ class CGN4124:
print("0x%02X: 0x%08X"%(addr, self.dma_csr.rd_reg(addr)))
print("Items in host memory:")
for item in range(self.PAGE_SIZE/0x20):
for item in range(self.dma_item_cnt*0x20):
print("Item %d:"%item)
for addr in range(0x0, 0x20, 0x4):
print("0x%02X: 0x%08X"%(item*0x20 + addr, self.rd_reg(self.HOST_BAR, item*0x20 + addr)))
......
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