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Production Test Suite - base
Commits
e1613c48
Commit
e1613c48
authored
Jul 12, 2013
by
Matthieu Cattin
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common: remove useless import (rawrabbit library).
parent
f23a9beb
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10 changed files
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4 additions
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10 deletions
+4
-10
csr.py
common/csr.py
+1
-1
ds18b20.py
common/ds18b20.py
+0
-1
eeprom_24aa64.py
common/eeprom_24aa64.py
+0
-1
gn4124.py
common/gn4124.py
+0
-1
i2c.py
common/i2c.py
+1
-1
ltc217x.py
common/ltc217x.py
+0
-1
max5442.py
common/max5442.py
+0
-1
onewire.py
common/onewire.py
+1
-1
si57x.py
common/si57x.py
+0
-1
spi.py
common/spi.py
+1
-1
No files found.
common/csr.py
View file @
e1613c48
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@@ -11,7 +11,7 @@ import sys
import
time
# Import specific modules
import
rr
# Class to access 32-bit wishbone registers on BAR0
...
...
common/ds18b20.py
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e1613c48
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@@ -13,7 +13,6 @@ import sys
import
time
# Import specific modules
import
rr
from
onewire
import
*
# Class to access the DS18B20 (temperature sensor & unique ID) chip.
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common/eeprom_24aa64.py
View file @
e1613c48
...
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@@ -13,7 +13,6 @@ import sys
import
time
# Import specific modules
import
rr
from
i2c
import
*
# Class to access the 24AA64 (64K EEPROM) chip.
...
...
common/gn4124.py
View file @
e1613c48
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@@ -12,7 +12,6 @@ import sys
import
time
# Import specific modules
import
rr
import
csr
# Class to access the GN4124 (PCIe bridge) chip.
...
...
common/i2c.py
View file @
e1613c48
...
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@@ -13,7 +13,7 @@ import sys
import
time
# Import specific modules
import
rr
# Class to access the wishbone to I2C master module from OpenCores
# http://opencores.org/project,i2c
...
...
common/ltc217x.py
View file @
e1613c48
...
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@@ -12,7 +12,6 @@ import sys
import
time
# Import specific modules
import
rr
from
spi
import
*
# Class to access the LTC217x (ADC) chip.
...
...
common/max5442.py
View file @
e1613c48
...
...
@@ -12,7 +12,6 @@ import sys
import
time
# Import specific modules
import
rr
from
spi
import
*
# Class to access the MAX5442 (DAC) chip.
...
...
common/onewire.py
View file @
e1613c48
...
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@@ -13,7 +13,7 @@ import sys
import
time
# Import specific modules
import
rr
# Class to access the wishbone to onewire master module from OpenCores
# http://opencores.org/project,sockit_owm
...
...
common/si57x.py
View file @
e1613c48
...
...
@@ -12,7 +12,6 @@ import sys
import
time
# Import specific modules
import
rr
from
i2c
import
*
# Class to access the Si57x (VCXO) chip.
...
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common/spi.py
View file @
e1613c48
...
...
@@ -12,7 +12,7 @@ import sys
import
time
# Import specific modules
import
rr
# Class to access the wishbone to SPI master module from OpenCores
# http://opencores.org/project,spi
...
...
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