board  = "spec"
target = "xilinx"
action = "synthesis"

syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_pts_ddr"
syn_project = "spec_pts_ddr.xise"
syn_tool = "ise"

files = ["spec_pts_ddr.ucf"]

modules = { "local" : "../rtl" }

ctrls = ["bank3_32b_32b"]