/*
  Register definitions for slave core: SPEC PTS clock counter test control and status registers

  * File           : clkcnt_csr.h
  * Author         : auto-generated by wbgen2 from clkcnt_csr.wb
  * Created        : Tue May 21 12:18:24 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE clkcnt_csr.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_CLKCNT_CSR_WB
#define __WBGEN2_REGDEFS_CLKCNT_CSR_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Counter full status */

/* definitions for field: Counter full in reg: Counter full status */
#define CLKCNT_STAT_CNT_FULL                  WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Reserved register in reg: Counter full status */
#define CLKCNT_STAT_RESERVED0_MASK            WBGEN2_GEN_MASK(1, 31)
#define CLKCNT_STAT_RESERVED0_SHIFT           1
#define CLKCNT_STAT_RESERVED0_W(value)        WBGEN2_GEN_WRITE(value, 1, 31)
#define CLKCNT_STAT_RESERVED0_R(reg)          WBGEN2_GEN_READ(reg, 1, 31)

/* definitions for register: Counter error status */

/* definitions for field: Counter error in reg: Counter error status */
#define CLKCNT_STAT_CNT_ERR                   WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Reserved register in reg: Counter error status */
#define CLKCNT_STAT_RESERVED1_MASK            WBGEN2_GEN_MASK(1, 31)
#define CLKCNT_STAT_RESERVED1_SHIFT           1
#define CLKCNT_STAT_RESERVED1_W(value)        WBGEN2_GEN_WRITE(value, 1, 31)
#define CLKCNT_STAT_RESERVED1_R(reg)          WBGEN2_GEN_READ(reg, 1, 31)

/* definitions for register: Clock output enable control */

/* definitions for field: Clock output enable in reg: Clock output enable control */
#define CLKCNT_CTRL_CLK_OE                    WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Reserved register in reg: Clock output enable control */
#define CLKCNT_CTRL_RESERVED2_MASK            WBGEN2_GEN_MASK(1, 31)
#define CLKCNT_CTRL_RESERVED2_SHIFT           1
#define CLKCNT_CTRL_RESERVED2_W(value)        WBGEN2_GEN_WRITE(value, 1, 31)
#define CLKCNT_CTRL_RESERVED2_R(reg)          WBGEN2_GEN_READ(reg, 1, 31)

/* definitions for register: Counter top value control */

/* definitions for field: Counter top value in reg: Counter top value control */
#define CLKCNT_CTRL_CNT_TOP_MASK              WBGEN2_GEN_MASK(0, 32)
#define CLKCNT_CTRL_CNT_TOP_SHIFT             0
#define CLKCNT_CTRL_CNT_TOP_W(value)          WBGEN2_GEN_WRITE(value, 0, 32)
#define CLKCNT_CTRL_CNT_TOP_R(reg)            WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: Counter value status */

/* definitions for field: Counter value in reg: Counter value status */
#define CLKCNT_STAT_CNT_VAL_MASK              WBGEN2_GEN_MASK(0, 32)
#define CLKCNT_STAT_CNT_VAL_SHIFT             0
#define CLKCNT_STAT_CNT_VAL_W(value)          WBGEN2_GEN_WRITE(value, 0, 32)
#define CLKCNT_STAT_CNT_VAL_R(reg)            WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: Counter reset control */

/* definitions for field: Counter reset in reg: Counter reset control */
#define CLKCNT_CTRL_CNT_RST                   WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Reserved register in reg: Counter reset control */
#define CLKCNT_CTRL_RESERVED3_MASK            WBGEN2_GEN_MASK(1, 31)
#define CLKCNT_CTRL_RESERVED3_SHIFT           1
#define CLKCNT_CTRL_RESERVED3_W(value)        WBGEN2_GEN_WRITE(value, 1, 31)
#define CLKCNT_CTRL_RESERVED3_R(reg)          WBGEN2_GEN_READ(reg, 1, 31)

/* definitions for register: Counter enable control */

/* definitions for field: Counter enable in reg: Counter enable control */
#define CLKCNT_CTRL_CNT_EN                    WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Reserved register in reg: Counter enable control */
#define CLKCNT_CTRL_RESERVED4_MASK            WBGEN2_GEN_MASK(1, 31)
#define CLKCNT_CTRL_RESERVED4_SHIFT           1
#define CLKCNT_CTRL_RESERVED4_W(value)        WBGEN2_GEN_WRITE(value, 1, 31)
#define CLKCNT_CTRL_RESERVED4_R(reg)          WBGEN2_GEN_READ(reg, 1, 31)

PACKED struct CLKCNT_WB {
  /* [0x0]: REG Counter full status */
  uint32_t STAT;
  /* [0x4]: REG Counter error status */
  uint32_t STAT;
  /* [0x8]: REG Clock output enable control */
  uint32_t CTRL;
  /* [0xc]: REG Counter top value control */
  uint32_t CTRL;
  /* [0x10]: REG Counter value status */
  uint32_t STAT;
  /* [0x14]: REG Counter reset control */
  uint32_t CTRL;
  /* [0x18]: REG Counter enable control */
  uint32_t CTRL;
};

#endif
