library ieee;
use ieee.std_logic_1164.all;

package phy_pkg is

  type t_phy_out is record
    rx_d: std_logic_vector(15 downto 0);
    rx_k: std_logic_vector(1 downto 0);
    rx_error: std_logic;
    tx_error: std_logic;
    tx_disparity: std_logic;
    rx_bitslide: std_logic_vector(4 downto 0);
    rx_clk: std_logic;
  end record;

  type t_phy_in is record
    tx_d: std_logic_vector(15 downto 0);
    tx_k: std_logic_vector(1 downto 0);
    loopen: std_logic;
    rst: std_logic;
  end record;

end phy_pkg;
