Wishbone slave for control and status registers related to the clock tests
H/W Address | Type | Name | VHDL/Verilog prefix | C prefix |
---|---|---|---|---|
0x0 | REG | Counter full status | clkcnt_stat | STAT |
0x1 | REG | Counter error status | clkcnt_stat | STAT |
0x2 | REG | Clock output enable control | clkcnt_ctrl | CTRL |
0x3 | REG | Counter top value control | clkcnt_ctrl | CTRL |
0x4 | REG | Counter value status | clkcnt_stat | STAT |
0x5 | REG | Counter reset control | clkcnt_ctrl | CTRL |
0x6 | REG | Counter enable control | clkcnt_ctrl | CTRL |
→ | rst_n_i | Counter full status: | ||
→ | clk_sys_i | clkcnt_stat_cnt_full_i | ← | |
⇒ | wb_adr_i[2:0] | clkcnt_stat_reserved0_i[30:0] | ⇐ | |
⇒ | wb_dat_i[31:0] | |||
⇐ | wb_dat_o[31:0] | Counter error status: | ||
→ | wb_cyc_i | clkcnt_stat_cnt_err_i | ← | |
⇒ | wb_sel_i[3:0] | clkcnt_stat_reserved1_i[30:0] | ⇐ | |
→ | wb_stb_i | |||
→ | wb_we_i | Clock output enable control: | ||
← | wb_ack_o | clkcnt_ctrl_clk_oe_o | → | |
← | wb_stall_o | clkcnt_ctrl_reserved2_o[30:0] | ⇒ | |
Counter top value control: | ||||
clkcnt_ctrl_cnt_top_o[31:0] | ⇒ | |||
Counter value status: | ||||
clkcnt_stat_cnt_val_i[31:0] | ⇐ | |||
Counter reset control: | ||||
clkcnt_ctrl_cnt_rst_o | → | |||
clkcnt_ctrl_reserved3_o[30:0] | ⇒ | |||
Counter enable control: | ||||
clkcnt_ctrl_cnt_en_o | → | |||
clkcnt_ctrl_reserved4_o[30:0] | ⇒ |
HW prefix: | clkcnt_stat |
HW address: | 0x0 |
C prefix: | STAT |
C offset: | 0x0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED0[30:23] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED0[22:15] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
RESERVED0[14:7] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED0[6:0] | CNT_FULL |
HW prefix: | clkcnt_stat |
HW address: | 0x1 |
C prefix: | STAT |
C offset: | 0x4 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED1[30:23] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED1[22:15] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
RESERVED1[14:7] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED1[6:0] | CNT_ERR |
HW prefix: | clkcnt_ctrl |
HW address: | 0x2 |
C prefix: | CTRL |
C offset: | 0x8 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED2[30:23] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED2[22:15] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
RESERVED2[14:7] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED2[6:0] | CLK_OE |
HW prefix: | clkcnt_ctrl |
HW address: | 0x3 |
C prefix: | CTRL |
C offset: | 0xc |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
CNT_TOP[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
CNT_TOP[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
CNT_TOP[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
CNT_TOP[7:0] |
HW prefix: | clkcnt_stat |
HW address: | 0x4 |
C prefix: | STAT |
C offset: | 0x10 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
CNT_VAL[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
CNT_VAL[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
CNT_VAL[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
CNT_VAL[7:0] |
HW prefix: | clkcnt_ctrl |
HW address: | 0x5 |
C prefix: | CTRL |
C offset: | 0x14 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED3[30:23] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED3[22:15] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
RESERVED3[14:7] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED3[6:0] | CNT_RST |
HW prefix: | clkcnt_ctrl |
HW address: | 0x6 |
C prefix: | CTRL |
C offset: | 0x18 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED4[30:23] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED4[22:15] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
RESERVED4[14:7] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED4[6:0] | CNT_EN |