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0377f85e
Commit
0377f85e
authored
Apr 24, 2014
by
Matthieu Cattin
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fmcadc100m_csr: Fix Sampling clock reg description.
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94555e16
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fmcadc100m_csr.py
test/fmcadc100m14b4cha/python/fmcadc100m_csr.py
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test/fmcadc100m14b4cha/python/fmcadc100m_csr.py
View file @
0377f85e
...
...
@@ -44,7 +44,7 @@ FMCADC100M_CSR=['FMC ADC 100MS/s core registers',{
'NB'
:[
0
,
'Number of remaining shots'
,
0xFFFF
],
'RESERVED'
:[
16
,
'Reserved'
,
0xFFFF
]}],
'TRIG_POS'
:[
0x1C
,
'Trigger address register'
,
{}],
'FS_FREQ'
:[
0x20
,
'Sampl
e rate
'
,
{}],
'FS_FREQ'
:[
0x20
,
'Sampl
ing clock [Hz]
'
,
{}],
'SR'
:[
0x24
,
'Sample rate'
,
{
'DECI'
:[
0
,
'Sample rate decimation factor'
,
0xFFFFFFFF
]}],
'PRE_SAMPLES'
:[
0x28
,
'Pre-trigger samples'
,
{}],
...
...
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