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Commit 0ce6d3a8 authored by Matthieu Cattin's avatar Matthieu Cattin
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fmcadc_csr, test32: Extend decimation register to 32 bits. Add a decimation test.

parent 70c5f9a7
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test/fmcadc100m14b4cha/python/fmcadc100m_csr.py
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......@@ -39,8 +39,7 @@ FMCADC100M_CSR=['FMC ADC 100MS/s core registers',{
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'TRIG_POS':[0x18, 'Trigger address register', {}],
'SR':[0x1C, 'Sample rate', {
'DECI':[0, 'Sample rate decimation factor', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'DECI':[0, 'Sample rate decimation factor', 0xFFFFFFFF]}],
'PRE_SAMPLES':[0x20, 'Pre-trigger samples', {}],
'POST_SAMPLES':[0x24, 'Post-trigger samples', {}],
'SAMPLES_CNT':[0x28, 'Samples counter', {}],
......
test/fmcadc100m14b4cha/python/test32.py 0 → 100755
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