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Production Test Suite
Commit 0ebb73e1 authored by Ross Millar's avatar Ross Millar
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fmcadc200k16b11cha_6ch.sh 0 → 100644
View file @ 0ebb73e1
#!/bin/sh
# Copyright CERN, 2011
# Author: Ross Millar <ross.millar@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
LOGDIR=./log_fmcadc200k16b11cha
mkdir -p $LOGDIR
sudo rm -fr $LOGDIR/pts*
serial=$1
if [ x$1 = x"" ]; then
echo -n "Please, input SERIAL number: "
read serial
fi
if [ x$serial = x"" ]; then
serial=0000
fi
extra_serial=$2
if [ x$2 = x"" ]; then
echo -n "Please, input extra SERIAL number: "
read extra_serial
fi
if [ x$extra_serial = x"" ]; then
extra_serial=0000
fi
echo -n "--------------------------------------------------------------\n"
sudo ./pts.py -b FmcAdc200k16b11cha -s $serial -e $extra_serial -t./test/fmcadc200k16b11cha/python -l $LOGDIR 08 01 09 03 04 05 06
echo -n "Press enter to exit... "
read tmp
test/fmcadc200k16b11cha/python/channel_order_test.py 0 → 100755
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc
from pylab import *
if __name__ == '__main__':
"""
Channel order test:
Forces ADC channel values digitally to their channel number, i.e. 1 - 16
Does acquisitions and checks all the channel orders are correct
"""
GN4124_CSR = 0x0
test_data =0
error_position =[]
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
gn4124 = gn4124.CGN4124(spec, GN4124_CSR)
fmc = fmc_adc.CFmcAdc100ks(spec)
# Set up memory pages
pages = gn4124.get_physical_addr()
chan = 1
post_trig = 9
pre_trig = 10
fmc.channel_order_en()
iteration_number = int(raw_input(" Number of iterations : "))
for iteration in range(iteration_number):
print "Iteration Number : %s"%iteration
channel_data = fmc.do_acq(1, "camera_link" ,"N", post_trig ,pre_trig,0)
for i in range(len(channel_data)):
for j in range(len(channel_data[0])):
if channel_data[i][j]!= i+1:
print "Error : Expected %d... %d found"%( i+1, channel_data[i][j])
raw_input(" Error Found : Press enter to continue ")
fmc.channel_order_dis()
print '\nBye bye ...'
sys.exit()
test/fmcadc200k16b11cha/python/ddr_burst_writes.py 0 → 100755
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc
#import fmc_adc_test_suite
from pylab import *
if __name__ == '__main__':
"""
Does successive burst writes to DDR3 controller. Requires hdl in 'misc' on ohwr for this project
Functions remain in fmc_adc.py
bug : ddr test contrroler hdl doesnt run on first attempt
"""
GN4124_CSR = 0x0
test_data = 1
ddr3_calib_done = 0x3 <<2
error_position =[]
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
gn4124 = gn4124.CGN4124(spec, GN4124_CSR)
fmc = fmc_adc.CFmcAdc100ks(spec)
#PAGES
write_size = int(raw_input("How many 16 bit writes ? : "))
fmc.ram_write_config(1,1,0x1)
fmc.ram_write_start()
while fmc.ram_wr_finished()!=1:
time.sleep(.1)
print "clearing ram"
raw_input("\nPress Enter for Ram Write")
# Do a number of 16 byte writes
for i in range(write_size):
start_write = i*8
end_write = (i*8)+7
fmc.ram_write_config(start_write,end_write,2)
fmc.ram_write_start()
while fmc.ram_wr_finished()!=1:
time.sleep(.025)
print "Finished Ram Write"
print "Last address position = %d" %((write_size*8)-1)
print '\nBye bye ...'
sys.exit()
test/fmcadc200k16b11cha/python/ddr_write_test.py 0 → 100755
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc
#import fmc_adc_test_suite
from pylab import *
if __name__ == '__main__':
"""
Does writes to DDR3 controller. Requires hdl in 'misc' on ohwr for this project
Functions remain in fmc_adc.py
bug : ddr test contrroler hdl doesnt run on first attempt
"""
GN4124_CSR = 0x0
test_data = 1
# OFFSETS for CSR1
ddr3_calib_done = 0x3 <<2
# Address of CSR2
error_position =[]
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
gn4124 = gn4124.CGN4124(spec, GN4124_CSR)
fmc = fmc_adc.CFmcAdc100ks(spec)
# Set local bus frequency
gn4124.set_local_bus_freq(160)
#print("GN4124 local bus frequency: %d") % gn4124.get_local_bus_freq()
#PAGES STUFF
pages = gn4124.get_physical_addr()
integer_plot = int(raw_input("integer plot : "))
start_write = int(raw_input("start position for write : "))
end_write = int(raw_input("end position for write : "))
print " 1 = Clear RAM, 2 = Write addr value, 3 = Write ABCDABCD, 4 = Write addr val to all addresses "
mode = int(raw_input("mode of operation : ")) & 0x7
# FMC RAM WRITE CONFIG
fmc.ram_write_config(start_write,end_write,mode)
time.sleep(.1)
# START THE RAM WRITE
fmc.ram_write_start()
time.sleep(.1)
# WAIT FOR THE WRITE TO FINISH
while fmc.ram_wr_finished()!=1:
time.sleep(.1)
print "waiting for ram write finish"
# SET UP THE DMA
print '\nReading data from memory page 1 (before)'
page1_data_before = gn4124.get_memory_page(1)
# print '\nPreparing DMA'
dma_length = 0x1000 # DMA length in bytes
gn4124.add_dma_item((start_write<<2)+(0*dma_length),pages[1], dma_length, 0,1)
gn4124.add_dma_item((start_write<<2)+(1*dma_length),pages[2], dma_length, 0,1)
gn4124.add_dma_item((start_write<<2)+(2*dma_length),pages[3], dma_length, 0,0)
page0_data = gn4124.get_memory_page(0)
gn4124.start_dma()
while('Done' != gn4124.get_dma_status()):
#print("DMA controller status : %s") % gn4124.get_dma_status()
time.sleep(.5)
print '\nWaiting for interrupt'
gn4124.wait_irq() # what genereates this interupt?
print '\nInterrupt received'
print("DMA controller status : %s") % gn4124.get_dma_status()
print "DDR calibration", fmc.check_ddr3_calib()
page1_data = gn4124.get_memory_page(1)
page2_data = gn4124.get_memory_page(2)
page3_data = gn4124.get_memory_page(3)
channels = []
channels_test=[]
for i in range(2**10):
channels_test.append(page1_data[i]&0xFFFFFFFF)
for i in range(2**10):
channels_test.append(page2_data[i]&0xFFFFFFFF)
print "\n\nexpected start position",hex(start_write)
print "start address read", hex(channels_test[0])
print "number of address locations out by", hex(start_write - channels_test[0]),"\n\n"
for i in range(2**10):
channels.append(page1_data[i] >>16 )
channels.append(page1_data[i] & 0xFFFF)
#channels.append(page1_data[i] & 0xFFFFFFFF)
for i in range(2**10):
channels.append(page2_data[i]>>16)
channels.append(page2_data[i] & 0xFFFF)
#CONVERT FROM 2s COMPLIMENT
#if integer_plot==1:
# for i in range(len(channels)):
# if(channels[i] & 0x8000):
# channels[i] = -0x10000 + channels[i]
# SORT INTO CHANNELS
time_base = arange(0,(len(channels)/16),1)
channel1 = channels[0::16]
channel2 = channels[1::16]
channel3 = channels[2::16]
channel4 = channels[3::16]
channel5 = channels[4::16]
channel6 = channels[5::16]
channel7 = channels[6::16]
channel8 = channels[7::16]
channel9 = channels[8::16]
channel10 = channels[9::16]
channel11 = channels[10::16]
channel12 = channels[11::16]
channel13 = channels[12::16]
channel14 = channels[13::16]
channel15 = channels[14::16]
channel16 = channels[15::16]
# WRITE TO FILE
file = open("adc_100k_acq.txt", 'w')
for i in range(len(channel1)):
if integer_plot==1:
file.write("%5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d\n" % (time_base[i], channel1[i], channel2[i], channel3[i], channel4[i], channel5[i], channel6[i], channel7[i], channel8[i], channel9[i], channel10[i], channel11[i], channel12[i], channel13[i], channel14[i], channel15[i], channel16[i]))
else:
file.write("%5d, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X\n" % (time_base[i], channel1[i], channel2[i], channel3[i], channel4[i], channel5[i], channel6[i], channel7[i], channel8[i], channel9[i], channel10[i], channel11[i], channel12[i], channel13[i], channel14[i], channel15[i], channel16[i]))
print '\nBye bye ...'
sys.exit()
test/fmcadc200k16b11cha/python/dma_ddr3.py 0 → 100755
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc
from pylab import *
if __name__ == '__main__':
GN4124_CSR = 0x0
addr_type = int(raw_input("decimal address -1 , hex addr - 2 : ")) & 0x3
if addr_type == 2:
hex_input_start = raw_input("Enter a start address in hex : ")
dma_start = int(hex_input_start, 16) & 0b1111111111111111111111111
hex_input_end = raw_input("Enter the end address in hex : ")
dma_end = int(hex_input_end, 16) & 0b1111111111111111111111111
else:
dma_start = int(raw_input("input start position : "))
dma_end = int(raw_input("input end position : "))
integer_plot = 1
print "dma start address selected", dma_start
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
gn4124 = gn4124.CGN4124(spec, GN4124_CSR)
fmc = fmc_adc.CFmcAdc100ks(spec)
fmc.stop_acq()
# Function in fmc_adc.py
pages_returned = fmc.dma_access(dma_start,dma_end)
channels = []
for j in range(len(pages_returned)):
for i in range(len(pages_returned[j])):
channels.append(pages_returned[j][i] & 0xFFFFFFFF)
#CONVERT FROM 2s COMPLIMENT
if integer_plot==1:
for i in range(len(channels)):
if(channels[i] & 0x8000):
channels[i] = -0x10000 + channels[i]
# Channels data kept in 32 bits so addr
channel1 = channels[0::8]
channel2 = channels[1::8]
channel3 = channels[2::8]
channel4 = channels[3::8]
channel5 = channels[4::8]
channel6 = channels[5::8]
channel7 = channels[6::8]
channel8 = channels[7::8]
time_base = arange(0,len(channel1),1 )
# WRITE TO FILE
file = open("adc_100k_acq.txt", 'w')
for i in range(len(channel1)):
if integer_plot==1:
file.write("%5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d\n" % (time_base[i], channel1[i], channel2[i], channel3[i], channel4[i], channel5[i], channel6[i], channel7[i], channel8[i]))
else:
file.write("%5d, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X\n" % (time_base[i], channel1[i], channel2[i], channel3[i], channel4[i], channel5[i], channel6[i], channel7[i], channel8[i]))
print '\nBye bye ...'
sys.exit()
test/fmcadc200k16b11cha/python/fmc_adc.py 0 → 100644
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
import sys
import rr
import random
import time
import spi
import ltc217x
import csr
#import max5442
import i2c
#import onewire
#import ds18b20
#import mcp9801
import gn4124
import si57x
import eeprom_24aa64
#import dac_AD5622
import ad5662_spi
import math
class CFmcAdc100ks:
"""
Contans all functions required for the full test suite production of the 200ksps 16bit ADC FMC
"""
# ADDRESSES - See firmware top level
# Test CSR
# EEPROM ADDRESS - see datasheet for device
EEPROM_ADDR = 0x50
DAC_ADDR = 0x0F
#MCP9801_ADDR = 0x48
FMC_CSR = {
0x00:'Control register',
0x04:'Status register',
0x08:'Trigger configuration register',
0x0C:'Trigger delay register',
0x10:'Software trigger register',
0x14:'Number of shots register',
0x18:'Trigger UTC (LSB) register',
0x1C:'Trigger UTC (MSB) register',
0x20:'Start UTC (LSB) register',
0x24:'Start UTC (MSB) register',
0x28:'Stop UTC (LSB) register',
0x2C:'Stop UTC (MSB) register',
0x30:'Decimation factor register',
0x34:'Pre-trigger samples register',
0x38:'Post-trigger samples register',
0x3C:'Samples counter register',
0x40:'CH1 current value register',
0x44:'CH2 current value register',
0x48:'CH3 current value register',
0x4C:'CH4 current value register',
0x50:'CH5 current value register',
0x54:'CH6 current value register',
0x58:'CH7 current value register',
0x5C:'CH8 current value register',
0x60:'CH9 current value register',
0x64:'CH10 current value register',
0x68:'CH11 current value register',
0x6C:'CH12 current value register',
0x70:'CH13 current value register',
0x74:'CH14 current value register',
0x78:'CH15 current value register',
0x7C:'CH16 current value register',
0x80:'Trigger Position',
0x84:'Test Register',
0x88:'Shot Counters Register',
0x8C:'Post Trig Counter',
0x90:'Pre Trig Counter',
0x94:'Spare',}
##########################################################################
# ADC CORE REGISTER ADDRESSES
##########################################################################
R_CTL = 0x00
R_STA = 0x04
R_TRIG_CFG = 0x08
R_TRIG_DLY = 0x0C
R_SW_TRIG = 0x10
R_SHOTS = 0x14
R_TRIG_UTC_L = 0x18
R_TRIG_UTC_H = 0x1C
R_START_UTC_L = 0x20
R_START_UTC_H = 0x24
R_STOP_UTC_L = 0x28
R_STOP_UTC_H = 0x2C
R_SRATE = 0x30
R_PRE_SAMPLES = 0x34
R_POST_SAMPLES = 0x38
R_SAMP_CNT = 0x3C
R_CH1_VALUE = 0x40
R_CH2_VALUE = 0x44
R_CH3_VALUE = 0x48
R_CH4_VALUE = 0x4C
R_CH5_VALUE = 0x50
R_CH6_VALUE = 0x54
R_CH7_VALUE = 0x58
R_CH8_VALUE = 0x5C
R_CH9_VALUE = 0x60
R_CH10_VALUE = 0x64
R_CH11_VALUE = 0x68
R_CH12_VALUE = 0x6C
R_CH13_VALUE = 0x70
R_CH14_VALUE = 0x74
R_CH15_VALUE = 0x78
R_CH16_VALUE = 0x7C
R_TRIGGER_POSITION = 0x80
R_TEST = 0x84
R_SHOT_COUNTER_VAL = 0x88
R_POST_TRIG_COUNTER_VAL = 0x8C
R_PRE_TRIG_COUNTER_VAL = 0x90
R_SPARE = 0x94
# CTL Register Addresses
CTL_FSM_CMD = 0x0
CTL_TEST_DATA_EN = 0x2
CTL_ADC_CONT_CMD = 0x3
CTL_CHAN_TEST =0x4
CTL_RANGE = 0x5
CTL_MASK = 0xFC
# I dont know...
RANGE_CMD_MASK = 0x10
# TRIG REGGISTER ADDRESSES
TRIG_CFG_HW_EN = 0
TRIG_CFG_SW_EN = 1
TRIG_CFG_INT_SEL = 2
TRIG_CFG_SLOPE = 7
#TRIG_CFG_DUMMY = 8
TRIG_CFG_EDGE_EN = 8
TRIG_CFG_DUMMY = 9
TRIG_CFG_INT_THRES = 16
# TRIG REG MASKS
INT_SEL_MASK = 0x0000007C
INT_THRES_MASK = 0xFFFF0000
INT_DUMMY_MASK = 0x0000FE00
# CTL REGISTER MASKS and Commands
FSM_CMD_MASK = 0x00000003
ADC_CONT_CMD_MASK = 0x00000008
FSM_CMD_START = 0x1
FSM_CMD_STOP = 0x2
FSM_MASK = 0x00000007
# ADC CORE STATES
FSM_STATES = ['N/A','IDLE','PRE_TRIG','WAIT_TRIG','WAIT_TRIG_WR',
'POST_TRIG','DECR_SHOT','N/A','others']
##########################################################################
# Carrier CSR REGISTER ADDRESSES
##########################################################################
R_CARRIER_INFO = 0x0
R_BITSTREAM_TYPE = 0x4
R_BITSTREAM_DATE = 0x8
R_CARRIER_STATUS = 0xC
R_CARRIER_CTL = 0x10
# Carrier CSR MASKS
R_WHOLE_REG_MASK = 0xFFFFFFFF
R_16_BITS_MASK = 0xFFFF
##########################################################################
# Test register addresses
##########################################################################
R_CTL_TEST =0x0
R_STA_TEST= 0x4
R_STA_2_TEST=0x8
R_SYS_CNT_VAL_TEST = 0xC
R_SYS_CNT_EN = 0x10
R_SYS_BUSY_CHECK = 0x14
R_LEDS_TEST = 0x18
##########################################################################
# IRQ CSR ADDRESSES
##########################################################################
R_CTL_MULTI_IRQ_LOAD = 0x0
R_CTL_IRQ_SRC = 0x4
R_CTL_MASK_INT = 0x8
##########################################################################
# UTC CSR ADDRESSES
##########################################################################
##########################################################################
# Test DDR3 CSR Addresses
##########################################################################
R_RAM_START = 0x0
R_START_RAM_ADR = 0x4
R_END_RAM_ADR = 0x8
R_FINISHED_FLAG = 0xC
R_DDR_TEST_MODE = 0x14
##########################################################################
# Wishbone Object Addresses
##########################################################################
FMC_CARRIER_CSR = 0x20000
FMC_SPI_ADDR = 0x40000
FMC_CSR_ADDR = 0x60000
FMC_SYS_I2C_ADDR = 0x80000
FMC_UTC_CORE = 0xA0000
FMC_IRQ_CORE = 0xC0000
#FMC_TEST_DDR_CSR_ADDR = 0xA0000
GN4124_CSR = 0x0
def __init__(self, bus):
self.bus = bus
##########################################################################
# Object Declerations
##########################################################################
#self.spec = rr.Gennum() # bind to the SPEC board
self.gn4124 = gn4124.CGN4124(self.bus , 0x0 )
#ADC carrier CSR
self.fmc_carrier_csr = csr.CCSR(self.bus, self.FMC_CARRIER_CSR)
# SPI controller for mez # bus , address of spi master , divider
self.spi_master = spi.COpenCoresSPI(self.bus,self.FMC_SPI_ADDR ,10)
self.pll_dac = ad5662_spi.CAD5662(self.spi_master, 0)
# CSR for ADC CORE
self.fmc_adc_csr = csr.CCSR(self.bus, self.FMC_CSR_ADDR)
# System I2C for EEPROM
self.fmc_sys_i2c = i2c.COpenCoresI2C(self.bus, self.FMC_SYS_I2C_ADDR, 249)
self.eeprom_24aa64 = eeprom_24aa64.C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR)
# Need to add UTC core
self.utc_core = csr.CCSR(self.bus, self.FMC_UTC_CORE)
# Need to add Interrupt controller
self.irq_core = csr.CCSR(self.bus , self.FMC_IRQ_CORE)
# DDR test CSR
#self.fmc_ddr_test = csr.CCSR(self.bus, self. FMC_TEST_DDR_CSR_ADDR)
self.dma_pages = self.gn4124.get_physical_addr()
##########################################################################
# DDR Controller Test - Uses
##########################################################################
# Configure the RAM write
#def ram_write_config(self,start,end,mode):
# self.fmc_ddr_test.wr_reg(self.R_START_RAM_ADR, start & 0xFFFFFFFF)
# self.fmc_ddr_test.wr_reg(self.R_END_RAM_ADR, end & 0xFFFFFFFF)
# self.fmc_ddr_test.wr_reg(self.R_DDR_TEST_MODE, mode & 0x7)
# start ram write for the test operation
#def ram_write_start(self):
# self.fmc_ddr_test.wr_reg(self.R_RAM_START, 0x1)
#def ram_wr_finished(self):
# return self.fmc_ddr_test.rd_reg(self.R_FINISHED_FLAG) & 0x1
##########################################################################
# Functions using the Carrier CSR
##########################################################################
def pcb_version(self):
pcb_ver = self.fmc_carrier_csr.rd_reg(self.R_CARRIER_INFO) & 0xF
return pcb_ver
def carrier_type(self):
carrier_type = (self.fmc_carrier_csr.rd_reg(self.R_CARRIER_INFO) >>16) & self.R_16_BITS_MASK
return carrier_type
def bitstream_type(self):
bitstream_type = self.fmc_carrier_csr.rd_reg(self.R_BITSTREAM_TYPE) & 0x1
return bitstream_type & self.R_WHOLE_REG_MASK
def bitstream_date(self):
mez_present = self.fmc_carrier_csr.rd_reg(self.R_BITSTREAM_DATE) & self.R_16_BITS_MASK
return mez_present
def carrier_csr_sta(self):
return self.fmc_carrier_csr.rd_reg(self.R_CARRIER_STATUS) & 0xF
def carrier_csr_ctl(self):
carrier_ctl = self.fmc_carrier_csr.rd_reg(self.R_CARRIER_CTL) & 0x3
return carrier_ctl
def check_mez_present(self):
mez_present = self.fmc_carrier_csr.rd_reg(self.R_CARRIER_STATUS) & 0x1
return mez_present
##########################################################################
# Functions using ADC Core CSR
##########################################################################
def test_data_en(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
print("R_CTL:%.8X")%reg
reg |= ((1<<self.CTL_TEST_DATA_EN) & self.CTL_MASK)
print("R_CTL:%.8X")%reg
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
def test_data_dis(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
print("R_CTL:%.8X")%reg
reg &= (~(1<<self.CTL_TEST_DATA_EN) & self.CTL_MASK)
print("R_CTL:%.8X")%reg
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
def channel_order_en(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
print("R_CTL:%.8X")%reg
reg |= ((1<<self.CTL_CHAN_TEST) & self.CTL_MASK)
print("R_CTL:%.8X")%reg
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
def channel_order_dis(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
print("R_CTL:%.8X")%reg
reg &= (~(1<<self.CTL_CHAN_TEST) & self.CTL_MASK)
print("R_CTL:%.8X")%reg
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
def set_decimation(self, factor):
self.fmc_adc_csr.wr_reg(self.R_SRATE, factor)
def get_decimation(self):
return self.fmc_adc_csr.rd_reg(self.R_SRATE)
# Set trigger configuration
def set_trig_config(self, hw_en, sw_en, int_sel, int_thres, slope, delay, edge):
# Hardware trigger enable
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_EN, hw_en)
# Software trigger enable
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_SW_EN, sw_en)
#Edge trigger enable
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_EDGE_EN,edge)
# Slope for threshold triger
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_SLOPE, slope)
# Internal trigger channel select (2 to 6)
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG)
reg &= ~self.INT_SEL_MASK
reg |= (int_sel<< self.TRIG_CFG_INT_SEL) & self.INT_SEL_MASK
#reg |= ((int_sel <<self.TRIG_CFG_INT_SEL) & self.INT_SEL_MASK)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg)
# Internal trigger threshold
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG)
reg &= ~self.INT_THRES_MASK
reg |= ((int_thres<<self.TRIG_CFG_INT_THRES) & self.INT_THRES_MASK)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg)
# Write zeros to dummy ###############CHANGED
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG)
reg &= ~self.INT_DUMMY_MASK
reg |= ((0<<self.TRIG_CFG_DUMMY) & self.INT_DUMMY_MASK)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg)
# Trigger delay (in sampling clock ticks)
self.fmc_adc_csr.wr_reg(self.R_TRIG_DLY, delay)
def get_trig_config(self):
return self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG) & 0xFFFFFFFF
# Start acquisition
def start_acq(self):
# Reads from the control register
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
reg &= ~self.FSM_CMD_MASK
reg |= ((self.FSM_CMD_START<<self.CTL_FSM_CMD) & self.FSM_CMD_MASK)
reg &= (self.CTL_MASK | self.FSM_CMD_MASK)
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
# Start ADC controller
def start_adc_cont(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
reg &= ~self.ADC_CONT_CMD_MASK
reg |= ((self.FSM_CMD_START<<self.CTL_ADC_CONT_CMD) & self.ADC_CONT_CMD_MASK)
reg &= (self.CTL_MASK | self.ADC_CONT_CMD_MASK)
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
# Stop acquisition
def stop_acq(self):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
reg &= ~self.FSM_CMD_MASK
reg |= ((self.FSM_CMD_STOP<<self.CTL_FSM_CMD) & self.FSM_CMD_MASK)
#print("R_CTL:%.8X")%reg
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
# Software trigger
def sw_trig(self):
while(3 != self.get_acq_fsm_state()):
print self.get_acq_fsm_state()
time.sleep(.1)
self.fmc_adc_csr.wr_reg(self.R_SW_TRIG, 0xFFFFFFFF)
# Set pre-trigger samples
def set_pre_trig_samples(self, samples):
self.fmc_adc_csr.wr_reg(self.R_PRE_SAMPLES, samples)
def get_pre_trig(self):
return self.fmc_adc_csr.rd_reg(self.R_PRE_TRIG_COUNTER_VAL)
# Set post-trigger samples
def set_post_trig_samples(self, samples):
self.fmc_adc_csr.wr_reg(self.R_POST_SAMPLES, samples)
# Get post-trigger value
def get_post_trig(self):
return self.fmc_adc_csr.rd_reg(self.R_POST_TRIG_COUNTER_VAL)
# Set number of shots
def set_shots(self, shots):
self.fmc_adc_csr.wr_reg(self.R_SHOTS, shots)
# Set range pin YET TO BE DEFINED
def set_range(self,range_val):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
reg &= ~self.RANGE_CMD_MASK
reg |= (( (range_val & 0x1) <<self.CTL_RANGE) & self.RANGE_CMD_MASK)
reg &= (self.CTL_MASK | self.ADC_CONT_CMD_MASK)
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
# Get ADC core status
def get_status(self):
return self.fmc_adc_csr.rd_reg(self.R_STA)
# Get number of shots
def get_shots(self):
return self.fmc_adc_csr.rd_reg(self.R_SHOT_COUNTER_VAL)
# Get acquisition state machine status
def get_acq_fsm_state(self):
state = (self.fmc_adc_csr.rd_reg(self.R_STA) & self.FSM_MASK)
#print("FSM state: %d")%state
return state
#self.FSM_STATES[state] # this should be used by the other status not this
# Read spare register
def get_spare_reg(self):
return self.fmc_adc_csr.rd_reg(self.R_SPARE)
# Return position of trigger in memory... aligned to first channel
def get_trig_pos(self):
return self.fmc_adc_csr.rd_reg(self.R_TRIGGER_POSITION)
def check_ddr3_calib(self):
return (self.fmc_carrier_csr.rd_reg(0x3<<2) & 0x8)>>3
##########################################################################
# Functions for SPI and i2c
##########################################################################
def spi_dac_write(self, data):
return self.pll_dac.set_offset(data & 0xFFFF)
def i2c_scan(self):
print '\nScan I2C bus'
return self.fmc_i2c.scan()
def sys_i2c_scan(self):
print '\nScan system I2C bus'
return self.fmc_sys_i2c.scan()
def sys_i2c_eeprom_write(self, addr, data):
return self.eeprom_24aa64.wr_data(addr, data)
def sys_i2c_eeprom_read(self, addr, size):
return self.eeprom_24aa64.rd_data(addr, size)
# Enable test data
##########################################################################
# Functions for IRQ CONTROLLER
##########################################################################
#def irq_load(self):
# need to find what this requires written
#def irq_src_load(self):
def wr_irq_mask(self, mask):
self.irq_core.wr_reg(self.R_CTL_MASK_INT,mask & 0xFFFFFFFF)
def rd_irq_mask(self):
return self.irq_core.rd_reg(self.R_CTL_MASK_INT)
def read_irq_src(self):
return self.irq_core.rd_reg(self.R_CTL_IRQ_SRC)
##########################################################################
# Functions for UTC Core
##########################################################################
##########################################################################
# Currently unused
##########################################################################
# Front panel LED manual control
def acq_led(self, state):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
#print("R_CTL:%.8X")%reg
if(state == 0):
reg &= (~(1<<self.CTL_ACQ_LED) & self.CTL_MASK)
else:
reg |= ((1<<self.CTL_ACQ_LED) & self.CTL_MASK)
#print("R_CTL:%.8X")%reg
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
def trig_led(self, state):
reg = self.fmc_adc_csr.rd_reg(self.R_CTL)
#print("R_CTL:%.8X")%reg
if(state == 0):
reg &= (~(1<<self.CTL_TRIG_LED) & self.CTL_MASK)
else:
reg |= ((1<<self.CTL_TRIG_LED) & self.CTL_MASK)
#print("R_CTL:%.8X")%reg
self.fmc_adc_csr.wr_reg(self.R_CTL, reg)
##########################################################################
# Acquisition Functions
##########################################################################
def mean(self,numberList):
if len(numberList)==0:
return int('nan')
intnums = [int(x) for x in numberList]
return sum(intnums)/len(numberList)
def dma_access(self, dma_start,dma_end):
dma_length=0x1000
pages_required = int(math.ceil(((dma_end-dma_start)/float(dma_length))))
for num in range(pages_required):
if pages_required==num+1:
end_character=0
length=(dma_end-(num*dma_length))
else:
end_character=1
length=dma_length
if num==0:
start_address=dma_start
else:
start_address=dma_start + num*dma_length
#print "gn4124.add_dma_item( %s, pages[%d], %d, 0,%d)"%(start_address,num+1,length,end_character)
self.gn4124.add_dma_item(start_address<<2, self.dma_pages[num+1],length,0, end_character)
time.sleep(.1)
page0_data = self.gn4124.get_memory_page(0)
self.gn4124.start_dma()
while('Done' != self.gn4124.get_dma_status()):
time.sleep(.5)
self.gn4124.wait_irq()
page_data =[]
for j in range(pages_required):
page_data.append(self.gn4124.get_memory_page(j+1))
return page_data
def do_small_acq(self, chan):
pre_trig_val = 10
post_trig_val = 9
pages = self.gn4124.get_physical_addr()
self.stop_acq()
self.set_shots(1)
time.sleep(.1)
self.set_pre_trig_samples(pre_trig_val)
time.sleep(.1)
self.set_post_trig_samples(post_trig_val)
time.sleep(.1)
self.set_decimation(1)
time.sleep(.1)
self.set_trig_config(0,1,0x1,0xFFFF,0,0)
time.sleep(.1)
self.start_acq()
self.start_adc_cont()
while self.get_status() !=3:
time.sleep(.1)
self.start_acq()
self.start_adc_cont()
self.sw_trig()
while self.get_status()!=0x1:
time.sleep(1)
trigger_position=self.get_trig_pos() & 0xFFFFFFFF
dma_start= trigger_position-(pre_trig_val*8)
self.gn4124.add_dma_item((dma_start<<2),pages[1],0x1000,0,0) # will need to add the gennum class to this file
# load array from pages
self.gn4124.start_dma()
while('Done' != self.gn4124.get_dma_status()):
time.sleep(.5)
self.gn4124.wait_irq()
page1_data = self.gn4124.get_memory_page(1)
# sort into chanels
channels = []
for i in range(2**10):
channels.append(page1_data[i] >>16 )
channels.append(page1_data[i] & 0xFFFF)
for i in range(len(channels)):
if(channels[i] & 0x8000):
channels[i] = -0x10000 + channels[i]
channel_requested = channels[(chan-1)::16]
return channel_requested[0: pre_trig_val + post_trig_val + 1]
def do_acq(self, chan, mode ,average,post_trig_val,pre_trig_val,thresh):
dma_length = 0x1000
self.start_adc_cont()
pages = self.gn4124.get_physical_addr()
self.stop_acq()
self.set_shots(1)
time.sleep(.1)
self.set_pre_trig_samples(pre_trig_val)
time.sleep(.1)
self.set_post_trig_samples(post_trig_val)
time.sleep(.1)
self.set_decimation(1)
time.sleep(.1)
if thresh!=1:
sw_trig_en =1
self.set_trig_config(0,1,0x0,0x8000,0,0,0)
#def set_trig_config(self, hw_en, sw_en, int_sel, int_thres, slope, delay, edge):
else:
print "Trigger Register Required to be set outwith this function for threshold triggers"
time.sleep(.1)
self.start_acq()
# it appears a threshold trigger can cause a trig before you reach this
if thresh!=1:
while self.get_status() !=3:
time.sleep(.1)
print "waiting for wait for trig state"
self.sw_trig()
print "software trig applied"
time.sleep(0.1)
while self.get_status()!=0x1:
time.sleep(1)
print "waiting for thresh trig"
trigger_position=self.get_trig_pos() & 0xFFFFFFFF
#print "trig remaineder /8 :", trigger_position%8
#if trigger_position%8!=0:
# print "\n\n\n ERROR \n\n\n"
dma_start= trigger_position-(pre_trig_val*8)
self.gn4124.add_dma_item((dma_start<<2)+(0*dma_length),pages[1], dma_length, 0,1)
self.gn4124.add_dma_item((dma_start<<2)+(1*dma_length),pages[2], dma_length, 0,1)
self.gn4124.add_dma_item((dma_start<<2)+(2*dma_length),pages[3], dma_length, 0,0)
# load array from pages
self.gn4124.start_dma()
while('Done' != self.gn4124.get_dma_status()):
time.sleep(.5)
self.gn4124.wait_irq()
page1_data = self.gn4124.get_memory_page(1)
page2_data = self.gn4124.get_memory_page(2)
page3_data = self.gn4124.get_memory_page(3)
# sort into chanels
channels = []
for i in range(2**10):
channels.append(page1_data[i] >>16 )
channels.append(page1_data[i] & 0xFFFF)
for i in range(2**10):
channels.append(page2_data[i]>>16)
channels.append(page2_data[i] & 0xFFFF)
for i in range(len(channels)):
if(channels[i] & 0x8000):
channels[i] = -0x10000 + channels[i]
if mode == "chan_select":
channel_requested = channels[(chan-1)::16]
if average.upper() =="Y":
return self.mean(channel_requested[0: pre_trig_val + post_trig_val + 1])
else:
return channel_requested[0: pre_trig_val + post_trig_val + 1]
elif mode == "camera_link":
split_channels=[]
#print "HERE"
for j in range(11):
# print channels[j::16]
split_chan = channels[j::16]
split_channels.append(split_chan[0:pre_trig_val +post_trig_val +1])
if average.upper() == "Y":
averaged =[]
for i in range(len(split_channels)):
averaged.append(self.mean(split_channels[i]))
return averaged
else:
return split_channels
#return split_channels[0: pre_trig_val + post_trig_val + 1]
elif mode == "all_chans":
split_channels=[]
for j in range(16):
#print channels[j::16]
split_chan = channels[j::16]
split_channels.append(split_chan[0:pre_trig_val +post_trig_val +1])
if average.upper() == "Y":
averaged =[]
for i in range(len(split_channels)):
averaged.append(self.mean(split_channels[i]))
return averaged
else:
return split_channels
else:
print "not a valid acq type"
return 0
test/fmcadc200k16b11cha/python/gnuplot_gen.py 0 → 100644
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
if __name__ == '__main__':
"""
This generates a GNUPLOT file for a text file generated by an ADC
Based on the output of the 16 bit 200k ADC,
Assumes the generated text file has data from 16 chanels
Currently required the text file to be called ... adc_100k_acq.txt
"""
# GNU PLOT GENERATION FUNCTIONS
class Plot_options:
def __init__(self,numero):
self.title=raw_input("Enter your Plot title : ")
self.xlabel=raw_input("Enter the label for your X-Axis : ")
self.ylabel=raw_input("Enter the label for your Y-Axis : ")
self.numero=numero
def area(self):
return self.numero * 2
def file_write(num_plots,array):
anotherarray=["Default Settings","New Settings"]
settings=simple_menu(anotherarray,"\nGNUPLOT OPTIONS")
if settings==1:
options=["dots","lines","curves"]
graph_style=simple_menu(options,"Select plot style")
style=options[graph_style-1]
filename_choice=simple_menu(["Write to file \"adcfmc200kdata.plot\"","write to a different file"],"Choose write file")
if filename_choice==1:
filename="adcfmc200kdata.plot"
elif filename_choice==2:
filename=str(raw_input("\n\nGive the name of the file you wish to write to, ending in .plot \n\n"))
file=open(filename,'w')
file.write("# Gnuplot script file for plotting data in file \"adc_acq.txt\" \n\n")
file.write("set autoscale # scale axes automatically \n")
file.write("unset log # remove any log-scaling \n")
file.write("unset label # remove any previous labels \n")
file.write("set title \"Adc-Fmc-200ks\" \n")
file.write("set xlabel \"Sample number\" \n")
file.write("set ylabel \"ADC raw data\" \n\n")
file.write("plot ")
elif settings==2:
plotinfo=Plot_options(2)
options=["dots","lines","curves"]
graph_style=simple_menu(options,"Select plot style")
style=options[graph_style-1]
filename_choice=simple_menu(["Write to file \"adc_fmc_100k_acq2.plot\"","write to a different file"],"Choose write file")
if filename_choice==1:
filename="adcfmc200kdata.plot"
elif filename_choice==2:
filename=str(raw_input("\n\nGive the name of the file you wish to write to, ending in .plot \n\n"))
file=open(filename,'w')
file.write("# Gnuplot script file for plotting data in file \"adc_acq.txt\" \n\n")
file.write("set autoscale # scale axes automatically \n")
file.write("unset log # remove any log-scaling \n")
file.write("unset label # remove any previous labels \n")
file.write("set title \"%s\" \n" %(plotinfo.title) )
file.write("set xlabel \"%s\" \n" %(plotinfo.xlabel) )
file.write("set ylabel \"%s\" \n\n" %(plotinfo.ylabel) )
file.write("plot ")
for i in range(num_plots):
file.write("\"adc_100k_acq.txt\" using 1:%d title \"Channel %d\" with %s" %((array[i]+1),array[i],style))
if i<=(num_plots-2):
file.write(",\\\n")
file.write("\n\npause -1 \"Hit return to continue\"")
print "\n\nFile \"%s\" has been written \n\n" % (filename)
def simple_menu(array,Description):
print Description
for i in range(len(array)):
print i+1,")", array[i]
return int(raw_input("please choose an option : "))
# CREATE GNUPLOT FILE
array=[]
num_of_channels=16
channel_selections=["All Channels","First ADC chip","Second ADC chip","Custom"]
print "\nCREATING THE PLOT FILE.....\n"
channel_choice=simple_menu(channel_selections,"Choose which channels to Plot")
if channel_choice==1:
for chans in range(num_of_channels):
array.append(chans+1)
k=num_of_channels
if channel_choice==2:
for chans in range(0,num_of_channels/2,1):
array.append(chans+1)
k=num_of_channels/2
if channel_choice==3:
for chans in range(num_of_channels/2,num_of_channels,1):
array.append(chans+1)
k=num_of_channels/2
if channel_choice==4:
k=int(raw_input("How many ADC channels do you wish to plot? "))
print "Select which channels you want to plot"
for h in range(k):
array.append(int(raw_input("choice %d :" %(h+1))))
print array
file_write(k,array)
print '\nBye bye ...'
sys.exit()
test/fmcadc200k16b11cha/python/number_of_acqs_test.py 0 → 100755
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc
from pylab import *
if __name__ == '__main__':
"""
Checks that the number of pre and post trigger samples are written to RAM.
Sets firmware to the a test mode which writes the value of the addr to that addr location
Reads the data back from the pre trig position and checks that the numbers are consecutive
right through to the end of post trig data.
After every acquisiton in the mode mentioned previously, it switches back to the normal mode,
and allows a longer time before the acq so that the list of consecutive addresses are overwritten
in ram
"""
GN4124_CSR = 0x0
ddr3_calib_done = 0x3 <<2
# Commands and variables
acq_start = 0x01
acq_stop = 0x02
decim_val = 1
trig_delay_val = 0
sw_trig = 0x00000001
adc_cont_start = 1
attempt_trig_read = 1
software_trigger = 0
integer_plot = 1
thresh_trig = 0
#Threshold Conditions
trigger_threshold=0x0001
slope=0
channel_for_thresh_trig=0x6
sw_trig_en=1
hw_trig_en=0
# acquires settings from user
shots_num = int(raw_input("input shots number : "))
pre_trig_val = int(raw_input(" input pre trig number : "))
post_trig_val =int(raw_input(" input post trig number : "))
num_it = int(raw_input("set number of test loop iterations : "))
test_data =0
error_position =[]
#trigger_register=((trigger_threshold<<16)+(0x0<<8)+(slope<<7)+(channel_for_thresh_trig<<2)+(sw_trig_en<<1) +hw_trig_en)
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
gn4124 = gn4124.CGN4124(spec, GN4124_CSR)
fmc = fmc_adc.CFmcAdc100ks(spec)
# Why am i not using the test suite version and does it matter?
# Set up memory pages
pages = gn4124.get_physical_addr()
# CSR CONFIGURATION
fmc.set_shots(shots_num)
time.sleep(.1)
fmc.set_pre_trig_samples(pre_trig_val)
time.sleep(.1)
fmc.set_post_trig_samples(post_trig_val)
time.sleep(.1)
fmc.set_decimation(decim_val)
time.sleep(.1)
fmc.set_trig_config(hw_trig_en, sw_trig_en, channel_for_thresh_trig, trigger_threshold, slope,trig_delay_val,thresh_trig)
time.sleep(.1)
fmc.set_decimation(1)
time.sleep(.1)
for iteration in range(num_it):
# Toggle between test data and normal mode
test_data=~test_data & 0x1
if test_data==1:
fmc.test_data_en()
time.sleep(.1)
else:
fmc.test_data_dis()
time.sleep(.1)
print "Test data %d"%test_data
# Stop Acq
fmc.stop_acq()
fmc.get_status()
while fmc.get_status()!=0x1:
time.sleep(.1)
# Start Acq
fmc.start_acq()
fmc.start_adc_cont()
time.sleep(.1)
# If a software trigger test
if sw_trig_en==1:
# Wait for State machine to reach correct state
while fmc.get_status() !=3: #"WAIT_TRIG"
time.sleep(.1)
if test_data == 1:
time.sleep(1)
print "Sleep for 0.5 second"
else:
time.sleep(3)
print "Sleep for 3 seconds - allows test results to be erased"
if sw_trig_en==1:
if shots_num>1:
for i in range(shots_num-1):
fmc.sw_trig()
smething=raw_input("Press Enter once you have changed signal type")
while fmc.get_status()!=0x3:
time.sleep(.2)
fmc.sw_trig()
else:
fmc.sw_trig()
print "Single Shot Trigger Applied"
fmc.get_shots()
else:
while fmc.get_status()!=0x1:
time.sleep(1)
time.sleep(.1)
# CHECK IF DDR3 SYNCED PROPERLY:
while fmc.check_ddr3_calib()!=0x1:
time.sleep(.5)
print "DDR not calibrated..."
# Find trigger position - bottom 16 bits of register
trigger_position=fmc.get_trig_pos() & 0xFFFFFFFF
# Define Where the acquisition starts
dma_start = trigger_position - (pre_trig_val*8)
dma_end = trigger_position + 7 +(post_trig_val*8)
page1_data_before = gn4124.get_memory_page(1)
dma_length = 0x1000 # DMA length in bytes
# READ FROM DDR TO MEMORY PAGES
#if (dma_end-dma_start)<=dma_length:
print "DMA LENGTH: ", dma_length
print "DMA START :", dma_start
print "DMA START (hex): ", hex(dma_start)
print "DMA END: ", dma_end
print "DMA END (hex): ", hex(dma_end)
print "trigger_position: ", trigger_position
print "trigger position (hex): ", hex(trigger_position)
print "DMA ACCESS LENGTH REQUIRED = ", dma_end-dma_start +1
# Retrieve 3 Pages of Data
if shots_num>1:
print "DMA from Start of RAM"
gn4124.add_dma_item(0*dma_length,pages[1], dma_length, 0,1)
gn4124.add_dma_item(1*dma_length,pages[2], dma_length, 0,1)
gn4124.add_dma_item(1*dma_length,pages[3], dma_length, 0,0)
else:
gn4124.add_dma_item((dma_start<<2)+(0*dma_length),pages[1], dma_length, 0,1)
gn4124.add_dma_item((dma_start<<2)+(1*dma_length),pages[2], dma_length, 0,1)
gn4124.add_dma_item((dma_start<<2)+(2*dma_length),pages[3], dma_length, 0,0)
# DMA
page0_data = gn4124.get_memory_page(0)
print("DMA controller status : %s") % gn4124.get_dma_status()
print '\n Start DMA transfer'
gn4124.start_dma()
while('Done' != gn4124.get_dma_status()):
print("DMA controller status : %s") % gn4124.get_dma_status()
time.sleep(.5)
print '\nWaiting for interrupt'
gn4124.wait_irq()
print '\nInterrupt received'
print("DMA controller status : %s") % gn4124.get_dma_status()
page1_data = gn4124.get_memory_page(1)
page2_data = gn4124.get_memory_page(2)
page3_data = gn4124.get_memory_page(3)
channels = []
channels_test = []
for i in range(2**10):
channels_test.append(page1_data[i]&0xFFFFFFFF)
for i in range(2**10):
channels_test.append(page2_data[i]&0xFFFFFFFF)
if test_data == 1:
print "\n\nExpected start position",hex(dma_start)
print "Start address read", hex(channels_test[0])
if hex(dma_start) !=hex(channels_test[0] ):
print "Error : Data received from address does not equal address value"
raw_input("Examine data : Press Enter to continue ")
for i in range(2**10):
channels.append(page1_data[i] >>16 )
channels.append(page1_data[i] & 0xFFFF)
for i in range(2**10):
channels.append(page2_data[i]>>16)
channels.append(page2_data[i] & 0xFFFF)
#CONVERT FROM 2s COMPLIMENT
if integer_plot==1:
for i in range(len(channels)):
if(channels[i] & 0x8000):
channels[i] = -0x10000 + channels[i]
# SORT INTO CHANNELS
time_base = arange(0,(len(channels)/16),1)
channel1 = channels[0::16]
channel2 = channels[1::16]
channel3 = channels[2::16]
channel4 = channels[3::16]
channel5 = channels[4::16]
channel6 = channels[5::16]
channel7 = channels[6::16]
channel8 = channels[7::16]
channel9 = channels[8::16]
channel10 = channels[9::16]
channel11 = channels[10::16]
channel12 = channels[11::16]
channel13 = channels[12::16]
channel14 = channels[13::16]
channel15 = channels[14::16]
channel16 = channels[15::16]
# WRITE TO FILE
file = open("adc_100k_acq.txt", 'w')
for i in range(len(channel1)):
if integer_plot==1:
file.write("%5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d, %5d\n" % (time_base[i], channel1[i], channel2[i], channel3[i], channel4[i], channel5[i], channel6[i], channel7[i], channel8[i], channel9[i], channel10[i], channel11[i], channel12[i], channel13[i], channel14[i], channel15[i], channel16[i]))
else:
file.write("%5d, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X, %5X\n" % (time_base[i], channel1[i], channel2[i], channel3[i], channel4[i], channel5[i], channel6[i], channel7[i], channel8[i], channel9[i], channel10[i], channel11[i], channel12[i], channel13[i], channel14[i], channel15[i], channel16[i]))
# Length of acq in terms of 32 bit words
length_of_acq = (pre_trig_val*8)+8+(post_trig_val*8)
print "length of acquisition in 32bit words: ", length_of_acq
print "num of acqs = ",(length_of_acq/8)
pos_of_break = []
# Loop just passed the acq lenghts
if test_data==1:
for j in range(length_of_acq+10):
# Look for break in consecutive numbers
if channels_test[j]!=channels_test[j+1]-1 :
# Note the position of the break
pos_of_break.append(j)
print pos_of_break
if (pos_of_break[0]+1)==length_of_acq:
print "No problems"
else:
error_position.append(pos_of_break[0])
raw_input("Press Enter Once the data has been examined")
print "Number of errors = ",len(error_position)
print "Iteration number ",iteration
print "Number of errors", len(error_position)
print "Position of Errors", error_position
print "Predicted positon of change : ",length_of_acq
print '\nBye bye ...'
sys.exit()
test/fmcadc200k16b11cha/python/sinewave_test.py 0 → 100755
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc
from pylab import *
import math
if __name__ == '__main__':
"""
Sinewave test
Requires sinewave input
Takes an acquired sinewave and compares to 2 ideal sinewaves,
an upper threshold and a lower threshold. If the acquired
sinewave is not within this an error is produced and the data is written to a file
"""
glitch_count = 0
error_threshold = 10
hw_en =1
sw_en =0
chan = 0xB
int_thresh = 0x0001
slope = 0
delay = 0
edge_detect =1
iteration = 0
thresh_trig_en = 1
edge_detection = 1
pre_trig = 0
post_trig = 500
# Acquires settings from user
for i in range(11):
print ("Chan %d - Camera Link %d")%(i+1,i+1)
# Obtain Data from user
chan = int(raw_input("Which Channel is the Sinewave input to? :"))
frequency_of_wave = int(raw_input("Please input the frequency of the sine wave : "))
num_of_loops = int(raw_input("Please select the number of iterations for the test : "))
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
gn4124 = gn4124.CGN4124(spec, 0x0)
fmc = fmc_adc.CFmcAdc100ks(spec)
# Carry out acquisition on channel with the sinewave input -
#channel_data = fmc.do_acq(chan, "chan_select" ,"N",post_trig ,pre_trig,thresh_trig_en,edge_detection)
# Set trigger Register
fmc.set_trig_config(hw_en,sw_en,chan,int_thresh,slope,delay,edge_detect)
for loop in range(num_of_loops):
channel_data = fmc.do_acq(chan, "chan_select" ,"n",500,0,1)
sine_wave=[]
time_base=[]
# Generated sinewave constants
amplitude = max(channel_data)
perfect_sine_high =[]
perfect_sine_low =[]
rad = 2*math.pi
sampling_rate = 200000
num_acq = post_trig + pre_trig + 1
no_samples_per_period = float(sampling_rate)/float(frequency_of_wave)
num_waves = float(num_acq)/no_samples_per_period
ideal_wave_size = (num_acq/num_waves)
position_of_ideal_peak = (num_acq/(4*num_waves))
# Detect Position of Peak
i = 0
peak_pos =0
num_1 = channel_data[0]
num_2 = channel_data[1]
if num_1<num_2:
i=0
while (num_1<num_2):
num_1=channel_data[i]
num_2=channel_data[i+1]
i=i+1
peak_pos = i
elif num_1>num_2:
i = 0
while (num_1>num_2):
num_1=channel_data[i]
num_2=channel_data[i+1]
i=i+1
trough_pos = i
peak_pos = trough_pos + (ideal_wave_size/2)
for i in range(int(num_acq)+1):
argument = (((float(i)*num_waves)/float(num_acq))*float(rad))
#print argument
sine_wave.append( int(amplitude*math.sin(argument)))
time_base.append(i)
# generate a couple of sine waves, an upper bound and a lower bound
# calculate their amplitude by measuring the the channel6 sine wave with min and max functions
for i in range(int(num_acq)):
argument = (((float(i)*num_waves)/float(num_acq))*float(rad))
perfect_sine_high.append( int(amplitude*math.sin(argument)) +1000 )
perfect_sine_low.append( int(amplitude*math.sin(argument)) -1000 )
time_base.append(i)
size_sine_list = len(perfect_sine_high)
# Align waves
if peak_pos >position_of_ideal_peak:
align_wave = (ideal_wave_size - (peak_pos - position_of_ideal_peak) )
elif peak_pos <=position_of_ideal_peak:
#align_wave = 26 - peak_pos
align_wave = position_of_ideal_peak - peak_pos
else:
align_wave = 0
"""
print "Wave aligned by...", int(align_wave)
print "Ideal peak : ",int(position_of_ideal_peak)
print "Real peak : ", peak_pos
print "Ideal wave size : ",ideal_wave_size
"""
glitch_found = 0
if len(channel_data)<len(perfect_sine_high):
loop_val = len(channel_data)
else:
loop_val = len(perfect_sine_high)
for i in range(loop_val):
real_val = channel_data[i]
upper_bound = perfect_sine_high[i+int(align_wave)]
lower_bound = perfect_sine_low[i+int(align_wave)]
if real_val<lower_bound or real_val>upper_bound:
glitch_found = 1
if glitch_found ==1:
print "glitch found in result"
else:
print "\n Valid Result\n"
"""
for i in range(len(channel_data)):
channel_data[i] = channel_data[i] * 0.000152
for i in range(len(perfect_sine_high)):
perfect_sine_high[i] = perfect_sine_high[i] * 0.000152
for i in range(len(perfect_sine_low)):
perfect_sine_low[i] = perfect_sine_low[i] * 0.000152
"""
if glitch_found ==1:
iteration = iteration +1
file_string = "adc_100k_acq_" + str(glitch_count) +".txt"
if iteration ==1:
file_string = "adc_100k_acq.txt"
# WRITE TO FILE
file = open(file_string, 'w')
for i in range(len(channel_data)):
file.write("%5d, %5f, %5f, %5f\n" % (time_base[i], channel_data[i], perfect_sine_high[i+int(align_wave)], perfect_sine_low[i+int(align_wave)]))
if iteration == error_threshold:
print "Error threshold reached...Please examine results "
break
print " %d Errors found from %d iterations"%(iteration,num_of_loops)
print "Examine results"
print '\nBye bye ...'
sys.exit()
test/fmcadc200k16b11cha/python/test08.py 0 → 100644
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
import sys
import rr
import time
import os
import fmc_adc_test_suite
from ptsexcept import *
import csr
"""
test00: Load firmware and test mezzanine presence line.
For test suite boards with 6ch adcs this test is required to be run first
"""
def main (default_directory='.'):
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../firmwares/TestSuite_6ch_ref.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
# Objects declaration
spec = rr.Gennum()
fmc = fmc_adc_test_suite.CFmcAdc100ks(spec)
# Check bitsteam type
bitstream_type = fmc.bitstream_type()
print('bitstream type:%.8X') % bitstream_type
if(bitstream_type == 0xFFFFFFFF):
raise PtsCritical ("Firmware not properly loaded.")
print "Pts Critical - firmware not loaded properly"
if(bitstream_type != 0x1):
raise PtsCritical ("Wrong bitstream type.")
print "Pts Critical - wrong bitstream"
# Dump carrier CSR to log
print("PCB version : %d") % ( fmc.pcb_version() ) # used to be a mask here
print("Carrier type : %d") % ( fmc.carrier_type()) # and here
print("Bitstream type : 0x%.8X") % (fmc.bitstream_type())
print("Bitstream date : 0x%.8X") % (fmc.bitstream_date())
print("Status : 0x%.8X") % (fmc.carrier_csr_sta())
print("Control : 0x%.8X") % (fmc.carrier_csr_ctl())
# Check mezzanine presence flag
status = fmc.check_mez_present()
print('carrier csr :%.8X') % status
if(status & 0x1):
print "Pts Critical - mez not pres"
raise PtsCritical ("Mezzanine not present or PRSNT_M2C_L faulty.")
if __name__ == '__main__' :
main()
test/fmcadc200k16b11cha/python/test09.py 0 → 100755
View file @ 0ebb73e1
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Ross Millar <ross.millar@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
## TEST FOR VCXO
import sys
import os
import os.path
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc_test_suite
from pylab import *
from ptsexcept import *
"""
Same as Test Suite test02 - however for FMCs with 6ch ADCs
Counts set number of clock ticks on the mez clock, in terms of the system clock.
Writes a new value to the DAC, which alters the mezzanine clock speed
Counts the same number of clock ticks on the mezzanine clock again
Compares the 2 resuls to see if the mez clock has changed appropriately
"""
def main(default_directory='.') :
# Objects declaration
spec = rr.Gennum()
fmc = fmc_adc_test_suite.CFmcAdc100ks(spec)
# Reset DAC register - Set VCXO to lowest frequency
fmc.spi_dac_write(0x0000)
# Number of sys clock ticks for counter on mezzanine clock to complete count
result = fmc.clock_comparison()
time.sleep(.1)
fmc.spi_dac_write(0xFFFF)
time.sleep(.1)
# Number of sys clock ticks for counter on mezzanine clock to complete count
result_1 = fmc.clock_comparison()
print "VCXO at lowest frequency - Number of system clock ticks for mezzanine clock count : %d" %result
print "VCXO at highest frequency - Number of system clock ticks for mezzanine clock count : %d" %result_1
if (result - result_1) >10:
print "DAC and VCXO fully working"
else:
print "Potential problem with the DAC"
print "Potential problem with the VCXO"
raise PtsError("VCXO or DAC operation failed")
if __name__ == '__main__':
main()
test/fmcadc200k16b11cha/python/threshold_acq.py 0 → 100755
View file @ 0ebb73e1
#!/usr/bin/env python
#coding: utf8
# Copyright CERN, 2011
# Author: Ross Millar <ross.millar@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc_test_suite
import fmc_adc
import cp210x_gpio
from pylab import *
#from ptsexcept import *
import fcntl, struct, termios, os
import time
import array
def main (default_directory='.'):
"""
path_fpga_loader = '../firmwares/fpga_loader';
path_firmware = '../main_firmware_8ch_ref.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
os.system( firmware_loader + ' ' + bitstream)
time.sleep(2);
#main_firmware_8ch_ref.bin
#Requires sinewave input
#Does an acquisition with a threshold trigger,
#checks the acquired data to see if it matches the result expected.
"""
hw_en =1
sw_en =0
chan_for_thresh = 0xB # check that this is masked in the fmc class
int_thresh = 0xF000 # 16 bit in twos comp
slope = 1 # 1 for positive, 0 for negative
delay = 0 # Trigger delay
edge_detect = 1 # Trig on Rising or falling edges, depends on slope
pre_trig_val = 100
post_trig_val = 500
thresh_negative = 0
thresh_positive = 0
error=0
print int(int_thresh)
# Object Declaration
spec = rr.Gennum() # bind to the SPEC board
fmc = fmc_adc.CFmcAdc100ks(spec)
# Set trigger Register
fmc.set_trig_config(hw_en,sw_en,chan_for_thresh,int_thresh,slope,delay,edge_detect)
#print bin(fmc.get_trig_config())
# Do acq on the same channel as selected channel for thresh trig
result = fmc.do_acq(chan_for_thresh, "chan_select" ,"n",post_trig_val,pre_trig_val,1)
#print bin(fmc.get_trig_config())
#print result
if (int_thresh & 0x8000) >> 15 ==0x1:
int_thresh = -0x10000 + int_thresh
print "converted int_thresh", int_thresh
thresh_negative = 1
else:
thresh_positive = 1
if thresh_positive and (slope == 0):
print "Thresh positive and slope positive"
if result[pre_trig_val-1]>int_thresh:
error = 1
if result[pre_trig_val]<=int_thresh:
error = 1
elif thresh_positive and (slope == 1):
if result[pre_trig_val-1]<int_thresh:
error = 1
if result[pre_trig_val]>=int_thresh:
error = 1
elif thresh_negative and (slope == 0):
if result[pre_trig_val-1]>int_thresh:
error = 1
if result[pre_trig_val]<=int_thresh:
error = 1
elif thresh_negative and (slope == 1):
if result[pre_trig_val-1]<int_thresh:
error = 1
if result[pre_trig_val]>=int_thresh:
error = 1
if error == 1:
print "Error with threshold trigger"
else:
print "Thresh Trig as expected"
for i in range(len(result)):
result[i] = result[i]*0.000152
time_base = arange(0,len(result),1)
#Change to Voltage level (depends on 'range setting in adc')
int_thresh=int_thresh*0.000152
# WRITE TO FILE
file = open("adc_100k_acq.txt", 'w')
for i in range(len(result)):
file.write("%5d, %5f, %5f\n" % (time_base[i], int_thresh, result[i]))
if __name__ == '__main__':
main()
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