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Production Test Suite
Commit 1149a8cf authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added spec pts vhdl

parent 203540cb
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Showing with 1145 additions and 1440 deletions
test/spec/vhdl/readme.txt 0 → 100644
View file @ 1149a8cf
Use file: vhdl_bkp_from_samuel/spec/trunk/hdl/
List of folders and the correspondance with the SPEC's test files
-----------------------------------------------------------------
test_ddr -> test07
test_dac_pll -> test08
test_flash_spec -> test03
test_fmc -> test01, test02
test_i2c_sfp -> test04
test_temp_sensor -> test09
test_si570 -> test06
test_sata_dp0 -> test05
test_usb_uart -> test10
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/intern_rst_generator.vhd
View file @ 1149a8cf
......@@ -73,10 +73,10 @@ end intern_rst_generator;
--=================================================================================================
architecture rtl of intern_rst_generator is
signal por_n_synch : std_logic_vector (1 downto 0);
signal por : std_logic;
signal counter : std_logic_vector (4 downto 0);
signal counter_top : std_logic_vector (4 downto 0):= "10000";
signal input_rst_n_synch : std_logic_vector (1 downto 0);
signal input_rst, input_rst_n : std_logic;
signal counter : std_logic_vector (4 downto 0);
signal counter_top : std_logic_vector (4 downto 0):= "10000";
--=================================================================================================
......@@ -87,18 +87,19 @@ begin
---------------------------------------------------------------------------------------------------
-- Input Synchronizer --
---------------------------------------------------------------------------------------------------
-- Synchronous process por_n_synchronizer: Synchronization of the POR input to the
-- clk_i, using a set of 2 registers
-- Synchronous process input_resets_synchronizer: Synchronization of the POR and VME reset inputs
-- to the clk_i, using a set of 2 registers
por_n_synchronizer: process (clk_i)
input_resets_synchronizer: process (clk_i)
begin
if rising_edge (clk_i) then
por_n_synch <= por_n_synch(0) & (por_n_i);
input_rst_n_synch <= input_rst_n_synch(0) & (input_rst_n);
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
por <= not por_n_synch(1);
input_rst_n <= por_n_i and vme_rst_n_i;
input_rst <= not input_rst_n_synch(1);
......@@ -110,7 +111,7 @@ begin
(width => 5)
port map
(clk_i => clk_i,
rst_i => por,
rst_i => input_rst,
counter_top_i => counter_top,
counter_incr_en_i => '1',
counter_o => counter,
......
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/ip_cores/VMEcore/.svn/entries deleted 100644 → 0
View file @ 203540cb
10
dir
0
http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl/VMEcore
http://svn.ohwr.org/vme64x-core
add
665b4545-5c6b-4c24-801b-41150b02b44b
VME_bus.vhd
file
add
VME_Funct_Match.vhd
file
add
VME_IRQ_Controller.vhd
file
add
VME_CR_pack.vhd
file
add
VME_Init.vhd
file
add
VME_Access_Decode.vhd
file
add
Manifest.py
file
add
VME_SharedComps.vhd
file
add
VME_Am_Match.vhd
file
add
VME64xCore_Top.vhd
file
add
vme64x_pack.vhd
file
add
VME_swapper.vhd
file
add
VME_CRAM.vhd
file
add
VME_Wb_master.vhd
file
add
VME_CSR_pack.vhd
file
add
VME_CR_CSR_Space.vhd
file
add
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/ip_cores/wb_i2c_master/.svn/entries deleted 100644 → 0
View file @ 203540cb
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dir
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http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl/wb_i2c_master
http://svn.ohwr.org/vme64x-core
add
665b4545-5c6b-4c24-801b-41150b02b44b
i2c_master_byte_ctrl.vhd
file
add
wb_i2c_master.vhd
file
add
xwb_i2c_master.vhd
file
add
i2c_master_bit_ctrl.vhd
file
add
i2c_master_top.vhd
file
add
Manifest.py
file
add
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/ip_cores/wb_onewire_master/.svn/entries deleted 100644 → 0
View file @ 203540cb
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dir
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http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl/wb_onewire_master
http://svn.ohwr.org/vme64x-core
add
665b4545-5c6b-4c24-801b-41150b02b44b
sockit_owm.v
file
add
xwb_onewire_master.vhd
file
add
wb_onewire_master.vhd
file
add
Manifest.py
file
add
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/ip_cores/wb_slave_adapter/.svn/entries deleted 100644 → 0
View file @ 203540cb
10
dir
0
http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl/wb_slave_adapter
http://svn.ohwr.org/vme64x-core
add
665b4545-5c6b-4c24-801b-41150b02b44b
wb_slave_adapter.vhd
file
add
Manifest.py
file
add
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/ip_cores/wb_spi/.svn/entries deleted 100644 → 0
View file @ 203540cb
10
dir
0
http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl/wb_spi
http://svn.ohwr.org/vme64x-core
add
665b4545-5c6b-4c24-801b-41150b02b44b
spi_top.v
file
add
wb_spi.vhd
file
add
spi_clgen.v
file
add
timescale.v
file
add
xwb_spi.vhd
file
add
spi_defines.v
file
add
spi_shift.v
file
add
Manifest.py
file
add
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/ip_cores/wb_uart/.svn/entries deleted 100644 → 0
View file @ 203540cb
10
dir
0
http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl/wb_uart
http://svn.ohwr.org/vme64x-core
add
665b4545-5c6b-4c24-801b-41150b02b44b
uart_baud_gen.vhd
file
add
build_wb.sh
file
add
uart_async_rx.vhd
file
add
uart.wb
file
add
uart_async_tx.vhd
file
add
newerversion
dir
add
README.txt
file
add
wb_simple_uart.vhd
file
add
manifest.py
file
add
uart_wb_slave.vhd
file
add
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/svec_pts_dac_vcxo_pll.vhd
View file @ 1149a8cf
......@@ -78,13 +78,14 @@
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2012 |
-- Version v1 |
-- Date 11/2012 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2011 v1 EG First version |
-- 11/2011 v2 EG Latest VMEcore version (ProgrID=5a); added internal reset upon power-up |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -158,14 +159,18 @@ entity svec_pts_dac_vcxo_pll is
vme_addr_oe_n_o : out std_logic;
-- DAC VCXO SPI
dac_vcxo_20m_sync_n_o : out std_logic; -- chip select
dac_vcxo_20m_sclk_o : out std_logic; -- clock
dac_vcxo_20m_din_o : out std_logic; -- data in
dac_vcxo_20m_sync_n_o : out std_logic; -- chip select
dac_vcxo_20m_sclk_o : out std_logic; -- clock
dac_vcxo_20m_din_o : out std_logic; -- data in
-- DAC PLL SPI
dac_pll_125m_sync_n_o : out std_logic; -- chip select
dac_pll_125m_sclk_o : out std_logic; -- clock
dac_pll_125m_din_o : out std_logic; -- data in
dac_pll_125m_sync_n_o : out std_logic; -- chip select
dac_pll_125m_sclk_o : out std_logic; -- clock
dac_pll_125m_din_o : out std_logic; -- data in
-- Auxiliary signal: internal reset pulse to LEMO L1
-- fp_gpio1_o : out std_logic; -- Lemo L1
-- fp_gpio1_a2b_o : out std_logic; -- Lemo L1 Output Enable
-- LEDs array
fp_ledn_o : out std_logic_vector(7 downto 0));
......@@ -183,7 +188,7 @@ architecture rtl of svec_pts_dac_vcxo_pll is
signal clk_pll2afpga_125m_ibuf, clk_125m_pll2afpga : std_logic;
-- Resets
signal local_rst_n, rst_n_a, local_rst, s_rst : std_logic;
signal rst_n_synch, pllref_clk_c_rst_synch : std_logic_vector(1 downto 0);
signal pllref_clk_c_rst_synch : std_logic_vector(1 downto 0);
signal pllref_125m_clk_c_rst, vcxo_20m_clk_c_rst : std_logic;
signal pll2afpga_125m_clk_c_rst : std_logic;
signal pll2afpga_clk_c_rst_synch : std_logic_vector(1 downto 0);
......@@ -286,6 +291,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Internal Reset --
---------------------------------------------------------------------------------------------------
-- Generation of a reset pulse for the initialization of the logic right after power-up.
internal_rst: intern_rst_generator
port map
(clk_i => clk_vcxo_20m,
......@@ -294,7 +300,11 @@ begin
rst_n_o => local_rst_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
local_rst <= not local_rst_n;
local_rst <= not local_rst_n;
-- Auxiliary signal: internal reset pulse to LEMO L1
-- fp_gpio1_o <= local_rst;
-- fp_gpio1_a2b_o <= '1';
---------------------------------------------------------------------------------------------------
-- WISHBONE DECODER --
......
test/svec/VHDL/svec_pts_dac_vcxo_pll/rtl/svec_pts_pkg.vhd
View file @ 1149a8cf
......@@ -16,13 +16,14 @@
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2012 |
-- Version v0.1 |
-- Date 11/2012 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 06/2012 v0.1 EG First version |
-- 06/2012 v1 EG First version |
-- 11/2011 v2 EG Latest VMEcore version (ProgrID=5a); added internal reset unit |
-- |
---------------------------------------------------------------------------------------------------
......
test/svec/VHDL/svec_pts_dac_vcxo_pll/ucf/svec_pts_dac_vcxo_pll.ucf
View file @ 1149a8cf
......@@ -289,3 +289,14 @@ NET "dac_pll_125m_sclk_o" IOSTANDARD = "LVCMOS33";
NET "dac_pll_125m_din_o" LOC = P25;
NET "dac_pll_125m_din_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Aux: internal reset pulse to LEMO
#----------------------------------------
#NET "fp_gpio1_o" LOC = T28;
#NET "fp_gpio1_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio1_a2b_o" LOC = T30;
#NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
test/svec/VHDL/svec_pts_fmcconnect/rtl/input_pins_wb_slave.vhd
View file @ 1149a8cf
......@@ -70,7 +70,7 @@ end input_pins_wb_slave;
architecture behavioral of input_pins_wb_slave is
signal input_pins_synch_0, input_pins_synch_1, input_pins_synched : std_logic_vector(95 downto 0);
signal dummy_reg : std_logic_vector(31 downto 0);
signal dummy_reg : std_logic_vector(31 downto 0) := x"C000FFEE"; -- initial value
--=================================================================================================
-- architecture begin
......
test/svec/VHDL/svec_pts_fmcconnect/rtl/svec_pts_pkg.vhd
View file @ 1149a8cf
......@@ -16,13 +16,14 @@
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2012 |
-- Version v0.1 |
-- Date 11/2012 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 06/2012 v0.1 EG First version |
-- 06/2012 v1 EG First version |
-- 11/2011 v2 EG Latest VMEcore version (ProgrID=5a); added internal reset unit |
-- |
---------------------------------------------------------------------------------------------------
......@@ -45,12 +46,15 @@
-- Libraries & Packages
--=================================================================================================
-- Standard library
-- Standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific libraries
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
--=================================================================================================
-- Package declaration for svec_pts_pkg
......@@ -99,51 +103,57 @@ package svec_pts_pkg is
---------------------------------------------------------------------------------------------------
component VME64xCore_Top
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack : out std_logic;
IRQ_i : in std_logic;
-- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0));
generic
(g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_cram_size : integer;
g_BoardID : integer;
g_ManufacturerID : integer;
g_RevisionID : integer;
g_ProgramID : integer);
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic;
debug : out std_logic_vector(7 downto 0));
end component;
......@@ -231,6 +241,19 @@ package svec_pts_pkg is
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component intern_rst_generator
port
(clk_i : in std_logic;
por_n_i : in std_logic;
vme_rst_n_i : in std_logic;
-------------------------------------------------------------
rst_n_o : out std_logic);
-------------------------------------------------------------
end component;
end svec_pts_pkg;
......
test/svec/VHDL/svec_pts_fmcsuppl_sfpeeprom/rtl/svec_pts_pkg.vhd
View file @ 1149a8cf
......@@ -16,13 +16,14 @@
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2012 |
-- Version v0.1 |
-- Date 11/2012 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 06/2012 v0.1 EG First version |
-- 06/2012 v1 EG First version |
-- 11/2011 v2 EG Latest VMEcore version (ProgrID=5a); added internal reset unit |
-- |
---------------------------------------------------------------------------------------------------
......@@ -45,12 +46,15 @@
-- Libraries & Packages
--=================================================================================================
-- Standard library
-- Standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific libraries
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
--=================================================================================================
-- Package declaration for svec_pts_pkg
......@@ -84,55 +88,60 @@ package svec_pts_pkg is
---------------------------------------------------------------------------------------------------
component VME64xCore_Top
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack : out std_logic;
IRQ_i : in std_logic;
-- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0));
generic
(g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_cram_size : integer;
g_BoardID : integer;
g_ManufacturerID : integer;
g_RevisionID : integer;
g_ProgramID : integer);
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic;
debug : out std_logic_vector(7 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component wb_addr_decoder
generic
......@@ -162,6 +171,36 @@ package svec_pts_pkg is
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component incr_counter
generic
(width : integer := 32);
port
(clk_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
counter_incr_en_i : in std_logic;
rst_i : in std_logic;
-------------------------------------------------------------
counter_is_full_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component intern_rst_generator
port
(clk_i : in std_logic;
por_n_i : in std_logic;
vme_rst_n_i : in std_logic;
-------------------------------------------------------------
rst_n_o : out std_logic);
-------------------------------------------------------------
end component;
end svec_pts_pkg;
......
test/svec/VHDL/svec_pts_lemo_pushbutt/rtl/pushbutt_eval_wb_slave.vhd
View file @ 1149a8cf
......@@ -66,8 +66,7 @@ entity pushbutt_eval_wb_slave is
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
-- Push Button
fp_pushbutton_i : in std_logic;
fp_ledn_o : out std_logic_vector(7 downto 0));
fp_pushbutton_i : in std_logic);
end pushbutt_eval_wb_slave;
......@@ -174,37 +173,5 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- LEDs --
---------------------------------------------------------------------------------------------------
drive_leds : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if rst_i = '1' or clear_regs = '1' then
leds <= "01111111";
led_divider <= (others => '0');
pushbutton_pushed <= '0';
else
led_divider <= led_divider+ 1;
if pushbutton_f_edge = '1' then
pushbutton_pushed <= '1';
end if;
if pushbutton_pushed = '1' then
leds <= "11111111";
else
if led_divider = 0 then
leds <= leds(6 downto 0) & leds(7);
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
fp_ledn_o <= leds;
end behavioral;
test/svec/VHDL/svec_pts_lemo_pushbutt/rtl/svec_pts_pkg.vhd
View file @ 1149a8cf
......@@ -16,13 +16,14 @@
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2012 |
-- Version v0.1 |
-- Date 11/2012 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 06/2012 v0.1 EG First version |
-- 06/2012 v1 EG First version |
-- 11/2011 v2 EG Latest VMEcore version (ProgrID=5a); added internal reset unit |
-- |
---------------------------------------------------------------------------------------------------
......@@ -45,12 +46,15 @@
-- Libraries & Packages
--=================================================================================================
-- Standard library
-- Standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific libraries
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
--=================================================================================================
-- Package declaration for svec_pts_pkg
......@@ -82,55 +86,60 @@ package svec_pts_pkg is
---------------------------------------------------------------------------------------------------
component VME64xCore_Top
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack : out std_logic;
IRQ_i : in std_logic;
-- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0));
generic
(g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_cram_size : integer;
g_BoardID : integer;
g_ManufacturerID : integer;
g_RevisionID : integer;
g_ProgramID : integer);
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic;
debug : out std_logic_vector(7 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component wb_addr_decoder
generic
......@@ -162,7 +171,6 @@ package svec_pts_pkg is
end component;
---------------------------------------------------------------------------------------------------
component fp_info_wb_slave
port
......@@ -189,7 +197,6 @@ package svec_pts_pkg is
end component;
---------------------------------------------------------------------------------------------------
component pushbutt_eval_wb_slave is
port
......@@ -202,11 +209,37 @@ package svec_pts_pkg is
wb_we_i : in std_logic;
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
fp_pushbutton_i : in std_logic;
fp_ledn_o : out std_logic_vector(7 downto 0));
fp_pushbutton_i : in std_logic);
end component;
---------------------------------------------------------------------------------------------------
component incr_counter
generic
(width : integer := 32);
port
(clk_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
counter_incr_en_i : in std_logic;
rst_i : in std_logic;
-------------------------------------------------------------
counter_is_full_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component intern_rst_generator
port
(clk_i : in std_logic;
por_n_i : in std_logic;
vme_rst_n_i : in std_logic;
-------------------------------------------------------------
rst_n_o : out std_logic);
-------------------------------------------------------------
end component;
end svec_pts_pkg;
......
test/svec/VHDL/svec_pts_si570_tempid_eeprom/rtl/clk_info_wb_slave.vhd
View file @ 1149a8cf
......@@ -93,7 +93,8 @@ end clk_info_wb_slave;
architecture behavioral of clk_info_wb_slave is
signal clk_ok_synch, clk_err_synch : std_logic_vector(1 downto 0);
signal reg2, reg3, reg5, reg6 : std_logic_vector(31 downto 0);
signal reg2, reg5, reg6 : std_logic_vector(31 downto 0);
signal reg3 : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- initial value
signal clk_err, oe_clk : std_logic;
--=================================================================================================
......@@ -128,7 +129,7 @@ begin
if rst_i = '1' then
wb_data_o <= (others => '0');
reg2 <= (others => '0');
reg3 <= x"0BEBC200";
reg3 <= x"FFFFFFFF";
reg5 <= (others => '0');
reg6 <= (others => '0');
else
......
test/svec/VHDL/svec_pts_si570_tempid_eeprom/rtl/svec_pts_pkg.vhd
View file @ 1149a8cf
......@@ -16,13 +16,14 @@
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2012 |
-- Version v1 |
-- Date 11/2012 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 06/2012 v0.1 EG First version |
-- 06/2012 v1 EG First version |
-- 11/2011 v2 EG Latest VMEcore version (ProgrID=5a); added internal reset unit |
-- |
---------------------------------------------------------------------------------------------------
......@@ -45,12 +46,15 @@
-- Libraries & Packages
--=================================================================================================
-- Standard library
-- Standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific libraries
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
--=================================================================================================
-- Package declaration for svec_pts_pkg
......@@ -85,51 +89,57 @@ package svec_pts_pkg is
---------------------------------------------------------------------------------------------------
component VME64xCore_Top
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack : out std_logic;
IRQ_i : in std_logic;
-- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0));
generic
(g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_cram_size : integer;
g_BoardID : integer;
g_ManufacturerID : integer;
g_RevisionID : integer;
g_ProgramID : integer);
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic;
debug : out std_logic_vector(7 downto 0));
end component;
......@@ -201,6 +211,19 @@ package svec_pts_pkg is
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component intern_rst_generator
port
(clk_i : in std_logic;
por_n_i : in std_logic;
vme_rst_n_i : in std_logic;
-------------------------------------------------------------
rst_n_o : out std_logic);
-------------------------------------------------------------
end component;
end svec_pts_pkg;
......
test/svec/VHDL/svec_pts_usb_vmep2/rtl/clk_info_wb_slave.vhd
View file @ 1149a8cf
......@@ -93,7 +93,8 @@ end clk_info_wb_slave;
architecture behavioral of clk_info_wb_slave is
signal clk_ok_synch, clk_err_synch : std_logic_vector(1 downto 0);
signal reg2, reg3, reg5, reg6 : std_logic_vector(31 downto 0);
signal reg2, reg5, reg6 : std_logic_vector(31 downto 0);
signal reg3 : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- initial value
signal clk_err, oe_clk : std_logic;
--=================================================================================================
......@@ -128,7 +129,7 @@ begin
if rst_i = '1' then
wb_data_o <= (others => '0');
reg2 <= (others => '0');
reg3 <= x"0BEBC200";
reg3 <= x"FFFFFFFF";
reg5 <= (others => '0');
reg6 <= (others => '0');
else
......
test/svec/VHDL/svec_pts_usb_vmep2/rtl/input_output_pins_wb_slave.vhd
View file @ 1149a8cf
......@@ -73,7 +73,8 @@ end input_output_pins_wb_slave;
architecture behavioral of input_output_pins_wb_slave is
signal input_pins_synch_0, input_pins_synch_1, input_pins_synched : std_logic_vector(31 downto 0);
signal dummy_reg, output_pins : std_logic_vector(31 downto 0);
signal output_pins : std_logic_vector(31 downto 0);
signal dummy_reg : std_logic_vector(31 downto 0) := x"C000FFEE"; -- initial value
--=================================================================================================
-- architecture begin
......
test/svec/VHDL/svec_pts_usb_vmep2/rtl/svec_pts_pkg.vhd
View file @ 1149a8cf
......@@ -16,13 +16,14 @@
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2012 |
-- Version v0.1 |
-- Date 11/2012 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 06/2012 v0.1 EG First version |
-- 06/2012 v1 EG First version |
-- 11/2011 v2 EG Latest VMEcore version (ProgrID=5a); added internal reset unit |
-- |
---------------------------------------------------------------------------------------------------
......@@ -45,12 +46,15 @@
-- Libraries & Packages
--=================================================================================================
-- Standard library
-- Standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific libraries
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
--=================================================================================================
-- Package declaration for svec_pts_pkg
......@@ -85,51 +89,57 @@ package svec_pts_pkg is
---------------------------------------------------------------------------------------------------
component VME64xCore_Top
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack : out std_logic;
IRQ_i : in std_logic;
-- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0));
generic
(g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_cram_size : integer;
g_BoardID : integer;
g_ManufacturerID : integer;
g_RevisionID : integer;
g_ProgramID : integer);
port
(clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic;
debug : out std_logic_vector(7 downto 0));
end component;
......@@ -218,6 +228,19 @@ package svec_pts_pkg is
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component intern_rst_generator
port
(clk_i : in std_logic;
por_n_i : in std_logic;
vme_rst_n_i : in std_logic;
-------------------------------------------------------------
rst_n_o : out std_logic);
-------------------------------------------------------------
end component;
end svec_pts_pkg;
......
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