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Production Test Suite
Commit 4e895887 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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tdc pts as sent at 7sols in march 2013

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test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/carrier_onewire.py deleted 100644 → 0
View file @ 0fe848e3
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Import system modules
import sys
import time
import os
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
# Import specific modules
import fmc_tdc
sys.path.append('../../../../fmc_delay/software/python/')
import fdelay_lib
FAMILY_CODE = 0x28
"""
test01: Carrier One Wire
"""
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/tdc_carrier_info.bit'#eva_tdc_for_v2.bit'#evas_tdc_irq6.bit'
FMC_TDC_CHANNEL_NB = 5
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM = '../firmwares/fmc_delay_spec.bin'
# SPEC object declaration
spec = rr.Gennum()
###########################################################################
# TDC
###########################################################################
# Bind SPEC object to FMC TDC card
print "\n-----------------------------------------------------------------"
print "---------------------------- FMC TDC ---------------------------- "
print "---------------------- Carrier 1 wire test ----------------------"
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
spec.bind(FMC_TDC_ADDR)
print "\n_________________________Initialisations_________________________\n"
# Load FMC TDC firmware
print "Loading FMC TDC firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
########################################################################
# Read unique ID and print to log
print "\n________________________Carrier unique ID________________________\n"
unique_id = tdc.carr_get_unique_id()
if(unique_id == -1):
print('/!\Cannot read DS18D20 1-wire thermometer/!\ ')
else:
print('Unique ID: %.12X') % unique_id
# Read temperatur and print to log
print "\n_______________________Carrier temperature_______________________\n"
temp = tdc.carr_get_temp()
print('Carrier temperature: %3.3f°C') % temp
if((unique_id & 0xFF) != FAMILY_CODE):
family_code = unique_id & 0xFF
print('family code: 0x%.8X') % family_code
print "\n-----------------------------------------------------------------"
if __name__ == '__main__' :
main()
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/csr.py deleted 100644 → 0
View file @ 0fe848e3
#!/usr/bin/python
import sys
import rr
import time
class CCSR:
def __init__(self, bus, base_addr):
self.base_addr = base_addr;
self.bus = bus;
def wr_reg(self, addr, val):
#print(" wr:%.8X reg:%.8X")%(val,(self.base_addr+addr))
self.bus.iwrite(0, self.base_addr + addr, 4, val)
def rd_reg(self, addr):
reg = self.bus.iread(0, self.base_addr + addr, 4)
#print(" reg:%.8X value:%.8X")%((self.base_addr+addr), reg)
return reg
def wr_bit(self, addr, bit, value):
reg = self.rd_reg(addr)
if(0==value):
reg &= ~(1<<bit)
else:
reg |= (1<<bit)
self.wr_reg(addr, reg)
def rd_bit(self, addr, bit):
if(self.rd_reg(addr) & (1<<bit)):
return 1
else:
return 0
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/ctri_test.py deleted 100644 → 0
View file @ 0fe848e3
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
####### n=0; while [[ $n -lt 10 ]]; do echo Iteration $n; sudo ./test05_v2.py; n=$((n+1)); done | tee -a tmp.txt #######
# Import system modules
import sys
import time
import os
import math
import pylab
from pylab import *
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
# Import specific modules
import fmc_tdc
sys.path.append('../../../../fmc_delay/software/python/')
import fdelay_lib
"""
test07: Tests the accuracy of the Fine Delay delta
"""
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/evas_tdc_irq8.bit'
FMC_TDC_CHANNEL_NB = 5
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM = '../firmwares/fmc_delay_spec.bin'
# SPEC object declaration
spec = rr.Gennum()
###########################################################################
# TDC
###########################################################################
# Bind SPEC object to FMC TDC card
print "-----------------------------------------------------------------"
print "---------------------------- FMC TDC ---------------------------- "
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
spec.bind(FMC_TDC_ADDR)
# Load FMC TDC firmware
print "\n_________________________Initialisations_________________________\n"
print "Loading FMC TDC firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# TDC configuration
print "\n__________________________Configuration__________________________\n"
tdc.config_acam()
tdc.set_irq_tstamp_thresh(0x100) # set to
tdc.set_irq_time_thresh(0xFF) # secs
time.sleep(1)
tdc.enable_channels()
for ch in range(1,FMC_TDC_CHANNEL_NB+1):
tdc.channel_term(ch, 1)
# Enable TDC core interrupts
#print "\n____________________________IRQ mask_____________________________\n"
#print('Set IRQ enable mask: %.4X')%tdc.set_irq_en_mask(0xC)
# Check ACAM status
print "\n___________________________ACAM reset____________________________\n"
tdc.reset_acam()
print "\n___________________________ACAM status___________________________\n"
acam_status_test = tdc.read_acam_status()-0xC4000800
if acam_status_test == 0:
print "ACAM status OK!"
else:
print "/!\ACAM not OK../!\ "
# Readback all ACAM configuration regs
print "\n_________________Reading back ACAM configuration_________________\n"
tdc.readback_acam_config()
# Enable timestamps aquisition
print "\n_______________________Starting aquisition_______________________\n"
tdc.start_acq()
all_periods_min = []
all_periods_max = []
# several iterations of sending pulses and retrieving timestamps
for m in range(1):
print "\n________________________Accuracy testing_________________________\n"
#tdc.check_irq()
time.sleep(10)
print "IRQ iteration: %d // Overflows: %d // IRQ source: %d // Write pointer: %d \r"%(m, tdc.get_overflow_counter(), tdc.get_irq_src(), tdc.get_pointer()),
timestamps = tdc.get_timestamps(1)
r_edge_timestamps = []
period_list = []
for i in range(len(timestamps)):
if ((timestamps[i][2] == 1) and (timestamps[i][1] == 4)):
r_edge_timestamps.append(timestamps[i][0])
r_edge_timestamps.sort()
for i in range(0,len(r_edge_timestamps)-1):
period = r_edge_timestamps[i+1] - r_edge_timestamps[i]
period_list.append(period)
current_max = max(period_list)
current_min = min(period_list)
span = current_max-current_min
print "\n__________________Itteration %d Accuracy Results_________________\n"%m
print "Number of timestamps : %d"%(len(timestamps))
print "Max of this itteration : %15.3f ps"%max(period_list)
print "Min of this itteration : %15.3f ps"%min(period_list)
print "Span of this itteration : %15.3f ps"%span
if span > 1600:
print "Span messed up!"
for i in range(len(timestamps)):
print timestamps[i]
all_periods_max.append(current_max)
all_periods_min.append(current_min)
"""
print "Max so far found at itteration %d: %15.3f ps"%(all_periods_max.index(max(all_periods_max)), max(all_periods_max))
print "Min so far found at itteration %d: %15.3f ps"%(all_periods_min.index(min(all_periods_min)), min(all_periods_min))
print "Span so far : %15.3f ps"%((max(all_periods_max))-(min(all_periods_min)))
"""
# out of the for loop!
print "\n___________________________ACAM status___________________________\n"
acam_status_test = tdc.read_acam_status()-0xC4000800
if acam_status_test == 0:
print "ACAM status OK!"
else:
print "/!\ACAM not OK../!\ "
print "\n_______________________Stopping aquisition_______________________\n"
tdc.stop_acq()
"""
print "\n_______________________! Final Results !_________________________\n"
#print all_periods_min
#print all_periods_max
print "\n\nAnd the final span after %d pulses is %7.3f ps!\n"%((256*m), (max(all_periods_max))-(min(all_periods_min)))
"""
print "\n-----------------------------------------------------------------\n\n\n"
if __name__ == '__main__' :
main()
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/ds18b20.py deleted 100644 → 0
View file @ 0fe848e3
#!/usr/bin/python
import sys
import rr
import time
import onewire
class CDS18B20:
# ROM commands
ROM_SEARCH = 0xF0
ROM_READ = 0x33
ROM_MATCH = 0x55
ROM_SKIP = 0xCC
ROM_ALARM_SEARCH = 0xEC
# DS18B20 fonctions commands
CONVERT_TEMP = 0x44
WRITE_SCRATCHPAD = 0x4E
READ_SCRATCHPAD = 0xBE
COPY_SCRATCHPAD = 0x48
RECALL_EEPROM = 0xB8
READ_POWER_SUPPLY = 0xB4
# Thermometer resolution configuration
RES = {'9-bit':0x0, '10-bit':0x1, '11-bit':0x2, '12-bit':0x3}
def __init__(self, onewire, port):
self.onewire = onewire
self.port = port
def read_serial_number(self):
#print('[DS18B20] Reading serial number')
if(1 != self.onewire.reset(self.port)):
print('[DS18B20] No presence pulse detected')
return -1
else:
#print('[DS18B20] Write ROM command %.2X') % self.ROM_READ
err = self.onewire.write_byte(self.port, self.ROM_READ)
if(err != 0):
print('[DS18B20] Write error')
return -1
family_code = self.onewire.read_byte(self.port)
serial_number = 0
for i in range(6):
serial_number |= self.onewire.read_byte(self.port) << (i*8)
crc = self.onewire.read_byte(self.port)
#print('[DS18B20] Family code : %.2X') % family_code
#print('[DS18B20] Serial number: %.12X') % serial_number
#print('[DS18B20] CRC : %.2X') % crc
return ((crc<<56) | (serial_number<<8) | family_code)
def access(self, serial_number):
#print('[DS18B20] Accessing device')
if(1 != self.onewire.reset(self.port)):
print('[DS18B20] No presence pulse detected')
return -1
else:
#print('[DS18B20] Write ROM command %.2X') % self.ROM_MATCH
err = self.onewire.write_byte(self.port, self.ROM_MATCH)
#print serial_number
block = []
for i in range(8):
block.append(serial_number & 0xFF)
serial_number >>= 8
#print block
self.onewire.write_block(self.port, block)
return 0
def read_temp(self, serial_number):
#print('[DS18B20] Reading temperature')
err = self.access(serial_number)
#print('[DS18B20] Write function command %.2X') % self.CONVERT_TEMP
err = self.onewire.write_byte(self.port, self.CONVERT_TEMP)
time.sleep(0.8)
err = self.access(serial_number)
#print('[DS18B20] Write function command %.2X') % self.READ_SCRATCHPAD
err = self.onewire.write_byte(self.port, self.READ_SCRATCHPAD)
data = self.onewire.read_block(self.port, 9)
#for i in range(9):
# print('Scratchpad data[%1d]: %.2X') % (i, data[i])
temp = (data[1] << 8) | (data[0])
if(temp & 0x1000):
temp = -0x10000 + temp
temp = temp/16.0
return temp
# Set temperature thresholds
# Configure thermometer resolution
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/fmc_tdc.py
View file @ 4e895887
......@@ -39,6 +39,10 @@ class CFMCTDC:
# TDC core WISHBONE adress
TDC_CORE_ADDR = 0x20000
# Carrier info WISHBONE adress
CARRIER_INFO_ADDR = 0xC0000
CSR_BSTM_TYPE = 0x04
# IRQ controller
IRQ_CONTROLLER_ADDR = 0xA0000
IRQ_CTRL_SRC = 0x4
......@@ -82,6 +86,7 @@ class CFMCTDC:
self.tdc_regs = csr.CCSR(self.bus, self.TDC_CORE_ADDR)
self.gnum = gn4124.CGN4124(self.bus, self.GNUM_CSR_ADDR)
self.irq_controller = csr.CCSR(self.bus, self.IRQ_CONTROLLER_ADDR)
self.carrier_csr = csr.CCSR(self.bus, self.CARRIER_INFO_ADDR)
# Set GNUM local bus frequency
self.gnum.set_local_bus_freq(160)
......@@ -111,6 +116,10 @@ class CFMCTDC:
###############################################################################################
# Read bitstream type
def read_bitstream_type(self):
return self.carrier_csr.rd_reg(0x04)
# Returns mezzanine unique ID
def mezz_get_unique_id(self):
return self.mezz_ds18b20.read_serial_number()
......@@ -204,6 +213,7 @@ class CFMCTDC:
# print "ERROR! ACAM IC8: reg 0x%02X: received 0x%08X; expected 0x%08X"%(i, self.tdc_regs.rd_reg(i), self.ACAM_READBACK_REGS[i])
# return acam_regs
def readback_acam_config(self):
self.tdc_regs.wr_reg(0xFC, 0x8)
time.sleep(1)
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/fmc_tdc0.py deleted 100644 → 0
View file @ 0fe848e3
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Import system modules
import sys
import time
import os
import math
import i2c
import onewire
import ds18b20
import eeprom_24aa64
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
import rr
from ptsexcept import *
import csr
import gn4124
"""
FMC TDC class
"""
class CFMCTDC:
# Wishbone core adresses
GNUM_CSR_ADDR = 0x0
TDC_CORE_ADDR = 0x80000
# Register addresses
ACAM_READBACK_ADDR = [0x40, 0x44, 0x48, 0x4C, 0X50, 0x54, 0x58, 0x5C, 0x60, 0x64, 0x68, 0x6C, 0x70, 0x78]
# DMA length in bytes
DMA_LENGTH = 4096
# Write pointer register
WP_MASK = 0xFFF
WP_OVERFLOW_MASK = 0xFFFFF000
# Timestamp meta-data
META_CHANNEL_MASK = 0xF
META_SLOPE_MASK = 0xF0
META_FIFO_LF_MASK = 0xF00
META_FIFO_EF_MASK = 0xF000
META_SLOPE = ['falling', 'rising']
def __init__(self, bus):
# Objects delcaration
self.bus = bus;
self.tdc_regs = csr.CCSR(self.bus, self.TDC_CORE_ADDR)
self.gnum = gn4124.CGN4124(self.bus, self.GNUM_CSR_ADDR)
# Set GNUM local bus frequency
self.gnum.set_local_bus_freq(160)
print "Gennum local bus clock %d MHz"%(self.gnum.get_local_bus_freq())
time.sleep(2)
# Reset FPGA
print "Resetting FPGA"
self.gnum.rstout33_cycle()
time.sleep(3)
# Get physical addresses of the memory pages for DMA transfer
self.dma_pages = self.gnum.get_physical_addr()
###############################################################################################
# Configures ACAM
def config_acam(self):
print "\n-- -- -- -- -- -- configuring acam -- -- -- -- -- --"
print "Configuring ACAM"
time.sleep(2)
self.tdc_regs.wr_reg(0x00, 0x1F0FC81)
self.tdc_regs.wr_reg(0x04, 0x0)
self.tdc_regs.wr_reg(0x08, 0xE02)
time.sleep(2)
self.tdc_regs.wr_reg(0x0C, 0x0)
self.tdc_regs.wr_reg(0x10, 0x200000F)
self.tdc_regs.wr_reg(0x14, 0x7D0)
self.tdc_regs.wr_reg(0x18, 0x3)
self.tdc_regs.wr_reg(0x1C, 0x1FEA)
self.tdc_regs.wr_reg(0x2C, 0xFF0000)
self.tdc_regs.wr_reg(0x30, 0x4000000)
self.tdc_regs.wr_reg(0x38, 0x0)
self.tdc_regs.wr_reg(0xFC, 0x4)
time.sleep(2)
def load_acam_config(self):
self.tdc_regs.wr_reg(0xFC, 0x4)
time.sleep(2)
def reset_acam(self):
print "\n-- -- -- -- -- -- resetting acam -- -- -- -- -- --"
print "Reseting ACAM"
self.tdc_regs.wr_reg(0xFC, 0x100)
time.sleep(2)
def readback_acam_config(self):
print "\n-- -- -- -- reading back acam configuration -- -- -- --"
print "Reading back ACAM configuration."
self.tdc_regs.wr_reg(0xFC, 0x8)
time.sleep(2)
for i in self.ACAM_READBACK_ADDR:
print "reg 0x%02X = 0x%08X"%(i, self.tdc_regs.rd_reg(i))
def read_acam_status(self):
self.tdc_regs.wr_reg(0xFC, 0x10)
return self.tdc_regs.rd_reg(0x70)
def enable_channels(self):
self.tdc_regs.wr_bit(0x84, 7, 1)
def channel_term(self, channel, enable):
self.tdc_regs.wr_bit(0x84, channel-1, enable)
#print "0x%08X"%self.tdc_regs.rd_reg(0x84)
def set_utc(self, utc):
self.tdc_regs.wr_reg(0x80, utc)
self.tdc_regs.wr_reg(0xFC, 0x200)
def get_utc(self):
return self.tdc_regs.rd_reg(0x94)
def start_acq(self):
print "\n-- -- -- -- -- -- -- -- -- -- -- -- -- -- --"
print "Start acquisition"
self.tdc_regs.wr_reg(0xFC, 0x1)
def stop_acq(self):
print "\n-- -- -- -- -- -- -- -- -- -- -- -- -- -- --"
print "Stop acquisition"
self.tdc_regs.wr_reg(0xFC, 0x2)
def get_pointer(self):
return (self.WP_MASK & self.tdc_regs.rd_reg(0x9C))
def get_overflow_counter(self):
return ((self.WP_OVERFLOW_MASK & self.tdc_regs.rd_reg(0x9C)) >> 12)
def get_timestamps(self, verbose=0):
# Read the number of bytes to be read from the board
dma_length = self.get_pointer()
carrier_addr = 0x0
# Calculate the number of DMA item required to get the data
items_required = int(math.ceil(dma_length/float(self.DMA_LENGTH)))
if(128 < items_required):
print('Required items: %d')%items_required
raise Exception('Current gn4124 class only supports up to 128 items.')
if(verbose):
print('Required items: %d')%items_required
# Configure DMA
for num in range(items_required):
if(items_required == num+1):
next_item = 0
item_length = (dma_length-(num*self.DMA_LENGTH))
else:
next_item = 1
item_length = self.DMA_LENGTH
if(0 == num):
item_start_addr = carrier_addr
else:
item_start_addr = carrier_addr + (num*self.DMA_LENGTH)
if(verbose):
print("item nb:%d item_carrier_addr:0x%.8X item_host_addr:0x%.8X item_length:%d next_item:%d)")%(num,item_start_addr,self.dma_pages[num+1],item_length,next_item)
self.gnum.add_dma_item(item_start_addr, self.dma_pages[num+1], item_length, 0, next_item)
if(verbose):
if(items_required > 1):
items = self.gnum.get_memory_page(0)
print('DMA items:')
for i in range(items_required*8):
print('%.4X: %.8X')%(i*4,items[i])
# Start DMA
dma_finished = 0
if(verbose):
print "Start DMA"
self.gnum.start_dma()
"""
# Poll on DMA status
print "Wait for DMA done"
while('Done' == self.gnum.get_dma_status()):
time.sleep(0.01)
print "DMA done!"
"""
# Wait for end of DMA interrupt
if(verbose):
print('Wait GN4124 interrupt')
self.gnum.wait_irq()
if(verbose):
print('GN4124 interrupt occured')
"""
print('irq mask:%.4X')%self.get_irq_en_mask() if(verbose)
while(0 == dma_finished):
irq_src = self.get_irq_source()
if(verbose):
print('IRQ source : %.4X')%irq_src
print('DMA status: %s')%self.gnum.get_dma_status()
if(irq_src & self.IRQ_SRC_DMA_END):
print('IRQ source : %.4X')%irq_src if(verbose)
self.clear_irq_source(self.IRQ_SRC_DMA_END)
print('IRQ source : %.4X')%self.get_irq_source() if(verbose)
dma_finished = 1
time.sleep(0.005)
print('DMA finished!') if(verbose)
"""
# Retrieve data from host memory
data = []
for i in range(items_required):
data += self.gnum.get_memory_page(i+1)
if(verbose):
print('data length:%d')%(len(data)*4)
# Format data
if(verbose):
print "Data"
raw_timestamps = []
timestamps = []
for i in range(0,dma_length/4,4):
timestamp = data[i+2] * 1E12 + data[i+1] * 8E3 + data[i] * 81.03
channel = self.META_CHANNEL_MASK & data[i+3]
slope = ((self.META_SLOPE_MASK & data[i+3]) >> 4)
fifo_lf = ((self.META_FIFO_LF_MASK & data[i+3]) >> 8)
fifo_ef = ((self.META_FIFO_EF_MASK & data[i+3]) >> 12)
raw_timestamps.append((data[i+3]<<96)+(data[i+2]<<64)+(data[i+1]<<32)+data[i])
timestamps.append([timestamp, channel, slope, fifo_lf, fifo_ef])
if(verbose):
print "[%03d] sec:%15.3f channel:%d slope:%7s fifo_lf:%d fifo_ef:%d"%(i/4,timestamp, channel, self.META_SLOPE[slope], fifo_lf, fifo_ef)
#print "[%03d] sec:%15.3f slope:%d fifo_lf:%d fifo_ef:%d"%(i/4,timestamp, slope, fifo_lf, fifo_ef)
if(verbose):
print "Number of timestamps = %d" % (len(timestamps))
for i in range(len(timestamps)):
print timestamps[i]
return timestamps
if __name__ == '__main__' :
main()
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/i2c.py deleted 100644 → 0
View file @ 0fe848e3
#!/usr/bin/python
import sys
import rr
import time
class COpenCoresI2C:
# OpenCores I2C registers description
R_PREL = 0x0
R_PREH = 0x4
R_CTR = 0x8
R_TXR = 0xC
R_RXR = 0xC
R_CR = 0x10
R_SR = 0x10
CTR_EN = (1<<7)
CR_STA = (1<<7)
CR_STO = (1<<6)
CR_RD = (1<<5)
CR_WR = (1<<4)
CR_ACK = (1<<3)
SR_RXACK = (1<<7)
SR_TIP = (1<<1)
def wr_reg(self, addr, val):
self.bus.iwrite(0, self.base_addr + addr, 4, val)
def rd_reg(self,addr):
return self.bus.iread(0, self.base_addr + addr, 4)
# Function called during object creation
# bus = host bus (PCIe, VME, etc...)
# base_addr = I2C core base address
# prescaler = SCK prescaler, prescaler = (Fsys/(5*Fsck))-1
def __init__(self, bus, base_addr, prescaler):
self.bus = bus
self.base_addr = base_addr
self.wr_reg(self.R_CTR, 0)
#print("prescaler: %.4X") % prescaler
self.wr_reg(self.R_PREL, (prescaler & 0xff))
#print("PREL: %.2X") % self.rd_reg(self.R_PREL)
self.wr_reg(self.R_PREH, (prescaler >> 8))
#print("PREH: %.2X") % self.rd_reg(self.R_PREH)
self.wr_reg(self.R_CTR, self.CTR_EN)
#print("CTR: %.2X") % self.rd_reg(self.R_CTR)
if(not(self.rd_reg(self.R_CTR) & self.CTR_EN)):
print "Warning! I2C core is not enabled!"
def wait_busy(self):
while(self.rd_reg(self.R_SR) & self.SR_TIP):
pass
def start(self, addr, write_mode):
#print('i2c:start: addr=%.2X')%addr
addr = addr << 1
#print('i2c:start: addr=%.2X')%addr
if(write_mode == False):
addr = addr | 1
#print('i2c:start: addr=%.2X')%addr
self.wr_reg(self.R_TXR, addr)
#print("R_TXR: %.2X") % self.rd_reg(self.R_TXR)
self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR)
self.wait_busy()
if(self.rd_reg(self.R_SR) & self.SR_RXACK):
raise Exception('No ACK upon address (device 0x%x not connected?)' % addr)
return "nack"
else:
return "ack"
def write(self, data, last):
self.wr_reg(self.R_TXR, data)
cmd = self.CR_WR
if(last):
cmd = cmd | self.CR_STO
self.wr_reg(self.R_CR, cmd)
self.wait_busy()
if(self.rd_reg(self.R_SR) & self.SR_RXACK):
raise Exception('No ACK upon write')
def read(self, last):
cmd = self.CR_RD
if(last):
cmd = cmd | self.CR_STO | self.CR_ACK
self.wr_reg(self.R_CR, cmd)
self.wait_busy()
return self.rd_reg(self.R_RXR)
def scan(self):
periph_addr = []
for i in range(0,128):
addr = i << 1
addr |= 1
self.wr_reg(self.R_TXR, addr)
self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR)
self.wait_busy()
if(not(self.rd_reg(self.R_SR) & self.SR_RXACK)):
periph_addr.append(i)
print("Device found at address: 0x%.2X") % i
self.wr_reg(self.R_TXR, 0)
self.wr_reg(self.R_CR, self.CR_STO | self.CR_WR)
self.wait_busy()
return periph_addr
##########################################
# Usage example
#gennum = rr.Gennum();
#i2c = COpenCoresI2C(gennum, 0x80000, 500);
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/onewire.py deleted 100644 → 0
View file @ 0fe848e3
#!/usr/bin/python
import sys
import rr
import time
class COpenCoresOneWire:
# OpenCores 1-wire registers description
R_CSR = 0x0
R_CDR = 0x4
CSR_DAT_MSK = (1<<0)
CSR_RST_MSK = (1<<1)
CSR_OVD_MSK = (1<<2)
CSR_CYC_MSK = (1<<3)
CSR_PWR_MSK = (1<<4)
CSR_IRQ_MSK = (1<<6)
CSR_IEN_MSK = (1<<7)
CSR_SEL_OFS = 8
CSR_SEL_MSK = (0xF<<8)
CSR_POWER_OFS = 16
CSR_POWER_MSK = (0xFFFF<<16)
CDR_NOR_MSK = (0xFFFF<<0)
CDR_OVD_OFS = 16
CDR_OVD_MSK = (0XFFFF<<16)
def wr_reg(self, addr, val):
self.bus.iwrite(0, self.base_addr + addr, 4, val)
def rd_reg(self,addr):
return self.bus.iread(0, self.base_addr + addr, 4)
# Function called during object creation
# bus = host bus (PCIe, VME, etc...)
# base_addr = 1-wire core base address
# clk_div_nor = clock divider normal operation, clk_div_nor = Fclk * 5E-6 - 1
# clk_div_ovd = clock divider overdrive operation, clk_div_ovd = Fclk * 1E-6 - 1
def __init__(self, bus, base_addr, clk_div_nor, clk_div_ovd):
self.bus = bus
self.base_addr = base_addr
#print('\n### Onewire class init ###')
#print("Clock divider (normal operation): %.4X") % clk_div_nor
#print("Clock divider (overdrive operation): %.4X") % clk_div_ovd
data = ((clk_div_nor & self.CDR_NOR_MSK) | ((clk_div_ovd<<self.CDR_OVD_OFS) & self.CDR_OVD_MSK))
#print('CRD register wr: %.8X') % data
self.wr_reg(self.R_CDR, data)
#print('CRD register rd: %.8X') % self.rd_reg(self.R_CDR)
# return: 1 -> presence pulse detected
# 0 -> no presence pulse detected
def reset(self, port):
data = ((port<<self.CSR_SEL_OFS) & self.CSR_SEL_MSK) | self.CSR_CYC_MSK | self.CSR_RST_MSK
#print('[onewire] Sending reset command, CSR: %.8X') % data
self.wr_reg(self.R_CSR, data)
while(self.rd_reg(self.R_CSR) & self.CSR_CYC_MSK):
pass
reg = self.rd_reg(self.R_CSR)
#print('[onewire] Reading CSR: %.8X') % reg
return ~reg & self.CSR_DAT_MSK
def slot(self, port, bit):
data = ((port<<self.CSR_SEL_OFS) & self.CSR_SEL_MSK) | self.CSR_CYC_MSK | (bit & self.CSR_DAT_MSK)
self.wr_reg(self.R_CSR, data)
while(self.rd_reg(self.R_CSR) & self.CSR_CYC_MSK):
pass
reg = self.rd_reg(self.R_CSR)
return reg & self.CSR_DAT_MSK
def read_bit(self, port):
return self.slot(port, 0x1)
def write_bit(self, port, bit):
return self.slot(port, bit)
def read_byte(self, port):
data = 0
for i in range(8):
data |= self.read_bit(port) << i
return data
def write_byte(self, port, byte):
data = 0
byte_old = byte
for i in range(8):
data |= self.write_bit(port, (byte & 0x1)) << i
byte >>= 1
if(byte_old == data):
return 0
else:
return -1
def write_block(self, port, block):
if(160 < len(block)):
return -1
data = []
for i in range(len(block)):
data.append(self.write_byte(port, block[i]))
return data
def read_block(self, port, length):
if(160 < length):
return -1
data = []
for i in range(length):
data.append(self.read_byte(port))
return data
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/termcolor.py deleted 100644 → 0
View file @ 0fe848e3
# coding: utf-8
# Copyright (c) 2008-2011 Volvox Development Team
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.
#
# Author: Konstantin Lepa <konstantin.lepa@gmail.com>
"""ANSII Color formatting for output in terminal."""
from __future__ import print_function
import os
__ALL__ = [ 'colored', 'cprint' ]
VERSION = (1, 1, 0)
ATTRIBUTES = dict(
list(zip([
'bold',
'dark',
'',
'underline',
'blink',
'',
'reverse',
'concealed'
],
list(range(1, 9))
))
)
del ATTRIBUTES['']
HIGHLIGHTS = dict(
list(zip([
'on_grey',
'on_red',
'on_green',
'on_yellow',
'on_blue',
'on_magenta',
'on_cyan',
'on_white'
],
list(range(40, 48))
))
)
COLORS = dict(
list(zip([
'grey',
'red',
'green',
'yellow',
'blue',
'magenta',
'cyan',
'white',
],
list(range(30, 38))
))
)
RESET = '\033[0m'
def colored(text, color=None, on_color=None, attrs=None):
"""Colorize text.
Available text colors:
red, green, yellow, blue, magenta, cyan, white.
Available text highlights:
on_red, on_green, on_yellow, on_blue, on_magenta, on_cyan, on_white.
Available attributes:
bold, dark, underline, blink, reverse, concealed.
Example:
colored('Hello, World!', 'red', 'on_grey', ['blue', 'blink'])
colored('Hello, World!', 'green')
"""
if os.getenv('ANSI_COLORS_DISABLED') is None:
fmt_str = '\033[%dm%s'
if color is not None:
text = fmt_str % (COLORS[color], text)
if on_color is not None:
text = fmt_str % (HIGHLIGHTS[on_color], text)
if attrs is not None:
for attr in attrs:
text = fmt_str % (ATTRIBUTES[attr], text)
text += RESET
return text
def cprint(text, color=None, on_color=None, attrs=None, **kwargs):
"""Print colorize text.
It accepts arguments of print function.
"""
print((colored(text, color, on_color, attrs)), **kwargs)
if __name__ == '__main__':
print('Current terminal type: %s' % os.getenv('TERM'))
print('Test basic colors:')
cprint('Grey color', 'grey')
cprint('Red color', 'red')
cprint('Green color', 'green')
cprint('Yellow color', 'yellow')
cprint('Blue color', 'blue')
cprint('Magenta color', 'magenta')
cprint('Cyan color', 'cyan')
cprint('White color', 'white')
print(('-' * 78))
print('Test highlights:')
cprint('On grey color', on_color='on_grey')
cprint('On red color', on_color='on_red')
cprint('On green color', on_color='on_green')
cprint('On yellow color', on_color='on_yellow')
cprint('On blue color', on_color='on_blue')
cprint('On magenta color', on_color='on_magenta')
cprint('On cyan color', on_color='on_cyan')
cprint('On white color', color='grey', on_color='on_white')
print('-' * 78)
print('Test attributes:')
cprint('Bold grey color', 'grey', attrs=['bold'])
cprint('Dark red color', 'red', attrs=['dark'])
cprint('Underline green color', 'green', attrs=['underline'])
cprint('Blink yellow color', 'yellow', attrs=['blink'])
cprint('Reversed blue color', 'blue', attrs=['reverse'])
cprint('Concealed Magenta color', 'magenta', attrs=['concealed'])
cprint('Bold underline reverse cyan color', 'cyan',
attrs=['bold', 'underline', 'reverse'])
cprint('Dark blink concealed white color', 'white',
attrs=['dark', 'blink', 'concealed'])
print(('-' * 78))
print('Test mixing:')
cprint('Underline red on grey color', 'red', 'on_grey',
['underline'])
cprint('Reversed green on red color', 'green', 'on_red', ['reverse'])
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test00.py
View file @ 4e895887
......@@ -90,7 +90,8 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "---------------------------- FMC TDC ---------------------------- "
print "-------------------- Mezzanine presence test --------------------"
print "-------------------- Mezzanine presence test --------------------\n"
print ("Test of the presence of the mezzanine, on the SPEC carrier.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
......@@ -115,9 +116,16 @@ def main (default_directory='.'):
bitstream_type = carrier_csr.rd_reg(CSR_BSTM_TYPE)
print('Bitstream type :%.8X') % bitstream_type
if(bitstream_type == 0xFFFFFFFF):
raise PtsError ("FATAL ERROR: Firmware not properly loaded")
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
raise PtsError ("FATAL ERROR: Wrong bitstream type loaded")
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
# Carrier Information
print "\n___________________________Carrier info__________________________\n"
......@@ -133,11 +141,15 @@ def main (default_directory='.'):
status = carrier_csr.rd_reg(CSR_STATUS)
if(status & STATUS_FMC_PRES):
print('Carrier csr status :%.8X') % status
print ("FATAL ERROR: Mezzanine appears missing.")
#raise PtsError ("FATAL ERROR: Mezzanine appears missing.")
msg = ("ERROR: Mezzanine appears missing.")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print("Mezzanine present OK\n")
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test01.py
View file @ 4e895887
......@@ -57,6 +57,7 @@
import sys
import time
import os
import math
# Add common modules location tp path
sys.path.append('../../../')
......@@ -103,8 +104,11 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "---------------------------- FMC TDC ---------------------------- "
print "--------------------- Mezzanine clocks test ---------------------"
print "----------------------------- FMC TDC -----------------------------"
print "--------------------------- Clocks test ---------------------------\n"
print ("Test of the PLL clocks: 31.25MHz FPGA_TDC_REF_CLK and 125MHz CLK125.\n"
"The test starts by configuring the PLL IC4. Then, to verify the clock\n"
"frequencies, there are dedicated counters implemented in the carrier FPGA.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
......@@ -130,11 +134,17 @@ def main (default_directory='.'):
# Check bitsteam type
bitstream_type = carrier_csr.rd_reg(CSR_BSTM_TYPE)
print('Bitstream type :%.8X') % bitstream_type
print('Bitstream type : 0x%.8X') % bitstream_type
if(bitstream_type == 0xFFFFFFFF):
raise PtsError ("FATAL ERROR: Firmware not properly loaded")
msg = ("FATAL ERROR: Firmware not properly loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
raise PtsError ("FATAL ERROR: Wrong bitstream type loaded")
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
# Carrier Information
print("PCB version : %d") % (PCB_VER_MASK & carrier_csr.rd_reg(CSR_TYPE_VER))
......@@ -147,42 +157,57 @@ def main (default_directory='.'):
# Check mezzanine presence flag
status = carrier_csr.rd_reg(CSR_STATUS)
if(status & STATUS_FMC_PRES):
print('Carrier csr status :%.8X') % status
print ("FATAL ERROR: Mezzanine appears missing.")
#raise PtsError ("FATAL ERROR: Mezzanine appears missing.")
print('Carrier csr status : 0x%.8X') % status
msg = ("FATAL ERROR: Mezzanine appears missing.")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print("Mezzanine present : OK")
time.sleep(3)
print "\n\n___________________________PLL status____________________________\n"
pll_status = carrier_csr.rd_reg(PLL_STATUS)
if pll_status == 1:
print ("PLL status OK\n")
else:
print ("ERROR: PLL IC4 status bit at zero %d\n")%carrier_csr.rd_reg(PLL_STATUS)
msg = ("ERROR: PLL IC4 status bit at zero.")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
print "\n_____________________________Clocks______________________________\n"
carrier_csr.wr_reg(EN_COUNTERS,0x1) # counters enabled
carrier_csr.wr_reg(RST_COUNTERS,0x1) # counters under reset
time.sleep(1)
carrier_csr.wr_reg(RST_COUNTERS,0x0) # counters reset release
time.sleep(2) # counters counting
clk_125M = carrier_csr.rd_reg(CLK_125M_COUNTER)/ (2*1e6)
clk_31M25 = carrier_csr.rd_reg(CLK_31M25_COUNTER)/ (2*1e6)
clk_31M25 = ((carrier_csr.rd_reg(CLK_31M25_COUNTER))/ (2*1e6))
clk_125M = ((carrier_csr.rd_reg(CLK_125M_COUNTER))/ (2*1e6))
# CLK125 125MHz clock evaluation
if (clk_125M > 131) or (clk_125M < 118): # 5% limits due to software inacuracies in time measurement (time.sleep(2))
raise PtsError("ERROR: PLL IC4 clock CLK125 measured frequency: %.2f MHz is out of accepted limits [118MHz..131MHz]") % (clk_125M)
else:
print("CLK125 measured frequency: %.2f MHz OK") % (clk_125M)
# FPGA_TDC_REF_CLK 31.25MHz clock evaluation
if (clk_31M25 > 32.8) or (clk_31M25 < 29.6): # 5% limits due to software inacuracies
raise PtsError("ERROR: PLL IC4 clock FPGA_TDC_REF_CLK measured frequency: %.2f MHz is out of accepted limits [29.6MHz..32.8MHz]") % (clk_31M25)
msg = (("ERROR: PLL IC4: FPGA_TDC_REF_CLK: measured frequency %.2f MHz is out of accepted limits [29.6MHz..32.8MHz]") % (clk_31M25))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print("FPGA_TDC_REF_CLK: measured frequency: %.2f MHz OK") % (clk_31M25)
# CLK125 125MHz clock evaluation
if (clk_125M > 131) or (clk_125M < 118): # 5% limits due to software inacuracies in time measurement (time.sleep(2))
msg = (("ERROR: PLL IC4: CLK125: measured frequency %.2f MHz is out of accepted limits [118MHz..131MHz]") % (clk_125M))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print("FPGA_TDC_REF_CLK measured frequency: %.2f MHz OK") % (clk_31M25)
print("CLK125: measured frequency: %.2f MHz OK") % (clk_125M)
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test02.py
View file @ 4e895887
......@@ -127,7 +127,10 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "------------------- Input channels to FPGA test -------------------"
print "------------------------- TDC_IN_FPGA test ------------------------\n"
print ("Test of the TDC_IN_FPGA[5..1] signals. The test is using the Fine Delay\n"
"board as pulse generator, sending pulses to each one of the TDC channels.\n"
"Dedicated counters in the carrier FPGA are counting the duration of the pulses.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
......@@ -151,10 +154,18 @@ def main (default_directory='.'):
# Check bitsteam type
bitstream_type = carrier_csr.rd_reg(CSR_BSTM_TYPE)
print('Bitstream type : 0x%.8X') % bitstream_type
if(bitstream_type == 0xFFFFFFFF):
raise PtsError ("FATAL ERROR: Firmware not properly loaded")
msg = ("FATAL ERROR: Firmware not properly loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
raise PtsError ("FATAL ERROR: Wrong bitstream type loaded")
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
print("PCB version : %d") % (PCB_VER_MASK & carrier_csr.rd_reg(CSR_TYPE_VER))
print("Carrier type : %d") % ((CARRIER_TYPE_MASK & carrier_csr.rd_reg(CSR_TYPE_VER))>>16)
......@@ -163,12 +174,16 @@ def main (default_directory='.'):
print("Status : 0x%.8X") % (carrier_csr.rd_reg(CSR_STATUS))
print("Control : 0x%.8X") % (carrier_csr.rd_reg(CSR_CTRL))
# Check mezzanine presence flag
status = carrier_csr.rd_reg(CSR_STATUS)
if(status & STATUS_FMC_PRES):
print('Carrier csr status :%.8X') % status
raise PtsError ("FATAL ERROR: Mezzanine appears missing.")
print('Carrier csr status : 0x%.8X') % status
msg = ("FATAL ERROR: Mezzanine appears missing.")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print("Mezzanine present OK")
print("Mezzanine present : OK")
# Enable input logic
# Channels enable activated
......@@ -180,10 +195,13 @@ def main (default_directory='.'):
counter_error = 0
for i in CHANNEL_COUNTERS:
if (carrier_csr.rd_reg(i) != 0):
print("ERROR: Unexpected failure of FPGA counter 0x%.2X; received 0x%.8X, expected 0x00000000")%(i, carrier_csr.rd_reg(i))
msg = (("ERROR: Unexpected failure of FPGA counter 0x%.2X; received 0x%.8X, expected 0x00000000")%(i, carrier_csr.rd_reg(i)))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
counter_error = 1
if (counter_error == 0):
print("Counters initialised OK")
print("Counters init : OK")
#-----> Fine Delay
print "\n___________________________Fine Delay____________________________"
......@@ -204,7 +222,13 @@ def main (default_directory='.'):
print "Firmware loaded!"
# Fine Delay object declaration
fdelay = fdelay_lib.FineDelay(spec.get_fd())
try:
fdelay = fdelay_lib.FineDelay(spec.get_fd())
except:
msg = ("ERROR: Fine Delay board Initiliazation failed")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Set UTC and Coarse time in the Fine Delay
fdelay.set_time(0, 0)
......@@ -223,6 +247,8 @@ def main (default_directory='.'):
fdelay.conf_pulsegen(3, enable, t_start_utc, t_start_coarse, width, delta, count)
fdelay.conf_pulsegen(4, enable, t_start_utc, t_start_coarse, width, delta, count)
print ("\nFine delay sending one pulse per channel of 1ms width..")
#-----> TDC
time.sleep(2)
# Bind SPEC object to FMC TDC card
......@@ -233,15 +259,20 @@ def main (default_directory='.'):
# Read counters
for i in CHANNEL_COUNTERS:
if (carrier_csr.rd_reg(i) == 0):
print("ERROR: TDC_IN_FPGA%d: No pulse arrived")%(CHANNEL_COUNTERS.index(i)+1)
msg = (("ERROR: TDC_IN_FPGA%d: No pulse arrived")%(CHANNEL_COUNTERS.index(i)+1))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
elif (carrier_csr.rd_reg(i) > 100500) or (carrier_csr.rd_reg(i) < 95000): # 0.5% acceptance limit
print("ERROR: TDC_IN_FPGA%d: Pulse width %.5f ms is outside accepted limits [1.005 ms .. 0.995 ms]")%(CHANNEL_COUNTERS.index(i)+1, carrier_csr.rd_reg(i)/1e5)
msg = (("ERROR: TDC_IN_FPGA%d: Pulse width %.5f ms is outside accepted limits [1.005 ms .. 0.995 ms]")%(CHANNEL_COUNTERS.index(i)+1, carrier_csr.rd_reg(i)/1e5))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print("TDC_IN_FPGA%d: Pulse width %.5f ms OK")%(CHANNEL_COUNTERS.index(i)+1, carrier_csr.rd_reg(i)/1e5)
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test03.py
View file @ 4e895887
......@@ -9,7 +9,7 @@
##-------------------------------------------------------------------------------------------------
## |
## TDC_IN_FPGA_ENABLE test |
## TDC ENABLE_INPUTS test with FPGA |
## |
##-------------------------------------------------------------------------------------------------
## |
......@@ -129,7 +129,13 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "-------------- Enable of Input channels to FPGA test --------------"
print "--------------------- TDC_IN_FPGA disable test --------------------\n"
print ("Test of the EN_INPUTS signal. The test is using the Fine Delay board\n"
"as pulse generator, sending pulses to each one of the TDC channels.\n"
"Dedicated counters in the carrier FPGA are counting the duration of the pulses.\n"
"When the EN_INPUTS is active, pulses should be arriving to all the channels;\n"
"when the EN_INPUTS is disabled no pulse should arrive.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
......@@ -154,9 +160,15 @@ def main (default_directory='.'):
# Check bitsteam type
bitstream_type = carrier_csr.rd_reg(CSR_BSTM_TYPE)
if(bitstream_type == 0xFFFFFFFF):
raise PtsError ("FATAL ERROR: Firmware not properly loaded")
msg = ("FATAL ERROR: Firmware not properly loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
raise PtsError ("FATAL ERROR: Wrong bitstream type loaded")
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
print("PCB version : %d") % (PCB_VER_MASK & carrier_csr.rd_reg(CSR_TYPE_VER))
print("Carrier type : %d") % ((CARRIER_TYPE_MASK & carrier_csr.rd_reg(CSR_TYPE_VER))>>16)
......@@ -167,19 +179,24 @@ def main (default_directory='.'):
status = carrier_csr.rd_reg(CSR_STATUS)
if(status & STATUS_FMC_PRES):
print('Carrier csr status :%.8X') % status
raise PtsError ("FATAL ERROR: Mezzanine appears missing.")
msg = ('FATAL ERROR: Mezzanine appears missing.')
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print("Mezzanine present OK")
print("Mezzanine present : OK")
# Check FPGA counters
counter_error = 0
for i in CHANNEL_COUNTERS:
if (carrier_csr.rd_reg(i) != 0):
print("ERROR: Unexpected failure of FPGA counter 0x%.2X; received 0x%.8X, expected 0x00000000")%(i, carrier_csr.rd_reg(i))
msg = (("ERROR: Unexpected failure of FPGA counter 0x%.2X; received 0x%.8X, expected 0x00000000")%(i, carrier_csr.rd_reg(i)))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
counter_error = 1
if (counter_error == 0):
print("Counters initialised OK")
print("Counters init : OK")
################################## Input logic Disabled ##################################
......@@ -204,7 +221,13 @@ def main (default_directory='.'):
print "Firmware loaded!"
# Fine Delay object declaration
fdelay = fdelay_lib.FineDelay(spec.get_fd())
try:
fdelay = fdelay_lib.FineDelay(spec.get_fd())
except:
msg = ("ERROR: Fine Delay board Initiliazation failed")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Set UTC and Coarse time in the Fine Delay
fdelay.set_time(0, 0)
......@@ -223,6 +246,7 @@ def main (default_directory='.'):
fdelay.conf_pulsegen(3, enable, t_start_utc, t_start_coarse, width, delta, count)
fdelay.conf_pulsegen(4, enable, t_start_utc, t_start_coarse, width, delta, count)
print ("\nFine delay sending one pulse per channel of 1ms width..")
#-----> TDC
time.sleep(2)
......@@ -234,9 +258,12 @@ def main (default_directory='.'):
# Read counters
for i in CHANNEL_COUNTERS:
if (carrier_csr.rd_reg(i) != 0):
print("ERROR: ENABLE_INPUTS signal: Disable of input TDC_IN_FPGA%d failed; pulse of %.5f ms arrived")%(CHANNEL_COUNTERS.index(i)+1,carrier_csr.rd_reg(i)/1e5)
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; pulse of %.5f ms arrived")%(CHANNEL_COUNTERS.index(i)+1,carrier_csr.rd_reg(i)/1e5))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print("ENABLE_INPUTS signal: Disable of input TDC_IN_FPGA%d OK") %(CHANNEL_COUNTERS.index(i)+1)
print("ENABLE_INPUTS disabled: TDC_IN_FPGA%d OK") %(CHANNEL_COUNTERS.index(i)+1)
################################## Input logic Enabled ##################################
......@@ -264,11 +291,14 @@ def main (default_directory='.'):
# Read counters
for i in CHANNEL_COUNTERS:
if (carrier_csr.rd_reg(i) != 0):
print("ENABLE_INPUTS signal: Enable of input TDC_IN_FPGA%d OK")%(CHANNEL_COUNTERS.index(i)+1)
print("ENABLE_INPUTS enabled: TDC_IN_FPGA%d OK")%(CHANNEL_COUNTERS.index(i)+1)
else:
print("ERROR: ENABLE_INPUTS signal: No pulse arrived to TDC_IN_FPGA%d")%(CHANNEL_COUNTERS.index(i)+1)
msg = (("ERROR: ENABLE_INPUTS enabled: TDC_IN_FPGA%d: No pulse arrived")%(CHANNEL_COUNTERS.index(i)+1))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test04.py
View file @ 4e895887
......@@ -83,7 +83,9 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- TDC PTS -----------------------------"
print "--------------------------- 1-Wire test ---------------------------"
print "--------------------- 1-Wire TEMPID IC14 test ---------------------\n"
print ("Test of the One-Wire thermometer with unique ID chip IC14. The test\n"
"reads the serial unique ID and takes a temperature measurement.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
......@@ -107,28 +109,60 @@ def main (default_directory='.'):
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# Check bitsteam type
bitstream_type = tdc.read_bitstream_type()
if(bitstream_type == 0xFFFFFFFF):
msg = ("FATAL ERROR: No access to TDC core")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print('Access to TDC core OK')
# Read unique ID and print to log
print "\n____________________________Unique ID____________________________\n"
unique_id = tdc.mezz_get_unique_id()
try:
unique_id = tdc.mezz_get_unique_id()
except:
msg = ("ERROR: TEMPID IC14: Cannot access the device")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
if(unique_id == -1):
raise PtsError("ERROR: TEMPID IC14: Cannot access the device")
msg = ("ERROR: TEMPID IC14: Cannot access the device")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print('TEMPID IC14: Unique ID: %.12X OK') % unique_id
print('TEMPID IC14: Unique ID: 0x%.12X OK') % unique_id
if((unique_id & 0xFF) != FAMILY_CODE):
family_code = unique_id & 0xFF
print('TEMPID IC14: Family Code: 0x%.8X') % family_code
raise PtsError ("ERROR: TEMPID IC14: Wrong Family Code:0x.2X is different than the expected:0x%.2X" % family_code,FAMILY_CODE)
msg = (("ERROR: TEMPID IC14: Wrong Family Code: 0x%.2X is different than the expected: 0x%.2X") %(family_code,FAMILY_CODE))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Read temperature and print to log
print "\n___________________________Temperature___________________________\n"
temp = tdc.mezz_get_temp()
if (temp > 100 or temp < 20):
raise PtsError ("ERROR: TEMPID IC14: Temperature measurement %3.3f°C is out of the accepted limits [20°C .. 100°C] " % temp)
if (temp > 60 or temp < 20):
msg = ("ERROR: TEMPID IC14: Temperature measurement %3.3f°C is out of the accepted limits [20°C .. 100°C] " % temp)
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print('TEMPID IC14: Temperature: %3.2f°C OK') % temp
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test05.py
View file @ 4e895887
......@@ -13,7 +13,7 @@
## |
##-------------------------------------------------------------------------------------------------
## |
## Description Testing of the "EEPROM 24AA64" chip on the TDC board (IC10). The firmware loaded |
## Description Testing of the "EEPROM 24AA64" chip on the TDC board (IC5). The firmware loaded |
## to the FPGA on the carrier implements the interface for the communication between |
## the PCIe bus and the I2C of the EEPROM; this interface is an I2C WISHBONE master, |
## running with a system clock of 50MHz. |
......@@ -63,7 +63,6 @@ import rr
# Import specific modules
import fmc_tdc
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
......@@ -82,7 +81,9 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- TDC PTS -----------------------------"
print "--------------------------- EEPROM test ---------------------------"
print "------------------------- EEPROM IC5 test -------------------------\n"
print ("Testing of the the EEPROM IC5. The test checks the communication\n"
"with the EEPROM, writes data to it and then reads them back.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
......@@ -105,36 +106,71 @@ def main (default_directory='.'):
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# Check bitsteam type
bitstream_type = tdc.read_bitstream_type()
if(bitstream_type == 0xFFFFFFFF):
msg = ("FATAL ERROR: No access to TDC core")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print('Access to TDC core OK')
print "\n__________________________EEPROM IC10 test_______________________\n"
# Scan FMC I2C bus
periph_addr = tdc.mezz_i2c_scan()
try:
periph_addr = tdc.mezz_i2c_scan()
except:
msg = ("ERROR: EEPROM IC5: No peripheral detected")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Check that the EEPROM is detected on the I2C bus
if(0 == len(periph_addr)):
raise PtsError("ERROR: EEPROM IC10: No peripheral detected on system management I2C bus")
msg = ("ERROR: EEPROM IC5: No peripheral detected on system management I2C bus")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
if(1 != len(periph_addr)):
raise PtsError("ERROR: EEPROM IC10: Signal integrity problem detected on system management I2C bus, %d devices detected instead of 1"%(len(periph_addr)))
msg = ("ERROR: EEPROM IC5: Signal integrity problem detected on system management I2C bus, %d devices detected instead of 1"%(len(periph_addr)))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
if(EEPROM_ADDR != periph_addr[0]):
raise PtsError("ERROR: EEPROM IC10: Wrong device mounted on system management I2C bus, address is:0x%.2X expected:0x%.2X"%(periph_addr[0],EEPROM_ADDR))
msg = ("ERROR: EEPROM IC5: Wrong device mounted on system management I2C bus, address is:0x%.2X expected:0x%.2X"%(periph_addr[0],EEPROM_ADDR))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Write, read back and compare
addr = 0x20
wr_data = [0x55, 0xAA, 0x00, 0xFF]
rd_data = []
print('EEPROM IC10: Writting data at EEPROM address 0x%.2X: ')%addr,
print('EEPROM IC5: Writting data at EEPROM address 0x%.2X: ')%addr,
print wr_data
tdc.mezz_i2c_eeprom_write(addr, wr_data)
time.sleep(0.1)
print('EEPROM IC10: Reading data from EEPROM address 0x%.2X:')%addr,
print('EEPROM IC5: Reading data from EEPROM address 0x%.2X:')%addr,
rd_data = tdc.mezz_i2c_eeprom_read(addr, len(wr_data))
print rd_data
if(rd_data != wr_data):
raise PtsError("ERROR: EEPROM IC10: Data reading/ writing failed")
msg = ("ERROR: EEPROM IC5: Data reading/ writing failed")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print('\nEEPROM IC10: Data comparison OK')
print('\nEEPROM IC5: Data comparison OK')
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test06.py
View file @ 4e895887
......@@ -14,7 +14,7 @@
##-------------------------------------------------------------------------------------------------
## |
## Description Testing of the communication with the ACAM chip IC8 of the TDC board. |
## The test is checking if the status of all the ACAM registers is as expected. |
## The test configures the ACAM chip and then checks the status of all its registers.|
## In detal these lines are tested: TDC_D[27..0], TDC_ADR[3..0], RESET_N, TDC_WRN, |
## TDC_RDN, TDC_CSN, TDC_OEN |
## |
......@@ -65,7 +65,6 @@ import csr
import fmc_tdc
##-------------------------------------------------------------------------------------------------
## Main --
##-------------------------------------------------------------------------------------------------
......@@ -74,7 +73,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_pllstatus.bit'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
# SPEC object declaration
......@@ -83,7 +82,10 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "---------------------- ACAM communication test --------------------"
print "-------------------- ACAM IC8 communication test ------------------\n"
print ("Testing of the communication with the ACAM chip IC8."
" The test\nconfigures the ACAM and then checks the status of its registers.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
......@@ -106,6 +108,21 @@ def main (default_directory='.'):
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# Check bitsteam type
bitstream_type = tdc.read_bitstream_type()
if(bitstream_type == 0xFFFFFFFF):
msg = ("FATAL ERROR: No access to TDC core")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print('Access to TDC core OK')
# TDC configuration
print "\n__________________________Configuration__________________________\n"
tdc.config_acam()
......@@ -118,7 +135,10 @@ def main (default_directory='.'):
if acam_status_test == 0:
print "ACAM IC8: Status register OK"
else:
raise PtsError ("ERROR: ACAM IC8: No communication")
msg = ("ERROR: ACAM IC8: No communication")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Check other ACAM configuration regs
print "\n______________________ACAM other registers________________________\n"
......@@ -129,9 +149,12 @@ def main (default_directory='.'):
if (acam_readback_regs[i] == tdc.ACAM_READBACK_REGS[i]):
print "ACAM IC8: reg 0x%02X: 0x%08X OK"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i])
else:
print "ERROR! ACAM IC8: Configuration registers failure; reg 0x%02X: received 0x%08X, expected 0x%08X"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i], tdc.ACAM_READBACK_REGS[i])
msg = ("ERROR: ACAM IC8: Configuration registers failure; reg 0x%02X: received 0x%08X, expected 0x%08X"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i], tdc.ACAM_READBACK_REGS[i]))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
os.close(spec.fd)
print "\n-----------------------------------------------------------------\n\n\n"
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test08.py
View file @ 4e895887
......@@ -9,7 +9,7 @@
##-------------------------------------------------------------------------------------------------
## |
## TDC Channels test |
## TDC ENABLE_INPUTS test with ACAM |
## |
##-------------------------------------------------------------------------------------------------
## |
......@@ -96,7 +96,12 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "-------------------------- Channels test --------------------------"
print "----------------- TDC_STOP channels disable test ------------------\n"
print ("Test of EN_INPUTS signal. The test is using the Fine Delay board as\n"
"pulse generator, sending pulses to each one of the TDC channels.\n"
"The test configures the ACAM chip and then retrieves the generated timestamps.\n"
"When the EN_INPUTS is disabled no pulse should be retrieved.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
......@@ -119,41 +124,58 @@ def main (default_directory='.'):
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# TDC configuration
# Check bitsteam type
bitstream_type = tdc.read_bitstream_type()
if(bitstream_type == 0xFFFFFFFF):
msg = ("FATAL ERROR: No access to TDC core")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print('Access to TDC core OK')
# Configure ACAM and TDC core registers
print "\n__________________________Configuration__________________________\n"
tdc.config_acam()
time.sleep(1)
# Check ACAM
print "\n______________________________ACAM________________________________\n"
tdc.reset_acam()
acam_status_test = tdc.read_acam_status()-0xC4000800
if acam_status_test == 0:
print "ACAM IC8: Status register OK"
else:
raise PtsError ("ERROR: ACAM IC8: No communication")
msg = ("ERROR: ACAM IC8: No communication")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
acam_readback_regs = []
acam_readback_regs = tdc.readback_acam_config()
for i in range(len(tdc.ACAM_READBACK_REGS)):
if (acam_readback_regs[i] == tdc.ACAM_READBACK_REGS[i]):
print "ACAM IC8: reg 0x%02X: 0x%08X OK"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i])
else:
print "ERROR! ACAM IC8: Configuration registers failure; reg 0x%02X: received 0x%08X, expected 0x%08X"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i], tdc.ACAM_READBACK_REGS[i])
msg = ("ERROR: ACAM IC8: Configuration registers failure; reg 0x%2X: received 0x%8X, expected 0x%8X"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i], tdc.ACAM_READBACK_REGS[i]))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Disable the 5 TDC channels
tdc.disable_channels()
for ch in range(1,FMC_TDC_CHANNEL_NB+1):
tdc.channel_term(ch, 1)
# Enable timestamps aquisition
# Enable timestamps aquisition (TDC_START_FPGA pulse sent at this step)
tdc.start_acq()
#-----> Fine Delay
# Bind SPEC object to FMC Fine Delay card
print "\n___________________________Fine Delay____________________________"
print "\nFine Delay initializations.."
# Bind SPEC object to FMC Fine Delay card
print "Fine Delay address to parse %s"%(FMC_DELAY_ADDR)
for name, value in spec.parse_addr(FMC_DELAY_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
......@@ -169,7 +191,13 @@ def main (default_directory='.'):
print "Firmware loaded!"
# Fine Delay object declaration
fdelay = fdelay_lib.FineDelay(spec.get_fd())
try:
fdelay = fdelay_lib.FineDelay(spec.get_fd())
except:
msg = ("ERROR: Fine Delay board Initiliazation failed")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Set UTC and Coarse time in the Fine Delay
fdelay.set_time(0, 0)
......@@ -186,7 +214,7 @@ def main (default_directory='.'):
for i in range(4): # one iteration per channel;
# channels 4 and 5 receive pulses at the same time
time.sleep(0.5) # somehow needed
time.sleep(0.5) # needed between iterations
#-----> Fine Delay
# Bind SPEC object to FMC Fine Delay card
......@@ -201,10 +229,11 @@ def main (default_directory='.'):
spec.bind(FMC_TDC_ADDR)
# Check if timestamps arrived
print "\n___________________Channel %d disable test___________________\n" %channel
print "\n___________________TDC_IN_FPGA%d disable test___________________\n" %channel
time.sleep(1.5)
print "The time now is : %s" %datetime.now()
print "The temperature now is : %3.3f°C" %tdc.mezz_get_temp()
print "Fine Delay sent : %d pulses of 200ns period"%(count)
print "TDC Write pointer : %d"%(tdc.get_pointer())
timestamps, data = tdc.get_timestamps(0)
......@@ -214,13 +243,15 @@ def main (default_directory='.'):
for m in range(len(timestamps)):
if ((timestamps[m][2] == 1) and (timestamps[m][1] == i)):
timestamp_arrived = timestamp_arrived+1
if (timestamp_arrived != 0):
raise PtsError("ERROR: Channel disabling failed; %d pulses sent, %d pulses received") %(count, timestamp_arrived)
#print("ERROR: Channel disabling failed; %d pulses sent, %d pulses received") %(count, timestamp_arrived)
if (timestamp_arrived != 0):
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; %d pulses sent, %d pulses received") %(channel, count, timestamp_arrived))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print("Channel disabling : OK! no pulses arrived")
else:
else: # channels 4 and 5 are receiving timestamps at the same time
timestamp_arrived_ch4 = 0
timestamp_arrived_ch5 = 0
......@@ -229,21 +260,25 @@ def main (default_directory='.'):
timestamp_arrived_ch4 = timestamp_arrived_ch4+1
elif ((timestamps[m][2] == 1) and (timestamps[m][1] == 4)):
timestamp_arrived_ch5 = timestamp_arrived_ch5+1
if (timestamp_arrived_ch4 != 0):
raise PtsError("ERROR: Channel disabling failed; %d pulses sent, %d pulses received") %(count, timestamp_arrived_ch4)
#print("ERROR: Channel disabling failed; %d pulses sent, %d pulses received") %(count, timestamp_arrived_ch4)
if (timestamp_arrived_ch4 != 0):
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; %d pulses sent, %d pulses received") %(channel, count, timestamp_arrived_ch4))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print("Channel disabling : OK! no pulses arrived")
if (timestamp_arrived_ch5 != 0):
print "\n___________________Channel 5 disable test____________________\n"
raise PtsError("ERROR: Channel disabling failed; %d pulses sent, %d pulses received") %(count, timestamp_arrived_ch5)
#print("ERROR: Channel disabling failed; %d pulses sent, %d pulses received") %(count, timestamp_arrived_ch5)
print "\n___________________TDC_IN_FPGA5 disable test____________________\n"
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; %d pulses sent, %d pulses received") %(count, timestamp_arrived_ch5))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print "\n___________________Channel 5 disable test____________________\n"
print "\n___________________TDC_IN_FPGA5 disable test____________________\n"
print("Channel disabling : OK! no pulses arrived")
os.close(spec.fd)
print "\n-----------------------------------------------------------------\n\n\n"
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test09.py
View file @ 4e895887
......@@ -9,7 +9,7 @@
##-------------------------------------------------------------------------------------------------
## |
## TDC Channels test |
## TDC_START_DIS, TDC_STOP_DIS test |
## |
##-------------------------------------------------------------------------------------------------
## |
......@@ -94,7 +94,13 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "-------------------------- Channels test --------------------------"
print "------------------ TDC_START_DIS, TDC_STOP_DIS test ---------------\n"
print ("Testing of the TDC_START_DIS and TDC_STOP_DIS signals;\n"
"upon activation, no timestamps should be registered by the ACAM.\n"
"The test configures the ACAM and is using thr Fine Delay as pulse\n"
"generator sending pulses to all the TDC channels; if there are\n"
"registered pulses one or both signals are faulty.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
......@@ -118,34 +124,55 @@ def main (default_directory='.'):
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# TDC configuration
# Check bitsteam type
bitstream_type = tdc.read_bitstream_type()
if(bitstream_type == 0xFFFFFFFF):
msg = ("FATAL ERROR: No access to TDC core")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print('Access to TDC core OK')
# Configure ACAM and TDC core registers
print "\n__________________________Configuration__________________________\n"
tdc.config_acam()
time.sleep(1)
# Check ACAM status
print "\n______________________________ACAM________________________________\n"
tdc.reset_acam()
acam_status_test = tdc.read_acam_status()-0xC4000800
if acam_status_test == 0:
print "ACAM status register OK!"
else:
raise PtsError ("ERROR: ACAM IC8: No communication")
acam_regs = []
acam_regs=tdc.readback_acam_config()
if (acam_regs == [0xC1F0FC81, 0xC0000000, 0xC0000E02, 0xC0000000, 0xC200000F, 0xC00007D0, 0xC00000FC, 0xC0001FEA, 0x00000000, 0x00000000, 0x00000000, 0xC3000000, 0xC4000800, 0xC0000000]):
print("\nCommunication with ACAM and ACAM registers OK!")
print "ACAM IC8: Status register OK"
else:
raise PtsError("\nERROR: ACAM IC8: Configuration registers failure")
msg = ("ERROR: ACAM IC8: No communication")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
acam_readback_regs = []
acam_readback_regs = tdc.readback_acam_config()
for i in range(len(tdc.ACAM_READBACK_REGS)):
if (acam_readback_regs[i] == tdc.ACAM_READBACK_REGS[i]):
print "ACAM IC8: reg 0x%02X: 0x%08X OK"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i])
else:
msg = ("ERROR: ACAM IC8: Configuration registers failure; reg 0x%2X: received 0x%8X, expected 0x%8X"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i], tdc.ACAM_READBACK_REGS[i]))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Enable the 5 TDC channels
# Enable terminations of channels 1,2,3,4
# channels 4 and 5 are receiving the same Fine Delay pulse; only channel 5 termination activated
tdc.enable_channels()
for ch in range(1,FMC_TDC_CHANNEL_NB+1):
tdc.channel_term(ch, 1)
tdc.channel_term(1, 1)
tdc.channel_term(2, 1)
tdc.channel_term(3, 1)
tdc.channel_term(5, 1)
# Enable timestamps aquisition
# Enable timestamps aquisition (TDC_START_FPGA pulse sent at this step)
tdc.start_acq()
# StartDis, StopDis
......@@ -154,9 +181,9 @@ def main (default_directory='.'):
#-----> Fine Delay
# Bind SPEC object to FMC Fine Delay card
print "\n___________________________Fine Delay____________________________"
print "\nFine Delay initializations.."
# Bind SPEC object to FMC Fine Delay card
print "Fine Delay address to parse %s"%(FMC_DELAY_ADDR)
for name, value in spec.parse_addr(FMC_DELAY_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
......@@ -172,7 +199,13 @@ def main (default_directory='.'):
print "Firmware loaded!"
# Fine Delay object declaration
fdelay = fdelay_lib.FineDelay(spec.get_fd())
try:
fdelay = fdelay_lib.FineDelay(spec.get_fd())
except:
msg = ("ERROR: Fine Delay board Initiliazation failed")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Set UTC and Coarse time in the Fine Delay
fdelay.set_time(0, 0)
......@@ -186,24 +219,16 @@ def main (default_directory='.'):
delta = 200000 # rising edges every 200 ns
count = 6
all_measurs = []
avg = []
print "\n____________________Fine Delay sending pulses____________________\n"
for i in range(4): # one iteration per channel;
# channels 4 and 5 receive pulses at the same time
#-----> Fine Delay
time.sleep(0.5) # somehow needed
time.sleep(0.5) # needed between iterations
channel = i+1
t_start_utc = fdelay.get_time().utc+1 # starting in 1 sec
fdelay.conf_pulsegen(channel, enable, t_start_utc, t_start_coarse, width, delta, count)
if (i < 3):
print "%d pulses sent to Channel %d" %(count,channel)
else:
print "%d pulses sent to Channel %d" %(count,channel)
print "%d pulses sent to Channel 5" %(count)
#-----> TDC
# Bind SPEC object to FMC TDC card
......@@ -214,13 +239,18 @@ def main (default_directory='.'):
print "\n___________________ACAM StartDis, StopDis test___________________\n"
print "The time now is : %s" %datetime.now()
print "The temperature now is : %3.3f°C" %tdc.mezz_get_temp()
print "Fine Delay sent : 6 pulses of 200ns period to each TDC channel"
print "TDC Write pointer : %d"%(tdc.get_pointer())
if (tdc.get_pointer() == 0):
print ("ACAM StartDis and StopDis signals : OK!")
else:
print ("ERROR: ACAM IC8: StartDis and/or StopDis: pulses registered, despite disabling;")
print (" %d pulses sent, %d timestamps registered") %(count*FMC_TDC_CHANNEL_NB,(tdc.get_pointer()/32))
msg = (("ERROR: ACAM IC8: StartDis and/or StopDis: pulses registered, despite disabling;\n"
" in total %d pulses sent, %d timestamps registered") %(count*FMC_TDC_CHANNEL_NB,(tdc.get_pointer()/32)))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
os.close(spec.fd)
print "\n-----------------------------------------------------------------\n\n\n"
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test10.py
View file @ 4e895887
......@@ -71,7 +71,7 @@ import csr
# Import specific modules
import fmc_tdc
sys.path.append('../../../../fmc_delay/software/python/')
sys.path.append('../../../common/fmc_delay/software/python/')
import fdelay_lib
......@@ -82,10 +82,11 @@ import fdelay_lib
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/tdc_allothertests.bit'#tdc_fpga_in.bit'#tdc_acam_misc.bit'#tdc_fpga_in.bit'tdc_pllstatus.bit'#eva_tdc_for_v2.bit' #evas_tdc_irq8.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM = '../firmwares/fmc_delay_spec.bin'
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_fpga_in.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FMC_TDC_CHANNEL_NB = 5
ERRFLAG_BASE = 0xC0000
......@@ -100,7 +101,14 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "-------------------------- Channels test --------------------------"
print "-------------------- TDC ACAM ERROR FLAG test ---------------------\n"
print ("Testing of the ACAM TDC_ERR signal. The ERR flag is configured to\n"
"get activated upon overflow on the interface FIFOs; an overflow\n"
"occurs when the timestamps arrival rate is higher than 31.25MHz.\n"
"The test is using the Fine Delay as pulse generator sending pulses\n"
"to the all the TDC channels with a total rate of 100MHz and is\n"
"monitiring the TDC_ERR signal.\n")
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
......@@ -111,57 +119,86 @@ def main (default_directory='.'):
# Load FMC TDC firmware
print "\n_________________________Initialisations_________________________\n"
print "Loading FMC TDC firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
firmware_loader = os.path.join(default_directory, FPGA_LOADER_PATH)
bitstream = os.path.join(default_directory, FMC_TDC_BITSTREAM_PATH)
os.system(firmware_loader + ' ' + bitstream)
time.sleep(1)
firmware_loader = os.path.join(default_directory, FPGA_LOADER_PATH)
bitstream = os.path.join(default_directory, FMC_TDC_BITSTREAM_PATH)
os.system(firmware_loader + ' ' + bitstream)
time.sleep(1)
print "Firmware loaded!"
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# TDC configuration
# Check bitsteam type
bitstream_type = tdc.read_bitstream_type()
if(bitstream_type == 0xFFFFFFFF):
msg = ("FATAL ERROR: No access to TDC core")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
if(bitstream_type != 0x1):
msg = ("FATAL ERROR: Wrong bitstream type loaded")
os.close(spec.fd)
print (msg)
raise PtsCritical (msg)
else:
print('Access to TDC core OK')
# Configure ACAM and TDC core registers
print "\n__________________________Configuration__________________________\n"
tdc.config_acam()
time.sleep(1)
# Check ACAM status
print "\n______________________________ACAM________________________________\n"
tdc.reset_acam()
acam_status_test = tdc.read_acam_status()-0xC4000800
if acam_status_test == 0:
print "ACAM IC8: Status register OK"
else:
raise PtsError ("ERROR: ACAM IC8: No communication")
msg = ("ERROR: ACAM IC8: No communication")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
acam_readback_regs = []
acam_readback_regs = tdc.readback_acam_config()
for i in range(len(tdc.ACAM_READBACK_REGS)):
if (acam_readback_regs[i] == tdc.ACAM_READBACK_REGS[i]):
print "ACAM IC8: reg 0x%02X: 0x%08X OK"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i])
else:
print "ERROR! ACAM IC8: Configuration registers failure; reg 0x%02X: received 0x%08X, expected 0x%08X"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i], tdc.ACAM_READBACK_REGS[i])
msg = ("ERROR: ACAM IC8: Configuration registers failure; reg 0x%2X: received 0x%8X, expected 0x%8X"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i], tdc.ACAM_READBACK_REGS[i]))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Enable terminations of channels 1,2,3,4
# channels 4 and 5 are receiving the same Fine Delay pulse; only channel 4 termination activated
tdc.enable_channels()
for ch in range(1,FMC_TDC_CHANNEL_NB):
tdc.channel_term(ch, 1)
tdc.channel_term(1, 1)
tdc.channel_term(2, 1)
tdc.channel_term(3, 1)
tdc.channel_term(5, 1)
# Enable timestamps aquisition
# Enable timestamps aquisition (TDC_START_FPGA pulse sent at this step)
tdc.start_acq()
acam_errflag_init = ERRFLAG_BASE.rd_reg(ERRFLAG_REG)
print "ACAM Error Flag : 0x%08X" %(acam_errflag_init)
# Check Effflag register
ERRFLAG_BASE.wr_reg(RST_ERRFLAG_REG,0x1)
ERRFLAG_BASE.wr_reg(RST_ERRFLAG_REG,0x0)
acam_errflag_init = ERRFLAG_BASE.rd_reg(ERRFLAG_REG)
print "ACAM Error Flag : 0x%08X" %(acam_errflag_init)
if acam_errflag_init != 0:
msg = ("ACAM Error Flag initial value: 0x%08X" %(acam_errflag_init))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print ("ACAM Error Flag initial value: 0x%08X OK" %(acam_errflag_init))
#-----> Fine Delay
# Bind SPEC object to FMC Fine Delay card
print "\n___________________________Fine Delay____________________________"
print "\nFine Delay initializations.."
# Bind SPEC object to FMC Fine Delay card
print "Fine Delay address to parse %s"%(FMC_DELAY_ADDR)
for name, value in spec.parse_addr(FMC_DELAY_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
......@@ -170,12 +207,20 @@ def main (default_directory='.'):
# Load FMC Fine Delay firmware
print "\nLoading FMC Fine Delay firmware...",
sys.stdout.flush()
spec.load_firmware(FMC_DELAY_BITSTREAM)
time.sleep(2)
firmware_loader = os.path.join(default_directory, FPGA_LOADER_PATH)
bitstream = os.path.join(default_directory, FMC_DELAY_BITSTREAM_PATH)
os.system(firmware_loader + ' ' + bitstream)
time.sleep(1)
print "Firmware loaded!"
# Fine Delay object declaration
fdelay = fdelay_lib.FineDelay(spec.get_fd())
try:
fdelay = fdelay_lib.FineDelay(spec.get_fd())
except:
msg = ("ERROR: Fine Delay board Initiliazation failed")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# Set UTC and Coarse time in the Fine Delay
fdelay.set_time(0, 0)
......@@ -187,18 +232,20 @@ def main (default_directory='.'):
t_start_coarse = 0
width = 50000 # pulse width 50 ns
delta = 100000 # rising edges every 100 ns
count = 3000
print "\n____________________Fine Delay sending pulses____________________"
print "...pulses being sent to all the channels at a rate > 40MHz\n"
count = 1000
# sending pulses to all the channels, so as to trigger the Error Flag of the Interface FIFOs
print "\n____________________Fine Delay sending pulses____________________"
print "\n...pulses being sent to all the channels at a rate > 40MHz\n"
t_start_utc = fdelay.get_time().utc+1
fdelay.conf_pulsegen(1, enable, t_start_utc, t_start_coarse, width, delta, count)
fdelay.conf_pulsegen(2, enable, t_start_utc, t_start_coarse, width, delta, count)
fdelay.conf_pulsegen(3, enable, t_start_utc, t_start_coarse, width, delta, count)
fdelay.conf_pulsegen(4, enable, t_start_utc, t_start_coarse, width, delta, count)
#-----> TDC
time.sleep(5)
#-----> TDC
# Bind SPEC object to FMC TDC card
spec.bind(FMC_TDC_ADDR)
......@@ -206,14 +253,19 @@ def main (default_directory='.'):
print "\n______________________ACAM ErrorFlag test________________________\n"
print "The time now is : %s" %datetime.now()
print "The temperature now is : %3.3f°C" %tdc.mezz_get_temp()
print "Fine Delay sent : 1000 pulses to each TDC channel"
print "TDC Write pointer : %d"%(tdc.get_pointer())
if ((ERRFLAG_BASE.rd_reg(ERRFLAG_REG)) != 0):
print "ACAM Error Flag : 0x%08X OK!" %(ERRFLAG_BASE.rd_reg(ERRFLAG_REG))
print ("ACAM Error Flag : 0x%08X OK!" %(ERRFLAG_BASE.rd_reg(ERRFLAG_REG)))
else:
print "ERROR: ACAM IC8: Error Flag not activated as expected"
msg = ("ERROR: ACAM IC8: Error Flag: not activated as expected")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
os.close(spec.fd)
print "\n-----------------------------------------------------------------\n\n\n"
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test12.py
View file @ 4e895887
......@@ -71,7 +71,9 @@ def main (default_directory='.'):
print "\n-------------------------------------------------------------------"
print "----------------------------- TDC PTS -----------------------------"
print "---------------------------- LEDs test ----------------------------"
print "---------------------------- LEDs test ----------------------------\n"
print ("Test of the front panel LEDs. For this test the operator’s intervention\n"
"is needed; when prompted, the operator should visually inspect the LEDs.\n")
# SPEC object declaration
spec = rr.Gennum()
......@@ -100,13 +102,17 @@ def main (default_directory='.'):
# Standard in/out redirection
sys.stdout = tmp_stdout;
sys.stdin = tmp_stdin;
sys.stdin = tmp_stdin;
if (ask == "N"):
raise PtsError ("ERROR: Front Panel LEDs")
msg = ("ERROR: Front Panel LEDs: Not blinking as expected")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
print ("LEDs inspected OK!")
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
......
test/fmctdc1ns5cha/software/pts.py
View file @ 4e895887
......@@ -297,6 +297,7 @@ class Suite(object):
log.write(' OK\n')
print 'test '+ shortname + ' OK\n'
log.write('\n')
log.write('------------------------\n')
log.write('Test suite finished.\n')
......
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