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Production Test Suite
Commit 542722f7 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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cleanup of vhdl folder

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test/spec/vhdl/general-cores/modules/genrams/Manifest.py deleted 100644 → 0
View file @ f584b6c1
files = [
"genram_pkg.vhd",
"memory_loader_pkg.vhd",
"generic_shiftreg_fifo.vhd",
"inferred_sync_fifo.vhd",
"inferred_async_fifo.vhd"];
if (target == "altera"):
modules = {"local" : "altera"}
elif (target == "xilinx" and syn_device[0:4].upper()=="XC6V"):
modules = {"local" : ["xilinx", "xilinx/virtex6"]}
elif (target == "xilinx"):
modules = {"local" : ["xilinx", "generic"]}
test/spec/vhdl/general-cores/modules/genrams/generic/Manifest.py deleted 100644 → 0
View file @ f584b6c1
files = ["generic_async_fifo.vhd",
"generic_sync_fifo.vhd"]
test/spec/vhdl/general-cores/modules/genrams/generic/generic_async_fifo.vhd deleted 100644 → 0
View file @ f584b6c1
-------------------------------------------------------------------------------
-- Title : Parametrizable asynchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_async_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component inferred_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_rd_empty : boolean;
g_with_rd_full : boolean;
g_with_rd_almost_empty : boolean;
g_with_rd_almost_full : boolean;
g_with_rd_count : boolean;
g_with_wr_empty : boolean;
g_with_wr_full : boolean;
g_with_wr_almost_empty : boolean;
g_with_wr_almost_full : boolean;
g_with_wr_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
begin -- syn
U_Inferred_FIFO : inferred_async_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_rd_empty => g_with_rd_empty,
g_with_rd_full => g_with_rd_full,
g_with_rd_almost_empty => g_with_rd_almost_empty,
g_with_rd_almost_full => g_with_rd_almost_full,
g_with_rd_count => g_with_rd_count,
g_with_wr_empty => g_with_wr_empty,
g_with_wr_full => g_with_wr_full,
g_with_wr_almost_empty => g_with_wr_almost_empty,
g_with_wr_almost_full => g_with_wr_almost_full,
g_with_wr_count => g_with_wr_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold)
port map (
rst_n_i => rst_n_i,
clk_wr_i => clk_wr_i,
d_i => d_i,
we_i => we_i,
wr_empty_o => wr_empty_o,
wr_full_o => wr_full_o,
wr_almost_empty_o => wr_almost_empty_o,
wr_almost_full_o => wr_almost_full_o,
wr_count_o => wr_count_o,
clk_rd_i => clk_rd_i,
q_o => q_o,
rd_i => rd_i,
rd_empty_o => rd_empty_o,
rd_full_o => rd_full_o,
rd_almost_empty_o => rd_almost_empty_o,
rd_almost_full_o => rd_almost_full_o,
rd_count_o => rd_count_o);
end syn;
test/spec/vhdl/general-cores/modules/genrams/generic/generic_sync_fifo.vhd deleted 100644 → 0
View file @ f584b6c1
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity generic_sync_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_empty : boolean := true; -- with empty flag
g_with_full : boolean := true; -- with full flag
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false; -- with words counter
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_sync_fifo;
architecture syn of generic_sync_fifo is
component inferred_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_empty : boolean;
g_with_full : boolean;
g_with_almost_empty : boolean;
g_with_almost_full : boolean;
g_with_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer;
g_register_flag_outputs : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
begin -- syn
U_Inferred_FIFO : inferred_sync_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_empty => g_with_empty,
g_with_full => g_with_full,
g_with_almost_empty => g_with_almost_empty,
g_with_almost_full => g_with_almost_full,
g_with_count => g_with_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold,
g_register_flag_outputs => g_register_flag_outputs)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => d_i,
we_i => we_i,
q_o => q_o,
rd_i => rd_i,
empty_o => empty_o,
full_o => full_o,
almost_empty_o => almost_empty_o,
almost_full_o => almost_full_o,
count_o => count_o);
end syn;
test/spec/vhdl/general-cores/modules/genrams/genram_pkg.vhd deleted 100644 → 0
View file @ f584b6c1
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-01-24
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
-- Generic RAM initialized with nothing.
constant c_generic_ram_nothing : t_generic_ram_init(-1 downto 0, -1 downto 0) :=
(others => (others => '0'));
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0):= f_gen_dummy_vec('1', (g_data_width+7)/8);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_simple_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width -1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
qb_o : out std_logic_vector(g_data_width -1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic := '0';
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
web_i : in std_logic := '0';
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_shiftreg_fifo
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
full_o : out std_logic;
almost_full_o : out std_logic;
q_valid_o : out std_logic
);
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector is
variable tmp : std_logic_vector(size-1 downto 0);
begin
for i in 0 to size-1 loop
tmp(i) := val;
end loop; -- i
return tmp;
end f_gen_dummy_vec;
end genram_pkg;
test/spec/vhdl/general-cores/modules/genrams/inferred_async_fifo.vhd deleted 100644 → 0
View file @ f584b6c1
-------------------------------------------------------------------------------
-- Title : Parametrizable asynchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_async_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-13
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity inferred_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end inferred_async_fifo;
architecture syn of inferred_async_fifo is
function f_bin2gray(bin : unsigned) return unsigned is
begin
return bin(bin'left) & (bin(bin'left-1 downto 0) xor bin(bin'left downto 1));
end f_bin2gray;
function f_gray2bin(gray : unsigned) return unsigned is
variable bin : unsigned(gray'left downto 0);
begin
-- gray to binary
for i in 0 to gray'left loop
bin(i) := '0';
for j in i to gray'left loop
bin(i) := bin(i) xor gray(j);
end loop; -- j
end loop; -- i
return bin;
end f_gray2bin;
subtype t_counter is unsigned(f_log2_size(g_size) downto 0);
type t_counter_block is record
bin, bin_next, gray, gray_next : t_counter;
bin_x, gray_x, gray_xm : t_counter;
end record;
type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem_type;
signal rcb, wcb : t_counter_block;
attribute ASYNC_REG : string;
attribute ASYNC_REG of wcb: signal is "TRUE";
attribute ASYNC_REG of rcb: signal is "TRUE";
signal full_int, empty_int : std_logic;
signal almost_full_int, almost_empty_int : std_logic;
signal going_full : std_logic;
signal wr_count, rd_count : t_counter;
signal we : std_logic;
begin -- syn
we <= we_i and not full_int;
p_mem_write : process(clk_wr_i)
begin
if rising_edge(clk_wr_i) then
if(we = '1') then
mem(to_integer(wcb.bin(wcb.bin'left-1 downto 0))) <= d_i;
end if;
end if;
end process;
p_mem_read : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
if(rd_i = '1' and empty_int = '0') then
q_o <= mem(to_integer(rcb.bin(rcb.bin'left-1 downto 0)));
end if;
end if;
end process;
wcb.bin_next <= wcb.bin + 1;
wcb.gray_next <= f_bin2gray(wcb.bin_next);
p_write_ptr : process(clk_wr_i, rst_n_i)
begin
if rst_n_i = '0' then
wcb.bin <= (others => '0');
wcb.gray <= (others => '0');
elsif rising_edge(clk_wr_i) then
if(we_i = '1' and full_int = '0') then
wcb.bin <= wcb.bin_next;
wcb.gray <= wcb.gray_next;
end if;
end if;
end process;
rcb.bin_next <= rcb.bin + 1;
rcb.gray_next <= f_bin2gray(rcb.bin_next);
p_read_ptr : process(clk_rd_i, rst_n_i)
begin
if rst_n_i = '0' then
rcb.bin <= (others => '0');
rcb.gray <= (others => '0');
elsif rising_edge(clk_rd_i) then
if(rd_i = '1' and empty_int = '0') then
rcb.bin <= rcb.bin_next;
rcb.gray <= rcb.gray_next;
end if;
end if;
end process;
p_sync_read_ptr : process(clk_wr_i)
begin
if rising_edge(clk_wr_i) then
rcb.gray_xm <= rcb.gray;
rcb.gray_x <= rcb.gray_xm;
end if;
end process;
p_sync_write_ptr : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
wcb.gray_xm <= wcb.gray;
wcb.gray_x <= wcb.gray_xm;
end if;
end process;
wcb.bin_x <= f_gray2bin(wcb.gray_x);
rcb.bin_x <= f_gray2bin(rcb.gray_x);
p_gen_empty : process(clk_rd_i, rst_n_i)
begin
if rst_n_i = '0' then
empty_int <= '1';
elsif rising_edge (clk_rd_i) then
if(rcb.gray = wcb.gray_x or (rd_i = '1' and (wcb.gray_x = rcb.gray_next))) then
empty_int <= '1';
else
empty_int <= '0';
end if;
end if;
end process;
p_gen_going_full : process(we_i, wcb, rcb)
begin
if ((wcb.bin (wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
and (wcb.bin(wcb.bin'left) /= rcb.bin_x(wcb.bin_x'left))) then
going_full <= '1';
elsif (we_i = '1'
and (wcb.bin_next(wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
and (wcb.bin_next(wcb.bin'left) /= rcb.bin_x(rcb.bin_x'left))) then
going_full <= '1';
else
going_full <= '0';
end if;
end process;
p_register_full : process(clk_wr_i, rst_n_i)
begin
if rst_n_i = '0' then
full_int <= '0';
elsif rising_edge (clk_wr_i) then
full_int <= going_full;
end if;
end process;
wr_full_o <= full_int;
rd_empty_o <= empty_int;
p_reg_almost_full : process(clk_wr_i, rst_n_i)
begin
if rst_n_i = '0' then
almost_full_int <= '0';
elsif rising_edge(clk_wr_i) then
wr_count <= wcb.bin - rcb.bin_x;
if (wr_count >= g_almost_full_threshold) then
almost_full_int <= '1';
else
almost_full_int <= '0';
end if;
end if;
end process;
p_reg_almost_empty : process(clk_rd_i, rst_n_i)
begin
if rst_n_i = '0' then
almost_empty_int <= '1';
elsif rising_edge(clk_rd_i) then
rd_count <= wcb.bin_x - rcb.bin;
if (rd_count <= g_almost_empty_threshold) then
almost_empty_int <= '1';
else
almost_empty_int <= '0';
end if;
end if;
end process;
rd_almost_empty_o <= almost_empty_int;
wr_almost_full_o <= almost_full_int;
wr_count_o <= std_logic_vector(wr_count(f_log2_size(g_size)-1 downto 0));
rd_count_o <= std_logic_vector(rd_count(f_log2_size(g_size)-1 downto 0));
end syn;
test/spec/vhdl/general-cores/modules/genrams/inferred_sync_fifo.vhd deleted 100644 → 0
View file @ f584b6c1
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo_std.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-09-18
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity inferred_sync_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_empty : boolean := true; -- with empty flag
g_with_full : boolean := true; -- with full flag
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false; -- with words counter
g_almost_empty_threshold : integer := 0; -- threshold for almost empty flag
g_almost_full_threshold : integer := 0; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end inferred_sync_fifo;
architecture syn of inferred_sync_fifo is
constant c_pointer_width : integer := f_log2_size(g_size);
signal rd_ptr, wr_ptr, wr_ptr_d0, rd_ptr_muxed : unsigned(c_pointer_width-1 downto 0);
signal usedw : unsigned(c_pointer_width downto 0);
signal full, empty : std_logic;
signal q_int : std_logic_vector(g_data_width-1 downto 0);
signal we : std_logic;
signal guard_bit : std_logic;
signal q_reg, q_comb : std_logic_vector(g_data_width-1 downto 0);
begin -- syn
--assert g_show_ahead = false report "Show ahead mode not implemented (yet). Sorry" severity failure;
we <= we_i and not full;
U_FIFO_Ram : generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
wea_i => we,
aa_i => std_logic_vector(wr_ptr(c_pointer_width-1 downto 0)),
da_i => d_i,
clkb_i => '0',
ab_i => std_logic_vector(rd_ptr_muxed(c_pointer_width-1 downto 0)),
qb_o => q_comb);
p_output_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rd_i = '1' then
q_reg <= q_comb;
end if;
end if;
end process;
process(rd_ptr, rd_i)
begin
if(rd_i = '1' and g_show_ahead) then
rd_ptr_muxed <= rd_ptr + 1;
elsif((rd_i = '1' and not g_show_ahead) or (g_show_ahead)) then
rd_ptr_muxed <= rd_ptr;
else
rd_ptr_muxed <= rd_ptr - 1;
end if;
end process;
-- q_o <= q_comb when g_show_ahead = true else q_reg;
q_o <= q_comb;
p_pointers : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ptr <= (others => '0');
rd_ptr <= (others => '0');
else
if(we_i = '1' and full = '0') then
wr_ptr <= wr_ptr + 1;
end if;
if(rd_i = '1' and empty = '0') then
rd_ptr <= rd_ptr + 1;
end if;
end if;
end if;
end process;
gen_comb_flags_showahead : if(g_show_ahead = true) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if ((rd_ptr + 1 = wr_ptr and rd_i = '1') or (rd_ptr = wr_ptr)) then
empty <= '1';
else
empty <= '0';
end if;
end if;
end process;
full <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
end generate gen_comb_flags_showahead;
gen_comb_flags : if(g_register_flag_outputs = false and g_show_ahead = false) generate
empty <= '1' when (wr_ptr = rd_ptr and guard_bit = '0') else '0';
full <= '1' when (wr_ptr = rd_ptr and guard_bit = '1') else '0';
p_guard_bit : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
guard_bit <= '0';
elsif(wr_ptr + 1 = rd_ptr and we_i = '1') then
guard_bit <= '1';
elsif(rd_i = '1') then
guard_bit <= '0';
end if;
end if;
end process;
end generate gen_comb_flags;
gen_registered_flags : if(g_register_flag_outputs = true and g_show_ahead = false) generate
p_reg_flags : process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
full <= '0';
empty <= '1';
else
if(usedw = 1 and rd_i = '1' and we_i = '0') then
empty <= '1';
elsif(we_i = '1' and rd_i = '0') then
empty <= '0';
end if;
if(usedw = g_size-2 and we_i = '1' and rd_i = '0') then
full <= '1';
elsif(usedw = g_size-1 and rd_i = '1' and we_i = '0') then
full <= '0';
end if;
end if;
end if;
end process;
end generate gen_registered_flags;
gen_with_word_counter : if(g_with_count or g_with_almost_empty or g_with_almost_full or g_register_flag_outputs) generate
p_usedw_counter : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
usedw <= (others => '0');
else
if(we_i = '1' and rd_i = '0' and full = '0') then
usedw <= usedw + 1;
elsif(we_i = '0' and rd_i = '1' and empty = '0') then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
count_o <= std_logic_vector(usedw(c_pointer_width-1 downto 0));
end generate gen_with_word_counter;
gen_with_almost_full : if(g_with_almost_full) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
almost_full_o <= '0';
else
if(usedw = g_almost_full_threshold-1) then
if(we_i = '1' and rd_i = '0') then
almost_full_o <= '1';
elsif(rd_i = '1' and we_i = '0') then
almost_full_o <= '0';
end if;
end if;
end if;
end if;
end process;
end generate gen_with_almost_full;
gen_with_almost_empty : if(g_with_almost_empty) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
almost_empty_o <= '1';
else
if(usedw = g_almost_empty_threshold+1) then
if(rd_i = '1' and we_i = '0') then
almost_empty_o <= '1';
elsif(we_i = '1' and rd_i = '0') then
almost_empty_o <= '0';
end if;
end if;
end if;
end if;
end process;
end generate gen_with_almost_empty;
full_o <= full;
empty_o <= empty;
end syn;
test/spec/vhdl/general-cores/modules/genrams/xilinx/Manifest.py deleted 100644 → 0
View file @ f584b6c1
files = [
"generic_dpram.vhd",
"generic_dpram_sameclock.vhd",
"generic_dpram_dualclock.vhd",
"generic_simple_dpram.vhd",
"generic_spram.vhd"
]
test/spec/vhdl/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd deleted 100644 → 0
View file @ f584b6c1
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_simple_dpram.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-03-04
-- Last update: 2013-03-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-04 1.0 wterpstra Initial version: wrapper to generic_dpram
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_simple_dpram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_simple_dpram;
architecture syn of generic_simple_dpram is
begin
-- Works well enough until a Xilinx guru can optimize it.
true_dp : generic_dpram
generic map(
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_dual_clock => g_dual_clock)
port map(
rst_n_i => rst_n_i,
clka_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => open,
clkb_i => clkb_i,
bweb_i => (others => '0'),
web_i => '0',
ab_i => ab_i,
db_i => (others => '0'),
qb_o => qb_o);
end syn;
test/spec/vhdl/spec_pts_ddr/rtl/Manifest.py
View file @ 542722f7
......@@ -3,19 +3,12 @@ files = [
"sdb_meta_pkg.vhd"
]
fetchto = "../../ip_cores"
modules = {
"local" : [
"../../common/rtl"
],
"svn" : [
"http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/common/rtl"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git::sdb_extension",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_32b_32b",
"git://ohwr.org/hdl-core-lib/wr-cores.git"
]
}
"local" : [
"../../common/rtl",
"../../ip-cores/general-cores",
"../../ip-cores/gn4124-core",
"../../ip-cores/wr-cores",
"../../ip-cores/ddr3-sp6-core",
]
}
\ No newline at end of file
test/spec/vhdl/spec_pts_ddr/spec_pts_ddr.ucf deleted 100644 → 0
View file @ f584b6c1
#===============================================================================
# The IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock inputs
#----------------------------------------
NET "clk20_vcxo_i" LOC = H12; # CLK25_VCXO
NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10 | IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9 | IOSTANDARD = "LVDS_25";
NET "fpga_pll_ref_clk_101_n_i" LOC = D11 | IOSTANDARD = "LVDS_25";
NET "fpga_pll_ref_clk_101_p_i" LOC = C11 | IOSTANDARD = "LVDS_25";
NET "fpga_pll_ref_clk0_123_n_i" LOC = B12 | IOSTANDARD = "LVDS_25";
NET "fpga_pll_ref_clk0_123_p_i" LOC = A12 | IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
#NET "sfp_rxn_i" LOC = C15;
#NET "sfp_rxp_i" LOC = D15;
#NET "sfp_txn_o" LOC = A16;
#NET "sfp_txp_o" LOC = B16;
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def0_b" LOC = G15;
NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_b" LOC = H14;
NET "sfp_rate_select_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interface (for VCXO)
#----------------------------------------
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "carrier_one_wire_b" LOC = D4;
NET "carrier_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GPIO[0]" LOC = U16;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GPIO[1]" LOC = AB19;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SATA
#----------------------------------------
#NET "sata0_rxn_i" LOC = C9;
#NET "sata0_rxp_i" LOC = D9;
#NET "sata0_txn_o" LOC = A8;
#NET "sata0_txp_o" LOC = B8;
#NET "sata1_rxn_i" LOC = C13;
#NET "sata1_rxp_i" LOC = D13;
#NET "sata1_txn_o" LOC = A14;
#NET "sata1_txp_o" LOC = B14;
#----------------------------------------
# FMC slot
#----------------------------------------
#NET "fmc_dp0_rxn_i" LOC = C7;
#NET "fmc_dp0_rxp_i" LOC = D7;
#NET "fmc_dp0_txn_o" LOC = A6;
#NET "fmc_dp0_txp_o" LOC = B6;
NET "fmc_gbtclk0_m2c_n_i" LOC = B10 | IOSTANDARD = "LVDS_25";
NET "fmc_gbtclk0_m2c_p_i" LOC = A10 | IOSTANDARD = "LVDS_25";
NET "fmc_la17n_i" LOC = AB13 | IOSTANDARD = "LVCMOS25";
NET "fmc_la19n_i" LOC = AB15 | IOSTANDARD = "LVCMOS25";
NET "fmc_la19p_i" LOC = Y15 | IOSTANDARD = "LVCMOS25";
NET "fmc_la20p_i" LOC = R11 | IOSTANDARD = "LVCMOS25";
NET "fmc_la20n_i" LOC = T11 | IOSTANDARD = "LVCMOS25";
NET "fmc_la14n_i" LOC = AB4 | IOSTANDARD = "LVCMOS25";
NET "fmc_la14p_i" LOC = AA4 | IOSTANDARD = "LVCMOS25";
NET "fmc_la17p_i" LOC = Y13 | IOSTANDARD = "LVCMOS25";
NET "fmc_la13n_i" LOC = AB9 | IOSTANDARD = "LVCMOS25";
NET "fmc_la13p_i" LOC = Y9 | IOSTANDARD = "LVCMOS25";
NET "fmc_la15p_i" LOC = V11 | IOSTANDARD = "LVCMOS25";
NET "fmc_la15n_i" LOC = W11 | IOSTANDARD = "LVCMOS25";
NET "fmc_la16p_i" LOC = W12 | IOSTANDARD = "LVCMOS25";
NET "fmc_la32n_i" LOC = A20 | IOSTANDARD = "LVCMOS25";
NET "fmc_la33p_i" LOC = C19 | IOSTANDARD = "LVCMOS25";
NET "fmc_la33n_i" LOC = A19 | IOSTANDARD = "LVCMOS25";
NET "fmc_la07p_i" LOC = U9 | IOSTANDARD = "LVCMOS25";
NET "fmc_la05p_i" LOC = AA6 | IOSTANDARD = "LVCMOS25";
NET "fmc_la07n_i" LOC = V9 | IOSTANDARD = "LVCMOS25";
NET "fmc_la08n_i" LOC = R8 | IOSTANDARD = "LVCMOS25";
NET "fmc_la08p_i" LOC = R9 | IOSTANDARD = "LVCMOS25";
NET "fmc_la06n_i" LOC = AB5 | IOSTANDARD = "LVCMOS25";
NET "fmc_la12p_i" LOC = T10 | IOSTANDARD = "LVCMOS25";
NET "fmc_la09n_i" LOC = AB7 | IOSTANDARD = "LVCMOS25";
NET "fmc_la16n_i" LOC = Y12 | IOSTANDARD = "LVCMOS25";
NET "fmc_la12n_i" LOC = U10 | IOSTANDARD = "LVCMOS25";
NET "fmc_la11p_i" LOC = W10 | IOSTANDARD = "LVCMOS25";
NET "fmc_la10n_i" LOC = AB8 | IOSTANDARD = "LVCMOS25";
NET "fmc_la11n_i" LOC = Y10 | IOSTANDARD = "LVCMOS25";
NET "fmc_la10p_i" LOC = AA8 | IOSTANDARD = "LVCMOS25";
NET "fmc_la09p_i" LOC = Y7 | IOSTANDARD = "LVCMOS25";
NET "fmc_la05n_i" LOC = AB6 | IOSTANDARD = "LVCMOS25";
NET "fmc_la27p_i" LOC = AA18 | IOSTANDARD = "LVCMOS25";
NET "fmc_la23n_i" LOC = AB16 | IOSTANDARD = "LVCMOS25";
NET "fmc_la22p_i" LOC = R13 | IOSTANDARD = "LVCMOS25";
NET "fmc_la22n_i" LOC = T14 | IOSTANDARD = "LVCMOS25";
NET "fmc_la18n_i" LOC = U12 | IOSTANDARD = "LVCMOS25";
NET "fmc_la18p_i" LOC = T12 | IOSTANDARD = "LVCMOS25";
NET "fmc_la23p_i" LOC = AA16 | IOSTANDARD = "LVCMOS25";
NET "fmc_la21p_i" LOC = V13 | IOSTANDARD = "LVCMOS25";
NET "fmc_la24p_i" LOC = W14 | IOSTANDARD = "LVCMOS25";
NET "fmc_la25n_i" LOC = U15 | IOSTANDARD = "LVCMOS25";
NET "fmc_tck_i" LOC = G8 | IOSTANDARD = "LVCMOS25";
NET "fmc_la25p_i" LOC = T15 | IOSTANDARD = "LVCMOS25";
NET "fmc_la27n_i" LOC = AB18 | IOSTANDARD = "LVCMOS25";
NET "fmc_la26p_i" LOC = Y17 | IOSTANDARD = "LVCMOS25";
NET "fmc_la21n_i" LOC = W13 | IOSTANDARD = "LVCMOS25";
NET "fmc_la26n_i" LOC = AB17 | IOSTANDARD = "LVCMOS25";
NET "fmc_la32p_i" LOC = B20 | IOSTANDARD = "LVCMOS25";
NET "fmc_la30n_i" LOC = W18 | IOSTANDARD = "LVCMOS25";
NET "fmc_la31n_i" LOC = C18 | IOSTANDARD = "LVCMOS25";
NET "fmc_la30p_i" LOC = V17 | IOSTANDARD = "LVCMOS25";
NET "fmc_tms_i" LOC = H10 | IOSTANDARD = "LVCMOS25";
NET "fmc_la29p_i" LOC = W17 | IOSTANDARD = "LVCMOS25";
NET "fmc_la29n_i" LOC = Y18 | IOSTANDARD = "LVCMOS25";
NET "fmc_tdo_i" LOC = F9 | IOSTANDARD = "LVCMOS25";
NET "fmc_la31p_i" LOC = D17 | IOSTANDARD = "LVCMOS25";
NET "fmc_la28n_i" LOC = W15 | IOSTANDARD = "LVCMOS25";
NET "fmc_la28p_i" LOC = Y16 | IOSTANDARD = "LVCMOS25";
NET "fmc_tdi_i" LOC = H11 | IOSTANDARD = "LVCMOS25";
NET "fmc_la24n_i" LOC = Y14 | IOSTANDARD = "LVCMOS25";
NET "fmc_clk0_m2c_n_i" LOC = F16 | IOSTANDARD = "LVCMOS25";
NET "fmc_clk0_m2c_p_i" LOC = E16 | IOSTANDARD = "LVCMOS25";
NET "fmc_prsnt_m2c_l_i" LOC = AB14 | IOSTANDARD = "LVCMOS25";
NET "fmc_pg_c2m_i" LOC = AA14 | IOSTANDARD = "LVCMOS25";
NET "fmc_la01p_i" LOC = AA12 | IOSTANDARD = "LVCMOS25";
NET "fmc_la06p_i" LOC = Y5 | IOSTANDARD = "LVCMOS25";
NET "fmc_la01n_i" LOC = AB12 | IOSTANDARD = "LVCMOS25";
NET "fmc_la03n_i" LOC = W8 | IOSTANDARD = "LVCMOS25";
NET "fmc_la04p_i" LOC = T8 | IOSTANDARD = "LVCMOS25";
NET "fmc_la03p_i" LOC = V7 | IOSTANDARD = "LVCMOS25";
NET "fmc_vrefam2c_D3_i" LOC = D3 | IOSTANDARD = "LVCMOS25";
NET "fmc_vrefam2c_A5_i" LOC = A5 | IOSTANDARD = "LVCMOS25";
NET "fmc_vrefam2c_G13_i" LOC = G13 | IOSTANDARD = "LVCMOS25";
NET "fmc_vrefam2c_D19_i" LOC = D19 | IOSTANDARD = "LVCMOS25";
NET "fmc_vrefam2c_V15_i" LOC = V15 | IOSTANDARD = "LVCMOS25";
NET "fmc_vrefam2c_U13_i" LOC = U13 | IOSTANDARD = "LVCMOS25";
NET "fmc_vrefam2c_AB10_i" LOC = AB10 | IOSTANDARD = "LVCMOS25";
NET "fmc_vrefam2c_Y8_i" LOC = Y8 | IOSTANDARD = "LVCMOS25";
NET "fmc_clk1_m2c_n_i" LOC = L22 | IOSTANDARD = "LVCMOS25";
NET "fmc_clk1_m2c_p_i" LOC = L20 | IOSTANDARD = "LVCMOS25";
NET "fmc_la00p_i" LOC = Y11 | IOSTANDARD = "LVCMOS25";
NET "fmc_io_scl_b" LOC = W6 | IOSTANDARD = "LVCMOS25"; # fmc_la02p
NET "fmc_la00n_i" LOC = AB11 | IOSTANDARD = "LVCMOS25";
NET "fmc_io_sda_b" LOC = Y6 | IOSTANDARD = "LVCMOS25"; # fmc_la02n
NET "fmc_la04n_i" LOC = U8 | IOSTANDARD = "LVCMOS25";
NET "fmc_scl_b" LOC = F7 | IOSTANDARD = "LVCMOS25";
NET "fmc_sda_b" LOC = F8 | IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SI57x interface
#----------------------------------------
NET "si570_scl_b" LOC = A18;
NET "si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "si570_sda_b" LOC = A17;
NET "si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "si570_oe" LOC = H13;
NET "si570_oe" IOSTANDARD = "LVCMOS25";
NET "si570_clk_n_i" LOC = F15;
NET "si570_clk_n_i" IOSTANDARD = "LVDS_25";
NET "si570_clk_p_i" LOC = F14;
NET "si570_clk_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# DDR3 interface
#----------------------------------------
NET "DDR3_CAS_N" LOC = M4;
NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_CK_N" LOC = K3;
NET "DDR3_CK_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CK_P" LOC = K4;
NET "DDR3_CK_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CKE" LOC = F2;
NET "DDR3_CKE" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDM" LOC = N4;
NET "DDR3_LDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDQS_N" LOC = N1;
NET "DDR3_LDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_LDQS_P" LOC = N3;
NET "DDR3_LDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_ODT" LOC = L6;
NET "DDR3_ODT" IOSTANDARD = "SSTL15_II";
NET "DDR3_RAS_N" LOC = M5;
NET "DDR3_RAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RESET_N" LOC = E3;
NET "DDR3_RESET_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDM" LOC = P3;
NET "DDR3_UDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDQS_N" LOC = V1;
NET "DDR3_UDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_UDQS_P" LOC = V2;
NET "DDR3_UDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[1]" LOC = K1;
NET "DDR3_A[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[2]" LOC = K5;
NET "DDR3_A[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[3]" LOC = M6;
NET "DDR3_A[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[4]" LOC = H3;
NET "DDR3_A[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[5]" LOC = M3;
NET "DDR3_A[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[6]" LOC = L4;
NET "DDR3_A[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[7]" LOC = K6;
NET "DDR3_A[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[8]" LOC = G3;
NET "DDR3_A[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[9]" LOC = G1;
NET "DDR3_A[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[10]" LOC = J4;
NET "DDR3_A[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[11]" LOC = E1;
NET "DDR3_A[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[12]" LOC = F1;
NET "DDR3_A[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[13]" LOC = J6;
NET "DDR3_A[13]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[14]" LOC = H5;
#NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[0]" LOC = J3;
NET "DDR3_BA[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[1]" LOC = J1;
NET "DDR3_BA[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[2]" LOC = H1;
NET "DDR3_BA[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[0]" LOC = R3;
NET "DDR3_DQ[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[1]" LOC = R1;
NET "DDR3_DQ[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[2]" LOC = P2;
NET "DDR3_DQ[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[3]" LOC = P1;
NET "DDR3_DQ[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[4]" LOC = L3;
NET "DDR3_DQ[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[5]" LOC = L1;
NET "DDR3_DQ[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[6]" LOC = M2;
NET "DDR3_DQ[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[7]" LOC = M1;
NET "DDR3_DQ[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[8]" LOC = T2;
NET "DDR3_DQ[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[9]" LOC = T1;
NET "DDR3_DQ[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[10]" LOC = U3;
NET "DDR3_DQ[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[11]" LOC = U1;
NET "DDR3_DQ[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[12]" LOC = W3;
NET "DDR3_DQ[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[13]" LOC = W1;
NET "DDR3_DQ[13]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[14]" LOC = Y2;
NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[15]" LOC = Y1;
NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = B2; # FPGA input
NET "uart_txd_o" IOSTANDARD = "LVCMOS25";
NET "uart_rxd_i" LOC = A2; # FPGA output
NET "uart_rxd_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Buttons and LEDs
#----------------------------------------
NET "aux_buttons_i[0]" LOC = C22;
NET "aux_buttons_i[0]" IOSTANDARD = "LVCMOS18";
NET "aux_buttons_i[1]" LOC = D21;
NET "aux_buttons_i[1]" IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[0]" IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[1]" IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[2]" IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[3]" LOC = C20;
NET "aux_leds_o[3]" IOSTANDARD = "LVCMOS18";
#===============================================================================
# IOBs
#===============================================================================
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
#===============================================================================
# Terminations
#===============================================================================
# DDR3
NET "DDR3_DQ[*]" IN_TERM = NONE;
NET "DDR3_LDQS_P" IN_TERM = NONE;
NET "DDR3_LDQS_N" IN_TERM = NONE;
NET "DDR3_UDQS_P" IN_TERM = NONE;
NET "DDR3_UDQS_N" IN_TERM = NONE;
#===============================================================================
# Timing constraints
#===============================================================================
# GN4124
NET "L_CLKp" TNM_NET = "l_clkp_grp";
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
NET "L2P_CLKN" TNM = "gn4124_data_bus_out";
NET "L2P_CLKP" TNM = "gn4124_data_bus_out";
NET "L2P_VALID" TNM = "gn4124_data_bus_out";
NET "L2P_DFRAME" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[0]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[1]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[2]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[3]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[4]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[5]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[6]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[7]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[8]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[9]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[10]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[11]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[12]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[13]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[14]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[15]" TNM = "gn4124_data_bus_out";
TIMEGRP "gn4124_data_bus_out" OFFSET = OUT AFTER "cmp_gn4124_core/io_clk" REFERENCE_PIN "L2P_CLKP";
NET "P2L_CLKN" TNM = "gn4124_data_bus_in";
NET "P2L_CLKP" TNM = "gn4124_data_bus_in";
NET "P2L_DFRAME" TNM = "gn4124_data_bus_in";
NET "P2L_VALID" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[0]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[1]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[2]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[3]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[4]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[5]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[6]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[7]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[8]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[9]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[10]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[11]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[12]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[13]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[14]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[15]" TNM = "gn4124_data_bus_in";
TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" RISING;
TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" FALLING;
# System clocks
NET "clk20_vcxo_i" TNM_NET = clk20_vcxo_i;
TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i" 50 ns HIGH 50 %;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50 %;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50 %;
NET "fpga_pll_ref_clk_101_n_i" TNM_NET = "fpga_pll_ref_clk_101_n_i";
TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50 %;
NET "fpga_pll_ref_clk_101_p_i" TNM_NET = "fpga_pll_ref_clk_101_p_i";
TIMESPEC TS_fpga_pll_ref_clk_101_p_i = PERIOD "fpga_pll_ref_clk_101_p_i" 8 ns HIGH 50 %;
NET "fpga_pll_ref_clk0_123_n_i" TNM_NET = "fpga_pll_ref_clk0_123_n_i";
TIMESPEC TS_fpga_pll_ref_clk0_123_n_i = PERIOD "fpga_pll_ref_clk0_123_n_i" 8 ns HIGH 50 %;
NET "fpga_pll_ref_clk0_123_p_i" TNM_NET = "fpga_pll_ref_clk0_123_p_i";
TIMESPEC TS_fpga_pll_ref_clk0_123_p_i = PERIOD "fpga_pll_ref_clk0_123_p_i" 8 ns HIGH 50 %;
NET "fmc_gbtclk0_m2c_n_i" TNM_NET = "fmc_gbtclk0_m2c_n_i";
TIMESPEC TS_fmc_gbtclk0_m2c_n_i = PERIOD "fmc_gbtclk0_m2c_n_i" 8 ns HIGH 50 %;
NET "fmc_gbtclk0_m2c_p_i" TNM_NET = "fmc_gbtclk0_m2c_p_i";
TIMESPEC TS_fmc_gbtclk0_m2c_p_i = PERIOD "fmc_gbtclk0_m2c_p_i" 8 ns HIGH 50 %;
NET "si570_clk_n_i" TNM_NET = si570_clk_n_i;
TIMESPEC TS_si570_clk_n_i = PERIOD "si570_clk_n_i" 10 ns HIGH 50%;
NET "si570_clk_p_i" TNM_NET = si570_clk_p_i;
TIMESPEC TS_si570_clk_p_i = PERIOD "si570_clk_p_i" 10 ns HIGH 50%;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
#===============================================================================
# False Path
#===============================================================================
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
test/spec/vhdl/spec_pts_ddr/syn/Makefile
View file @ 542722f7
......@@ -3,284 +3,175 @@
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := spec_pts_ddr.xise
ISE_CRAP := *.b spec_pts_ddr_summary.html *.tcl spec_pts_ddr.bld spec_pts_ddr.cmd_log *.drc spec_pts_ddr.lso *.ncd spec_pts_ddr.ngc spec_pts_ddr.ngd spec_pts_ddr.ngr spec_pts_ddr.pad spec_pts_ddr.par spec_pts_ddr.pcf spec_pts_ddr.prj spec_pts_ddr.ptwx spec_pts_ddr.stx spec_pts_ddr.syr spec_pts_ddr.twr spec_pts_ddr.twx spec_pts_ddr.gise spec_pts_ddr.unroutes spec_pts_ddr.ut spec_pts_ddr.xpi spec_pts_ddr.xst spec_pts_ddr_bitgen.xwbt spec_pts_ddr_envsettings.html spec_pts_ddr_guide.ncd spec_pts_ddr_map.map spec_pts_ddr_map.mrp spec_pts_ddr_map.ncd spec_pts_ddr_map.ngm spec_pts_ddr_map.xrpt spec_pts_ddr_ngdbuild.xrpt spec_pts_ddr_pad.csv spec_pts_ddr_pad.txt spec_pts_ddr_par.xrpt spec_pts_ddr_summary.xml spec_pts_ddr_usage.xml spec_pts_ddr_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
TOP_MODULE := spec_pts_ddr
PROJECT := spec_pts_ddr
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH := /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt
TCL_INTERPRETER := xtclsh.exe
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx150t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
all: bitstream
SOURCES_VHDLFile := \
../rtl/sdb_meta_pkg.vhd \
../rtl/spec_pts_ddr.vhd
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
SOURCES_UCFFile := \
../spec_pts_ddr.ucf
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=spec_pts_ddr
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_UCFFile), echo "xfile add $(sourcefile)" >> $@ &)
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
CWD := $(shell pwd)
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
FILES := ../spec_pts_ddr.ucf \
../rtl/spec_pts_ddr.vhd \
../rtl/sdb_meta_pkg.vhd \
../../common/rtl/spec_pts_pkg.vhd \
../../common/rtl/carrier_csr.vhd \
../../common/rtl/clkcnt_csr.vhd \
../../common/rtl/incr_counter.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_decode32.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/wbmaster32.vhd \
../../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_ctrl_regs.vhd \
../../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_stat_regs.vhd \
../../ip_cores/gn4124-core/trunk/hdl/common/rtl/wb_addr_decoder.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_32b_32b.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd \
../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd \
../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd \
../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd \
../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd \
../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd \
../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd \
../../ip_cores/wr-cores/modules/wr_tlu/wb_cores_pkg_gsi.vhd \
../../ip_cores/wr-cores/modules/wr_tlu/wb_timestamp_latch.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
run.tcl \
spec_pts_ddr.xise
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place ^& Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
test/spec/vhdl/spec_pts_ddr/syn/Manifest.py
View file @ 542722f7
board = "spec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_pts_ddr"
syn_project = "spec_pts_ddr.xise"
syn_tool = "ise"
files = ["../spec_pts_ddr.ucf"]
files = ["spec_pts_ddr.ucf"]
modules = { "local" : "../rtl" }
ctrls = ["bank3_32b_32b"]
\ No newline at end of file
test/spec/vhdl/spec_pts_ddr/syn/spec_pts_ddr.xise
View file @ 542722f7
......@@ -12,6 +12,380 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="spec_pts_ddr.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../rtl/spec_pts_ddr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../rtl/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../common/rtl/spec_pts_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../common/rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../common/rtl/clkcnt_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../common/rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/common/rtl/dummy_ctrl_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/common/rtl/dummy_stat_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/gn4124-core/hdl/common/rtl/wb_addr_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
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<file xil_pn:name="../../ip-cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
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<autoManagedFiles>
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......@@ -19,6 +393,9 @@
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<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
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<file xil_pn:name="../../ip-cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
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<properties>
......@@ -54,7 +431,6 @@
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Consider Include Files in Search" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
......@@ -339,29 +715,13 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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<file xil_pn:name="../spec_pts_ddr.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</files>
<bindings>
<binding xil_pn:location="/spec_pts_ddr" xil_pn:name="../spec_pts_ddr.ucf"/>
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project>
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