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7cb377e4
Commit
7cb377e4
authored
Jan 30, 2014
by
Matthieu Cattin
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fmc_adc_spec/svec: Remove the mezzanine reset release (unactive by default in gw).
parent
f9820796
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3 changed files
with
2 additions
and
11 deletions
+2
-11
fmc_adc_spec.py
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
+0
-4
fmc_adc_svec.py
test/fmcadc100m14b4cha/python/fmc_adc_svec.py
+0
-5
svec_carrier_csr.py
test/fmcadc100m14b4cha/python/svec_carrier_csr.py
+2
-2
No files found.
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @
7cb377e4
...
...
@@ -77,10 +77,6 @@ class CFmcAdc100mSpec:
if
(
ct
==
0xFFFFFFFF
):
raise
FmcAdc100mSpecOperationError
(
"Bitstream not properly loaded."
)
# Release the mezzanine software reset
self
.
set_sw_rst
(
1
)
time
.
sleep
(
0.001
)
# gives time for ddr core to calibrates
# Configure VIC
#self.vic.print_regs()
self
.
vic
.
set_polarity
(
1
)
# output active high
...
...
test/fmcadc100m14b4cha/python/fmc_adc_svec.py
View file @
7cb377e4
...
...
@@ -69,11 +69,6 @@ class CFmcAdc100mSvec:
if
(
ct
==
0xFFFFFFFF
):
raise
FmcAdc100mSvecOperationError
(
"Bitstream not properly loaded."
)
# Release the mezzanines software reset
self
.
set_sw_rst
(
0
,
1
)
self
.
set_sw_rst
(
1
,
1
)
time
.
sleep
(
0.001
)
# gives time for ddr core to calibrates
# Configure VIC
#self.vic.print_regs()
self
.
vic
.
set_polarity
(
1
)
# output active high
...
...
test/fmcadc100m14b4cha/python/svec_carrier_csr.py
View file @
7cb377e4
...
...
@@ -25,7 +25,7 @@ CARRIER_CSR=['Carrier control and status registers',{
'LED'
:[
0
,
'Front panel LEDs'
,
0xFFFF
],
'RESERVED'
:[
16
,
'Reserved'
,
0xFFFF
]}],
'RST'
:[
0x0C
,
'Reset'
,
{
'FMC0'
:[
0
,
'FMC 1 software reset'
,
0x1
],
'FMC1'
:[
1
,
'FMC 2 software reset'
,
0x1
],
'FMC0'
:[
0
,
'FMC 1 software reset
(active low)
'
,
0x1
],
'FMC1'
:[
1
,
'FMC 2 software reset
(active low)
'
,
0x1
],
'RESERVED'
:[
2
,
'Reserved'
,
0x3FFFFFFF
]}]
}]
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