fmc_adc, fmc_adc_spec: Change wb cores base addresses to fit new mapping.

The fmc adc mezzanine related cores are now in a wrapper with a wb crossbar.

fmc_adc, fmc_adc_spec: Change wb cores base addresses to fit new mapping.
The fmc adc mezzanine related cores are now in a wrapper with a wb crossbar.
87ee725f · Matthieu Cattin · 58ccbf2c · 87ee725f · 87ee725f
Commit 87ee725f authored Jul 04, 2013 by Matthieu Cattin
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fmc_adc.py test/fmcadc100m14b4cha/python/fmc_adc.py +5 -5

fmc_adc_spec.py test/fmcadc100m14b4cha/python/fmc_adc_spec.py +4 -4

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--- a/test/fmcadc100m14b4cha/python/fmc_adc.py
+++ b/test/fmcadc100m14b4cha/python/fmc_adc.py
@@ -75,19 +75,19 @@ class FmcAdc100mOperationError(Exception):

 class CFmcAdc100m:

-    FMC_SYS_I2C_ADDR = 0x1600
+    FMC_SYS_I2C_ADDR = 0x3000
    EEPROM_ADDR = 0x50

-    FMC_SPI_ADDR = 0x1700
+    FMC_SPI_ADDR = 0x3100
    FMC_SPI_DIV = 100
    FMC_SPI_SS = {'ADC': 0,'DAC1': 1,'DAC2': 2,'DAC3': 3,'DAC4': 4}

-    FMC_I2C_ADDR = 0x1800
+    FMC_I2C_ADDR = 0x3200
    SI570_ADDR = 0x55

-    FMC_ONEWIRE_ADDR = 0x1A00
+    FMC_ONEWIRE_ADDR = 0x3400

-    FMC_CSR_ADDR = 0x1900
+    FMC_CSR_ADDR = 0x3300


    """

--- a/test/fmcadc100m14b4cha/python/fmc_adc_spec.py
+++ b/test/fmcadc100m14b4cha/python/fmc_adc_spec.py
@@ -37,10 +37,10 @@ class CFmcAdc100mSpec:

    # Wishbone core base addresses
    GNUM_DMA_CSR_ADDR = 0x1000
-    ONEWIRE_ADDR = 0x1200
-    CSR_ADDR = 0x1300
-    UTC_CORE_ADDR = 0x1400
-    IRQ_CONTROLLER_ADDR = 0x1500
+    ONEWIRE_ADDR = 0x1100
+    CSR_ADDR = 0x1200
+    UTC_CORE_ADDR = 0x1300
+    IRQ_CONTROLLER_ADDR = 0x1400

    # Onewire core port
    DS18B20_PORT = 0