Commit 9d93e5ae authored by Matthieu Cattin's avatar Matthieu Cattin

fmc_adc: Fix syntax issues.

parent a6719521
......@@ -128,8 +128,8 @@ class CFmcAdc100m:
self.adc_core_offset = offset + 0x2000
# FOR SVEC ONLY
self.DDR_DAT_ADDR = self.adc_mezz_offset + DDR_DAT_ADDR
self.DDR_ADR_ADDR = self.adc_mezz_offset + DDR_ADR_ADDR
self.DDR_DAT_ADDR = self.adc_mezz_offset + self.DDR_DAT_ADDR
self.DDR_ADR_ADDR = self.adc_mezz_offset + self.DDR_ADR_ADDR
try:
# Objects declaration
......@@ -901,11 +901,11 @@ class CFmcAdc100m:
def get_data(self, carrier_addr, data):
self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, carrier_addr)
for i in range(len(data)):
self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, data[i]))
self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, data[i])
# Clear DDR
def get_data(self):
self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, 0x0)
for i in range(0x4000000):
self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, 0x0))
self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, 0x0)
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