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Commit a951c1a9 authored by Matthieu Cattin's avatar Matthieu Cattin
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fmc_adc: Update fmc-adc core csr description, add methods to access new features. 

- nb. remaining shots
- sampling frequency
- internal trigger test mode
- internal trigger threshold filter
- variable saturation (set to max at init)
parent 019be8e1
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Showing with 100 additions and 24 deletions
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @ a951c1a9
......@@ -137,6 +137,7 @@ class CFmcAdc100m:
self.fmc_eic = CCSR(self.bus, self.adc_mezz_offset + self.FMC_EIC_ADDR, FMC_ADC_EIC_REGS)
self.utc_core = CCSR(self.bus, self.adc_mezz_offset + self.UTC_CORE_ADDR, UTC_CORE_REGS)
#self.print_adc_core_config()
# Set channels gain to 1
self.fmc_adc_csr.set_field('CH1_GAIN', 'VAL', 0x8000)
......@@ -144,6 +145,12 @@ class CFmcAdc100m:
self.fmc_adc_csr.set_field('CH3_GAIN', 'VAL', 0x8000)
self.fmc_adc_csr.set_field('CH4_GAIN', 'VAL', 0x8000)
# Set channels saturation to max
self.fmc_adc_csr.set_field('CH1_SAT', 'VAL', 0x7FFF)
self.fmc_adc_csr.set_field('CH2_SAT', 'VAL', 0x7FFF)
self.fmc_adc_csr.set_field('CH3_SAT', 'VAL', 0x7FFF)
self.fmc_adc_csr.set_field('CH4_SAT', 'VAL', 0x7FFF)
# Enable mezzanine clock and offset DACs
self.en_sampfreq()
self.dc_offset_reset()
......@@ -646,7 +653,7 @@ class CFmcAdc100m:
#def get_channel_config(self, channel):
# Set trigger configuration
def set_trig_config(self, hw_sel, hw_pol, hw_en, sw_en, channel, int_thres, delay):
def set_trig_config(self, hw_sel, hw_pol, hw_en, sw_en, channel, int_thres, delay, int_thres_filt=0):
ch = self.channel_check(channel)
try:
# Hardware trigger select (ext/int)
......@@ -663,6 +670,8 @@ class CFmcAdc100m:
self.fmc_adc_csr.set_field('TRIG_CFG', 'INT_TRIG_THRES', int_thres)
# Trigger delay (in sampling clock ticks)
self.fmc_adc_csr.set_reg('TRIG_DLY', delay)
# Internal trigger threshold filter
self.fmc_adc_csr.set_field('TRIG_CFG', 'INT_TRIG_THRES_FILT', int_thres_filt)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
......@@ -734,6 +743,20 @@ class CFmcAdc100m:
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Enable internal trigger test mode
def int_trig_tst_en(self):
try:
self.fmc_adc_csr.set_field('TRIG_CFG', 'INT_TRIG_TEST_EN', 1)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Disable internal trigger test mode
def int_trig_tst_dis(self):
try:
self.fmc_adc_csr.set_field('TRIG_CFG', 'INT_TRIG_TEST_EN', 0)
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Enable test data
def test_data_en(self):
try:
......@@ -803,6 +826,20 @@ class CFmcAdc100m:
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get pre-trigger samples
def get_pre_trig_samples(self):
try:
return self.fmc_adc_csr.get_reg('PRE_SAMPLES')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get post-trigger samples
def get_post_trig_samples(self):
try:
return self.fmc_adc_csr.get_reg('POST_SAMPLES')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Set number of shots
def set_shots(self, shots):
try:
......@@ -810,6 +847,20 @@ class CFmcAdc100m:
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get number of shots
def get_shots(self):
try:
return self.fmc_adc_csr.get_field('SHOTS', 'NB')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get number of remaining shots
def get_rem_shots(self):
try:
return self.fmc_adc_csr.get_field('SHOTS_CNT', 'NB')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get acquisition state machine status
def get_acq_fsm_state(self):
try:
......@@ -895,6 +946,13 @@ class CFmcAdc100m:
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
# Get sampling frequency
def get_samp_freq(self):
try:
return self.fmc_adc_csr.get_reg('FS_FREQ')
except CSRDeviceOperationError as e:
raise FmcAdc100mOperationError(e)
#======================================================================
# Si570 programmable oscillator
......
test/fmcadc100m14b4cha/python/fmcadc100m_csr.py
View file @ a951c1a9
......@@ -31,65 +31,83 @@ FMCADC100M_CSR=['FMC ADC 100MS/s core registers',{
'HW_TRIG_EN':[2, 'Hardware trigger enable', 0x1],
'SW_TRIG_EN':[3, 'Software trigger enable', 0x1],
'INT_TRIG_SEL':[4, 'Channel selection for internal trigger', 0x3],
'RESERVED':[5, 'Reserved', 0x3FF],
'INT_TRIG_TEST_EN':[6, 'Enable internal trigger test mode', 0x1],
'RESERVED':[7, 'Reserved', 0x1],
'INT_TRIG_THRES_FILT':[8, 'Internal trigger threshold glitch filter', 0xFF],
'INT_TRIG_THRES':[16, 'Threshold for internal trigger (two\'s compl.)', 0xFFFF]}],
'TRIG_DLY':[0x0C, 'Trigger delay', {}],
'SW_TRIG':[0x10, 'Software trigger', {}],
'SHOTS':[0x14, 'Number of shots', {
'NB':[0, 'Number of shots', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'TRIG_POS':[0x18, 'Trigger address register', {}],
'SR':[0x1C, 'Sample rate', {
'SHOTS_CNT':[0x18, 'Remaining shots counter', {
'NB':[0, 'Number of remaining shots', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'TRIG_POS':[0x1C, 'Trigger address register', {}],
'FS_FREQ':[0x20, 'Sample rate', {}],
'SR':[0x24, 'Sample rate', {
'DECI':[0, 'Sample rate decimation factor', 0xFFFFFFFF]}],
'PRE_SAMPLES':[0x20, 'Pre-trigger samples', {}],
'POST_SAMPLES':[0x24, 'Post-trigger samples', {}],
'SAMPLES_CNT':[0x28, 'Samples counter', {}],
'CH1_CTL':[0x2C, 'Channel 1 control register', {
'PRE_SAMPLES':[0x28, 'Pre-trigger samples', {}],
'POST_SAMPLES':[0x2C, 'Post-trigger samples', {}],
'SAMPLES_CNT':[0x30, 'Samples counter', {}],
'CH1_CTL':[0x34, 'Channel 1 control register', {
'SSR':[0, 'Solid state relays control for channel 1', 0x7F],
'RESERVED':[7, 'Reserved', 0x1FFFFFF]}],
'CH1_STA':[0x30, 'Channel 1 status register', {
'CH1_STA':[0x38, 'Channel 1 status register', {
'VAL':[0, 'Channel 1 current ADC value', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH1_GAIN':[0x34, 'Channel 1 gain calibration register', {
'CH1_GAIN':[0x3C, 'Channel 1 gain calibration register', {
'VAL':[0, 'Gain calibration for channel 1', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH1_OFFSET':[0x38, 'Channel 1 offset calibration register', {
'CH1_OFFSET':[0x40, 'Channel 1 offset calibration register', {
'VAL':[0, 'Offset calibration for channel 1', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH2_CTL':[0x3C, 'Channel 2 control register', {
'CH1_SAT':[0x44, 'Channel 1 saturation register', {
'VAL':[0, 'Saturation value for channel 1', 0x7FFF],
'RESERVED':[15, 'Reserved', 0x1FFFF]}],
'CH2_CTL':[0x48, 'Channel 2 control register', {
'SSR':[0, 'Solid state relays control for channel 2', 0x7F],
'RESERVED':[7, 'Reserved', 0x1FFFFFF]}],
'CH2_STA':[0x40, 'Channel 2 status register', {
'CH2_STA':[0x4C, 'Channel 2 status register', {
'VAL':[0, 'Channel 2 current ADC value', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH2_GAIN':[0x44, 'Channel 2 gain calibration register', {
'CH2_GAIN':[0x50, 'Channel 2 gain calibration register', {
'VAL':[0, 'Gain calibration for channel 2', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH2_OFFSET':[0x48, 'Channel 2 offset calibration register', {
'CH2_OFFSET':[0x54, 'Channel 2 offset calibration register', {
'VAL':[0, 'Offset calibration for channel 2', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH3_CTL':[0x4C, 'Channel 3 control register', {
'CH2_SAT':[0x58, 'Channel 2 saturation register', {
'VAL':[0, 'Saturation value for channel 2', 0x7FFF],
'RESERVED':[15, 'Reserved', 0x1FFFF]}],
'CH3_CTL':[0x5C, 'Channel 3 control register', {
'SSR':[0, 'Solid state relays control for channel 3', 0x7F],
'RESERVED':[7, 'Reserved', 0x1FFFFFF]}],
'CH3_STA':[0x50, 'Channel 3 status register', {
'CH3_STA':[0x60, 'Channel 3 status register', {
'VAL':[0, 'Channel 3 current ADC value', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH3_GAIN':[0x54, 'Channel 3 gain calibration register', {
'CH3_GAIN':[0x64, 'Channel 3 gain calibration register', {
'VAL':[0, 'Gain calibration for channel 3', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH3_OFFSET':[0x58, 'Channel 3 offset calibration register', {
'CH3_OFFSET':[0x68, 'Channel 3 offset calibration register', {
'VAL':[0, 'Offset calibration for channel 3', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH4_CTL':[0x5C, 'Channel 4 control register', {
'CH3_SAT':[0x6C, 'Channel 3 saturation register', {
'VAL':[0, 'Saturation value for channel 3', 0x7FFF],
'RESERVED':[15, 'Reserved', 0x1FFFF]}],
'CH4_CTL':[0x70, 'Channel 4 control register', {
'SSR':[0, 'Solid state relays control for channel 4', 0x7F],
'RESERVED':[7, 'Reserved', 0x1FFFFFF]}],
'CH4_STA':[0x60, 'Channel 4 status register', {
'CH4_STA':[0x74, 'Channel 4 status register', {
'VAL':[0, 'Channel 4 current ADC value', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH4_GAIN':[0x64, 'Channel 4 gain calibration register', {
'CH4_GAIN':[0x78, 'Channel 4 gain calibration register', {
'VAL':[0, 'Gain calibration for channel 4', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH4_OFFSET':[0x68, 'Channel 4 offset calibration register', {
'CH4_OFFSET':[0x7C, 'Channel 4 offset calibration register', {
'VAL':[0, 'Offset calibration for channel 4', 0xFFFF],
'RESERVED':[16, 'Reserved', 0xFFFF]}]
'RESERVED':[16, 'Reserved', 0xFFFF]}],
'CH4_SAT':[0x80, 'Channel 4 saturation register', {
'VAL':[0, 'Saturation value for channel 4', 0x7FFF],
'RESERVED':[15, 'Reserved', 0x1FFFF]}]
}]
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