Commit b60697d6 authored by Matthieu Cattin's avatar Matthieu Cattin

test07: Increase the tolerance for the mid-range DAC test.

parent d7ba1a4f
......@@ -54,7 +54,7 @@ DAC_SET_SLEEP = 0.01 # in [s]
ADC_NEG = -32768.0
ADC_MID = 0.0
ADC_POS = 32764.0 # not 32767.0 because the ADC is 14-bit left-shifted by 2, the last 2 bits are always 0
ADC_TOL = 200.0
ADC_TOL = 300.0
def hex2signed(value):
......
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