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Commit b718a368 authored by Matthieu Cattin's avatar Matthieu Cattin
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Replace gtp fmc clock test by a new project. 

The fmc reference clock for gtp firmware implements a gtp wrapper (only to get the reference clocks).
Each clock increments a counter which is latch every second to a register accessible via VME.
parent 2479d102
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test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/Manifest.py 0 → 100644
View file @ b718a368
files = ["fmc_refclk_test.vhd",
"fmc_refclk_test_tile.vhd",
"mgt_usrclk_source_pll.vhd"]
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/coregen.cgc 0 → 100644
View file @ b718a368
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test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/coregen.cgp 0 → 100644
View file @ b718a368
# Date: Thu Nov 1 11:26:58 2012
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx150t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: eb716463
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test.gise 0 → 100644
View file @ b718a368
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fmc_refclk_test.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fmc_refclk_test.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test.vhd 0 → 100755
View file @ b718a368
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : fmc_refclk_test.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module fmc_refclk_test (a GTP Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity fmc_refclk_test is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_CLK25_DIVIDER_0 : integer := 5;
WRAPPER_CLK25_DIVIDER_1 : integer := 5;
WRAPPER_PLL_DIVSEL_FB_0 : integer := 2;
WRAPPER_PLL_DIVSEL_FB_1 : integer := 2;
WRAPPER_PLL_DIVSEL_REF_0 : integer := 1;
WRAPPER_PLL_DIVSEL_REF_1 : integer := 1;
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_PLLLKDET1_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXDISPERR0_OUT : out std_logic_vector(3 downto 0);
TILE0_RXDISPERR1_OUT : out std_logic_vector(3 downto 0);
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(3 downto 0);
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(3 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(31 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(31 downto 0);
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_RXEQMIX0_IN : in std_logic_vector(1 downto 0);
TILE0_RXEQMIX1_IN : in std_logic_vector(1 downto 0);
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE0_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0);
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARISK0_IN : in std_logic_vector(3 downto 0);
TILE0_TXCHARISK1_IN : in std_logic_vector(3 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(31 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(31 downto 0);
TILE0_TXOUTCLK0_OUT : out std_logic;
TILE0_TXOUTCLK1_OUT : out std_logic;
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXDIFFCTRL0_IN : in std_logic_vector(3 downto 0);
TILE0_TXDIFFCTRL1_IN : in std_logic_vector(3 downto 0);
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic;
TILE0_TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
TILE0_TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0);
--_________________________________________________________________________
--_________________________________________________________________________
--TILE1 (X0_Y1)
------------------------ Loopback and Powerdown Ports ----------------------
TILE1_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE1_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE1_CLK00_IN : in std_logic;
TILE1_CLK01_IN : in std_logic;
TILE1_GTPRESET0_IN : in std_logic;
TILE1_GTPRESET1_IN : in std_logic;
TILE1_PLLLKDET0_OUT : out std_logic;
TILE1_PLLLKDET1_OUT : out std_logic;
TILE1_RESETDONE0_OUT : out std_logic;
TILE1_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE1_RXDISPERR0_OUT : out std_logic_vector(3 downto 0);
TILE1_RXDISPERR1_OUT : out std_logic_vector(3 downto 0);
TILE1_RXNOTINTABLE0_OUT : out std_logic_vector(3 downto 0);
TILE1_RXNOTINTABLE1_OUT : out std_logic_vector(3 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE1_RXENMCOMMAALIGN0_IN : in std_logic;
TILE1_RXENMCOMMAALIGN1_IN : in std_logic;
TILE1_RXENPCOMMAALIGN0_IN : in std_logic;
TILE1_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE1_RXDATA0_OUT : out std_logic_vector(31 downto 0);
TILE1_RXDATA1_OUT : out std_logic_vector(31 downto 0);
TILE1_RXUSRCLK0_IN : in std_logic;
TILE1_RXUSRCLK1_IN : in std_logic;
TILE1_RXUSRCLK20_IN : in std_logic;
TILE1_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE1_RXEQMIX0_IN : in std_logic_vector(1 downto 0);
TILE1_RXEQMIX1_IN : in std_logic_vector(1 downto 0);
TILE1_RXN0_IN : in std_logic;
TILE1_RXN1_IN : in std_logic;
TILE1_RXP0_IN : in std_logic;
TILE1_RXP1_IN : in std_logic;
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE1_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0);
TILE1_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0);
---------------------------- TX/RX Datapath Ports --------------------------
TILE1_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE1_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE1_TXCHARISK0_IN : in std_logic_vector(3 downto 0);
TILE1_TXCHARISK1_IN : in std_logic_vector(3 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE1_TXDATA0_IN : in std_logic_vector(31 downto 0);
TILE1_TXDATA1_IN : in std_logic_vector(31 downto 0);
TILE1_TXOUTCLK0_OUT : out std_logic;
TILE1_TXOUTCLK1_OUT : out std_logic;
TILE1_TXUSRCLK0_IN : in std_logic;
TILE1_TXUSRCLK1_IN : in std_logic;
TILE1_TXUSRCLK20_IN : in std_logic;
TILE1_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE1_TXDIFFCTRL0_IN : in std_logic_vector(3 downto 0);
TILE1_TXDIFFCTRL1_IN : in std_logic_vector(3 downto 0);
TILE1_TXN0_OUT : out std_logic;
TILE1_TXN1_OUT : out std_logic;
TILE1_TXP0_OUT : out std_logic;
TILE1_TXP1_OUT : out std_logic;
TILE1_TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
TILE1_TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0)
);
end fmc_refclk_test;
architecture RTL of fmc_refclk_test is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "fmc_refclk_test,s6_gtpwizard_v1_11,{gtp0_protocol_file=Start_from_scratch,gtp1_protocol_file=Use_GTP0_settings}";
--***************************** Signal Declarations *****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tile0_plllkdet0_i : std_logic;
signal tile0_plllkdet1_i : std_logic;
signal tile1_plllkdet0_i : std_logic;
signal tile1_plllkdet1_i : std_logic;
signal tile0_plllkdet0_i2 : std_logic;
signal count00 : std_logic_vector(4 downto 0);
signal tile0_plllkdet1_i2 : std_logic;
signal count10 : std_logic_vector(4 downto 0);
signal tile1_plllkdet0_i2 : std_logic;
signal count01 : std_logic_vector(4 downto 0);
signal tile1_plllkdet1_i2 : std_logic;
signal count11 : std_logic_vector(4 downto 0);
--*************************** Component Declarations **************************
component fmc_refclk_test_tile
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 5;
TILE_CLK25_DIVIDER_1 : integer := 5;
TILE_PLL_DIVSEL_FB_0 : integer := 2;
TILE_PLL_DIVSEL_FB_1 : integer := 2;
TILE_PLL_DIVSEL_REF_0 : integer := 1;
TILE_PLL_DIVSEL_REF_1 : integer := 1;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXDISPERR0_OUT : out std_logic_vector(3 downto 0);
RXDISPERR1_OUT : out std_logic_vector(3 downto 0);
RXNOTINTABLE0_OUT : out std_logic_vector(3 downto 0);
RXNOTINTABLE1_OUT : out std_logic_vector(3 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN : in std_logic;
RXENMCOMMAALIGN1_IN : in std_logic;
RXENPCOMMAALIGN0_IN : in std_logic;
RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(31 downto 0);
RXDATA1_OUT : out std_logic_vector(31 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXEQMIX0_IN : in std_logic_vector(1 downto 0);
RXEQMIX1_IN : in std_logic_vector(1 downto 0);
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0);
RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0);
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic_vector(3 downto 0);
TXCHARISK1_IN : in std_logic_vector(3 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(31 downto 0);
TXDATA1_IN : in std_logic_vector(31 downto 0);
TXOUTCLK0_OUT : out std_logic;
TXOUTCLK1_OUT : out std_logic;
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXDIFFCTRL0_IN : in std_logic_vector(3 downto 0);
TXDIFFCTRL1_IN : in std_logic_vector(3 downto 0);
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic;
TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0)
);
end component;
--********************************* Main Body of Code**************************
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
simulation : if WRAPPER_SIMULATION = 1 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i2;
process(TILE0_CLK00_IN,TILE0_GTPRESET0_IN)
begin
if (TILE0_GTPRESET0_IN = '1') then
count00 <= "00000";
elsif(TILE0_CLK00_IN'event and TILE0_CLK00_IN ='1') then
if((count00 = "10100") or (tile0_plllkdet0_i = '0')) then
count00 <= "00000";
else
count00 <= count00 + "00001";
end if;
end if;
end process;
process(TILE0_CLK00_IN,tile0_plllkdet0_i)
begin
if(tile0_plllkdet0_i = '0') then
tile0_plllkdet0_i2 <= '0';
elsif(TILE0_CLK00_IN'event and TILE0_CLK00_IN ='1') then
if((count00 = "10100") and (tile0_plllkdet0_i = '1')) then
tile0_plllkdet0_i2 <= '1';
end if;
end if;
end process;
TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i2;
process(TILE0_CLK01_IN,TILE0_GTPRESET1_IN)
begin
if (TILE0_GTPRESET1_IN = '1') then
count10 <= "00000";
elsif(TILE0_CLK01_IN'event and TILE0_CLK01_IN ='1') then
if((count10 = "10100") or (tile0_plllkdet1_i = '0')) then
count10 <= "00000";
else
count10 <= count10 + "00001";
end if;
end if;
end process;
process(TILE0_CLK01_IN,tile0_plllkdet1_i)
begin
if(tile0_plllkdet1_i = '0') then
tile0_plllkdet1_i2 <= '0';
elsif(TILE0_CLK01_IN'event and TILE0_CLK01_IN ='1') then
if((count10 = "10100") and (tile0_plllkdet1_i = '1')) then
tile0_plllkdet1_i2 <= '1';
end if;
end if;
end process;
TILE1_PLLLKDET0_OUT <= tile1_plllkdet0_i2;
process(TILE1_CLK00_IN,TILE1_GTPRESET0_IN)
begin
if (TILE1_GTPRESET0_IN = '1') then
count01 <= "00000";
elsif(TILE1_CLK00_IN'event and TILE1_CLK00_IN ='1') then
if((count01 = "10100") or (tile1_plllkdet0_i = '0')) then
count01 <= "00000";
else
count01 <= count01 + "00001";
end if;
end if;
end process;
process(TILE1_CLK00_IN,tile1_plllkdet0_i)
begin
if(tile1_plllkdet0_i = '0') then
tile1_plllkdet0_i2 <= '0';
elsif(TILE1_CLK00_IN'event and TILE1_CLK00_IN ='1') then
if((count01 = "10100") and (tile1_plllkdet0_i = '1')) then
tile1_plllkdet0_i2 <= '1';
end if;
end if;
end process;
TILE1_PLLLKDET1_OUT <= tile1_plllkdet1_i2;
process(TILE1_CLK01_IN,TILE1_GTPRESET1_IN)
begin
if (TILE1_GTPRESET1_IN = '1') then
count11 <= "00000";
elsif(TILE1_CLK01_IN'event and TILE1_CLK01_IN ='1') then
if((count11 = "10100") or (tile1_plllkdet1_i = '0')) then
count11 <= "00000";
else
count11 <= count11 + "00001";
end if;
end if;
end process;
process(TILE1_CLK01_IN,tile1_plllkdet1_i)
begin
if(tile1_plllkdet1_i = '0') then
tile1_plllkdet1_i2 <= '0';
elsif(TILE1_CLK01_IN'event and TILE1_CLK01_IN ='1') then
if((count11 = "10100") and (tile1_plllkdet1_i = '1')) then
tile1_plllkdet1_i2 <= '1';
end if;
end if;
end process;
end generate simulation;
implementation : if WRAPPER_SIMULATION = 0 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i;
TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i;
TILE1_PLLLKDET0_OUT <= tile1_plllkdet0_i;
TILE1_PLLLKDET1_OUT <= tile1_plllkdet1_i;
end generate implementation;
--------------------------- Tile Instances -------------------------------
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
tile0_fmc_refclk_test_i : fmc_refclk_test_tile
generic map
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP,
TILE_CLK25_DIVIDER_0 => WRAPPER_CLK25_DIVIDER_0,
TILE_CLK25_DIVIDER_1 => WRAPPER_CLK25_DIVIDER_1,
TILE_PLL_DIVSEL_FB_0 => WRAPPER_PLL_DIVSEL_FB_0,
TILE_PLL_DIVSEL_FB_1 => WRAPPER_PLL_DIVSEL_FB_1,
TILE_PLL_DIVSEL_REF_0 => WRAPPER_PLL_DIVSEL_REF_0,
TILE_PLL_DIVSEL_REF_1 => WRAPPER_PLL_DIVSEL_REF_1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL1"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN => TILE0_LOOPBACK0_IN,
LOOPBACK1_IN => TILE0_LOOPBACK1_IN,
--------------------------------- PLL Ports --------------------------------
CLK00_IN => TILE0_CLK00_IN,
CLK01_IN => TILE0_CLK01_IN,
GTPRESET0_IN => TILE0_GTPRESET0_IN,
GTPRESET1_IN => TILE0_GTPRESET1_IN,
PLLLKDET0_OUT => tile0_plllkdet0_i,
PLLLKDET1_OUT => tile0_plllkdet1_i,
RESETDONE0_OUT => TILE0_RESETDONE0_OUT,
RESETDONE1_OUT => TILE0_RESETDONE1_OUT,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT,
RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT,
RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT,
RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN => TILE0_RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1_IN => TILE0_RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0_IN => TILE0_RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1_IN => TILE0_RXENPCOMMAALIGN1_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => TILE0_RXDATA0_OUT,
RXDATA1_OUT => TILE0_RXDATA1_OUT,
RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN,
RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN,
RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN,
RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXEQMIX0_IN => TILE0_RXEQMIX0_IN,
RXEQMIX1_IN => TILE0_RXEQMIX1_IN,
RXN0_IN => TILE0_RXN0_IN,
RXN1_IN => TILE0_RXN1_IN,
RXP0_IN => TILE0_RXP0_IN,
RXP1_IN => TILE0_RXP1_IN,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0_OUT => TILE0_RXLOSSOFSYNC0_OUT,
RXLOSSOFSYNC1_OUT => TILE0_RXLOSSOFSYNC1_OUT,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT => TILE0_GTPCLKOUT0_OUT,
GTPCLKOUT1_OUT => TILE0_GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN => TILE0_TXCHARISK0_IN,
TXCHARISK1_IN => TILE0_TXCHARISK1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => TILE0_TXDATA0_IN,
TXDATA1_IN => TILE0_TXDATA1_IN,
TXOUTCLK0_OUT => TILE0_TXOUTCLK0_OUT,
TXOUTCLK1_OUT => TILE0_TXOUTCLK1_OUT,
TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN,
TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN,
TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN,
TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXDIFFCTRL0_IN => TILE0_TXDIFFCTRL0_IN,
TXDIFFCTRL1_IN => TILE0_TXDIFFCTRL1_IN,
TXN0_OUT => TILE0_TXN0_OUT,
TXN1_OUT => TILE0_TXN1_OUT,
TXP0_OUT => TILE0_TXP0_OUT,
TXP1_OUT => TILE0_TXP1_OUT,
TXPREEMPHASIS0_IN => TILE0_TXPREEMPHASIS0_IN,
TXPREEMPHASIS1_IN => TILE0_TXPREEMPHASIS1_IN
);
--_________________________________________________________________________
--_________________________________________________________________________
--TILE1 (X0_Y1)
tile1_fmc_refclk_test_i : fmc_refclk_test_tile
generic map
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP,
TILE_CLK25_DIVIDER_0 => WRAPPER_CLK25_DIVIDER_0,
TILE_CLK25_DIVIDER_1 => WRAPPER_CLK25_DIVIDER_1,
TILE_PLL_DIVSEL_FB_0 => WRAPPER_PLL_DIVSEL_FB_0,
TILE_PLL_DIVSEL_FB_1 => WRAPPER_PLL_DIVSEL_FB_1,
TILE_PLL_DIVSEL_REF_0 => WRAPPER_PLL_DIVSEL_REF_0,
TILE_PLL_DIVSEL_REF_1 => WRAPPER_PLL_DIVSEL_REF_1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL1"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN => TILE1_LOOPBACK0_IN,
LOOPBACK1_IN => TILE1_LOOPBACK1_IN,
--------------------------------- PLL Ports --------------------------------
CLK00_IN => TILE1_CLK00_IN,
CLK01_IN => TILE1_CLK01_IN,
GTPRESET0_IN => TILE1_GTPRESET0_IN,
GTPRESET1_IN => TILE1_GTPRESET1_IN,
PLLLKDET0_OUT => tile1_plllkdet0_i,
PLLLKDET1_OUT => tile1_plllkdet1_i,
RESETDONE0_OUT => TILE1_RESETDONE0_OUT,
RESETDONE1_OUT => TILE1_RESETDONE1_OUT,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXDISPERR0_OUT => TILE1_RXDISPERR0_OUT,
RXDISPERR1_OUT => TILE1_RXDISPERR1_OUT,
RXNOTINTABLE0_OUT => TILE1_RXNOTINTABLE0_OUT,
RXNOTINTABLE1_OUT => TILE1_RXNOTINTABLE1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN => TILE1_RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1_IN => TILE1_RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0_IN => TILE1_RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1_IN => TILE1_RXENPCOMMAALIGN1_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => TILE1_RXDATA0_OUT,
RXDATA1_OUT => TILE1_RXDATA1_OUT,
RXUSRCLK0_IN => TILE1_RXUSRCLK0_IN,
RXUSRCLK1_IN => TILE1_RXUSRCLK1_IN,
RXUSRCLK20_IN => TILE1_RXUSRCLK20_IN,
RXUSRCLK21_IN => TILE1_RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXEQMIX0_IN => TILE1_RXEQMIX0_IN,
RXEQMIX1_IN => TILE1_RXEQMIX1_IN,
RXN0_IN => TILE1_RXN0_IN,
RXN1_IN => TILE1_RXN1_IN,
RXP0_IN => TILE1_RXP0_IN,
RXP1_IN => TILE1_RXP1_IN,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0_OUT => TILE1_RXLOSSOFSYNC0_OUT,
RXLOSSOFSYNC1_OUT => TILE1_RXLOSSOFSYNC1_OUT,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT => TILE1_GTPCLKOUT0_OUT,
GTPCLKOUT1_OUT => TILE1_GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN => TILE1_TXCHARISK0_IN,
TXCHARISK1_IN => TILE1_TXCHARISK1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => TILE1_TXDATA0_IN,
TXDATA1_IN => TILE1_TXDATA1_IN,
TXOUTCLK0_OUT => TILE1_TXOUTCLK0_OUT,
TXOUTCLK1_OUT => TILE1_TXOUTCLK1_OUT,
TXUSRCLK0_IN => TILE1_TXUSRCLK0_IN,
TXUSRCLK1_IN => TILE1_TXUSRCLK1_IN,
TXUSRCLK20_IN => TILE1_TXUSRCLK20_IN,
TXUSRCLK21_IN => TILE1_TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXDIFFCTRL0_IN => TILE1_TXDIFFCTRL0_IN,
TXDIFFCTRL1_IN => TILE1_TXDIFFCTRL1_IN,
TXN0_OUT => TILE1_TXN0_OUT,
TXN1_OUT => TILE1_TXN1_OUT,
TXP0_OUT => TILE1_TXP0_OUT,
TXP1_OUT => TILE1_TXP1_OUT,
TXPREEMPHASIS0_IN => TILE1_TXPREEMPHASIS0_IN,
TXPREEMPHASIS1_IN => TILE1_TXPREEMPHASIS1_IN
);
end RTL;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test.vho 0 → 100755
View file @ b718a368
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : instantiation_template.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Instantiation Template
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- Use the templates in this file to add the components generated by the wizard to your
-- design.
--**************************Component Declarations*****************************
component fmc_refclk_test
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_PLLLKDET1_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXDISPERR0_OUT : out std_logic_vector(3 downto 0);
TILE0_RXDISPERR1_OUT : out std_logic_vector(3 downto 0);
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(3 downto 0);
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(3 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(31 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(31 downto 0);
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_RXEQMIX0_IN : in std_logic_vector(1 downto 0);
TILE0_RXEQMIX1_IN : in std_logic_vector(1 downto 0);
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE0_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0);
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARISK0_IN : in std_logic_vector(3 downto 0);
TILE0_TXCHARISK1_IN : in std_logic_vector(3 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(31 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(31 downto 0);
TILE0_TXOUTCLK0_OUT : out std_logic;
TILE0_TXOUTCLK1_OUT : out std_logic;
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXDIFFCTRL0_IN : in std_logic_vector(3 downto 0);
TILE0_TXDIFFCTRL1_IN : in std_logic_vector(3 downto 0);
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic;
TILE0_TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
TILE0_TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0);
--_________________________________________________________________________
--_________________________________________________________________________
--TILE1 (X0_Y1)
------------------------ Loopback and Powerdown Ports ----------------------
TILE1_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE1_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE1_CLK00_IN : in std_logic;
TILE1_CLK01_IN : in std_logic;
TILE1_GTPRESET0_IN : in std_logic;
TILE1_GTPRESET1_IN : in std_logic;
TILE1_PLLLKDET0_OUT : out std_logic;
TILE1_PLLLKDET1_OUT : out std_logic;
TILE1_RESETDONE0_OUT : out std_logic;
TILE1_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE1_RXDISPERR0_OUT : out std_logic_vector(3 downto 0);
TILE1_RXDISPERR1_OUT : out std_logic_vector(3 downto 0);
TILE1_RXNOTINTABLE0_OUT : out std_logic_vector(3 downto 0);
TILE1_RXNOTINTABLE1_OUT : out std_logic_vector(3 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE1_RXENMCOMMAALIGN0_IN : in std_logic;
TILE1_RXENMCOMMAALIGN1_IN : in std_logic;
TILE1_RXENPCOMMAALIGN0_IN : in std_logic;
TILE1_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE1_RXDATA0_OUT : out std_logic_vector(31 downto 0);
TILE1_RXDATA1_OUT : out std_logic_vector(31 downto 0);
TILE1_RXUSRCLK0_IN : in std_logic;
TILE1_RXUSRCLK1_IN : in std_logic;
TILE1_RXUSRCLK20_IN : in std_logic;
TILE1_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE1_RXEQMIX0_IN : in std_logic_vector(1 downto 0);
TILE1_RXEQMIX1_IN : in std_logic_vector(1 downto 0);
TILE1_RXN0_IN : in std_logic;
TILE1_RXN1_IN : in std_logic;
TILE1_RXP0_IN : in std_logic;
TILE1_RXP1_IN : in std_logic;
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE1_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0);
TILE1_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0);
---------------------------- TX/RX Datapath Ports --------------------------
TILE1_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE1_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE1_TXCHARISK0_IN : in std_logic_vector(3 downto 0);
TILE1_TXCHARISK1_IN : in std_logic_vector(3 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE1_TXDATA0_IN : in std_logic_vector(31 downto 0);
TILE1_TXDATA1_IN : in std_logic_vector(31 downto 0);
TILE1_TXOUTCLK0_OUT : out std_logic;
TILE1_TXOUTCLK1_OUT : out std_logic;
TILE1_TXUSRCLK0_IN : in std_logic;
TILE1_TXUSRCLK1_IN : in std_logic;
TILE1_TXUSRCLK20_IN : in std_logic;
TILE1_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE1_TXDIFFCTRL0_IN : in std_logic_vector(3 downto 0);
TILE1_TXDIFFCTRL1_IN : in std_logic_vector(3 downto 0);
TILE1_TXN0_OUT : out std_logic;
TILE1_TXN1_OUT : out std_logic;
TILE1_TXP0_OUT : out std_logic;
TILE1_TXP1_OUT : out std_logic;
TILE1_TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
TILE1_TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0)
);
end component;
----------------------------- The GTP Wrapper -----------------------------
fmc_refclk_test_i : fmc_refclk_test
generic map
(
WRAPPER_SIM_GTPRESET_SPEEDUP => 0, // Set this to 1 for simulation
WRAPPER_SIMULATION => 0 // Set this to 1 for simulation
)
port map
(
--_____________________________________________________________________
--_____________________________________________________________________
--TILE0 (X1_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_LOOPBACK0_IN => ,
TILE0_LOOPBACK1_IN => ,
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN => tile1_gtp0_refclk_i,
TILE0_CLK01_IN => tile1_gtp0_refclk_i,
TILE0_GTPRESET0_IN => ,
TILE0_GTPRESET1_IN => ,
TILE0_PLLLKDET0_OUT => ,
TILE0_PLLLKDET1_OUT => ,
TILE0_RESETDONE0_OUT => ,
TILE0_RESETDONE1_OUT => ,
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXDISPERR0_OUT => ,
TILE0_RXDISPERR1_OUT => ,
TILE0_RXNOTINTABLE0_OUT => ,
TILE0_RXNOTINTABLE1_OUT => ,
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN => ,
TILE0_RXENMCOMMAALIGN1_IN => ,
TILE0_RXENPCOMMAALIGN0_IN => ,
TILE0_RXENPCOMMAALIGN1_IN => ,
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT => ,
TILE0_RXDATA1_OUT => ,
TILE0_RXUSRCLK0_IN => ,
TILE0_RXUSRCLK1_IN => ,
TILE0_RXUSRCLK20_IN => ,
TILE0_RXUSRCLK21_IN => ,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_RXEQMIX0_IN => ,
TILE0_RXEQMIX1_IN => ,
TILE0_RXN0_IN => ,
TILE0_RXN1_IN => ,
TILE0_RXP0_IN => ,
TILE0_RXP1_IN => ,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE0_RXLOSSOFSYNC0_OUT => ,
TILE0_RXLOSSOFSYNC1_OUT => ,
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT => ,
TILE0_GTPCLKOUT1_OUT => ,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARISK0_IN => ,
TILE0_TXCHARISK1_IN => ,
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN => ,
TILE0_TXDATA1_IN => ,
TILE0_TXOUTCLK0_OUT => ,
TILE0_TXOUTCLK1_OUT => ,
TILE0_TXUSRCLK0_IN => ,
TILE0_TXUSRCLK1_IN => ,
TILE0_TXUSRCLK20_IN => ,
TILE0_TXUSRCLK21_IN => ,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXDIFFCTRL0_IN => ,
TILE0_TXDIFFCTRL1_IN => ,
TILE0_TXN0_OUT => ,
TILE0_TXN1_OUT => ,
TILE0_TXP0_OUT => ,
TILE0_TXP1_OUT => ,
TILE0_TXPREEMPHASIS0_IN => ,
TILE0_TXPREEMPHASIS1_IN => ,
--_____________________________________________________________________
--_____________________________________________________________________
--TILE1 (X0_Y1)
------------------------ Loopback and Powerdown Ports ----------------------
TILE1_LOOPBACK0_IN => ,
TILE1_LOOPBACK1_IN => ,
--------------------------------- PLL Ports --------------------------------
TILE1_CLK00_IN => tile1_gtp0_refclk_i,
TILE1_CLK01_IN => tile1_gtp0_refclk_i,
TILE1_GTPRESET0_IN => ,
TILE1_GTPRESET1_IN => ,
TILE1_PLLLKDET0_OUT => ,
TILE1_PLLLKDET1_OUT => ,
TILE1_RESETDONE0_OUT => ,
TILE1_RESETDONE1_OUT => ,
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE1_RXDISPERR0_OUT => ,
TILE1_RXDISPERR1_OUT => ,
TILE1_RXNOTINTABLE0_OUT => ,
TILE1_RXNOTINTABLE1_OUT => ,
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE1_RXENMCOMMAALIGN0_IN => ,
TILE1_RXENMCOMMAALIGN1_IN => ,
TILE1_RXENPCOMMAALIGN0_IN => ,
TILE1_RXENPCOMMAALIGN1_IN => ,
------------------- Receive Ports - RX Data Path interface -----------------
TILE1_RXDATA0_OUT => ,
TILE1_RXDATA1_OUT => ,
TILE1_RXUSRCLK0_IN => ,
TILE1_RXUSRCLK1_IN => ,
TILE1_RXUSRCLK20_IN => ,
TILE1_RXUSRCLK21_IN => ,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE1_RXEQMIX0_IN => ,
TILE1_RXEQMIX1_IN => ,
TILE1_RXN0_IN => ,
TILE1_RXN1_IN => ,
TILE1_RXP0_IN => ,
TILE1_RXP1_IN => ,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE1_RXLOSSOFSYNC0_OUT => ,
TILE1_RXLOSSOFSYNC1_OUT => ,
---------------------------- TX/RX Datapath Ports --------------------------
TILE1_GTPCLKOUT0_OUT => ,
TILE1_GTPCLKOUT1_OUT => ,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE1_TXCHARISK0_IN => ,
TILE1_TXCHARISK1_IN => ,
------------------ Transmit Ports - TX Data Path interface -----------------
TILE1_TXDATA0_IN => ,
TILE1_TXDATA1_IN => ,
TILE1_TXOUTCLK0_OUT => ,
TILE1_TXOUTCLK1_OUT => ,
TILE1_TXUSRCLK0_IN => ,
TILE1_TXUSRCLK1_IN => ,
TILE1_TXUSRCLK20_IN => ,
TILE1_TXUSRCLK21_IN => ,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE1_TXDIFFCTRL0_IN => ,
TILE1_TXDIFFCTRL1_IN => ,
TILE1_TXN0_OUT => ,
TILE1_TXN1_OUT => ,
TILE1_TXP0_OUT => ,
TILE1_TXP1_OUT => ,
TILE1_TXPREEMPHASIS0_IN => ,
TILE1_TXPREEMPHASIS1_IN =>
);
-----------------------Dedicated GTP Reference Clock Inputs ---------------
-- Each dedicated refclk you are using in your design will need its own IBUFDS instance
tile0_refclk_ibufds_i : IBUFDS
port map
(
O => tile0_gtp0_refclk_i,
I => , -- Connect to package pin AG18
IB => -- Connect to package pin AH18
);
tile1_refclk_ibufds_i : IBUFDS
port map
(
O => tile1_gtp0_refclk_i,
I => , -- Connect to package pin B13
IB => -- Connect to package pin A13
);
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test.xco 0 → 100644
View file @ b718a368
##############################################################
#
# Xilinx Core Generator version 13.3
# Date: Thu Nov 1 11:36:21 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:s6_gtpwizard:1.11
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx150t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Spartan-6_FPGA_GTP_Transceiver_Wizard xilinx.com:ip:s6_gtpwizard:1.11
# END Select
# BEGIN Parameters
CSET advanced_clocking=false
CSET cb_master_bottom=GTP0_DUAL_X1Y0
CSET cb_master_top=GTP0_DUAL_X0Y1
CSET cb_seq_1_1=00000000
CSET cb_seq_1_1_disp=false
CSET cb_seq_1_1_k=false
CSET cb_seq_1_1_mask=true
CSET cb_seq_1_2=00000000
CSET cb_seq_1_2_disp=false
CSET cb_seq_1_2_k=false
CSET cb_seq_1_2_mask=true
CSET cb_seq_1_3=00000000
CSET cb_seq_1_3_disp=false
CSET cb_seq_1_3_k=false
CSET cb_seq_1_3_mask=true
CSET cb_seq_1_4=00000000
CSET cb_seq_1_4_disp=false
CSET cb_seq_1_4_k=false
CSET cb_seq_1_4_mask=true
CSET cb_seq_2_1=00000000
CSET cb_seq_2_1_disp=false
CSET cb_seq_2_1_k=false
CSET cb_seq_2_1_mask=true
CSET cb_seq_2_2=00000000
CSET cb_seq_2_2_disp=false
CSET cb_seq_2_2_k=false
CSET cb_seq_2_2_mask=true
CSET cb_seq_2_3=00000000
CSET cb_seq_2_3_disp=false
CSET cb_seq_2_3_k=false
CSET cb_seq_2_3_mask=true
CSET cb_seq_2_4=00000000
CSET cb_seq_2_4_disp=false
CSET cb_seq_2_4_k=false
CSET cb_seq_2_4_mask=true
CSET cb_sequence_1_max_skew=1
CSET cb_sequence_2_max_skew=1
CSET cb_sequence_length=1
CSET component_name=fmc_refclk_test
CSET gtp0_bytes_to_reduce_error=8
CSET gtp0_cb2_inh_cc_period=8
CSET gtp0_cc_keep_one_idle=false
CSET gtp0_cc_seq_1_1=00000000
CSET gtp0_cc_seq_1_1_disp=false
CSET gtp0_cc_seq_1_1_k=true
CSET gtp0_cc_seq_1_1_mask=true
CSET gtp0_cc_seq_1_2=00000000
CSET gtp0_cc_seq_1_2_disp=false
CSET gtp0_cc_seq_1_2_k=true
CSET gtp0_cc_seq_1_2_mask=true
CSET gtp0_cc_seq_1_3=00000000
CSET gtp0_cc_seq_1_3_disp=false
CSET gtp0_cc_seq_1_3_k=true
CSET gtp0_cc_seq_1_3_mask=true
CSET gtp0_cc_seq_1_4=00000000
CSET gtp0_cc_seq_1_4_disp=false
CSET gtp0_cc_seq_1_4_k=true
CSET gtp0_cc_seq_1_4_mask=true
CSET gtp0_cc_seq_2_1=00000000
CSET gtp0_cc_seq_2_1_disp=false
CSET gtp0_cc_seq_2_1_k=true
CSET gtp0_cc_seq_2_1_mask=true
CSET gtp0_cc_seq_2_2=00000000
CSET gtp0_cc_seq_2_2_disp=false
CSET gtp0_cc_seq_2_2_k=true
CSET gtp0_cc_seq_2_2_mask=true
CSET gtp0_cc_seq_2_3=00000000
CSET gtp0_cc_seq_2_3_disp=false
CSET gtp0_cc_seq_2_3_k=true
CSET gtp0_cc_seq_2_3_mask=true
CSET gtp0_cc_seq_2_4=00000000
CSET gtp0_cc_seq_2_4_disp=false
CSET gtp0_cc_seq_2_4_k=true
CSET gtp0_cc_seq_2_4_mask=true
CSET gtp0_cc_sequence_length=1
CSET gtp0_cdr_ph_adj_time=01010
CSET gtp0_chan_bond_keep_align=false
CSET gtp0_clk_cor_precedence=true
CSET gtp0_clk_cor_repeat_wait=5
CSET gtp0_comma_alignment=Any_Byte_Boundary
CSET gtp0_comma_mask=1111111111
CSET gtp0_comma_preset=K28.5
CSET gtp0_dec_mcomma_detect=false
CSET gtp0_dec_pcomma_detect=false
CSET gtp0_dec_valid_comma_only=false
CSET gtp0_decoding=8B/10B
CSET gtp0_disable_ac_coupling=true
CSET gtp0_driver_swing=Use_TXDIFFCTRL_Port
CSET gtp0_en_idle_reset_buf=false
CSET gtp0_en_mode_reset_buf=false
CSET gtp0_en_rate_reset_buf=false
CSET gtp0_en_realign_reset_buf=false
CSET gtp0_encoding=8B/10B
CSET gtp0_errors_to_lose_sync=128
CSET gtp0_fifo_lower_bounds=16
CSET gtp0_fifo_upper_bounds=18
CSET gtp0_highpass_pole_location=Use_RXEQPOLE_Port
CSET gtp0_mcomma_detect=true
CSET gtp0_minus_comma=1010000011
CSET gtp0_pci_express_mode=false
CSET gtp0_pcomma_detect=true
CSET gtp0_pll_rate=1.25
CSET gtp0_plus_comma=0101111100
CSET gtp0_pma_cdr_scan=false
CSET gtp0_pma_rx_cfg=0DCE089
CSET gtp0_pma_tx_cfg=0DCE089
CSET gtp0_ppm_offset=0_(Synchronous)
CSET gtp0_preemphasis_level=Use_TXPREEMPHASIS_Port
CSET gtp0_protocol_file=Start_from_scratch
CSET gtp0_refclk_x0_y0=REFCLK0_X0Y0
CSET gtp0_refclk_x0_y1=REFCLK0_X0Y1
CSET gtp0_refclk_x1_y0=REFCLK0_X1Y0
CSET gtp0_refclk_x1_y1=REFCLK0_X1Y1
CSET gtp0_reference_clock=125.00
CSET gtp0_rx_datapath_width=32
CSET gtp0_rx_decode_seq_match=true
CSET gtp0_rx_divider=/2
CSET gtp0_rx_en_idle_hold_cdr=false
CSET gtp0_rx_en_idle_hold_dfe=false
CSET gtp0_rx_en_idle_reset_fr=false
CSET gtp0_rx_en_idle_reset_ph=false
CSET gtp0_rx_fifo_addr_mode=Fast
CSET gtp0_rx_idle_hi_cnt=1000
CSET gtp0_rx_idle_lo_cnt=0000
CSET gtp0_rx_line_rate=1.25
CSET gtp0_rx_oob_threshold=110
CSET gtp0_rx_slide_mode=PCS
CSET gtp0_rx_status_fmt=PCIe
CSET gtp0_rx_termination_voltage=VTTRX
CSET gtp0_rxlossofsyncport=true
CSET gtp0_rxprbserr_loopback=false
CSET gtp0_rxrundisp_indicates_cc=false
CSET gtp0_rxusrclk_source=TXOUTCLK
CSET gtp0_sata_rx_burst_val=4
CSET gtp0_sata_rx_idle_val=4
CSET gtp0_sata_tx_burst_val=15
CSET gtp0_second_order_cdr_loop=false
CSET gtp0_show_realign_comma=false
CSET gtp0_target_line_rate=1.25
CSET gtp0_termination_ctrl=10100
CSET gtp0_termination_imp=50
CSET gtp0_termination_ovrd=false
CSET gtp0_trans_time_from_p2=60
CSET gtp0_trans_time_non_p2=25
CSET gtp0_trans_time_rate=65535
CSET gtp0_trans_time_to_p2=100
CSET gtp0_tx_datapath_width=32
CSET gtp0_tx_divider=/2
CSET gtp0_tx_drive_mode=false
CSET gtp0_tx_line_rate=1.25
CSET gtp0_txrx_invert=011
CSET gtp0_txusrclk_source=TXOUTCLK
CSET gtp0_use_cc=false
CSET gtp0_use_comma_detect=true
CSET gtp0_use_port_enmcommaalign=true
CSET gtp0_use_port_enpcommaalign=true
CSET gtp0_use_port_loopback=true
CSET gtp0_use_port_phystatus=false
CSET gtp0_use_port_pllpowerdown=false
CSET gtp0_use_port_refclkout=false
CSET gtp0_use_port_refclkpowerdown=false
CSET gtp0_use_port_rxbufreset=false
CSET gtp0_use_port_rxbufstatus=false
CSET gtp0_use_port_rxbyteisaligned=false
CSET gtp0_use_port_rxbyterealign=false
CSET gtp0_use_port_rxcdrreset=false
CSET gtp0_use_port_rxchariscomma=false
CSET gtp0_use_port_rxcharisk=false
CSET gtp0_use_port_rxcommadet=false
CSET gtp0_use_port_rxlossofsync=true
CSET gtp0_use_port_rxpolarity=false
CSET gtp0_use_port_rxpowerdown=false
CSET gtp0_use_port_rxrecclk=false
CSET gtp0_use_port_rxreset=false
CSET gtp0_use_port_rxrundisp=false
CSET gtp0_use_port_rxslide=false
CSET gtp0_use_port_rxstatus=false
CSET gtp0_use_port_rxvalid=false
CSET gtp0_use_port_txbufstatus=false
CSET gtp0_use_port_txbypass8b10b=false
CSET gtp0_use_port_txchardispmode=false
CSET gtp0_use_port_txchardispval=false
CSET gtp0_use_port_txcomstart=false
CSET gtp0_use_port_txcomtype=false
CSET gtp0_use_port_txdetectrx=false
CSET gtp0_use_port_txelecidle=false
CSET gtp0_use_port_txenprbstst=false
CSET gtp0_use_port_txinhibit=false
CSET gtp0_use_port_txkerr=false
CSET gtp0_use_port_txoutclk=true
CSET gtp0_use_port_txpdownasynch=false
CSET gtp0_use_port_txpolarity=false
CSET gtp0_use_port_txpowerdown=false
CSET gtp0_use_port_txprbsforceerr=false
CSET gtp0_use_port_txreset=false
CSET gtp0_use_port_txrundisp=false
CSET gtp0_use_prbs_detector=false
CSET gtp0_use_resistor_cal_circuit=false
CSET gtp0_use_rx_eq=false
CSET gtp0_use_rx_oob=false
CSET gtp0_use_rxbuffer=true
CSET gtp0_use_two_cc_sequences=false
CSET gtp0_use_txbuffer=true
CSET gtp0_wideband_highpass_mix=Use_RXEQMIX_Port
CSET gtp1_bytes_to_reduce_error=8
CSET gtp1_cb2_inh_cc_period=8
CSET gtp1_cc_keep_one_idle=false
CSET gtp1_cc_seq_1_1=00000000
CSET gtp1_cc_seq_1_1_disp=false
CSET gtp1_cc_seq_1_1_k=true
CSET gtp1_cc_seq_1_1_mask=true
CSET gtp1_cc_seq_1_2=00000000
CSET gtp1_cc_seq_1_2_disp=false
CSET gtp1_cc_seq_1_2_k=true
CSET gtp1_cc_seq_1_2_mask=true
CSET gtp1_cc_seq_1_3=00000000
CSET gtp1_cc_seq_1_3_disp=false
CSET gtp1_cc_seq_1_3_k=true
CSET gtp1_cc_seq_1_3_mask=true
CSET gtp1_cc_seq_1_4=00000000
CSET gtp1_cc_seq_1_4_disp=false
CSET gtp1_cc_seq_1_4_k=true
CSET gtp1_cc_seq_1_4_mask=true
CSET gtp1_cc_seq_2_1=00000000
CSET gtp1_cc_seq_2_1_disp=false
CSET gtp1_cc_seq_2_1_k=true
CSET gtp1_cc_seq_2_1_mask=true
CSET gtp1_cc_seq_2_2=00000000
CSET gtp1_cc_seq_2_2_disp=false
CSET gtp1_cc_seq_2_2_k=true
CSET gtp1_cc_seq_2_2_mask=true
CSET gtp1_cc_seq_2_3=00000000
CSET gtp1_cc_seq_2_3_disp=false
CSET gtp1_cc_seq_2_3_k=true
CSET gtp1_cc_seq_2_3_mask=true
CSET gtp1_cc_seq_2_4=00000000
CSET gtp1_cc_seq_2_4_disp=false
CSET gtp1_cc_seq_2_4_k=true
CSET gtp1_cc_seq_2_4_mask=true
CSET gtp1_cc_sequence_length=1
CSET gtp1_cdr_ph_adj_time=01010
CSET gtp1_chan_bond_keep_align=false
CSET gtp1_clk_cor_precedence=true
CSET gtp1_clk_cor_repeat_wait=5
CSET gtp1_comma_alignment=Any_Byte_Boundary
CSET gtp1_comma_mask=1111111111
CSET gtp1_comma_preset=K28.5
CSET gtp1_dec_mcomma_detect=false
CSET gtp1_dec_pcomma_detect=false
CSET gtp1_dec_valid_comma_only=false
CSET gtp1_decoding=8B/10B
CSET gtp1_disable_ac_coupling=true
CSET gtp1_driver_swing=Use_TXDIFFCTRL_Port
CSET gtp1_en_idle_reset_buf=false
CSET gtp1_en_mode_reset_buf=false
CSET gtp1_en_rate_reset_buf=false
CSET gtp1_en_realign_reset_buf=false
CSET gtp1_encoding=8B/10B
CSET gtp1_errors_to_lose_sync=128
CSET gtp1_fifo_lower_bounds=16
CSET gtp1_fifo_upper_bounds=18
CSET gtp1_highpass_pole_location=Use_RXEQPOLE_Port
CSET gtp1_mcomma_detect=true
CSET gtp1_minus_comma=1010000011
CSET gtp1_pci_express_mode=false
CSET gtp1_pcomma_detect=true
CSET gtp1_pll_rate=1.25
CSET gtp1_plus_comma=0101111100
CSET gtp1_pma_cdr_scan=false
CSET gtp1_pma_rx_cfg=0DCE089
CSET gtp1_pma_tx_cfg=0DCE089
CSET gtp1_ppm_offset=0_(Synchronous)
CSET gtp1_preemphasis_level=Use_TXPREEMPHASIS_Port
CSET gtp1_protocol_file=Use_GTP0_settings
CSET gtp1_refclk_x0_y0=Use_GTP0_PLL
CSET gtp1_refclk_x0_y1=REFCLK0_X0Y1
CSET gtp1_refclk_x1_y0=REFCLK0_X1Y0
CSET gtp1_refclk_x1_y1=Use_GTP0_PLL
CSET gtp1_reference_clock=125.00
CSET gtp1_rx_datapath_width=32
CSET gtp1_rx_decode_seq_match=true
CSET gtp1_rx_divider=/2
CSET gtp1_rx_en_idle_hold_cdr=false
CSET gtp1_rx_en_idle_hold_dfe=false
CSET gtp1_rx_en_idle_reset_fr=false
CSET gtp1_rx_en_idle_reset_ph=false
CSET gtp1_rx_fifo_addr_mode=Fast
CSET gtp1_rx_idle_hi_cnt=1000
CSET gtp1_rx_idle_lo_cnt=0000
CSET gtp1_rx_line_rate=1.25
CSET gtp1_rx_oob_threshold=110
CSET gtp1_rx_slide_mode=PCS
CSET gtp1_rx_status_fmt=PCIe
CSET gtp1_rx_termination_voltage=VTTRX
CSET gtp1_rxlossofsyncport=true
CSET gtp1_rxprbserr_loopback=false
CSET gtp1_rxrundisp_indicates_cc=false
CSET gtp1_rxusrclk_source=TXOUTCLK
CSET gtp1_sata_rx_burst_val=4
CSET gtp1_sata_rx_idle_val=4
CSET gtp1_sata_tx_burst_val=15
CSET gtp1_second_order_cdr_loop=false
CSET gtp1_show_realign_comma=false
CSET gtp1_target_line_rate=1.25
CSET gtp1_termination_ctrl=10100
CSET gtp1_termination_imp=50
CSET gtp1_termination_ovrd=false
CSET gtp1_trans_time_from_p2=60
CSET gtp1_trans_time_non_p2=25
CSET gtp1_trans_time_rate=65535
CSET gtp1_trans_time_to_p2=100
CSET gtp1_tx_datapath_width=32
CSET gtp1_tx_divider=/2
CSET gtp1_tx_drive_mode=false
CSET gtp1_tx_line_rate=1.25
CSET gtp1_txrx_invert=011
CSET gtp1_txusrclk_source=TXOUTCLK
CSET gtp1_use_cc=false
CSET gtp1_use_comma_detect=true
CSET gtp1_use_port_enmcommaalign=true
CSET gtp1_use_port_enpcommaalign=true
CSET gtp1_use_port_loopback=true
CSET gtp1_use_port_phystatus=false
CSET gtp1_use_port_pllpowerdown=false
CSET gtp1_use_port_refclkout=false
CSET gtp1_use_port_refclkpowerdown=false
CSET gtp1_use_port_rxbufreset=false
CSET gtp1_use_port_rxbufstatus=false
CSET gtp1_use_port_rxbyteisaligned=false
CSET gtp1_use_port_rxbyterealign=false
CSET gtp1_use_port_rxcdrreset=false
CSET gtp1_use_port_rxchariscomma=false
CSET gtp1_use_port_rxcharisk=false
CSET gtp1_use_port_rxcommadet=false
CSET gtp1_use_port_rxlossofsync=true
CSET gtp1_use_port_rxpolarity=false
CSET gtp1_use_port_rxpowerdown=false
CSET gtp1_use_port_rxrecclk=false
CSET gtp1_use_port_rxreset=false
CSET gtp1_use_port_rxrundisp=false
CSET gtp1_use_port_rxslide=false
CSET gtp1_use_port_rxstatus=false
CSET gtp1_use_port_rxvalid=false
CSET gtp1_use_port_txbufstatus=false
CSET gtp1_use_port_txbypass8b10b=false
CSET gtp1_use_port_txchardispmode=false
CSET gtp1_use_port_txchardispval=false
CSET gtp1_use_port_txcomstart=false
CSET gtp1_use_port_txcomtype=false
CSET gtp1_use_port_txdetectrx=false
CSET gtp1_use_port_txelecidle=false
CSET gtp1_use_port_txenprbstst=false
CSET gtp1_use_port_txinhibit=false
CSET gtp1_use_port_txkerr=false
CSET gtp1_use_port_txoutclk=true
CSET gtp1_use_port_txpdownasynch=false
CSET gtp1_use_port_txpolarity=false
CSET gtp1_use_port_txpowerdown=false
CSET gtp1_use_port_txprbsforceerr=false
CSET gtp1_use_port_txreset=false
CSET gtp1_use_port_txrundisp=false
CSET gtp1_use_prbs_detector=false
CSET gtp1_use_resistor_cal_circuit=false
CSET gtp1_use_rx_eq=false
CSET gtp1_use_rx_oob=false
CSET gtp1_use_rxbuffer=true
CSET gtp1_use_two_cc_sequences=false
CSET gtp1_use_txbuffer=true
CSET gtp1_wideband_highpass_mix=Use_RXEQMIX_Port
CSET refclk_ac_coupling_x0_y0=false
CSET refclk_ac_coupling_x0_y1=false
CSET refclk_ac_coupling_x1_y0=false
CSET refclk_ac_coupling_x1_y1=false
CSET use_cb=false
CSET use_gtp_dual_x0_y0=false
CSET use_gtp_dual_x0_y1=true
CSET use_gtp_dual_x1_y0=true
CSET use_gtp_dual_x1_y1=false
CSET use_port_drp=false
CSET use_port_plllkdet=true
CSET use_port_plllkdeten=true
CSET use_two_cb_sequences=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-04-06T10:16:39.000Z
# END Extra information
GENERATE
# CRC: 9dfef97b
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test.xise 0 → 100644
View file @ b718a368
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fmc_refclk_test/example_design/mgt_usrclk_source_pll.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="fmc_refclk_test/example_design/frame_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="fmc_refclk_test/example_design/frame_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
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<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
Core name: Xilinx LogiCORE Spartan-6 FPGA GTP Transceiver Wizard
Version: 1.11
Release Date: October 19, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Other Information
8. Core Release History
9. Legal Disclaimer
================================================================================
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP Spartan-6 FPGA
GTP Transceiver Wizard v1.11 solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/intellectual-property/S6_FPGA_GTP_Transceiver_Wizard.htm">www.xilinx.com/products/intellectual-property/S6_FPGA_GTP_Transceiver_Wizard.htm</A>
2. NEW FEATURES
- ISE 13.3 software support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Spartan-6 XC LX/LXT
Spartan-6 XA LX/LXT
Spartan-6 XQ LX/LXT
4. RESOLVED ISSUES
1. Attribute Updates
Description: The following Attributes were updated :
- PMA_RX_CFG setting for PCIE
- RCV_TERM_VTTRX for SRIO, XAUI, SDI protocols
Version(s) Fixed:
CR 615296, 613303
2. Renamed REFCLKOUT to REFCLKPLL in GUI
Description: In page 4 of GUI, the options to choose TX/RXUSRCLK
source has been modified - REFCLKOUT is renamed to REFCLKPLL
Version(s) Fixed:
CR 620887
5. KNOWN ISSUES
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. OTHER INFORMATION
8. CORE RELEASE HISTORY
Date By Version Description
================================================================================
10/19/2011 Xilinx. Inc. 1.11 ISE 13.3 support
06/22/2011 Xilinx, Inc. 1.10 ISE 13.2 support
03/01/2011 Xilinx, Inc. 1.9 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
================================================================================
9. LEGAL DISCLAIMER
(c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/example_design/fmc_refclk_test_top.ucf 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : fmc_refclk_test_top.ucf
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
## Device: xc6slx150t
## Package: fgg900
################################## Clock Constraints ##########################
# User Clock Constraints
NET "tile0_txusrclk0_i" TNM_NET = "tile0_txusrclk0_i";
TIMESPEC "TS_tile0_txusrclk0_i" = PERIOD "tile0_txusrclk0_i" 8.0;
NET "tile0_txusrclk20_i" TNM_NET = "tile0_txusrclk20_i";
TIMESPEC "TS_tile0_txusrclk20_i" = PERIOD "tile0_txusrclk20_i" 32.0;
NET "tile1_txusrclk0_i" TNM_NET = "tile1_txusrclk0_i";
TIMESPEC "TS_tile1_txusrclk0_i" = PERIOD "tile1_txusrclk0_i" 8.0;
NET "tile1_txusrclk20_i" TNM_NET = "tile1_txusrclk20_i";
TIMESPEC "TS_tile1_txusrclk20_i" = PERIOD "tile1_txusrclk20_i" 32.0;
######################## locs for top level ports ######################
######################### mgt clock module constraints ########################
NET TILE0_GTP0_REFCLK_PAD_N_IN LOC=AH18;
NET TILE0_GTP0_REFCLK_PAD_P_IN LOC=AG18;
NET TILE1_GTP0_REFCLK_PAD_N_IN LOC=A13;
NET TILE1_GTP0_REFCLK_PAD_P_IN LOC=B13;
################################# mgt wrapper constraints #####################
##---------- Set placement for tile0_rocketio_wrapper_i/GTPA1_DUAL ------
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i LOC=GTPA1_DUAL_X1Y0;
##---------- Set placement for tile1_rocketio_wrapper_i/GTPA1_DUAL ------
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i LOC=GTPA1_DUAL_X0Y1;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/example_design/fmc_refclk_test_top.vhd 0 → 100755
View file @ b718a368
This source diff could not be displayed because it is too large. You can view the blob instead.
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/example_design/frame_check.vhd 0 → 100755
View file @ b718a368
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : frame_check.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module FRAME_CHECK
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***********************************Entity Declaration************************
entity FRAME_CHECK is
generic
(
RX_DATA_WIDTH : integer := 16;
USE_COMMA : integer := 1;
NONE_MSB_FIRST_DEC : integer := 0;
CHANBOND_SEQ_LEN : integer := 1;
WORDS_IN_BRAM : integer := 256;
CONFIG_INDEPENDENT_LANES : integer := 0;
START_OF_PACKET_CHAR : std_logic_vector := x"55fb";
MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port
(
-- User Interface
RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0);
RX_ENMCOMMA_ALIGN : out std_logic;
RX_ENPCOMMA_ALIGN : out std_logic;
RX_ENCHAN_SYNC : out std_logic;
RX_CHANBOND_SEQ : in std_logic;
-- Control Interface
INC_IN : in std_logic;
INC_OUT : out std_logic;
PATTERN_MATCH_N : out std_logic;
RESET_ON_ERROR : in std_logic;
-- Error Monitoring
ERROR_COUNT : out std_logic_vector(7 downto 0);
-- Track Data
TRACK_DATA : out std_logic;
-- System Interface
USER_CLK : in std_logic;
SYSTEM_RESET : in std_logic
);
end FRAME_CHECK;
architecture RTL of FRAME_CHECK is
--***********************************Parameter Declarations********************
constant DLY : time := 1 ns;
--***************************Internal Register Declarations********************
signal begin_r : std_logic;
signal data_error_detected_r : std_logic;
signal error_count_r : unsigned(8 downto 0);
signal error_detected_r : std_logic;
signal read_counter_i : unsigned(8 downto 0);
signal rx_chanbond_seq_r : std_logic;
signal rx_chanbond_seq_r2 : std_logic;
signal rx_chanbond_seq_r3 : std_logic;
signal rx_data_r : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal rx_data_r2 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal rx_data_r3 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal rx_data_r4 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal rx_data_r5 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal rx_data_r6 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal rx_data_r7 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal rx_data_r_track : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal start_of_packet_detected_r : std_logic;
signal track_data_r : std_logic;
signal track_data_r2 : std_logic;
signal track_data_r3 : std_logic;
signal track_data_r4 : std_logic;
signal sel : std_logic_vector(1 downto 0);
signal bram_data_r : std_logic_vector(31 downto 0);
--*********************************Wire Declarations***************************
signal bram_data_i : std_logic_vector(31 downto 0);
signal chanbondseq_in_data : std_logic;
signal error_detected_c : std_logic;
signal input_to_chanbond_data_i : std_logic;
signal input_to_chanbond_reg_i : std_logic;
signal next_begin_c : std_logic;
signal next_data_error_detected_c : std_logic;
signal next_track_data_c : std_logic;
signal start_of_packet_detected_c : std_logic;
signal rx_chanbond_reg : std_logic_vector((CHANBOND_SEQ_LEN-1) downto 0);
signal rx_chanbond_reg_bitwise_or_i: std_logic;
signal rx_data_aligned : std_logic_vector((RX_DATA_WIDTH-1) downto 0);
signal rx_data_has_start_char_c : std_logic;
signal rx_data_matches_bram_c : std_logic;
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
signal tied_to_vcc_i : std_logic;
--*********************************Main Body of Code***************************
begin
--_______________________ Static signal Assigments _______________________
tied_to_ground_i <= '0';
tied_to_ground_vec_i <= (others=>'0');
tied_to_vcc_i <= '1';
--______________________ Register RXDATA once to ease timing ______________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
rx_data_r <= RX_DATA ;
end if;
end process;
--________________________________ State machine __________________________
-- State registers
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if((RESET_ON_ERROR ='1') or (SYSTEM_RESET = '1')) then
begin_r <= '1' ;
track_data_r <= '0' ;
data_error_detected_r <= '0' ;
else
begin_r <= next_begin_c ;
track_data_r <= next_track_data_c ;
data_error_detected_r <= next_data_error_detected_c ;
end if;
end if;
end process;
-- Next state logic
next_begin_c <= (begin_r and not start_of_packet_detected_r) or data_error_detected_r ;
next_track_data_c <= (begin_r and start_of_packet_detected_r) or (track_data_r and not error_detected_r);
next_data_error_detected_c <= (track_data_r and error_detected_r);
start_of_packet_detected_c <= INC_IN when (CONFIG_INDEPENDENT_LANES=0) else rx_data_has_start_char_c;
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
start_of_packet_detected_r <= start_of_packet_detected_c ;
end if;
end process;
-- Registering for timing
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
track_data_r2 <= track_data_r ;
end if;
end process;
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
track_data_r3 <= track_data_r2 ;
end if;
end process;
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
track_data_r4 <= track_data_r3 ;
end if;
end process;
--______________________________ Capture incoming data ____________________
datapath_width_32_or_40: if ((RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=40)) generate
-- Comma realignment logic might be needed. 4 levels of registering for RXDATA to meet timing
-- In 4 Byte scenario, when align_comma_word=1, Comma can appear on any of the four bytes.
-- { BYTE3 | BYTE2 | BYTE1 | BYTE0 } - Comma can appear on BYTE0/1/2/3
-- If Comma appears on BYTE1/2/3, RX_DATA is realigned so that Comma appears on BYTE0 in rx_data_r_track
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if((RESET_ON_ERROR='1') or (SYSTEM_RESET='1')) then
sel <= "00";
elsif ((begin_r= '1') and (rx_chanbond_seq_r = '0')) then
-- if Comma appears on BYTE3 ..
if(rx_data_r((RX_DATA_WIDTH - 1) downto (3*(RX_DATA_WIDTH/4))) = START_OF_PACKET_CHAR) then
sel <= "11";
-- if Comma appears on BYTE2 ..
elsif(rx_data_r((3*(RX_DATA_WIDTH/4) - 1) downto (RX_DATA_WIDTH/2)) = START_OF_PACKET_CHAR) then
sel <= "01";
-- if Comma appears on BYTE1 ..
elsif(rx_data_r(((RX_DATA_WIDTH/2)-1) downto (RX_DATA_WIDTH/4)) = START_OF_PACKET_CHAR) then
sel <= "10";
-- if Comma appears on BYTE0 ..
elsif(rx_data_r(((RX_DATA_WIDTH/4) - 1) downto 0) = START_OF_PACKET_CHAR) then
sel <= "00";
end if;
end if;
end if;
end process;
none_msbfirst_decoding: if (NONE_MSB_FIRST_DEC=1) generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
rx_data_r3 <= (others => '0') ;
else
if(sel = "10") then
rx_data_r3 <= rx_data_r2(((RX_DATA_WIDTH/4) -1) downto 0) & rx_data_r((RX_DATA_WIDTH - 1) downto (RX_DATA_WIDTH/4)) ;
elsif(sel = "01") then
rx_data_r3 <= rx_data_r2(((RX_DATA_WIDTH/2) -1) downto 0) & rx_data_r((RX_DATA_WIDTH - 1) downto (RX_DATA_WIDTH/2)) ;
elsif(sel = "11") then
rx_data_r3 <= rx_data_r2((3*(RX_DATA_WIDTH/4) - 1) downto 0) & rx_data_r((RX_DATA_WIDTH-1) downto 3*(RX_DATA_WIDTH/4)) ;
else
rx_data_r3 <= rx_data_r2 ;
end if;
end if;
end if;
end process;
end generate none_msbfirst_decoding;
not_none_msbfirst_decoding: if (NONE_MSB_FIRST_DEC=0) generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
rx_data_r3 <= (others => '0') ;
else
if(sel = "10") then
rx_data_r3 <= rx_data_r(((RX_DATA_WIDTH/4) - 1) downto 0) & rx_data_r2((RX_DATA_WIDTH-1) downto (RX_DATA_WIDTH/4)) ;
elsif(sel = "01") then
rx_data_r3 <= rx_data_r(((RX_DATA_WIDTH/2) -1) downto 0) & rx_data_r2((RX_DATA_WIDTH - 1) downto (RX_DATA_WIDTH/2)) ;
elsif(sel = "11") then
rx_data_r3 <= rx_data_r((3*(RX_DATA_WIDTH/4) -1) downto 0) & rx_data_r2((RX_DATA_WIDTH - 1) downto 3*(RX_DATA_WIDTH/4)) ;
else
rx_data_r3 <= rx_data_r2 ;
end if;
end if;
end if;
end process;
end generate not_none_msbfirst_decoding;
end generate datapath_width_32_or_40;
datapath_width_16_or_20: if ((RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=20)) generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if((RESET_ON_ERROR='1') or (SYSTEM_RESET='1')) then
sel <= "00";
elsif ((begin_r= '1') and (rx_chanbond_seq_r = '0')) then
-- if Comma appears on BYTE0 ..
if(rx_data_r(((RX_DATA_WIDTH/2) - 1) downto 0) = START_OF_PACKET_CHAR) then
sel <= "00";
-- if Comma appears on BYTE1 ..
elsif(rx_data_r((RX_DATA_WIDTH-1) downto (RX_DATA_WIDTH/2)) = START_OF_PACKET_CHAR) then
sel <= "01";
end if;
end if;
end if;
end process;
none_msbfirst_decoding: if (NONE_MSB_FIRST_DEC=1) generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
rx_data_r3 <= (others => '0') ;
else
if(sel = "01") then
rx_data_r3 <= rx_data_r2(((RX_DATA_WIDTH/2) - 1) downto 0) & rx_data_r((RX_DATA_WIDTH-1) downto (RX_DATA_WIDTH/2)) ;
else
rx_data_r3 <= rx_data_r2 ;
end if;
end if;
end if;
end process;
end generate none_msbfirst_decoding;
not_none_msbfirst_decoding: if (NONE_MSB_FIRST_DEC=0) generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
rx_data_r3 <= (others => '0') ;
else
if(sel = "01") then
rx_data_r3 <= rx_data_r(((RX_DATA_WIDTH/2) - 1) downto 0) & rx_data_r2((RX_DATA_WIDTH-1) downto (RX_DATA_WIDTH/2)) ;
else
rx_data_r3 <= rx_data_r2 ;
end if;
end if;
end if;
end process;
end generate not_none_msbfirst_decoding;
end generate datapath_width_16_or_20;
datapath_width_32_40_16_or_20: if ((RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=20) or (RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=40)) generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
rx_data_r2 <= (others => '0') ;
rx_data_r4 <= (others => '0') ;
rx_data_r5 <= (others => '0') ;
rx_data_r6 <= (others => '0') ;
rx_data_r7 <= (others => '0') ;
rx_data_r_track <= (others => '0') ;
else
rx_data_r2 <= rx_data_r ;
rx_data_r4 <= rx_data_r3 ;
rx_data_r5 <= rx_data_r4 ;
rx_data_r6 <= rx_data_r5 ;
rx_data_r7 <= rx_data_r6 ;
rx_data_r_track <= rx_data_r7 ;
end if;
end if;
end process;
rx_data_aligned <= rx_data_r3;
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
rx_chanbond_seq_r <= RX_CHANBOND_SEQ ;
rx_chanbond_seq_r2 <= rx_chanbond_seq_r ;
rx_chanbond_seq_r3 <= rx_chanbond_seq_r2 ;
end if;
end process;
input_to_chanbond_reg_i <= rx_chanbond_seq_r2;
input_to_chanbond_data_i <= tied_to_ground_i;
end generate datapath_width_32_40_16_or_20;
datapath_width_8_or_10: if ((RX_DATA_WIDTH=8) or (RX_DATA_WIDTH=10)) generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
rx_data_r2 <= (others => '0') ;
rx_data_r3 <= (others => '0') ;
rx_data_r4 <= (others => '0') ;
rx_data_r5 <= (others => '0') ;
rx_data_r_track <= (others => '0') ;
else
rx_data_r2 <= rx_data_r ;
rx_data_r3 <= rx_data_r2 ;
rx_data_r4 <= rx_data_r3 ;
rx_data_r5 <= rx_data_r4 ;
rx_data_r_track <= rx_data_r5 ;
end if;
end if;
end process;
rx_data_aligned <= RX_DATA;
input_to_chanbond_reg_i <= RX_CHANBOND_SEQ;
input_to_chanbond_data_i <= RX_CHANBOND_SEQ;
end generate datapath_width_8_or_10;
--___________________________ Code for Channel bonding ____________________
-- code to prevent checking of clock correction sequences for the start of packet char
register_chan_seq: for i in 0 to (CHANBOND_SEQ_LEN-1) generate
case_i_equal_to_0: if (i=0) generate
rx_chanbond_reg_0 : FD port map (Q => rx_chanbond_reg(i),D => input_to_chanbond_reg_i,C => USER_CLK);
end generate case_i_equal_to_0;
case_i_greater_than_0: if (i>0) generate
rx_chanbond_reg_i :FD port map (Q => rx_chanbond_reg(i),D => rx_chanbond_reg(i-1),C => USER_CLK);
end generate case_i_greater_than_0;
end generate register_chan_seq;
chanbondseq_in_data <= input_to_chanbond_data_i or rx_chanbond_reg_bitwise_or_i;
process(rx_chanbond_reg)
variable rx_chanbond_var : std_logic;
variable i : std_logic;
begin
rx_chanbond_var := '0';
bit_wise_or : for i in 0 to (CHANBOND_SEQ_LEN-1) loop
rx_chanbond_var := rx_chanbond_var or rx_chanbond_reg(i);
end loop;
rx_chanbond_reg_bitwise_or_i <= rx_chanbond_var;
end process;
width_32_or_16_or_8 : if ((RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=8)) generate
rx_data_has_start_char_c <= '1' when ((rx_data_aligned(7 downto 0) = START_OF_PACKET_CHAR) and (chanbondseq_in_data='0')) else '0';
end generate width_32_or_16_or_8;
width_40_or_20_or_10 : if (((RX_DATA_WIDTH=40) or (RX_DATA_WIDTH=20)) or (RX_DATA_WIDTH=10)) generate
rx_data_has_start_char_c <= '1' when ((rx_data_aligned(9 downto 0) = START_OF_PACKET_CHAR) and (chanbondseq_in_data='0')) else '0';
end generate width_40_or_20_or_10;
--_____________________________ Assign output ports _______________________
INC_OUT <= start_of_packet_detected_c;
PATTERN_MATCH_N <= data_error_detected_r;
TRACK_DATA <= track_data_r;
-- Drive the enamcommaalign port of the mgt for alignment
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
RX_ENMCOMMA_ALIGN <= '0' ;
else
RX_ENMCOMMA_ALIGN <= '1' ;
end if;
end if;
end process;
-- Drive the enapcommaalign port of the mgt for alignment
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
RX_ENPCOMMA_ALIGN <= '0' ;
else
RX_ENPCOMMA_ALIGN <= '1' ;
end if;
end if;
end process;
-- Drive the enchansync port of the mgt for channel bonding
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET = '1') then
RX_ENCHAN_SYNC <= '0' ;
else
RX_ENCHAN_SYNC <= '1' ;
end if;
end if;
end process;
--___________________________ Check incoming data for errors ______________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
bram_data_r <= bram_data_i ;
end if;
end process;
--An error is detected when data read for the BRAM does not match the incoming data
use_40bit : if RX_DATA_WIDTH = 40 generate
rx_data_matches_bram_c <= '0' when (rx_data_r_track /= (tied_to_ground_vec_i(7 downto 0) & bram_data_r)) else '1';
end generate use_40bit;
not_40bit : if RX_DATA_WIDTH /= 40 generate
rx_data_matches_bram_c <= '0' when (rx_data_r_track /= bram_data_r((RX_DATA_WIDTH-1) downto 0)) else '1';
end generate not_40bit;
error_detected_c <= track_data_r4 and not rx_data_matches_bram_c;
enable_error_check : if USE_COMMA = 1 generate
--We register the error_detected signal for use with the error counter logic
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(not(track_data_r = '1')) then
error_detected_r <= '0' ;
else
error_detected_r <= error_detected_c ;
end if;
end if;
end process;
end generate enable_error_check;
disable_error_check : if USE_COMMA = 0 generate
-- Since the comma detect logic has not been enabled, the error counter has been disabled since
-- it doesnt make sense to be searching for an align character in the data. To enable the error
-- count again, please see the code above
error_detected_r <= '0';
end generate disable_error_check;
--We count the total number of errors we detect. By keeping a count we make it less likely that we will miss
--errors we did not directly observe. This counter must be reset when it reaches its max value
process ( USER_CLK )
begin
if( USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET='1') then
error_count_r <= (others => '0') ;
elsif(error_detected_r = '1') then
error_count_r <= error_count_r + 1 ;
end if;
end if;
end process;
--Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches
--max value) to the module output
ERROR_COUNT <= std_logic_vector(error_count_r(7 downto 0));
--____________________________ Counter to read from BRAM __________________________
four_byte : if RX_DATA_WIDTH > 20 generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))) then
read_counter_i <= (others => '0') ;
elsif(((start_of_packet_detected_r and not track_data_r)='1')) then
read_counter_i <= "000000001" ;
else read_counter_i <= read_counter_i + 1 ;
end if;
end if;
end process;
end generate four_byte;
one_or_two_byte : if RX_DATA_WIDTH <= 20 generate
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))
or ((start_of_packet_detected_r and not track_data_r)='1')) then
read_counter_i <= (others => '0') ;
else read_counter_i <= read_counter_i + 1 ;
end if;
end if;
end process;
end generate one_or_two_byte;
--________________________________ BRAM Instantiation _____________________________
dual_port_block_ram_i : RAMB16_S36_S36
generic map
(
INIT_00 => MEM_00,
INIT_01 => MEM_01,
INIT_02 => MEM_02,
INIT_03 => MEM_03,
INIT_04 => MEM_04,
INIT_05 => MEM_05,
INIT_06 => MEM_06,
INIT_07 => MEM_07,
INIT_08 => MEM_08,
INIT_09 => MEM_09,
INIT_0A => MEM_0A,
INIT_0B => MEM_0B,
INIT_0C => MEM_0C,
INIT_0D => MEM_0D,
INIT_0E => MEM_0E,
INIT_0F => MEM_0F,
INIT_10 => MEM_10,
INIT_11 => MEM_11,
INIT_12 => MEM_12,
INIT_13 => MEM_13,
INIT_14 => MEM_14,
INIT_15 => MEM_15,
INIT_16 => MEM_16,
INIT_17 => MEM_17,
INIT_18 => MEM_18,
INIT_19 => MEM_19,
INIT_1A => MEM_1A,
INIT_1B => MEM_1B,
INIT_1C => MEM_1C,
INIT_1D => MEM_1D,
INIT_1E => MEM_1E,
INIT_1F => MEM_1F,
INIT_20 => MEM_20,
INIT_21 => MEM_21,
INIT_22 => MEM_22,
INIT_23 => MEM_23,
INIT_24 => MEM_24,
INIT_25 => MEM_25,
INIT_26 => MEM_26,
INIT_27 => MEM_27,
INIT_28 => MEM_28,
INIT_29 => MEM_29,
INIT_2A => MEM_2A,
INIT_2B => MEM_2B,
INIT_2C => MEM_2C,
INIT_2D => MEM_2D,
INIT_2E => MEM_2E,
INIT_2F => MEM_2F,
INIT_30 => MEM_30,
INIT_31 => MEM_31,
INIT_32 => MEM_32,
INIT_33 => MEM_33,
INIT_34 => MEM_34,
INIT_35 => MEM_35,
INIT_36 => MEM_36,
INIT_37 => MEM_37,
INIT_38 => MEM_38,
INIT_39 => MEM_39,
INIT_3A => MEM_3A,
INIT_3B => MEM_3B,
INIT_3C => MEM_3C,
INIT_3D => MEM_3D,
INIT_3E => MEM_3E,
INIT_3F => MEM_3F,
INITP_00 => MEMP_00,
INITP_01 => MEMP_01,
INITP_02 => MEMP_02,
INITP_03 => MEMP_03,
INITP_04 => MEMP_04,
INITP_05 => MEMP_05,
INITP_06 => MEMP_06,
INITP_07 => MEMP_07
)
port map
(
ADDRA => std_logic_vector(read_counter_i),
DIA => tied_to_ground_vec_i(31 downto 0),
DIPA => tied_to_ground_vec_i(3 downto 0),
DOA => bram_data_i,
DOPA => open,
WEA => tied_to_ground_i,
ENA => tied_to_vcc_i,
SSRA => tied_to_ground_i,
CLKA => USER_CLK,
ADDRB => tied_to_ground_vec_i(8 downto 0),
DIB => tied_to_ground_vec_i(31 downto 0),
DIPB => tied_to_ground_vec_i(3 downto 0),
DOB => open,
DOPB => open,
WEB => tied_to_ground_i,
ENB => tied_to_ground_i,
SSRB => tied_to_ground_i,
CLKB => tied_to_ground_i
);
end RTL;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/example_design/frame_gen.vhd 0 → 100755
View file @ b718a368
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : frame_gen.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module FRAME_GEN
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizar
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***********************************Entity Declaration************************
entity FRAME_GEN is
generic
(
WORDS_IN_BRAM : integer := 256;
MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port
(
-- User Interface
TX_DATA : out std_logic_vector(39 downto 0);
TX_CHARISK : out std_logic_vector(3 downto 0);
-- System Interface
USER_CLK : in std_logic;
SYSTEM_RESET : in std_logic
);
end FRAME_GEN;
architecture RTL of FRAME_GEN is
--***********************************Parameter Declarations********************
constant DLY : time := 1 ns;
--********************************* Wire Declarations**************************
signal tx_charisk_i : std_logic_vector(3 downto 0);
signal tx_data_bram_i : std_logic_vector(31 downto 0);
signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
signal tied_to_ground_i : std_logic;
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(15 downto 0);
--***************************Internal signalister Declarations********************
signal read_counter_i : unsigned(8 downto 0);
--*********************************Main Body of Code***************************
begin
tied_to_ground_vec_i <= (others=>'0');
tied_to_ground_i <= '0';
tied_to_vcc_i <= '1';
--__________________________ Counter to read from BRAM ____________________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))then
read_counter_i <= (others => '0') ;
else
read_counter_i <= read_counter_i + 1 ;
end if;
end if;
end process;
-- Assign TX_DATA to BRAM output
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET='1') then
TX_DATA <= (others => '0') ;
else
TX_DATA <= (tied_to_ground_vec_i(7 downto 0) & tx_data_bram_i) ;
end if;
end if;
end process;
-- Assign TX_CHARISK to BRAM output
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(SYSTEM_RESET='1') then
TX_CHARISK <= (others => '0') ;
else
TX_CHARISK <= tx_charisk_i ;
end if;
end if;
end process;
--______________________________ BRAM Instantiation _______________________
dual_port_block_ram_i : RAMB16_S36_S36
generic map
(
INIT_00 => MEM_00,
INIT_01 => MEM_01,
INIT_02 => MEM_02,
INIT_03 => MEM_03,
INIT_04 => MEM_04,
INIT_05 => MEM_05,
INIT_06 => MEM_06,
INIT_07 => MEM_07,
INIT_08 => MEM_08,
INIT_09 => MEM_09,
INIT_0A => MEM_0A,
INIT_0B => MEM_0B,
INIT_0C => MEM_0C,
INIT_0D => MEM_0D,
INIT_0E => MEM_0E,
INIT_0F => MEM_0F,
INIT_10 => MEM_10,
INIT_11 => MEM_11,
INIT_12 => MEM_12,
INIT_13 => MEM_13,
INIT_14 => MEM_14,
INIT_15 => MEM_15,
INIT_16 => MEM_16,
INIT_17 => MEM_17,
INIT_18 => MEM_18,
INIT_19 => MEM_19,
INIT_1A => MEM_1A,
INIT_1B => MEM_1B,
INIT_1C => MEM_1C,
INIT_1D => MEM_1D,
INIT_1E => MEM_1E,
INIT_1F => MEM_1F,
INIT_20 => MEM_20,
INIT_21 => MEM_21,
INIT_22 => MEM_22,
INIT_23 => MEM_23,
INIT_24 => MEM_24,
INIT_25 => MEM_25,
INIT_26 => MEM_26,
INIT_27 => MEM_27,
INIT_28 => MEM_28,
INIT_29 => MEM_29,
INIT_2A => MEM_2A,
INIT_2B => MEM_2B,
INIT_2C => MEM_2C,
INIT_2D => MEM_2D,
INIT_2E => MEM_2E,
INIT_2F => MEM_2F,
INIT_30 => MEM_30,
INIT_31 => MEM_31,
INIT_32 => MEM_32,
INIT_33 => MEM_33,
INIT_34 => MEM_34,
INIT_35 => MEM_35,
INIT_36 => MEM_36,
INIT_37 => MEM_37,
INIT_38 => MEM_38,
INIT_39 => MEM_39,
INIT_3A => MEM_3A,
INIT_3B => MEM_3B,
INIT_3C => MEM_3C,
INIT_3D => MEM_3D,
INIT_3E => MEM_3E,
INIT_3F => MEM_3F,
INITP_00 => MEMP_00,
INITP_01 => MEMP_01,
INITP_02 => MEMP_02,
INITP_03 => MEMP_03,
INITP_04 => MEMP_04,
INITP_05 => MEMP_05,
INITP_06 => MEMP_06,
INITP_07 => MEMP_07
)
port map
(
ADDRA => std_logic_vector(read_counter_i),
DIA => tied_to_ground_vec_i(31 downto 0),
DIPA => tied_to_ground_vec_i(3 downto 0),
DOA => tx_data_bram_i,
DOPA => tx_charisk_i,
WEA => tied_to_ground_i,
ENA => tied_to_vcc_i,
SSRA => tied_to_ground_i,
CLKA => USER_CLK,
ADDRB => tied_to_ground_vec_i(8 downto 0),
DIB => tied_to_ground_vec_i(31 downto 0),
DIPB => tied_to_ground_vec_i(3 downto 0),
DOB => open,
DOPB => open,
WEB => tied_to_ground_i,
ENB => tied_to_ground_i,
SSRB => tied_to_ground_i,
CLKB => tied_to_ground_i
);
end RTL;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/example_design/gtp_attributes.ucf 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : gtp_attributes.ucf
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## GTP ATTRIBUTES
## This file contains the attributes for the active GTP transceivers in the
## design. If you would like to use this file in your design, please make
## sure that the path to the GTPA1_DUAL instance is correct.
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
############################## Active GTP Attributes #######################
##_____________________ Attributes for GTPA1_DUAL 0___________________
##PLL Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLKINDC_B_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLKRCV_TRST_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i OOB_CLK_DIVIDER_0 = 4;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_COM_CFG_0 = 24'h21680a;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_CP_CFG_0 = 8'h00;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_RXDIVSEL_OUT_0 = 2;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_SATA_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_SOURCE_0 = "PLL0";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_TXDIVSEL_OUT_0 = 2;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLLLKDET_CFG_0 = 3'b111;
##
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLKINDC_B_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLKRCV_TRST_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i OOB_CLK_DIVIDER_1 = 4;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_COM_CFG_1 = 24'h21680a;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_CP_CFG_1 = 8'h00;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_RXDIVSEL_OUT_1 = 2;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_SATA_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_SOURCE_1 = "PLL1";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLL_TXDIVSEL_OUT_1 = 2;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PLLLKDET_CFG_1 = 3'b111;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_COM_CFG_EAST = 36'h000008000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_COM_CFG_WEST = 36'h00000a000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TST_ATTR_0 = 32'h00000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TST_ATTR_1 = 32'h00000000;
##TX Interface Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_OUT_GTP_SEL_0 = "TXOUTCLK0";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_TDCC_CFG_0 = 2'b00;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_OUT_GTP_SEL_1 = "TXOUTCLK1";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_TDCC_CFG_1 = 2'b00;
##TX Buffer and Phase Alignment Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_TX_CFG_0 = 20'h00082;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_BUFFER_USE_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_XCLK_SEL_0 = "TXOUT";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TXRX_INVERT_0 = 3'b011;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_TX_CFG_1 = 20'h00082;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_BUFFER_USE_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_XCLK_SEL_1 = "TXOUT";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TXRX_INVERT_1 = 3'b011;
##TX Driver and OOB signalling Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CM_TRIM_0 = 2'b00;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_IDLE_DELAY_0 = 3'b011;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CM_TRIM_1 = 2'b00;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_IDLE_DELAY_1 = 3'b011;
##TX PIPE/SATA Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i COM_BURST_VAL_0 = 4'b1111;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i COM_BURST_VAL_1 = 4'b1111;
##RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i AC_CAP_DIS_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i OOBDETECT_THRESHOLD_0 = 3'b110;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_CDR_SCAN_0 = 27'h6404040;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_RX_CFG_0 = 25'h05ce008;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_RXSYNC_CFG_0 = 7'h00;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RCV_TERM_GND_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RCV_TERM_VTTRX_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RXEQ_CFG_0 = 8'b01111011;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TERMINATION_CTRL_0 = 5'b10100;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TERMINATION_OVRD_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_DETECT_RX_CFG_0 = 14'h1832;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i AC_CAP_DIS_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i OOBDETECT_THRESHOLD_1 = 3'b110;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_CDR_SCAN_1 = 27'h6404040;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_RX_CFG_1 = 25'h05ce008;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PMA_RXSYNC_CFG_1 = 7'h00;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RCV_TERM_GND_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RCV_TERM_VTTRX_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RXEQ_CFG_1 = 8'b01111011;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TERMINATION_CTRL_1 = 5'b10100;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TERMINATION_OVRD_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TX_DETECT_RX_CFG_1 = 14'h1832;
##PRBS Detection Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RXPRBSERR_LOOPBACK_0 = 1'b0;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RXPRBSERR_LOOPBACK_1 = 1'b0;
##Comma Detection and Alignment Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i ALIGN_COMMA_WORD_0 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i COMMA_10B_ENABLE_0 = 10'b1111111111;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i DEC_MCOMMA_DETECT_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i DEC_PCOMMA_DETECT_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i DEC_VALID_COMMA_ONLY_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i MCOMMA_10B_VALUE_0 = 10'b1010000011;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i MCOMMA_DETECT_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PCOMMA_10B_VALUE_0 = 10'b0101111100;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PCOMMA_DETECT_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_SLIDE_MODE_0 = "PCS";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i ALIGN_COMMA_WORD_1 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i COMMA_10B_ENABLE_1 = 10'b1111111111;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i DEC_MCOMMA_DETECT_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i DEC_PCOMMA_DETECT_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i DEC_VALID_COMMA_ONLY_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i MCOMMA_10B_VALUE_1 = 10'b1010000011;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i MCOMMA_DETECT_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PCOMMA_10B_VALUE_1 = 10'b0101111100;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PCOMMA_DETECT_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_SLIDE_MODE_1 = "PCS";
##RX Loss-of-sync State Machine Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_LOS_INVALID_INCR_0 = 8;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_LOS_THRESHOLD_0 = 128;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_LOSS_OF_SYNC_FSM_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_LOS_INVALID_INCR_1 = 8;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_LOS_THRESHOLD_1 = 128;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_LOSS_OF_SYNC_FSM_1 = "TRUE";
##RX Elastic Buffer and Phase alignment Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_BUFFER_USE_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_BUF_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_IDLE_HI_CNT_0 = 4'b1000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_IDLE_LO_CNT_0 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_XCLK_SEL_0 = "RXREC";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_BUFFER_USE_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_BUF_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_IDLE_HI_CNT_1 = 4'b1000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_IDLE_LO_CNT_1 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_XCLK_SEL_1 = "RXREC";
##Clock Correction Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_ADJ_LEN_0 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_DET_LEN_0 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_KEEP_IDLE_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_MAX_LAT_0 = 18;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_MIN_LAT_0 = 16;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_PRECEDENCE_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_REPEAT_WAIT_0 = 5;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_1_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_2_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_3_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_4_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_ENABLE_0 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_1_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_2_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_3_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_4_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_ENABLE_0 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_USE_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_CORRECT_USE_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_DECODE_SEQ_MATCH_0 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_ADJ_LEN_1 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_DET_LEN_1 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_KEEP_IDLE_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_MAX_LAT_1 = 18;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_MIN_LAT_1 = 16;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_PRECEDENCE_1 = "TRUE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_REPEAT_WAIT_1 = 5;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_1_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_2_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_3_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_4_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_ENABLE_1 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_1_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_2_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_3_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_4_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_ENABLE_1 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_USE_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CLK_CORRECT_USE_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_DECODE_SEQ_MATCH_1 = "TRUE";
##Channel Bonding Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_1_MAX_SKEW_0 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_2_MAX_SKEW_0 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_KEEP_ALIGN_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_1_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_2_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_3_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_4_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_ENABLE_0 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_1_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_2_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_3_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_4_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_ENABLE_0 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_USE_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_LEN_0 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_MODE_RESET_BUF_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_1_MAX_SKEW_1 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_2_MAX_SKEW_1 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_KEEP_ALIGN_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_1_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_2_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_3_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_4_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_ENABLE_1 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_1_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_2_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_3_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_4_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_ENABLE_1 = 4'b0000;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_USE_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_LEN_1 = 1;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_MODE_RESET_BUF_1 = "FALSE";
##RX PCI Express Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CB2_INH_CC_PERIOD_0 = 8;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CDR_PH_ADJ_TIME_0 = 5'b01010;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PCI_EXPRESS_MODE_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_HOLD_CDR_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_FR_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_PH_0 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_STATUS_FMT_0 = "PCIE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_FROM_P2_0 = 12'h03c;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_NON_P2_0 = 8'h19;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_TO_P2_0 = 10'h064;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CB2_INH_CC_PERIOD_1 = 8;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i CDR_PH_ADJ_TIME_1 = 5'b01010;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i PCI_EXPRESS_MODE_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_HOLD_CDR_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_FR_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_PH_1 = "FALSE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i RX_STATUS_FMT_1 = "PCIE";
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_FROM_P2_1 = 12'h03c;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_NON_P2_1 = 8'h19;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_TO_P2_1 = 10'h064;
##RX SATA Attributes
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_BURST_VAL_0 = 3'b100;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_IDLE_VAL_0 = 3'b100;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_BURST_0 = 9;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_INIT_0 = 27;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_WAKE_0 = 9;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_BURST_0 = 5;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_INIT_0 = 15;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_WAKE_0 = 5;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_BURST_VAL_1 = 3'b100;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_IDLE_VAL_1 = 3'b100;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_BURST_1 = 9;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_INIT_1 = 27;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_WAKE_1 = 9;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_BURST_1 = 5;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_INIT_1 = 15;
INST fmc_refclk_test_i/tile0_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_WAKE_1 = 5;
##_____________________ Attributes for GTPA1_DUAL 1___________________
##PLL Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLKINDC_B_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLKRCV_TRST_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i OOB_CLK_DIVIDER_0 = 4;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_COM_CFG_0 = 24'h21680a;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_CP_CFG_0 = 8'h00;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_RXDIVSEL_OUT_0 = 2;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_SATA_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_SOURCE_0 = "PLL0";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_TXDIVSEL_OUT_0 = 2;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLLLKDET_CFG_0 = 3'b111;
##
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLKINDC_B_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLKRCV_TRST_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i OOB_CLK_DIVIDER_1 = 4;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_COM_CFG_1 = 24'h21680a;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_CP_CFG_1 = 8'h00;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_RXDIVSEL_OUT_1 = 2;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_SATA_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_SOURCE_1 = "PLL1";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLL_TXDIVSEL_OUT_1 = 2;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PLLLKDET_CFG_1 = 3'b111;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_COM_CFG_EAST = 36'h000008000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_COM_CFG_WEST = 36'h00000a000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TST_ATTR_0 = 32'h00000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TST_ATTR_1 = 32'h00000000;
##TX Interface Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_OUT_GTP_SEL_0 = "TXOUTCLK0";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_TDCC_CFG_0 = 2'b00;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_OUT_GTP_SEL_1 = "TXOUTCLK1";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_TDCC_CFG_1 = 2'b00;
##TX Buffer and Phase Alignment Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_TX_CFG_0 = 20'h00082;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_BUFFER_USE_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_XCLK_SEL_0 = "TXOUT";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TXRX_INVERT_0 = 3'b011;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_TX_CFG_1 = 20'h00082;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_BUFFER_USE_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_XCLK_SEL_1 = "TXOUT";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TXRX_INVERT_1 = 3'b011;
##TX Driver and OOB signalling Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CM_TRIM_0 = 2'b00;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_IDLE_DELAY_0 = 3'b011;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CM_TRIM_1 = 2'b00;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_IDLE_DELAY_1 = 3'b011;
##TX PIPE/SATA Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i COM_BURST_VAL_0 = 4'b1111;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i COM_BURST_VAL_1 = 4'b1111;
##RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i AC_CAP_DIS_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i OOBDETECT_THRESHOLD_0 = 3'b110;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_CDR_SCAN_0 = 27'h6404040;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_RX_CFG_0 = 25'h05ce008;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_RXSYNC_CFG_0 = 7'h00;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RCV_TERM_GND_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RCV_TERM_VTTRX_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RXEQ_CFG_0 = 8'b01111011;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TERMINATION_CTRL_0 = 5'b10100;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TERMINATION_OVRD_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_DETECT_RX_CFG_0 = 14'h1832;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i AC_CAP_DIS_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i OOBDETECT_THRESHOLD_1 = 3'b110;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_CDR_SCAN_1 = 27'h6404040;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_RX_CFG_1 = 25'h05ce008;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PMA_RXSYNC_CFG_1 = 7'h00;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RCV_TERM_GND_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RCV_TERM_VTTRX_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RXEQ_CFG_1 = 8'b01111011;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TERMINATION_CTRL_1 = 5'b10100;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TERMINATION_OVRD_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TX_DETECT_RX_CFG_1 = 14'h1832;
##PRBS Detection Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RXPRBSERR_LOOPBACK_0 = 1'b0;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RXPRBSERR_LOOPBACK_1 = 1'b0;
##Comma Detection and Alignment Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i ALIGN_COMMA_WORD_0 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i COMMA_10B_ENABLE_0 = 10'b1111111111;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i DEC_MCOMMA_DETECT_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i DEC_PCOMMA_DETECT_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i DEC_VALID_COMMA_ONLY_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i MCOMMA_10B_VALUE_0 = 10'b1010000011;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i MCOMMA_DETECT_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PCOMMA_10B_VALUE_0 = 10'b0101111100;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PCOMMA_DETECT_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_SLIDE_MODE_0 = "PCS";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i ALIGN_COMMA_WORD_1 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i COMMA_10B_ENABLE_1 = 10'b1111111111;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i DEC_MCOMMA_DETECT_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i DEC_PCOMMA_DETECT_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i DEC_VALID_COMMA_ONLY_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i MCOMMA_10B_VALUE_1 = 10'b1010000011;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i MCOMMA_DETECT_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PCOMMA_10B_VALUE_1 = 10'b0101111100;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PCOMMA_DETECT_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_SLIDE_MODE_1 = "PCS";
##RX Loss-of-sync State Machine Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_LOS_INVALID_INCR_0 = 8;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_LOS_THRESHOLD_0 = 128;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_LOSS_OF_SYNC_FSM_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_LOS_INVALID_INCR_1 = 8;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_LOS_THRESHOLD_1 = 128;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_LOSS_OF_SYNC_FSM_1 = "TRUE";
##RX Elastic Buffer and Phase alignment Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_BUFFER_USE_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_BUF_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_IDLE_HI_CNT_0 = 4'b1000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_IDLE_LO_CNT_0 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_XCLK_SEL_0 = "RXREC";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_BUFFER_USE_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_BUF_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_IDLE_HI_CNT_1 = 4'b1000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_IDLE_LO_CNT_1 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_XCLK_SEL_1 = "RXREC";
##Clock Correction Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_ADJ_LEN_0 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_DET_LEN_0 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_KEEP_IDLE_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_MAX_LAT_0 = 18;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_MIN_LAT_0 = 16;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_PRECEDENCE_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_REPEAT_WAIT_0 = 5;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_1_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_2_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_3_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_4_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_ENABLE_0 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_1_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_2_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_3_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_4_0 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_ENABLE_0 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_USE_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_CORRECT_USE_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_DECODE_SEQ_MATCH_0 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_ADJ_LEN_1 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_DET_LEN_1 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_KEEP_IDLE_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_MAX_LAT_1 = 18;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_MIN_LAT_1 = 16;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_PRECEDENCE_1 = "TRUE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_REPEAT_WAIT_1 = 5;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_1_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_2_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_3_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_4_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_1_ENABLE_1 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_1_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_2_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_3_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_4_1 = 10'b0100000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_ENABLE_1 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_COR_SEQ_2_USE_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CLK_CORRECT_USE_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_DECODE_SEQ_MATCH_1 = "TRUE";
##Channel Bonding Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_1_MAX_SKEW_0 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_2_MAX_SKEW_0 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_KEEP_ALIGN_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_1_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_2_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_3_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_4_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_ENABLE_0 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_1_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_2_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_3_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_4_0 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_ENABLE_0 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_USE_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_LEN_0 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_MODE_RESET_BUF_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_1_MAX_SKEW_1 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_2_MAX_SKEW_1 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_KEEP_ALIGN_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_1_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_2_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_3_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_4_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_1_ENABLE_1 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_1_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_2_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_3_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_4_1 = 10'b0000000000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_ENABLE_1 = 4'b0000;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_2_USE_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CHAN_BOND_SEQ_LEN_1 = 1;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_MODE_RESET_BUF_1 = "FALSE";
##RX PCI Express Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CB2_INH_CC_PERIOD_0 = 8;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CDR_PH_ADJ_TIME_0 = 5'b01010;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PCI_EXPRESS_MODE_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_HOLD_CDR_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_FR_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_PH_0 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_STATUS_FMT_0 = "PCIE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_FROM_P2_0 = 12'h03c;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_NON_P2_0 = 8'h19;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_TO_P2_0 = 10'h064;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CB2_INH_CC_PERIOD_1 = 8;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i CDR_PH_ADJ_TIME_1 = 5'b01010;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i PCI_EXPRESS_MODE_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_HOLD_CDR_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_FR_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_EN_IDLE_RESET_PH_1 = "FALSE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i RX_STATUS_FMT_1 = "PCIE";
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_FROM_P2_1 = 12'h03c;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_NON_P2_1 = 8'h19;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i TRANS_TIME_TO_P2_1 = 10'h064;
##RX SATA Attributes
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_BURST_VAL_0 = 3'b100;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_IDLE_VAL_0 = 3'b100;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_BURST_0 = 9;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_INIT_0 = 27;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_WAKE_0 = 9;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_BURST_0 = 5;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_INIT_0 = 15;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_WAKE_0 = 5;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_BURST_VAL_1 = 3'b100;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_IDLE_VAL_1 = 3'b100;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_BURST_1 = 9;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_INIT_1 = 27;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MAX_WAKE_1 = 9;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_BURST_1 = 5;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_INIT_1 = 15;
INST fmc_refclk_test_i/tile1_fmc_refclk_test_i/gtpa1_dual_i SATA_MIN_WAKE_1 = 5;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/example_design/mgt_usrclk_source_pll.vhd 0 → 100755
View file @ b718a368
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : mgt_usrclk_source_pll.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module MGT_USRCLK_SOURCE_PLL (for use with GTP Transceivers)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***********************************Entity Declaration*******************************
entity MGT_USRCLK_SOURCE_PLL is
generic
(
MULT : integer := 2;
DIVIDE : integer := 2;
FEEDBACK : string := "CLKFBOUT";
CLK_PERIOD : real := 8.0;
OUT0_DIVIDE : integer := 2;
OUT1_DIVIDE : integer := 2;
OUT2_DIVIDE : integer := 2;
OUT3_DIVIDE : integer := 2
);
port
(
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic;
CLK_IN : in std_logic;
CLKFB_IN : in std_logic;
CLKFB_OUT : out std_logic;
PLL_LOCKED_OUT : out std_logic;
PLL_RESET_IN : in std_logic
);
end MGT_USRCLK_SOURCE_PLL;
architecture RTL of MGT_USRCLK_SOURCE_PLL is
--*********************************Wire Declarations**********************************
signal tied_to_ground_vec_i : std_logic_vector(15 downto 0);
signal tied_to_ground_i : std_logic;
signal tied_to_vcc_i : std_logic;
signal clkout0_i : std_logic;
signal clkout1_i : std_logic;
signal clkout2_i : std_logic;
signal clkout3_i : std_logic;
begin
--*********************************** Beginning of Code *******************************
-- Static signal Assigments
tied_to_ground_i <= '0';
tied_to_ground_vec_i <= (others=>'0');
tied_to_vcc_i <= '1';
-- Instantiate a PLL module to divide the reference clock. Uses internal feedback
-- for improved jitter performance, and to avoid consuming an additional BUFG
pll_adv_i : PLL_BASE
generic map
(
CLKFBOUT_MULT => MULT,
DIVCLK_DIVIDE => DIVIDE,
CLK_FEEDBACK => FEEDBACK,
CLKFBOUT_PHASE => 0.0,
COMPENSATION => "SYSTEM_SYNCHRONOUS",
CLKIN_PERIOD => CLK_PERIOD,
CLKOUT0_DIVIDE => OUT0_DIVIDE,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => OUT1_DIVIDE,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => OUT2_DIVIDE,
CLKOUT2_PHASE => 0.0,
CLKOUT3_DIVIDE => OUT3_DIVIDE,
CLKOUT3_PHASE => 0.0
)
port map
(
CLKIN => CLK_IN,
CLKFBIN => CLKFB_IN,
CLKOUT0 => clkout0_i,
CLKOUT1 => clkout1_i,
CLKOUT2 => clkout2_i,
CLKOUT3 => clkout3_i,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => CLKFB_OUT,
LOCKED => PLL_LOCKED_OUT,
RST => PLL_RESET_IN
);
clkout0_bufg_i : BUFG
port map
(
O => CLK0_OUT,
I => clkout0_i
);
clkout1_bufg_i : BUFG
port map
(
O => CLK1_OUT,
I => clkout1_i
);
clkout2_bufg_i : BUFG
port map
(
O => CLK2_OUT,
I => clkout2_i
);
clkout3_bufg_i : BUFG
port map
(
O => CLK3_OUT,
I => clkout3_i
);
end RTL;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/fmc_refclk_test.pf 0 → 100755
View file @ b718a368
description=User generated protocol
gtp0_target_line_rate=1.25
gtp0_pll_rate=1.25
gtp0_tx_line_rate=1.25
gtp0_tx_divider=/2
gtp0_tx_datapath_width=32
gtp0_encoding=8B/10B
gtp0_rx_line_rate=1.25
gtp0_rx_divider=/2
gtp0_rx_datapath_width=32
gtp0_decoding=8B/10B
gtp0_reference_clock=125.00
gtp1_target_line_rate=1.25
gtp1_pll_rate=1.25
gtp1_tx_line_rate=1.25
gtp1_tx_divider=/2
gtp1_tx_datapath_width=32
gtp1_encoding=8B/10B
gtp1_rx_line_rate=1.25
gtp1_rx_divider=/2
gtp1_rx_datapath_width=32
gtp1_decoding=8B/10B
gtp1_reference_clock=125.00
gtp0_use_port_txbypass8b10b=false
gtp0_use_port_txchardispmode=false
gtp0_use_port_txchardispval=false
gtp0_use_port_txkerr=false
gtp0_use_port_txrundisp=false
gtp0_use_port_rxchariscomma=false
gtp0_use_port_rxcharisk=false
gtp0_use_port_rxrundisp=false
gtp1_use_port_txbypass8b10b=false
gtp1_use_port_txchardispmode=false
gtp1_use_port_txchardispval=false
gtp1_use_port_txkerr=false
gtp1_use_port_txrundisp=false
gtp1_use_port_rxchariscomma=false
gtp1_use_port_rxcharisk=false
gtp1_use_port_rxrundisp=false
gtp0_use_txbuffer=true
gtp0_txusrclk_source=TXOUTCLK
gtp0_use_rxbuffer=true
gtp0_rxusrclk_source=TXOUTCLK
gtp0_use_port_rxreset=false
gtp0_use_port_rxrecclk=false
gtp0_use_port_rxbufstatus=false
gtp0_use_port_rxbufreset=false
gtp0_use_port_txoutclk=true
gtp0_use_port_txreset=false
gtp0_use_port_txbufstatus=false
gtp0_use_port_refclkout=false
gtp1_use_txbuffer=true
gtp1_txusrclk_source=TXOUTCLK
gtp1_use_rxbuffer=true
gtp1_rxusrclk_source=TXOUTCLK
gtp1_use_port_rxreset=false
gtp1_use_port_rxrecclk=false
gtp1_use_port_rxbufstatus=false
gtp1_use_port_rxbufreset=false
gtp1_use_port_txoutclk=true
gtp1_use_port_txreset=false
gtp1_use_port_txbufstatus=false
gtp1_use_port_refclkout=false
gtp0_use_comma_detect=true
gtp0_dec_valid_comma_only=false
gtp0_comma_preset=K28.5
gtp0_plus_comma=0101111100
gtp0_minus_comma=1010000011
gtp0_comma_mask=1111111111
gtp0_comma_alignment=Any_Byte_Boundary
gtp0_use_port_enpcommaalign=true
gtp0_use_port_enmcommaalign=true
gtp0_use_port_rxslide=false
gtp0_use_port_rxbyteisaligned=false
gtp0_use_port_rxbyterealign=false
gtp0_use_port_rxcommadet=false
gtp1_use_comma_detect=true
gtp1_dec_valid_comma_only=false
gtp1_comma_preset=K28.5
gtp1_plus_comma=0101111100
gtp1_minus_comma=1010000011
gtp1_comma_mask=1111111111
gtp1_comma_alignment=Any_Byte_Boundary
gtp1_use_port_enpcommaalign=true
gtp1_use_port_enmcommaalign=true
gtp1_use_port_rxslide=false
gtp1_use_port_rxbyteisaligned=false
gtp1_use_port_rxbyterealign=false
gtp1_use_port_rxcommadet=false
gtp0_preemphasis_level=Use_TXPREEMPHASIS_Port
gtp0_driver_swing=Use_TXDIFFCTRL_Port
gtp0_wideband_highpass_mix=Use_RXEQMIX_Port
gtp0_disable_ac_coupling=true
gtp0_rx_termination_voltage=VTTRX
gtp0_use_port_txpolarity=false
gtp0_use_port_txinhibit=false
gtp0_use_port_rxcdrreset=false
gtp0_use_port_rxpolarity=false
gtp1_preemphasis_level=Use_TXPREEMPHASIS_Port
gtp1_driver_swing=Use_TXDIFFCTRL_Port
gtp1_wideband_highpass_mix=Use_RXEQMIX_Port
gtp1_disable_ac_coupling=true
gtp1_rx_termination_voltage=VTTRX
gtp1_use_port_txpolarity=false
gtp1_use_port_txinhibit=false
gtp1_use_port_rxcdrreset=false
gtp1_use_port_rxpolarity=false
gtp0_use_rx_oob=false
gtp0_rx_oob_threshold=110
gtp0_use_prbs_detector=false
gtp0_use_port_txenprbstst=false
gtp0_use_port_txprbsforceerr=false
gtp0_use_port_rxlossofsync=true
gtp0_rxlossofsyncport=true
gtp0_errors_to_lose_sync=128
gtp0_bytes_to_reduce_error=8
gtp1_use_rx_oob=false
gtp1_rx_oob_threshold=110
gtp1_use_prbs_detector=false
gtp1_use_port_txenprbstst=false
gtp1_use_port_txprbsforceerr=false
gtp1_use_port_rxlossofsync=true
gtp1_rxlossofsyncport=true
gtp1_errors_to_lose_sync=128
gtp1_bytes_to_reduce_error=8
gtp0_rx_status_fmt=PCIe
gtp0_pci_express_mode=false
gtp0_sata_tx_burst_val=15
gtp0_sata_rx_burst_val=4
gtp0_sata_rx_idle_val=4
gtp0_trans_time_to_p2=100
gtp0_trans_time_from_p2=60
gtp0_trans_time_non_p2=25
gtp0_use_port_loopback=true
gtp0_use_port_rxpowerdown=false
gtp0_use_port_rxstatus=false
gtp0_use_port_rxvalid=false
gtp0_use_port_txcomstart=false
gtp0_use_port_txcomtype=false
gtp0_use_port_txpowerdown=false
gtp0_use_port_txdetectrx=false
gtp0_use_port_txelecidle=false
gtp0_use_port_phystatus=false
gtp1_rx_status_fmt=PCIe
gtp1_pci_express_mode=false
gtp1_sata_tx_burst_val=15
gtp1_sata_rx_burst_val=4
gtp1_sata_rx_idle_val=4
gtp1_trans_time_to_p2=100
gtp1_trans_time_from_p2=60
gtp1_trans_time_non_p2=25
gtp1_use_port_loopback=true
gtp1_use_port_rxpowerdown=false
gtp1_use_port_rxstatus=false
gtp1_use_port_rxvalid=false
gtp1_use_port_txcomstart=false
gtp1_use_port_txcomtype=false
gtp1_use_port_txpowerdown=false
gtp1_use_port_txdetectrx=false
gtp1_use_port_txelecidle=false
gtp1_use_port_phystatus=false
use_cb=false
use_two_cb_sequences=false
cb_sequence_length=1
cb_sequence_1_max_skew=1
cb_sequence_2_max_skew=1
cb_seq_1_1_mask=true
cb_seq_1_1=00000000
cb_seq_1_1_k=false
cb_seq_1_1_disp=false
cb_seq_1_2_mask=true
cb_seq_1_2=00000000
cb_seq_1_2_k=false
cb_seq_1_2_disp=false
cb_seq_1_3_mask=true
cb_seq_1_3=00000000
cb_seq_1_3_k=false
cb_seq_1_3_disp=false
cb_seq_1_4_mask=true
cb_seq_1_4=00000000
cb_seq_1_4_k=false
cb_seq_1_4_disp=false
cb_seq_2_1_mask=true
cb_seq_2_1=00000000
cb_seq_2_1_k=false
cb_seq_2_1_disp=false
cb_seq_2_2_mask=true
cb_seq_2_2=00000000
cb_seq_2_2_k=false
cb_seq_2_2_disp=false
cb_seq_2_3_mask=true
cb_seq_2_3=00000000
cb_seq_2_3_k=false
cb_seq_2_3_disp=false
cb_seq_2_4_mask=true
cb_seq_2_4=00000000
cb_seq_2_4_k=false
cb_seq_2_4_disp=false
gtp0_use_cc=false
gtp0_cc_sequence_length=1
gtp0_fifo_upper_bounds=18
gtp0_fifo_lower_bounds=16
gtp0_use_two_cc_sequences=false
gtp1_use_cc=false
gtp1_cc_sequence_length=1
gtp1_fifo_upper_bounds=18
gtp1_fifo_lower_bounds=16
gtp1_use_two_cc_sequences=false
gtp0_cc_seq_1_1_mask=true
gtp0_cc_seq_1_1=00000000
gtp0_cc_seq_1_1_k=true
gtp0_cc_seq_1_1_disp=false
gtp0_cc_seq_1_2_mask=true
gtp0_cc_seq_1_2=00000000
gtp0_cc_seq_1_2_k=true
gtp0_cc_seq_1_2_disp=false
gtp0_cc_seq_1_3_mask=true
gtp0_cc_seq_1_3=00000000
gtp0_cc_seq_1_3_k=true
gtp0_cc_seq_1_3_disp=false
gtp0_cc_seq_1_4_mask=true
gtp0_cc_seq_1_4=00000000
gtp0_cc_seq_1_4_k=true
gtp0_cc_seq_1_4_disp=false
gtp0_cc_seq_2_1_mask=true
gtp0_cc_seq_2_1=00000000
gtp0_cc_seq_2_1_k=true
gtp0_cc_seq_2_1_disp=false
gtp0_cc_seq_2_2_mask=true
gtp0_cc_seq_2_2=00000000
gtp0_cc_seq_2_2_k=true
gtp0_cc_seq_2_2_disp=false
gtp0_cc_seq_2_3_mask=true
gtp0_cc_seq_2_3=00000000
gtp0_cc_seq_2_3_k=true
gtp0_cc_seq_2_3_disp=false
gtp0_cc_seq_2_4_mask=true
gtp0_cc_seq_2_4=00000000
gtp0_cc_seq_2_4_k=true
gtp0_cc_seq_2_4_disp=false
gtp1_cc_seq_1_1_mask=true
gtp1_cc_seq_1_1=00000000
gtp1_cc_seq_1_1_k=true
gtp1_cc_seq_1_1_disp=false
gtp1_cc_seq_1_2_mask=true
gtp1_cc_seq_1_2=00000000
gtp1_cc_seq_1_2_k=true
gtp1_cc_seq_1_2_disp=false
gtp1_cc_seq_1_3_mask=true
gtp1_cc_seq_1_3=00000000
gtp1_cc_seq_1_3_k=true
gtp1_cc_seq_1_3_disp=false
gtp1_cc_seq_1_4_mask=true
gtp1_cc_seq_1_4=00000000
gtp1_cc_seq_1_4_k=true
gtp1_cc_seq_1_4_disp=false
gtp1_cc_seq_2_1_mask=true
gtp1_cc_seq_2_1=00000000
gtp1_cc_seq_2_1_k=true
gtp1_cc_seq_2_1_disp=false
gtp1_cc_seq_2_2_mask=true
gtp1_cc_seq_2_2=00000000
gtp1_cc_seq_2_2_k=true
gtp1_cc_seq_2_2_disp=false
gtp1_cc_seq_2_3_mask=true
gtp1_cc_seq_2_3=00000000
gtp1_cc_seq_2_3_k=true
gtp1_cc_seq_2_3_disp=false
gtp1_cc_seq_2_4_mask=true
gtp1_cc_seq_2_4=00000000
gtp1_cc_seq_2_4_k=true
gtp1_cc_seq_2_4_disp=false
gtp0_ppm_offset=0_(Synchronous)
gtp0_txrx_invert=011
gtp0_dec_mcomma_detect=false
gtp0_dec_pcomma_detect=false
gtp0_mcomma_detect=true
gtp0_pcomma_detect=true
gtp0_use_rx_eq=false
gtp0_termination_ctrl=10100
gtp0_termination_ovrd=false
gtp0_highpass_pole_location=Use_RXEQPOLE_Port
gtp0_use_resistor_cal_circuit=false
gtp0_second_order_cdr_loop=false
gtp0_use_port_pllpowerdown=false
gtp0_use_port_refclkpowerdown=false
gtp0_use_port_txpdownasynch=false
gtp0_rx_decode_seq_match=true
gtp0_rx_slide_mode=PCS
gtp0_termination_imp=50
gtp0_cdr_ph_adj_time=01010
gtp0_rx_en_idle_reset_fr=false
gtp0_rx_en_idle_hold_cdr=false
gtp0_rx_en_idle_reset_ph=false
gtp0_rx_en_idle_hold_dfe=false
gtp0_en_idle_reset_buf=false
gtp0_rx_idle_hi_cnt=1000
gtp0_rx_idle_lo_cnt=0000
gtp0_en_mode_reset_buf=false
gtp0_en_rate_reset_buf=false
gtp0_en_realign_reset_buf=false
gtp0_rx_fifo_addr_mode=Fast
gtp0_pma_cdr_scan=false
gtp0_pma_rx_cfg=0DCE089
gtp0_pma_tx_cfg=0DCE089
gtp0_rxprbserr_loopback=false
gtp0_show_realign_comma=false
gtp0_trans_time_rate=65535
gtp0_tx_drive_mode=false
gtp0_chan_bond_keep_align=false
gtp0_cb2_inh_cc_period=8
gtp0_rxrundisp_indicates_cc=false
gtp0_cc_keep_one_idle=false
gtp0_clk_cor_precedence=true
gtp0_clk_cor_repeat_wait=5
gtp1_ppm_offset=0_(Synchronous)
gtp1_txrx_invert=011
gtp1_dec_mcomma_detect=false
gtp1_dec_pcomma_detect=false
gtp1_mcomma_detect=true
gtp1_pcomma_detect=true
gtp1_use_rx_eq=false
gtp1_termination_ctrl=10100
gtp1_termination_ovrd=false
gtp1_highpass_pole_location=Use_RXEQPOLE_Port
gtp1_use_resistor_cal_circuit=false
gtp1_second_order_cdr_loop=false
gtp1_use_port_pllpowerdown=false
gtp1_use_port_refclkpowerdown=false
gtp1_use_port_txpdownasynch=false
gtp1_rx_decode_seq_match=true
gtp1_rx_slide_mode=PCS
gtp1_termination_imp=50
gtp1_cdr_ph_adj_time=01010
gtp1_rx_en_idle_reset_fr=false
gtp1_rx_en_idle_hold_cdr=false
gtp1_rx_en_idle_reset_ph=false
gtp1_rx_en_idle_hold_dfe=false
gtp1_en_idle_reset_buf=false
gtp1_rx_idle_hi_cnt=1000
gtp1_rx_idle_lo_cnt=0000
gtp1_en_mode_reset_buf=false
gtp1_en_rate_reset_buf=false
gtp1_en_realign_reset_buf=false
gtp1_rx_fifo_addr_mode=Fast
gtp1_pma_cdr_scan=false
gtp1_pma_rx_cfg=0DCE089
gtp1_pma_tx_cfg=0DCE089
gtp1_rxprbserr_loopback=false
gtp1_show_realign_comma=false
gtp1_trans_time_rate=65535
gtp1_tx_drive_mode=false
gtp1_chan_bond_keep_align=false
gtp1_cb2_inh_cc_period=8
gtp1_rxrundisp_indicates_cc=false
gtp1_cc_keep_one_idle=false
gtp1_clk_cor_precedence=true
gtp1_clk_cor_repeat_wait=5
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/chipscope_project.cpj 0 → 100755
View file @ b718a368
This source diff could not be displayed because it is too large. You can view the blob instead.
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/data_vio.ngc 0 → 100644
View file @ b718a368
This source diff could not be displayed because it is too large. You can view the blob instead.
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/icon.ngc 0 → 100644
View file @ b718a368
This source diff could not be displayed because it is too large. You can view the blob instead.
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/ila.ngc 0 → 100644
View file @ b718a368
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test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/implement.bat 0 → 100755
View file @ b718a368
REM
REM ____ ____
REM / /\/ /
REM /___/ \ / Vendor: Xilinx
REM \ \ \/ Version : 1.11
REM \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
REM / / Filename : implement_sh.ejava
REM /___/ /\
REM \ \ / \
REM \___\/\___\
REM
REM
REM implement.sh script
REM Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
REM
REM Set XST as default synthesizer
REM Read command line arguments
REM Change CWD to results
REM Clean results directory
REM Create results directory
REM Change current directory to results
ECHO WARNING: Removing existing results directory
RMDIR /S /Q results
MKDIR results
COPY xst.prj .\results\
COPY xst.scr .\results\
COPY *.ngc .\results\
REM Run Synthesis
ECHO "### Running Xst - "
xst -ifn xst.scr
COPY fmc_refclk_test_top.ngc .\results
cd .\results
REM Run ngdbuild
ngdbuild -uc ..\..\example_design\fmc_refclk_test_top.ucf -p xc6slx150t-fgg900-3 fmc_refclk_test_top.ngc fmc_refclk_test_top.ngd
REM end run ngdbuild section
REM Run map
ECHO 'Running NGD'
map -register_duplication on -global_opt speed -logic_opt on -retiming on -timing -ol high -p xc6slx150t-fgg900-3 -o mapped.ncd fmc_refclk_test_top.ngd
REM Run par
ECHO 'Running par'
par -ol high mapped.ncd routed.ncd
REM Report par results
ECHO 'Running design through bitgen'
bitgen -w routed.ncd
REM Trace Report
ECHO 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
REM Run netgen
ECHO 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -dir . -tm fmc_refclk_test_top -w routed.ncd routed.vhd
REM Change directory to implement
CD ..
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/implement.sh 0 → 100755
View file @ b718a368
#!/bin/bash
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : implement_sh.ejava
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## implement.sh script
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
#-----------------------------------------------------------------------------
# Script to synthesize and implement the RTL provided for the wizard
#-----------------------------------------------------------------------------
##---------------------Change CWD to results-------------------------------------
#Clean results directory
#Create results directory
#Change current directory to results
echo "WARNING: Removing existing results directory"
rm -rf results
mkdir results
cp xst.prj ./results
cp xst.scr ./results
cp *.ngc ./results
##-----------------------------Run Synthesis-------------------------------------
echo "### Running Xst - "
xst -ifn xst.scr
cp fmc_refclk_test_top.ngc ./results
cd ./results
##-------------------------------Run ngdbuild---------------------------------------
echo 'Running ngdbuild'
ngdbuild -uc ../../example_design/fmc_refclk_test_top.ucf -p xc6slx150t-fgg900-3 fmc_refclk_test_top.ngc fmc_refclk_test_top.ngd
#end run ngdbuild section
##-------------------------------Run map-------------------------------------------
echo 'Running map'
map -register_duplication on -global_opt speed -logic_opt on -retiming on -timing -ol high -p xc6slx150t-fgg900-3 -o mapped.ncd fmc_refclk_test_top.ngd
##-------------------------------Run par-------------------------------------------
echo 'Running par'
par -ol high mapped.ncd routed.ncd
##---------------------------Report par results-------------------------------------
echo 'Running design through bitgen'
bitgen -w routed.ncd
##-------------------------------Trace Report---------------------------------------
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
##-------------------------------Run netgen------------------------------------------
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -dir . -tm fmc_refclk_test_top -w routed.ncd routed.vhd
#Change directory to implement
cd ..
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/implement_synplify.bat 0 → 100755
View file @ b718a368
REM
REM ____ ____
REM / /\/ /
REM /___/ \ / Vendor: Xilinx
REM \ \ \/ Version : 1.11
REM \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
REM / / Filename : implement_synplify_bat.ejava
REM /___/ /\
REM \ \ / \
REM \___\/\___\
REM
REM
REM implement_synplify.bat script
REM Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
REM
REM Set XST as default synthesizer
REM Read command line arguments
REM Change CWD to results
REM Clean results directory
REM Create results directory
REM Change current directory to results
ECHO WARNING: Removing existing results directory
RMDIR /S /Q results
MKDIR results
COPY synplify.prj .\results\
COPY *.ngc .\results\
REM Run Synthesis
ECHO "### Running Synplify Pro - "
synplify_pro -batch synplify.prj
COPY fmc_refclk_test_top.edf .\results
cd .\results
REM Run ngdbuild
ngdbuild -uc ..\..\example_design\fmc_refclk_test_top.ucf -p xc6slx150t-fgg900-3 fmc_refclk_test_top.edf fmc_refclk_test_top.ngd
REM end run ngdbuild section
REM Run map
ECHO 'Running NGD'
map -register_duplication on -global_opt speed -logic_opt on -retiming on -timing -ol high -w -p xc6slx150t-fgg900-3 -o mapped.ncd fmc_refclk_test_top.ngd
REM Run par
ECHO 'Running par'
par -ol high -w mapped.ncd routed.ncd mapped.pcf
REM Report par results
ECHO 'Running design through bitgen'
bitgen -g GWE_cycle:Done -g GTS_cycle:Done -g DriveDone:Yes -g StartupClk:Cclk -w routed.ncd
REM Trace Report
ECHO 'Running trce'
trce -e -l 1000 -s -3 routed -o routed mapped.pcf
REM Run netgen
ECHO 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -dir . -tm fmc_refclk_test_top -w routed.ncd routed.vhd
REM Change directory to implement
CD ..
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/implement_synplify.sh 0 → 100755
View file @ b718a368
#!/bin/bash
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : implement_synplify_sh.ejava
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## implement_synplify.sh script
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
#-----------------------------------------------------------------------------
# Script to synthesize and implement the RTL provided for the wizard
#-----------------------------------------------------------------------------
##---------------------Change CWD to results-------------------------------------
#Clean results directory
#Create results directory
#Change current directory to results
echo "WARNING: Removing existing results directory"
rm -rf results
mkdir results
cp synplify.prj ./results
cp *.ngc ./results
##-----------------------------Run Synthesis-------------------------------------
echo "### Running Synplify Pro - "
synplify_pro -batch synplify.prj
cp fmc_refclk_test_top.edf ./results
cd ./results
##-------------------------------Run ngdbuild---------------------------------------
echo 'Running ngdbuild'
ngdbuild -uc ../../example_design/fmc_refclk_test_top.ucf -p xc6slx150t-fgg900-3 fmc_refclk_test_top.edf fmc_refclk_test_top.ngd
#end run ngdbuild section
##-------------------------------Run map-------------------------------------------
echo 'Running map'
map -register_duplication on -global_opt speed -logic_opt on -retiming on -timing -ol high -w -p xc6slx150t-fgg900-3 -o mapped.ncd fmc_refclk_test_top.ngd
##-------------------------------Run par-------------------------------------------
echo 'Running par'
par -ol high -w mapped.ncd routed.ncd mapped.pcf
##---------------------------Report par results-------------------------------------
echo 'Running design through bitgen'
bitgen -g GWE_cycle:Done -g GTS_cycle:Done -g DriveDone:Yes -g StartupClk:Cclk -w routed.ncd
##-------------------------------Trace Report---------------------------------------
echo 'Running trce'
trce -e -l 1000 -s -3 routed -o routed mapped.pcf
##-------------------------------Run netgen------------------------------------------
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -dir . -tm fmc_refclk_test_top -w routed.ncd routed.vhd
#Change directory to implement
cd ..
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/null_vio.ngc 0 → 100644
View file @ b718a368
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.5e
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36=;m1Co95Gbg9'0=<73`i1<75fe;29?l5>2900e8j50;9l1f<722wim>4?:483>5}#>908h6Fl4:Jab>"303:0en4?::kf>5<<a:31<75f5e83>>i2k3:17pl9e;293?6=8r.=<7;=;Ia7?Mda3->3655f4383>>o3;3:17d:;:188m13=831b8;4?::k73?6=3f?<6=44}c50>5<0290;w)8?:408Lf2<@kl0(9658:k76?6=3`>86=44i5694?=n<<0;66g;6;29?l202900c8950;9~f20=83=1<7>t$72917=Ok=1Cnk5+498;?l252900e9=50;9j01<722c?97>5;h65>5<<a==1<75`5683>>{e?>0;6:4?:1y'25<2:2Bh86Fmf:&7<?><a=81<75f4283>>o3<3:17d:::188m10=831b8:4?::m63?6=3th=j7>57;294~"183?97Em;;I`e?!2?211b8?4?::k77?6=3`>?6=44i5794?=n<?0;66g;7;29?j302900qo9?:186>5<7s-<;68>4Hb68Lg`<,=21;6g;2;29?l242900e9:50;9j00<722e>;7>5;|`45?6=?3:1<v*90;71?Me33Ahm7):7:2g8m14=831b8>4?::k70?6=3`>>6=44i5494?=n<>0;66a:7;29?xd0:3:1;7>50z&54?353Ai?7Eli;%6;>6d<a=81<75f4283>>o3<3:17d:::188m10=831b8:4?::m63?6=3th<87>57;294~"183?97Em;;I`e?!2?2:h0e9<50;9j06<722c?87>5;h66>5<<a=<1<75f4683>>i2?3:17pl85;292?6=8r.=<7;>;Ia7?Mda3->3645f4383>>o3;3:17d:;:188m13=831b8;4?::m63?6=3ty:>7>5az\26>;fm3i01l=5c:?b4?e<50i1o6368;a89<2=k272<7m4=9a9g>;?03i0q~?<:181[7434=<69:4}r37>5<5sW;?7098:578yv722909wS?:;<54>10<uz;=6=4={_35?8102==0q~?8:181[7034<n69=4}r3;>5<5sW;3708j:508yv7>2909wS?6;<4f>12<uz;j6=4={_3b?80b2=?0q~?m:181[7e34<n6984}r3`>5<5sW;h708j:558yv7c2909wS?k;<55>15<uz;n6=4={_3f?8142=90q~?i:181[7a34=869<4}r03>5<5sW8;709<:568yv462909wS<>;<50>13<uz896=4={_01?8142=<0q~<<:181[4434=86994}r07>5<5sW8?708i:518yv422909wS<:;<4e>14<uz8=6=4={_05?80a2=>0q~<8:181[4034<m69;4}r0;>5<5sW837099:508yv4>2909wS<6;<4e>10<uz8j6=4={_0b?80a2==0q~<m:181[4e34=;69=4}r0`>5<5sW8h709?:508yv4c2909wS<k;<53>12<uz8m6=4={_0e?8172=?0q~=?:181[5734<96894}r12>5<4sW9:708k:538920=<=1v><50;0xZ64<5><1885rs2194?4|V:901:85479~w62=839pR>:4=70901=:??0?;6s|3483>7}Y;<16;:4;3:p73<72;qU?;5276876>{t==0;64u2c480b>;1:3>8707i:2c89<d=;h165:4<a:?:7?5f342m6>o4=9`97d=:0>08m6s|5483>f}:k?0>463ne;g89d5=m27j<7k4=8a9a>;>03o014:5e:?:4?c<51i1i6378;g89=1=99164l4>0:p24<72;q6:?4;2:?ba?3d3ty=?7>59z?5`?3034k868j4=`291a=:1j0>h6368;7g?8?32<n014>55e9><f<2l27347;k;|q5g?6=:r7ji7=6;<56>01<uz<n6=4={<4f>01<5>;18?5rs7d94?4|5?l19:5270872>{t?90;6?u271863>;093><7p}81;296~;093?<709::508yv152909w09=:458923=<?1v:=50;0x925==>16;<4;3:p31<72;q6;94:7:?41?223ty<:7>52z?42?3034=:69:4}r54>5<5s4=<6894=63900=z{>21<7=t=9`955=:0l0:<6377;6`?xu013:1?v37f;33?8?528:015l54b9~w2g=839p14=5119>=3<68273j7:l;|q4f?6=;r72;7??;<;b>46<50918n5rs6a94?5|50h1==529d824>;>?3>h7p}8d;297~;>n3;;70o=:0289<d=<j1v:k50;0x9d3=99165k4;c:p3c<72;q6454<9:?;e?303ty3<7>52z?;g?5>342n6894}r:2>5<5s43;6>74=80912=z{181<7<t=8697<=:1?0>;6s|8283>7}:11085636a;74?xu?<3:1>v36c;1:?8?b2<=0q~6::1818g72:301l<5569~w=0=838p1l=5389>e0<2?2wxm;4?:2y><<<2?273;7;j;<:b>1d<uzk<6=4<{<:g>01<51h19h528d87f>{ti10;6>u290863>;?n3?n707=:5`8yvg>2908w07::4589<5==l165;4;b:ped<72:q6544:7:?:3?3b343j69l4}rca>5<4s43o6894=8`91`=:1l0?n6s|ab83>6}:i80>;636f;7f?8g52=h0q~ok:1818g32<=01l;54c9~wd`=838p1;:5569>31<3=2wxn=4?:3y>20<2?27<>7::;|qa5?6=:r7=:7;8;<57>11<uzh96=4={<44>01<5>818:5rsc194?4|5?219:5275872>{tj=0;6?u268863>;0:3>=7p}m5;296~;1i3?<709;:568yvd12909w08m:458924=<=1vo950;cx93d=<;16:l4;2:?5=?2534<369<4=75907=:>?0?>6395;61?8032=8015655b9><<<3:2wxn54?:`y>2g<3;27=m7:<;<4:>15<5?218>5266877>;1>3>8708::518932=<:164n4:c:?;`?253tyi57>5az?5f?2334<j69:4=7;901=:>10?86397;67?8012=>01;;5459>21<3<272<7;l;<;2>14<uzhj6=4n{<4a>13<5?k1885268871>;103>>7088:578930=<<16:84;5:?50?22343?68m4=87907=z{kh1<7=t=8:91f=:100?>6385;60?xuek3:18v36c;7`?8?c2=801:<5429>31<3;2wxni4?:5y>e5<2k27j=7:=;<51>14<5>>18?5rscg94?5|5h919n52a5876>;0=3>?7psa15794?7|@kl0qc?;6;295~Nen2we=9950;3xLg`<ug;?47>51zJab>{i9=31<7?tHcd8yk73i3:1=vFmf:m51d=83;pDoh4}o37g?6=9rBij6sa15f94?7|@kl0qc?;e;295~Nen2we=9h50;3xLg`<ug;><7>51zJab>{i9<;1<7?tHcd8yk72:3:1=vFmf:m505=83;pDoh4}o360?6=9rBij6sa14794?7|@kl0qc?:6;295~Nen2we=8950;3xLg`<ug;>47>51zJab>{i9<31<7?tHcd8yk72i3:1=vFmf:m50d=83;pDoh4}o36g?6=9rBij6sa14f94?7|@kl0qc?:e;295~Nen2we=8h50;3xLg`<ug;=<7>51zJab>{i9?;1<7?tHcd8yk71:3:1=vFmf:m535=83;pDoh4}o350?6=9rBij6sa17794?7|@kl0qc?96;295~Nen2we=;950;3xLg`<ug;=47>51zJab>{i9?31<7?tHcd8yk71i3:1=vFmf:m53d=83;pDoh4}o35g?6=9rBij6sa17f94?7|@kl0qc?9e;295~Nen2we=;h50;3xLg`<ug;<<7>51zJab>{i9>;1<7?tHcd8yk70:3:1=vFmf:m525=83;pDoh4}o340?6=9rBij6sa16794?7|@kl0qc?86;295~Nen2we=:950;3xLg`<ug;<47>51zJab>{i9>31<7?tHcd8yk70i3:1=vFmf:m52d=83;pDoh4}o34g?6=9rBij6sa16f94?7|@kl0qc?8e;295~Nen2we=:h50;3xLg`<ug;3<7>51zJab>{i91;1<7?tHcd8yk7?:3:1=vFmf:m5=5=83;pDoh4}o3;0?6=9rBij6sa19794?7|@kl0qc?76;295~Nen2we=5950;3xLg`<ug;347>51zJab>{i9131<7?tHcd8yk7?i3:1=vFmf:m5=d=83;pDoh4}o3;g?6=9rBij6sa19f94?7|@kl0qc?7e;295~Nen2we=5h50;3xLg`<ug;2<7>51zJab>{i90;1<7?tHcd8yk7>:3:1=vFmf:m5<5=83;pDoh4}o3:0?6=9rBij6sa18794?7|@kl0qc?66;295~Nen2we=4950;3xLg`<ug;247>51zJab>{i9031<7?tHcd8yk7>i3:1=vFmf:m5<d=83;pDoh4}o3:g?6=9rBij6sa18f94?7|@kl0qpsr@AAx5c1=m:k38n8n}ABA5{GHYqvLM
\ No newline at end of file
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/shared_vio.ngc 0 → 100644
View file @ b718a368
This source diff could not be displayed because it is too large. You can view the blob instead.
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/synplify.prj 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : synplify.prj
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## synplify.prj
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
add_file -vhdl "../example_design/mgt_usrclk_source_pll.vhd"
add_file -vhdl "../example_design/frame_gen.vhd"
add_file -vhdl "../example_design/frame_check.vhd"
add_file -vhdl "../../fmc_refclk_test_tile.vhd"
add_file -vhdl "../../fmc_refclk_test.vhd"
add_file -vhdl "../example_design/fmc_refclk_test_top.vhd"
project -result_file "fmc_refclk_test_top.edf"
set_option -top_module fmc_refclk_test_top
set_option -technology spartan6
set_option -part xc6slx150t
set_option -package fgg900
set_option -speed_grade -3
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
#map options
set_option -frequency 160.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -vlog_std v2001
#Do not generate ncf constraints file
set_option -write_apr_constraint 0
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/xst.prj 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : xst.prj
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## xst.prj
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
vhdl work "../example_design/mgt_usrclk_source_pll.vhd"
vhdl work "../example_design/frame_gen.vhd"
vhdl work "../example_design/frame_check.vhd"
vhdl work "../../fmc_refclk_test_tile.vhd"
vhdl work "../../fmc_refclk_test.vhd"
vhdl work "../example_design/fmc_refclk_test_top.vhd"
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/implement/xst.scr 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : xst.scr
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## xst.scr
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
run
-ifn xst.prj
-ifmt mixed
-ofn fmc_refclk_test_top.ngc
-ofmt NGC
-p xc6slx150t-3fgg900
-top fmc_refclk_test_top
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter ()
-case maintain
-slice_utilization_ratio 100
-fsm_extract YES
-fsm_encoding Auto
-ram_extract No
-ram_style Auto
-rom_extract No
-rom_style Auto
-shreg_extract YES
-resource_sharing YES
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 16
-register_duplication YES
-equivalent_register_removal YES
-register_balancing No
-signal_encoding user
-iob true
-slice_utilization_ratio_maxmargin 5
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/s6_gtpwizard_v1_11_readme.txt 0 → 100644
View file @ b718a368
Core name: Xilinx LogiCORE Spartan-6 FPGA GTP Transceiver Wizard
Version: 1.11
Release Date: October 19, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Other Information
8. Core Release History
9. Legal Disclaimer
================================================================================
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Spartan-6 FPGA
GTP Transceiver Wizard v1.11 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/S6_FPGA_GTP_Transceiver_Wizard.htm
2. NEW FEATURES
- ISE 13.3 software support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Spartan-6 XC LX/LXT
Spartan-6 XA LX/LXT
Spartan-6 XQ LX/LXT
4. RESOLVED ISSUES
1. Attribute Updates
Description: The following Attributes were updated :
- PMA_RX_CFG setting for PCIE
- RCV_TERM_VTTRX for SRIO, XAUI, SDI protocols
Version(s) Fixed:
CR 615296, 613303
2. Renamed REFCLKOUT to REFCLKPLL in GUI
Description: In page 4 of GUI, the options to choose TX/RXUSRCLK
source has been modified - REFCLKOUT is renamed to REFCLKPLL
Version(s) Fixed:
CR 620887
5. KNOWN ISSUES
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. OTHER INFORMATION
8. CORE RELEASE HISTORY
Date By Version Description
================================================================================
10/19/2011 Xilinx. Inc. 1.11 ISE 13.3 support
06/22/2011 Xilinx, Inc. 1.10 ISE 13.2 support
03/01/2011 Xilinx, Inc. 1.9 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
================================================================================
9. LEGAL DISCLAIMER
(c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/demo_tb.vhd 0 → 100755
View file @ b718a368
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : demo_tb.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module DEMO_TB
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library std; -- for Printing
use std.textio.all;
entity DEMO_TB is
end DEMO_TB;
architecture RTL of DEMO_TB is
--*************************Parameter Declarations******************************
constant GTP0_REFCLK_PERIOD : time := 8.0 ns;
constant GTP1_REFCLK_PERIOD : time := 8.0 ns;
--**************************** Component Declarations *************************
component fmc_refclk_test_top
generic
(
EXAMPLE_CONFIG_INDEPENDENT_LANES: integer := 1;
EXAMPLE_LANE_WITH_START_CHAR : integer := 0;
EXAMPLE_WORDS_IN_BRAM : integer := 512;
EXAMPLE_SIM_GTPRESET_SPEEDUP : integer := 1;
EXAMPLE_USE_CHIPSCOPE : integer := 0; --0 - drive resets from top level ports
EXAMPLE_SIMULATION : integer := 0 -- Set to 1 in testbench for simulation
);
port
(
TILE0_GTP0_REFCLK_PAD_N_IN : in std_logic;
TILE0_GTP0_REFCLK_PAD_P_IN : in std_logic;
TILE1_GTP0_REFCLK_PAD_N_IN : in std_logic;
TILE1_GTP0_REFCLK_PAD_P_IN : in std_logic;
GTP0_RESET_IN : in std_logic;
GTP1_RESET_IN : in std_logic;
TILE0_GTP0_PLLLKDET_OUT : out std_logic;
TILE0_GTP1_PLLLKDET_OUT : out std_logic;
TILE1_GTP0_PLLLKDET_OUT : out std_logic;
TILE1_GTP1_PLLLKDET_OUT : out std_logic;
TRACK_DATA_OUT : out std_logic;
RXN_IN : in std_logic_vector(3 downto 0);
RXP_IN : in std_logic_vector(3 downto 0);
TXN_OUT : out std_logic_vector(3 downto 0);
TXP_OUT : out std_logic_vector(3 downto 0)
);
end component;
component SIM_RESET_MGT_MODEL
port
(
GSR_IN : in std_logic
);
end component;
--************************Internal Register Declarations***********************
--************************** Register Declarations ****************************
signal gtp0_refclk_n_r : std_logic;
signal gtp1_refclk_n_r : std_logic;
signal drp_clk_r : std_logic;
signal gtp0_usrclk_r : std_logic;
signal gtp1_usrclk_r : std_logic;
signal gsr_r : std_logic;
signal gts_r : std_logic;
signal reset_i : std_logic;
signal track_data_high_r : std_logic;
signal track_data_low_r : std_logic;
--********************************Wire Declarations**********************************
----------------------------------- Global Signals ------------------------------
signal gtp0_refclk_p_r : std_logic;
signal gtp1_refclk_p_r : std_logic;
signal tied_to_ground_i : std_logic;
---------------------------- Example Module Connections -------------------------
signal rxn_in_i : std_logic_vector(3 downto 0);
signal rxp_in_i : std_logic_vector(3 downto 0);
signal txn_out_i : std_logic_vector(3 downto 0);
signal txp_out_i : std_logic_vector(3 downto 0);
signal tile0_gtp0_plllkdet_i : std_logic;
signal tile0_gtp1_plllkdet_i : std_logic;
signal tile1_gtp0_plllkdet_i : std_logic;
signal tile1_gtp1_plllkdet_i : std_logic;
signal track_data_i : std_logic;
--*********************************Main Body of Code**********************************
begin
-- ------------------------------- Tie offs -------------------------------
tied_to_ground_i <= '0';
-- ------------------------- MGT Serial Connections -----------------------
rxn_in_i <= txn_out_i;
rxp_in_i <= txp_out_i;
------- Instantiate the ROC module for resetting the VHDL MGT Smart Model ------
sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL
port map
(
GSR_IN => reset_i
);
---------------------- Generate Reference Clock input --------------------
process
begin
gtp0_refclk_n_r <= '1';
wait for GTP0_REFCLK_PERIOD/2;
gtp0_refclk_n_r <= '0';
wait for GTP0_REFCLK_PERIOD/2;
end process;
gtp0_refclk_p_r <= not gtp0_refclk_n_r;
process
begin
gtp1_refclk_n_r <= '1';
wait for GTP1_REFCLK_PERIOD/2;
gtp1_refclk_n_r <= '0';
wait for GTP1_REFCLK_PERIOD/2;
end process;
gtp1_refclk_p_r <= not gtp1_refclk_n_r;
---------------------------------- Resets ----------------------------------
process
begin
reset_i <= '1';
wait for 100 ns;
reset_i <= '0';
wait;
end process;
-------------------------------- Track Data --------------------------------
process
procedure tbprint (message : in string) is
variable outline : line;
begin
write(outline, string'("## Time: "));
write(outline, NOW, RIGHT, 0, ps);
write(outline, string'(" "));
write(outline, string'(message));
writeline(output,outline);
end tbprint;
begin
track_data_high_r <= '0';
wait for 47 us;
if (track_data_i = '1') then
track_data_high_r <= '1';
end if;
wait for 2 us;
if ((track_data_high_r = '1') and (track_data_low_r = '0')) then
tbprint("------- TEST PASSED -------");
assert false report "Simulation Stopped." severity failure;
else
tbprint("####### ERROR: TEST FAILED ! #######");
assert false report "Test Failed." severity failure;
end if;
end process;
process
begin
track_data_low_r <= '0';
wait for 47 us;
wait until track_data_i = '0';
track_data_low_r <= '1';
end process;
------------------- Instantiate an fmc_refclk_test_top module -----------------
fmc_refclk_test_top_i : fmc_refclk_test_top
generic map
(
EXAMPLE_SIMULATION => 1, -- Set to 1 for simulation
EXAMPLE_SIM_GTPRESET_SPEEDUP=> 1, -- Speedup is turned on for simulation
EXAMPLE_USE_CHIPSCOPE => 0 --1 - use chipscope to drive resets,
--0 - drive resets from top level ports
)
port map
(
TILE0_GTP0_REFCLK_PAD_N_IN => gtp0_refclk_n_r,
TILE0_GTP0_REFCLK_PAD_P_IN => gtp0_refclk_p_r,
TILE1_GTP0_REFCLK_PAD_N_IN => gtp0_refclk_n_r,
TILE1_GTP0_REFCLK_PAD_P_IN => gtp0_refclk_p_r,
GTP0_RESET_IN => reset_i,
GTP1_RESET_IN => reset_i,
TILE0_GTP0_PLLLKDET_OUT => tile0_gtp0_plllkdet_i,
TILE0_GTP1_PLLLKDET_OUT => tile0_gtp1_plllkdet_i,
TILE1_GTP0_PLLLKDET_OUT => tile1_gtp0_plllkdet_i,
TILE1_GTP1_PLLLKDET_OUT => tile1_gtp1_plllkdet_i,
TRACK_DATA_OUT => track_data_i,
RXN_IN => rxn_in_i,
RXP_IN => rxp_in_i,
TXN_OUT => txn_out_i,
TXP_OUT => txp_out_i
);
end RTL;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/demo_tb_imp.vhd 0 → 100755
View file @ b718a368
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : demo_tb_imp.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module DEMO_TB_IMP
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std; -- for Printing
use std.textio.all;
entity DEMO_TB_IMP is
end DEMO_TB_IMP;
architecture RTL of DEMO_TB_IMP is
--*************************Parameter Declarations******************************
constant GTP0_REFCLK_PERIOD : time := 8.0 ns;
constant GTP1_REFCLK_PERIOD : time := 8.0 ns;
--**************************** Component Declarations *************************
component fmc_refclk_test_top
port
(
TILE0_GTP0_REFCLK_PAD_N_IN : in std_logic;
TILE0_GTP0_REFCLK_PAD_P_IN : in std_logic;
TILE1_GTP0_REFCLK_PAD_N_IN : in std_logic;
TILE1_GTP0_REFCLK_PAD_P_IN : in std_logic;
GTP0_RESET_IN : in std_logic;
GTP1_RESET_IN : in std_logic;
TILE0_GTP0_PLLLKDET_OUT : out std_logic;
TILE0_GTP1_PLLLKDET_OUT : out std_logic;
TILE1_GTP0_PLLLKDET_OUT : out std_logic;
TILE1_GTP1_PLLLKDET_OUT : out std_logic;
TRACK_DATA_OUT : out std_logic;
RXN_IN : in std_logic_vector(3 downto 0);
RXP_IN : in std_logic_vector(3 downto 0);
TXN_OUT : out std_logic_vector(3 downto 0);
TXP_OUT : out std_logic_vector(3 downto 0)
);
end component;
--************************Internal Register Declarations***********************
--************************** Register Declarations ****************************
signal gtp0_refclk_n_r : std_logic;
signal gtp1_refclk_n_r : std_logic;
signal drp_clk_r : std_logic;
signal gtp0_usrclk_r : std_logic;
signal gtp1_usrclk_r : std_logic;
signal gsr_r : std_logic;
signal gts_r : std_logic;
signal reset_i : std_logic;
signal track_data_high_r : std_logic;
signal track_data_low_r : std_logic;
--********************************Wire Declarations**********************************
----------------------------------- Global Signals ------------------------------
signal gtp0_refclk_p_r : std_logic;
signal gtp1_refclk_p_r : std_logic;
signal tied_to_ground_i : std_logic;
---------------------------- Example Module Connections -------------------------
signal rxn_in_i : std_logic_vector(3 downto 0);
signal rxp_in_i : std_logic_vector(3 downto 0);
signal txn_out_i : std_logic_vector(3 downto 0);
signal txp_out_i : std_logic_vector(3 downto 0);
signal tile0_gtp0_plllkdet_i : std_logic;
signal tile0_gtp1_plllkdet_i : std_logic;
signal tile1_gtp0_plllkdet_i : std_logic;
signal tile1_gtp1_plllkdet_i : std_logic;
signal track_data_i : std_logic;
--*********************************Main Body of Code**********************************
begin
-- ------------------------------- Tie offs -------------------------------
tied_to_ground_i <= '0';
-- ------------------------- MGT Serial Connections -----------------------
rxn_in_i <= txn_out_i;
rxp_in_i <= txp_out_i;
---------------------- Generate Reference Clock input --------------------
process
begin
gtp0_refclk_n_r <= '1';
wait for GTP0_REFCLK_PERIOD/2;
gtp0_refclk_n_r <= '0';
wait for GTP0_REFCLK_PERIOD/2;
end process;
gtp0_refclk_p_r <= not gtp0_refclk_n_r;
process
begin
gtp1_refclk_n_r <= '1';
wait for GTP1_REFCLK_PERIOD/2;
gtp1_refclk_n_r <= '0';
wait for GTP1_REFCLK_PERIOD/2;
end process;
gtp1_refclk_p_r <= not gtp1_refclk_n_r;
---------------------------------- Resets ----------------------------------
process
begin
reset_i <= '1';
wait for 100 ns;
reset_i <= '0';
wait;
end process;
-------------------------------- Track Data --------------------------------
process
procedure tbprint (message : in string) is
variable outline : line;
begin
write(outline, string'("## Time: "));
write(outline, NOW, RIGHT, 0, ps);
write(outline, string'(" "));
write(outline, string'(message));
writeline(output,outline);
end tbprint;
begin
track_data_high_r <= '0';
wait for 197 us;
if (track_data_i = '1') then
track_data_high_r <= '1';
end if;
wait for 2 us;
if ((track_data_high_r = '1') and (track_data_low_r = '0')) then
tbprint("------- TEST PASSED -------");
assert false report "Simulation Stopped." severity failure;
else
tbprint("####### ERROR: TEST FAILED ! #######");
assert false report "Test Failed." severity failure;
end if;
end process;
process
begin
track_data_low_r <= '0';
wait for 197 us;
wait until track_data_i = '0';
track_data_low_r <= '1';
end process;
------------------- Instantiate an fmc_refclk_test_top module -----------------
fmc_refclk_test_top_i : fmc_refclk_test_top
port map
(
TILE0_GTP0_REFCLK_PAD_N_IN => gtp0_refclk_n_r,
TILE0_GTP0_REFCLK_PAD_P_IN => gtp0_refclk_p_r,
TILE1_GTP0_REFCLK_PAD_N_IN => gtp0_refclk_n_r,
TILE1_GTP0_REFCLK_PAD_P_IN => gtp0_refclk_p_r,
GTP0_RESET_IN => reset_i,
GTP1_RESET_IN => reset_i,
TILE0_GTP0_PLLLKDET_OUT => tile0_gtp0_plllkdet_i,
TILE0_GTP1_PLLLKDET_OUT => tile0_gtp1_plllkdet_i,
TILE1_GTP0_PLLLKDET_OUT => tile1_gtp0_plllkdet_i,
TILE1_GTP1_PLLLKDET_OUT => tile1_gtp1_plllkdet_i,
TRACK_DATA_OUT => track_data_i,
RXN_IN => rxn_in_i,
RXP_IN => rxp_in_i,
TXN_OUT => txn_out_i,
TXP_OUT => txp_out_i
);
end RTL;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/simulate_isim.bat 0 → 100755
View file @ b718a368
REM ################################################################################
REM ## ____ ____
REM ## / /\/ /
REM ## /___/ \ / Vendor: Xilinx
REM ## \ \ \/ Version : 1.11
REM ## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
REM ## / / Filename : simulate_isim.bat
REM ## /___/ /\
REM ## \ \ / \
REM ## \___\/\___\
REM ##
REM ##
REM ## Script SIMULATE_ISIM.BAT
REM ## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
REM ***************************** Beginning of Script ***************************
mkdir work
REM MGT Wrapper
vhpcomp -work work ..\..\..\fmc_refclk_test_tile.vhd
vhpcomp -work work ..\..\..\fmc_refclk_test.vhd
vhpcomp -work work ..\..\example_design\mgt_usrclk_source_pll.vhd
REM Example Design modules
vhpcomp -work work ..\..\example_design\frame_gen.vhd
vhpcomp -work work ..\..\example_design\frame_check.vhd
vhpcomp -work work ..\..\example_design\fmc_refclk_test_top.vhd
REM Other modules
vhpcomp -work work ..\sim_reset_mgt_model.vhd
REM Testbench file
vhpcomp -work work ..\demo_tb.vhd
REM Compile and link source files
fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe
REM ##--Generate waveform trace--##
.\demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/simulate_isim.sh 0 → 100755
View file @ b718a368
#!/bin/sh
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : simulate_isim.sh
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## Script SIMULATE_ISIM.SH
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##***************************** Beginning of Script ***************************
mkdir work
##MGT Wrapper
vhpcomp -work work ../../../fmc_refclk_test_tile.vhd;
vhpcomp -work work ../../../fmc_refclk_test.vhd;
vhpcomp -work work ../../example_design/mgt_usrclk_source_pll.vhd;
##Example Design modules
vhpcomp -work work ../../example_design/frame_gen.vhd;
vhpcomp -work work ../../example_design/frame_check.vhd;
vhpcomp -work work ../../example_design/fmc_refclk_test_top.vhd;
##Other modules
vhpcomp -work work ../sim_reset_mgt_model.vhd;
##Testbench file
vhpcomp -work work ../demo_tb.vhd;
#Compile and link source files
fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe
##--Generate waveform trace--##
./demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/simulate_mti.do 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 GTP Wizard
## / / Filename : simulate_mti.do
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## Script SIMULATE_MTI.DO
## Generated by Xilinx Spartan-6 GTP Wizard
##***************************** Beginning of Script ***************************
## If MTI_LIBS is defined, map unisim and simprim directories using MTI_LIBS
## This mode of mapping the unisims libraries is provided for backward
## compatibility with previous wizard releases. If you don't set MTI_LIBS
## the unisim libraries will be loaded from the paths set up by compxlib in
## your modelsim.ini file
set XILINX $env(XILINX)
if [info exists env(MTI_LIBS)] {
set MTI_LIBS $env(MTI_LIBS)
vlib UNISIM
vlib SECUREIP
vmap UNISIM $MTI_LIBS/unisim
vmap SECUREIP $MTI_LIBS/secureip
}
## Create and map work directory
vlib work
vmap work work
##MGT Wrapper
vcom -93 -work work ../../../fmc_refclk_test_tile.vhd;
vcom -93 -work work ../../../fmc_refclk_test.vhd;
vcom -93 -work work ../../example_design/mgt_usrclk_source_pll.vhd;
##Example Design modules
vcom -93 -work work ../../example_design/frame_gen.vhd;
vcom -93 -work work ../../example_design/frame_check.vhd;
vcom -93 -work work ../../example_design/fmc_refclk_test_top.vhd;
vcom -93 -work work ../demo_tb.vhd;
##Other modules
vcom -93 -work work ../sim_reset_mgt_model.vhd;
##Load Design
vsim -t 1ps work.DEMO_TB -voptargs="+acc"
##Load signals in wave window
view wave
do wave_mti.do
##Run simulation
run 50 us
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/simulate_ncsim.bat 0 → 100755
View file @ b718a368
REM ############################################################################
REM ____ ____
REM / /\/ /
REM /___/ \ / Vendor: Xilinx
REM \ \ \/ Version : 1.11
REM \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
REM / / Filename : simulate_ncsim.bat
REM /___/ /\
REM \ \ / \
REM \___\/\___\
REM
REM
REM Script SIMULATE_NCSIM.BAT
REM Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
REM
REM *************************** Beginning of Script ***************************
REM Ensure the follwoing
REM The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,
REM UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.
REM Variables LMC_HOME and XILINX are set
REM Define the mapping for the work library in cds.lib file. DEFINE work ./work
mkdir work
REM MGT Wrapper
ncvhdl -RELAX -V93 -work work ../../../fmc_refclk_test_tile.vhd;
ncvhdl -RELAX -V93 -work work ../../../fmc_refclk_test.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/mgt_usrclk_source_pll.vhd;
REM Example Design modules
ncvhdl -RELAX -V93 -work work ../../example_design/frame_gen.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/frame_check.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/fmc_refclk_test_top.vhd;
ncvhdl -RELAX -V93 -work work ../demo_tb.vhd;
REM Other modules
ncvhdl -RELAX -V93 -work work ../sim_reset_mgt_model.vhd;
REM Elaborate Design
ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB
ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv"
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/simulate_ncsim.sh 0 → 100755
View file @ b718a368
#!/bin/sh
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : simulate_ncsim.sh
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## Script SIMULATE_NCSIM.SH
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
##***************************** Beginning of Script ***************************
#Ensure the follwoing
#The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,
#UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.
#Variables LMC_HOME and XILINX are set
#Define the mapping for the work library in cds.lib file. DEFINE work ./work
mkdir work
##MGT Wrapper
ncvhdl -RELAX -V93 -work work ../../../fmc_refclk_test_tile.vhd;
ncvhdl -RELAX -V93 -work work ../../../fmc_refclk_test.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/mgt_usrclk_source_pll.vhd;
##Example Design modules
ncvhdl -RELAX -V93 -work work ../../example_design/frame_gen.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/frame_check.vhd;
ncvhdl -RELAX -V93 -work work ../../example_design/fmc_refclk_test_top.vhd;
ncvhdl -RELAX -V93 -work work ../demo_tb.vhd;
##Other modules
ncvhdl -RELAX -V93 -work work ../sim_reset_mgt_model.vhd;
##Elaborate Design
ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB
ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv"
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/simulate_vcs.sh 0 → 100755
View file @ b718a368
#!/bin/sh
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : simulate_vcs.sh
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## Script SIMULATE_VCS.SH
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
##
## (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##***************************** Beginning of Script ***************************
rm -rf simv* csrc DVEfiles AN.DB
vhdlan \
../../../fmc_refclk_test_tile.vhd \
../../../fmc_refclk_test.vhd \
../../example_design/mgt_usrclk_source_pll.vhd \
../../example_design/frame_gen.vhd \
../../example_design/frame_check.vhd \
../../example_design/fmc_refclk_test_top.vhd \
../demo_tb.vhd
vcs +vcs+lic+wait \
-debug \
DEMO_TB
./simv -ucli -i ucli_commands.key
dve -vpd vcdplus.vpd -session vcs_session.tcl
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/ucli_commands.key 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : ucli_commands.key
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## Script UCLI_COMMANDS.KEY
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
## (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
call {$vcdpluson}
run
call {$vcdplusclose}
quit
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/vcs_session.tcl 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : vcs_session.tcl
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
##
## Script VCS_SESSION.TCL
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
##
## (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
gui_open_window Wave
gui_sg_create fmc_refclk_test_Group
gui_list_add_group -id Wave.1 {fmc_refclk_test_Group}
gui_sg_addsignal -group fmc_refclk_test_Group {{FRAME_CHECK_MODULE}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:begin_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:track_data_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:data_error_detected_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:start_of_packet_detected_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:RX_DATA}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:ERROR_COUNT}
gui_sg_addsignal -group fmc_refclk_test_Group {{FRAME_CHECK_MODULE}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:begin_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:track_data_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:data_error_detected_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:start_of_packet_detected_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:RX_DATA}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile0_frame_check:ERROR_COUNT}
gui_sg_addsignal -group fmc_refclk_test_Group {{FRAME_CHECK_MODULE}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:begin_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:track_data_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:data_error_detected_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:start_of_packet_detected_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:RX_DATA}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:ERROR_COUNT}
gui_sg_addsignal -group fmc_refclk_test_Group {{FRAME_CHECK_MODULE}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:begin_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:track_data_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:data_error_detected_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:start_of_packet_detected_r}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:RX_DATA}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:tile1_frame_check:ERROR_COUNT}
gui_sg_addsignal -group fmc_refclk_test_Group {{TILE0_fmc_refclk_test}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {{Loopback and Powerdown Ports}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:LOOPBACK0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:LOOPBACK1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{PLL Ports}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:CLK00_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:CLK01_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:GTPRESET0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:GTPRESET1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:PLLLKDET0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:PLLLKDET1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RESETDONE0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RESETDONE1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - 8b10b Decoder}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXDISPERR0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXDISPERR1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXNOTINTABLE0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXNOTINTABLE1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - Comma Detection and Alignment}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXENMCOMMAALIGN0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXENMCOMMAALIGN1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXENPCOMMAALIGN0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXENPCOMMAALIGN1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - RX Data Path interface}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXDATA0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXDATA1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXUSRCLK0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXUSRCLK1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXUSRCLK20_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXUSRCLK21_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXEQMIX0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXEQMIX1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXN0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXN1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXP0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXP1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - RX Loss-of-sync State Machine}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXLOSSOFSYNC0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXLOSSOFSYNC1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {{TX/RX Datapath Ports}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:GTPCLKOUT0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:GTPCLKOUT1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {{Transmit Ports - 8b10b Encoder Control}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXCHARISK0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXCHARISK1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Transmit Ports - TX Data Path interface}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXDATA0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXDATA1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXOUTCLK0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXOUTCLK1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXUSRCLK0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXUSRCLK1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXUSRCLK20_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXUSRCLK21_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Transmit Ports - TX Driver and OOB signalling}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXDIFFCTRL0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXDIFFCTRL1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXN0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXN1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXP0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXP1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXPREEMPHASIS0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXPREEMPHASIS1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{TILE1_fmc_refclk_test}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {{Loopback and Powerdown Ports}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:LOOPBACK0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:LOOPBACK1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{PLL Ports}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:CLK00_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:CLK01_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:GTPRESET0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:GTPRESET1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:PLLLKDET0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:PLLLKDET1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RESETDONE0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RESETDONE1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - 8b10b Decoder}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXDISPERR0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXDISPERR1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXNOTINTABLE0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXNOTINTABLE1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - Comma Detection and Alignment}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXENMCOMMAALIGN0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXENMCOMMAALIGN1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXENPCOMMAALIGN0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXENPCOMMAALIGN1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - RX Data Path interface}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXDATA0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXDATA1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXUSRCLK0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXUSRCLK1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXUSRCLK20_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXUSRCLK21_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXEQMIX0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXEQMIX1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXN0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXN1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXP0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXP1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Receive Ports - RX Loss-of-sync State Machine}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXLOSSOFSYNC0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXLOSSOFSYNC1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {{TX/RX Datapath Ports}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:GTPCLKOUT0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:GTPCLKOUT1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {{Transmit Ports - 8b10b Encoder Control}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXCHARISK0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXCHARISK1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Transmit Ports - TX Data Path interface}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXDATA0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXDATA1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXOUTCLK0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXOUTCLK1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXUSRCLK0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXUSRCLK1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXUSRCLK20_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXUSRCLK21_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {{Transmit Ports - TX Driver and OOB signalling}} -divider
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXDIFFCTRL0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXDIFFCTRL1_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXN0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXN1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXP0_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXP1_OUT}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXPREEMPHASIS0_IN}
gui_sg_addsignal -group fmc_refclk_test_Group {:fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXPREEMPHASIS1_IN}
gui_zoom -window Wave.1 -full
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/wave_isim.tcl 0 → 100755
View file @ b718a368
###############################################################################
## isim_wave.tcl
###############################################################################
onerror {resume}
wcfg new
divider add "FRAME CHECK MODULE tile0_frame_check0"
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check0/begin_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check0/track_data_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check0/data_error_detected_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check0/start_of_packet_detected_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check0/RX_DATA
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check0/ERROR_COUNT
divider add "FRAME CHECK MODULE tile0_frame_check1"
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check1/begin_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check1/track_data_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check1/data_error_detected_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check1/start_of_packet_detected_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check1/RX_DATA
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE0_frame_check1/ERROR_COUNT
divider add "FRAME CHECK MODULE tile0_frame_check0"
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check0/begin_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check0/track_data_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check0/data_error_detected_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check0/start_of_packet_detected_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check0/RX_DATA
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check0/ERROR_COUNT
divider add "FRAME CHECK MODULE tile0_frame_check1"
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check1/begin_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check1/track_data_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check1/data_error_detected_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check1/start_of_packet_detected_r
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check1/RX_DATA
wave add /DEMO_TB/fmc_refclk_test_top_i/TILE1_frame_check1/ERROR_COUNT
divider add "Loopback and Powerdown Ports"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/LOOPBACK0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/LOOPBACK1_IN
divider add "PLL Ports"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/CLK00_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/CLK01_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/GTPRESET0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/GTPRESET1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/PLLLKDET0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/PLLLKDET1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RESETDONE0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RESETDONE1_OUT
divider add "Receive Ports - 8b10b Decoder"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXDISPERR0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXDISPERR1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXNOTINTABLE0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXNOTINTABLE1_OUT
divider add "Receive Ports - Comma Detection and Alignment"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXENMCOMMAALIGN0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXENMCOMMAALIGN1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXENPCOMMAALIGN0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXENPCOMMAALIGN1_IN
divider add "Receive Ports - RX Data Path interface"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXDATA0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXDATA1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXUSRCLK0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXUSRCLK1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXUSRCLK20_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXUSRCLK21_IN
divider add "Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXEQMIX0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXEQMIX1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXN0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXN1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXP0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXP1_IN
divider add "Receive Ports - RX Loss-of-sync State Machine"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXLOSSOFSYNC0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXLOSSOFSYNC1_OUT
divider add "TX/RX Datapath Ports"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/GTPCLKOUT0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/GTPCLKOUT1_OUT
divider add "Transmit Ports - 8b10b Encoder Control"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXCHARISK0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXCHARISK1_IN
divider add "Transmit Ports - TX Data Path interface"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXDATA0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXDATA1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXOUTCLK0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXOUTCLK1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXUSRCLK0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXUSRCLK1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXUSRCLK20_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXUSRCLK21_IN
divider add "Transmit Ports - TX Driver and OOB signalling"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXDIFFCTRL0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXDIFFCTRL1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXN0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXN1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXP0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXP1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXPREEMPHASIS0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXPREEMPHASIS1_IN
divider add "Loopback and Powerdown Ports"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/LOOPBACK0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/LOOPBACK1_IN
divider add "PLL Ports"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/CLK00_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/CLK01_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/GTPRESET0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/GTPRESET1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/PLLLKDET0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/PLLLKDET1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RESETDONE0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RESETDONE1_OUT
divider add "Receive Ports - 8b10b Decoder"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXDISPERR0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXDISPERR1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXNOTINTABLE0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXNOTINTABLE1_OUT
divider add "Receive Ports - Comma Detection and Alignment"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXENMCOMMAALIGN0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXENMCOMMAALIGN1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXENPCOMMAALIGN0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXENPCOMMAALIGN1_IN
divider add "Receive Ports - RX Data Path interface"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXDATA0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXDATA1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXUSRCLK0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXUSRCLK1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXUSRCLK20_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXUSRCLK21_IN
divider add "Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXEQMIX0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXEQMIX1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXN0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXN1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXP0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXP1_IN
divider add "Receive Ports - RX Loss-of-sync State Machine"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXLOSSOFSYNC0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXLOSSOFSYNC1_OUT
divider add "TX/RX Datapath Ports"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/GTPCLKOUT0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/GTPCLKOUT1_OUT
divider add "Transmit Ports - 8b10b Encoder Control"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXCHARISK0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXCHARISK1_IN
divider add "Transmit Ports - TX Data Path interface"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXDATA0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXDATA1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXOUTCLK0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXOUTCLK1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXUSRCLK0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXUSRCLK1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXUSRCLK20_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXUSRCLK21_IN
divider add "Transmit Ports - TX Driver and OOB signalling"
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXDIFFCTRL0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXDIFFCTRL1_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXN0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXN1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXP0_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXP1_OUT
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXPREEMPHASIS0_IN
wave add /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXPREEMPHASIS1_IN
run 50 us
quit
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/wave_mti.do 0 → 100755
View file @ b718a368
###############################################################################
## wave_mti.do
###############################################################################
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {FRAME CHECK MODULE tile0_frame_check0 }
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check0/begin_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check0/track_data_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check0/data_error_detected_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check0/start_of_packet_detected_r
add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check0/RX_DATA
add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check0/ERROR_COUNT
add wave -noupdate -divider {FRAME CHECK MODULE tile0_frame_check1 }
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check1/begin_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check1/track_data_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check1/data_error_detected_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check1/start_of_packet_detected_r
add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check1/RX_DATA
add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/tile0_frame_check1/ERROR_COUNT
add wave -noupdate -divider {FRAME CHECK MODULE tile1_frame_check0 }
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check0/begin_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check0/track_data_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check0/data_error_detected_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check0/start_of_packet_detected_r
add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check0/RX_DATA
add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check0/ERROR_COUNT
add wave -noupdate -divider {FRAME CHECK MODULE tile1_frame_check1 }
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check1/begin_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check1/track_data_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check1/data_error_detected_r
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check1/start_of_packet_detected_r
add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check1/RX_DATA
add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/tile1_frame_check1/ERROR_COUNT
add wave -noupdate -divider {TILE0_fmc_refclk_test }
add wave -noupdate -divider {Loopback and Powerdown Ports }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/LOOPBACK0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/LOOPBACK1_IN
add wave -noupdate -divider {PLL Ports }
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/CLK00_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/CLK01_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/GTPRESET0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/GTPRESET1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/PLLLKDET0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/PLLLKDET1_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RESETDONE0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RESETDONE1_OUT
add wave -noupdate -divider {Receive Ports - 8b10b Decoder }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXDISPERR0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXDISPERR1_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXNOTINTABLE0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXNOTINTABLE1_OUT
add wave -noupdate -divider {Receive Ports - Comma Detection and Alignment }
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXENMCOMMAALIGN0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXENMCOMMAALIGN1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXENPCOMMAALIGN0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXENPCOMMAALIGN1_IN
add wave -noupdate -divider {Receive Ports - RX Data Path interface }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXDATA0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXDATA1_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXUSRCLK0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXUSRCLK1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXUSRCLK20_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXUSRCLK21_IN
add wave -noupdate -divider {Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXEQMIX0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXEQMIX1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXN0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXN1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXP0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXP1_IN
add wave -noupdate -divider {Receive Ports - RX Loss-of-sync State Machine }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXLOSSOFSYNC0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/RXLOSSOFSYNC1_OUT
add wave -noupdate -divider {TX/RX Datapath Ports }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/GTPCLKOUT0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/GTPCLKOUT1_OUT
add wave -noupdate -divider {Transmit Ports - 8b10b Encoder Control }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXCHARISK0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXCHARISK1_IN
add wave -noupdate -divider {Transmit Ports - TX Data Path interface }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXDATA0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXDATA1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXOUTCLK0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXOUTCLK1_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXUSRCLK0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXUSRCLK1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXUSRCLK20_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXUSRCLK21_IN
add wave -noupdate -divider {Transmit Ports - TX Driver and OOB signalling }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXDIFFCTRL0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXDIFFCTRL1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXN0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXN1_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXP0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXP1_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXPREEMPHASIS0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile0_fmc_refclk_test_i/TXPREEMPHASIS1_IN
add wave -noupdate -divider {TILE1_fmc_refclk_test }
add wave -noupdate -divider {Loopback and Powerdown Ports }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/LOOPBACK0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/LOOPBACK1_IN
add wave -noupdate -divider {PLL Ports }
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/CLK00_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/CLK01_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/GTPRESET0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/GTPRESET1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/PLLLKDET0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/PLLLKDET1_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RESETDONE0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RESETDONE1_OUT
add wave -noupdate -divider {Receive Ports - 8b10b Decoder }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXDISPERR0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXDISPERR1_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXNOTINTABLE0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXNOTINTABLE1_OUT
add wave -noupdate -divider {Receive Ports - Comma Detection and Alignment }
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXENMCOMMAALIGN0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXENMCOMMAALIGN1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXENPCOMMAALIGN0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXENPCOMMAALIGN1_IN
add wave -noupdate -divider {Receive Ports - RX Data Path interface }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXDATA0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXDATA1_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXUSRCLK0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXUSRCLK1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXUSRCLK20_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXUSRCLK21_IN
add wave -noupdate -divider {Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXEQMIX0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXEQMIX1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXN0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXN1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXP0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXP1_IN
add wave -noupdate -divider {Receive Ports - RX Loss-of-sync State Machine }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXLOSSOFSYNC0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/RXLOSSOFSYNC1_OUT
add wave -noupdate -divider {TX/RX Datapath Ports }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/GTPCLKOUT0_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/GTPCLKOUT1_OUT
add wave -noupdate -divider {Transmit Ports - 8b10b Encoder Control }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXCHARISK0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXCHARISK1_IN
add wave -noupdate -divider {Transmit Ports - TX Data Path interface }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXDATA0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXDATA1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXOUTCLK0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXOUTCLK1_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXUSRCLK0_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXUSRCLK1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXUSRCLK20_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXUSRCLK21_IN
add wave -noupdate -divider {Transmit Ports - TX Driver and OOB signalling }
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXDIFFCTRL0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXDIFFCTRL1_IN
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXN0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXN1_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXP0_OUT
add wave -noupdate -format Logic /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXP1_OUT
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXPREEMPHASIS0_IN
add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/fmc_refclk_test_top_i/fmc_refclk_test_i/tile1_fmc_refclk_test_i/TXPREEMPHASIS1_IN
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 282
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {5236 ps}
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/functional/wave_ncsim.sv 0 → 100755
View file @ b718a368
###############################################################################
## wave_ncsim.sv
###############################################################################
window new WaveWindow -name "Waves for Spartan-6 GTP Wizard Example Design"
waveform using "Waves for Spartan-6 GTP Wizard Example Design"
waveform add -label FRAME_CHECK_MODULE -comment tile0_frame_check0
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile0_frame_check0:begin_r
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile0_frame_check0:track_data_r
waveform add -siganls :fmc_refclk_test_top_i+delimiter+tile0_frame_check0:data_error_detected_r
wavefrom add -siganls :fmc_refclk_test_top_i+delimiter+tile0_frame_check0:start_of_packet_detected_r
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile0_frame_check0:RX_DATA
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile0_frame_check0:ERROR_COUNT
waveform add -label FRAME_CHECK_MODULE -comment tile0_frame_check1
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile0_frame_check1:begin_r
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile0_frame_check1:track_data_r
waveform add -siganls :fmc_refclk_test_top_i+delimiter+tile0_frame_check1:data_error_detected_r
wavefrom add -siganls :fmc_refclk_test_top_i+delimiter+tile0_frame_check1:start_of_packet_detected_r
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile0_frame_check1:RX_DATA
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile0_frame_check1:ERROR_COUNT
waveform add -label FRAME_CHECK_MODULE -comment tile1_frame_check0
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile1_frame_check0:begin_r
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile1_frame_check0:track_data_r
waveform add -siganls :fmc_refclk_test_top_i+delimiter+tile1_frame_check0:data_error_detected_r
wavefrom add -siganls :fmc_refclk_test_top_i+delimiter+tile1_frame_check0:start_of_packet_detected_r
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile1_frame_check0:RX_DATA
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile1_frame_check0:ERROR_COUNT
waveform add -label FRAME_CHECK_MODULE -comment tile1_frame_check1
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile1_frame_check1:begin_r
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile1_frame_check1:track_data_r
waveform add -siganls :fmc_refclk_test_top_i+delimiter+tile1_frame_check1:data_error_detected_r
wavefrom add -siganls :fmc_refclk_test_top_i+delimiter+tile1_frame_check1:start_of_packet_detected_r
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile1_frame_check1:RX_DATA
waveform add -signals :fmc_refclk_test_top_i+delimiter+tile1_frame_check1:ERROR_COUNT
waveform add -label TILE0_fmc_refclk_test -comment TILE0_fmc_refclk_test
waveform add -label Loopback_and_Powerdown_Ports -comment Loopback_and_Powerdown_Ports
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:LOOPBACK0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:LOOPBACK1_IN
waveform add -label PLL_Ports -comment PLL_Ports
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:CLK00_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:CLK01_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:GTPRESET0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:GTPRESET1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:PLLLKDET0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:PLLLKDET1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RESETDONE0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RESETDONE1_OUT
waveform add -label Receive_Ports_-_8b10b_Decoder -comment Receive_Ports_-_8b10b_Decoder
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXDISPERR0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXDISPERR1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXNOTINTABLE0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXNOTINTABLE1_OUT
waveform add -label Receive_Ports_-_Comma_Detection_and_Alignment -comment Receive_Ports_-_Comma_Detection_and_Alignment
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXENMCOMMAALIGN0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXENMCOMMAALIGN1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXENPCOMMAALIGN0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXENPCOMMAALIGN1_IN
waveform add -label Receive_Ports_-_RX_Data_Path_interface -comment Receive_Ports_-_RX_Data_Path_interface
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXDATA0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXDATA1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXUSRCLK0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXUSRCLK1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXUSRCLK20_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXUSRCLK21_IN
waveform add -label Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR -comment Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXEQMIX0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXEQMIX1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXN0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXN1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXP0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXP1_IN
waveform add -label Receive_Ports_-_RX_Loss-of-sync_State_Machine -comment Receive_Ports_-_RX_Loss-of-sync_State_Machine
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXLOSSOFSYNC0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:RXLOSSOFSYNC1_OUT
waveform add -label TX/RX_Datapath_Ports -comment TX/RX_Datapath_Ports
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:GTPCLKOUT0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:GTPCLKOUT1_OUT
waveform add -label Transmit_Ports_-_8b10b_Encoder_Control -comment Transmit_Ports_-_8b10b_Encoder_Control
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXCHARISK0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXCHARISK1_IN
waveform add -label Transmit_Ports_-_TX_Data_Path_interface -comment Transmit_Ports_-_TX_Data_Path_interface
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXDATA0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXDATA1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXOUTCLK0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXOUTCLK1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXUSRCLK0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXUSRCLK1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXUSRCLK20_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXUSRCLK21_IN
waveform add -label Transmit_Ports_-_TX_Driver_and_OOB_signalling -comment Transmit_Ports_-_TX_Driver_and_OOB_signalling
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXDIFFCTRL0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXDIFFCTRL1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXN0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXN1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXP0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXP1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXPREEMPHASIS0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile0_fmc_refclk_test_i:TXPREEMPHASIS1_IN
waveform add -label TILE1_fmc_refclk_test -comment TILE1_fmc_refclk_test
waveform add -label Loopback_and_Powerdown_Ports -comment Loopback_and_Powerdown_Ports
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:LOOPBACK0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:LOOPBACK1_IN
waveform add -label PLL_Ports -comment PLL_Ports
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:CLK00_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:CLK01_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:GTPRESET0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:GTPRESET1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:PLLLKDET0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:PLLLKDET1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RESETDONE0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RESETDONE1_OUT
waveform add -label Receive_Ports_-_8b10b_Decoder -comment Receive_Ports_-_8b10b_Decoder
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXDISPERR0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXDISPERR1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXNOTINTABLE0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXNOTINTABLE1_OUT
waveform add -label Receive_Ports_-_Comma_Detection_and_Alignment -comment Receive_Ports_-_Comma_Detection_and_Alignment
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXENMCOMMAALIGN0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXENMCOMMAALIGN1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXENPCOMMAALIGN0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXENPCOMMAALIGN1_IN
waveform add -label Receive_Ports_-_RX_Data_Path_interface -comment Receive_Ports_-_RX_Data_Path_interface
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXDATA0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXDATA1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXUSRCLK0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXUSRCLK1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXUSRCLK20_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXUSRCLK21_IN
waveform add -label Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR -comment Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXEQMIX0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXEQMIX1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXN0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXN1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXP0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXP1_IN
waveform add -label Receive_Ports_-_RX_Loss-of-sync_State_Machine -comment Receive_Ports_-_RX_Loss-of-sync_State_Machine
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXLOSSOFSYNC0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:RXLOSSOFSYNC1_OUT
waveform add -label TX/RX_Datapath_Ports -comment TX/RX_Datapath_Ports
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:GTPCLKOUT0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:GTPCLKOUT1_OUT
waveform add -label Transmit_Ports_-_8b10b_Encoder_Control -comment Transmit_Ports_-_8b10b_Encoder_Control
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXCHARISK0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXCHARISK1_IN
waveform add -label Transmit_Ports_-_TX_Data_Path_interface -comment Transmit_Ports_-_TX_Data_Path_interface
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXDATA0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXDATA1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXOUTCLK0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXOUTCLK1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXUSRCLK0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXUSRCLK1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXUSRCLK20_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXUSRCLK21_IN
waveform add -label Transmit_Ports_-_TX_Driver_and_OOB_signalling -comment Transmit_Ports_-_TX_Driver_and_OOB_signalling
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXDIFFCTRL0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXDIFFCTRL1_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXN0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXN1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXP0_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXP1_OUT
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXPREEMPHASIS0_IN
waveform add -signals :fmc_refclk_test_top_i:fmc_refclk_test_i:tile1_fmc_refclk_test_i:TXPREEMPHASIS1_IN
console submit -using simulator -wait no "run 50 us"
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/netlist/simulate_mti.do 0 → 100755
View file @ b718a368
################################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 GTP Wizard
## / / Filename : simulate_mti.do
## /___/ /\
## \ \ / \
## \___\/\___\
##
##
## Script SIMULATE_MTI.DO
## Generated by Xilinx Spartan-6 GTP Wizard
##***************************** Beginning of Script ***************************
## If MTI_LIBS is defined, map unisim and simprim directories using MTI_LIBS
## This mode of mapping the unisims libraries is provided for backward
## compatibility with previous wizard releases. If you don't set MTI_LIBS
## the unisim libraries will be loaded from the paths set up by compxlib in
## your modelsim.ini file
set XILINX $env(XILINX)
if [info exists env(MTI_LIBS)] {
set MTI_LIBS $env(MTI_LIBS)
vlib SECUREIP
vmap SIMPRIM $MTI_LIBS/simprim
vmap SECUREIP $MTI_LIBS/secureip
}
## Create and map work directory
vlib work
vmap work work
##Other modules
vcom -93 -work work ../../implement/results/routed.vhd;
vcom -93 -work work ../demo_tb_imp.vhd;
##Load Design
vsim -t 1ps -L SECUREIP -L SIMPRIM -sdftyp /DEMO_TB_IMP/fmc_refclk_test_top_i=../../implement/results/routed.sdf +no_notifier +notimingchecks work.DEMO_TB_IMP -voptargs="+acc"
##Run simulation
run 200 us
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test/simulation/sim_reset_mgt_model.vhd 0 → 100755
View file @ b718a368
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : sim_reset_mgt_model.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module SIM_RESET_MGT_MODEL
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
-- The Reset On Configuration(ROC) module is part of the UNISIM library
-- and is required for emulating the GSR pulse at the beginning of functional
-- simulation in order to correctly reset the VHDL MGT smart model.This module
-- is required for simulation only.
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration *****************************
entity SIM_RESET_MGT_MODEL is
port
(
GSR_IN : in std_logic
);
end SIM_RESET_MGT_MODEL;
architecture BEHAVIORAL of SIM_RESET_MGT_MODEL is
--********************************* Main Body of Code****************************
begin
GSR <= GSR_IN;
------------------------------ ROCBUF Instantiation -----------------------
-- This component is required for correctly resetting the VHDL GTP component on configuration
-- It is for simulation alone and will be ripped out during synthesis.
U1 : ROCBUF
port map
(
I => GSR,
O => open
);
end BEHAVIORAL;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test_flist.txt 0 → 100644
View file @ b718a368
# Output products list for <fmc_refclk_test>
fmc_refclk_test/doc/s6_gtpwizard_v1_11_vinfo.html
fmc_refclk_test/doc/ug546_s6_gtpwizard.pdf
fmc_refclk_test/example_design/fmc_refclk_test_top.ucf
fmc_refclk_test/example_design/fmc_refclk_test_top.vhd
fmc_refclk_test/example_design/frame_check.vhd
fmc_refclk_test/example_design/frame_gen.vhd
fmc_refclk_test/example_design/gtp_attributes.ucf
fmc_refclk_test/example_design/mgt_usrclk_source_pll.vhd
fmc_refclk_test/fmc_refclk_test.pf
fmc_refclk_test/implement/chipscope_project.cpj
fmc_refclk_test/implement/data_vio.ngc
fmc_refclk_test/implement/icon.ngc
fmc_refclk_test/implement/ila.ngc
fmc_refclk_test/implement/implement.bat
fmc_refclk_test/implement/implement.sh
fmc_refclk_test/implement/implement_synplify.bat
fmc_refclk_test/implement/implement_synplify.sh
fmc_refclk_test/implement/null_vio.ngc
fmc_refclk_test/implement/shared_vio.ngc
fmc_refclk_test/implement/synplify.prj
fmc_refclk_test/implement/xst.prj
fmc_refclk_test/implement/xst.scr
fmc_refclk_test/s6_gtpwizard_v1_11_readme.txt
fmc_refclk_test/simulation/demo_tb.vhd
fmc_refclk_test/simulation/demo_tb_imp.vhd
fmc_refclk_test/simulation/functional/simulate_isim.bat
fmc_refclk_test/simulation/functional/simulate_isim.sh
fmc_refclk_test/simulation/functional/simulate_mti.do
fmc_refclk_test/simulation/functional/simulate_ncsim.bat
fmc_refclk_test/simulation/functional/simulate_ncsim.sh
fmc_refclk_test/simulation/functional/simulate_vcs.sh
fmc_refclk_test/simulation/functional/ucli_commands.key
fmc_refclk_test/simulation/functional/vcs_session.tcl
fmc_refclk_test/simulation/functional/wave_isim.tcl
fmc_refclk_test/simulation/functional/wave_mti.do
fmc_refclk_test/simulation/functional/wave_ncsim.sv
fmc_refclk_test/simulation/netlist/simulate_mti.do
fmc_refclk_test/simulation/sim_reset_mgt_model.vhd
fmc_refclk_test.gise
fmc_refclk_test.vhd
fmc_refclk_test.vho
fmc_refclk_test.xco
fmc_refclk_test.xise
fmc_refclk_test_flist.txt
fmc_refclk_test_tile.vhd
fmc_refclk_test_xmdf.tcl
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test_tile.vhd 0 → 100755
View file @ b718a368
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : fmc_refclk_test_tile.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module fmc_refclk_test_tile (a GTPA1_DUAL Tile Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity fmc_refclk_test_tile is
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 5;
TILE_CLK25_DIVIDER_1 : integer := 5;
TILE_PLL_DIVSEL_FB_0 : integer := 2;
TILE_PLL_DIVSEL_FB_1 : integer := 2;
TILE_PLL_DIVSEL_REF_0 : integer := 1;
TILE_PLL_DIVSEL_REF_1 : integer := 1;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXDISPERR0_OUT : out std_logic_vector(3 downto 0);
RXDISPERR1_OUT : out std_logic_vector(3 downto 0);
RXNOTINTABLE0_OUT : out std_logic_vector(3 downto 0);
RXNOTINTABLE1_OUT : out std_logic_vector(3 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN : in std_logic;
RXENMCOMMAALIGN1_IN : in std_logic;
RXENPCOMMAALIGN0_IN : in std_logic;
RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(31 downto 0);
RXDATA1_OUT : out std_logic_vector(31 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXEQMIX0_IN : in std_logic_vector(1 downto 0);
RXEQMIX1_IN : in std_logic_vector(1 downto 0);
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0);
RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0);
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARISK0_IN : in std_logic_vector(3 downto 0);
TXCHARISK1_IN : in std_logic_vector(3 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(31 downto 0);
TXDATA1_IN : in std_logic_vector(31 downto 0);
TXOUTCLK0_OUT : out std_logic;
TXOUTCLK1_OUT : out std_logic;
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXDIFFCTRL0_IN : in std_logic_vector(3 downto 0);
TXDIFFCTRL1_IN : in std_logic_vector(3 downto 0);
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic;
TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0)
);
end fmc_refclk_test_tile;
architecture RTL of fmc_refclk_test_tile is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA0_OUT <= rxdata0_i;
-- The GTP transmits little endian data (TXDATA(7 downto 0) transmitted first)
txdata0_i <= TXDATA0_IN;
-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA1_OUT <= rxdata1_i;
-- The GTP transmits little endian data (TXDATA(7 downto 0) transmitted first)
txdata1_i <= TXDATA1_IN;
----------------------------- GTPA1_DUAL Instance --------------------------
gtpa1_dual_i:GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_TX_ELEC_IDLE_LEVEL => ("Z"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => ("000"),
SIM_REFCLK1_SOURCE => ("000"),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
--PLL Attributes
CLKINDC_B_0 => (TRUE),
CLKRCV_TRST_0 => (TRUE),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (2),
PLL_SATA_0 => (FALSE),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (2),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (TRUE),
CLKRCV_TRST_1 => (TRUE),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (2),
PLL_SATA_1 => (FALSE),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (2),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"00000a000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("TXOUTCLK0"),
TX_TDCC_CFG_0 => ("00"),
CLK_OUT_GTP_SEL_1 => ("TXOUTCLK1"),
TX_TDCC_CFG_1 => ("00"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"00082"),
TX_BUFFER_USE_0 => (TRUE),
TX_XCLK_SEL_0 => ("TXOUT"),
TXRX_INVERT_0 => ("011"),
PMA_TX_CFG_1 => (x"00082"),
TX_BUFFER_USE_1 => (TRUE),
TX_XCLK_SEL_1 => ("TXOUT"),
TXRX_INVERT_1 => ("011"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (TRUE),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce008"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (FALSE),
RCV_TERM_VTTRX_0 => (TRUE),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (FALSE),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (TRUE),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce008"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (FALSE),
RCV_TERM_VTTRX_1 => (TRUE),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (FALSE),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (FALSE),
DEC_PCOMMA_DETECT_0 => (FALSE),
DEC_VALID_COMMA_ONLY_0 => (FALSE),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (TRUE),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (TRUE),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (FALSE),
DEC_PCOMMA_DETECT_1 => (FALSE),
DEC_VALID_COMMA_ONLY_1 => (FALSE),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (TRUE),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (TRUE),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (TRUE),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (TRUE),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (TRUE),
RX_EN_IDLE_RESET_BUF_0 => (FALSE),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (TRUE),
RX_EN_IDLE_RESET_BUF_1 => (FALSE),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
CLK_COR_KEEP_IDLE_0 => (FALSE),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (TRUE),
CLK_COR_REPEAT_WAIT_0 => (5),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0100000000"),
CLK_COR_SEQ_1_3_0 => ("0100000000"),
CLK_COR_SEQ_1_4_0 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0100000000"),
CLK_COR_SEQ_2_3_0 => ("0100000000"),
CLK_COR_SEQ_2_4_0 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (FALSE),
CLK_CORRECT_USE_0 => (FALSE),
RX_DECODE_SEQ_MATCH_0 => (TRUE),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
CLK_COR_KEEP_IDLE_1 => (FALSE),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (TRUE),
CLK_COR_REPEAT_WAIT_1 => (5),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0100000000"),
CLK_COR_SEQ_1_3_1 => ("0100000000"),
CLK_COR_SEQ_1_4_1 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0100000000"),
CLK_COR_SEQ_2_3_1 => ("0100000000"),
CLK_COR_SEQ_2_4_1 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (FALSE),
CLK_CORRECT_USE_1 => (FALSE),
RX_DECODE_SEQ_MATCH_1 => (TRUE),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
CHAN_BOND_SEQ_1_1_0 => ("0000000000"),
CHAN_BOND_SEQ_1_2_0 => ("0000000000"),
CHAN_BOND_SEQ_1_3_0 => ("0000000000"),
CHAN_BOND_SEQ_1_4_0 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (FALSE),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
CHAN_BOND_SEQ_1_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2_1 => ("0000000000"),
CHAN_BOND_SEQ_1_3_1 => ("0000000000"),
CHAN_BOND_SEQ_1_4_1 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (FALSE),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (FALSE),
RX_EN_IDLE_HOLD_CDR_0 => (FALSE),
RX_EN_IDLE_RESET_FR_0 => (FALSE),
RX_EN_IDLE_RESET_PH_0 => (FALSE),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (FALSE),
RX_EN_IDLE_HOLD_CDR_1 => (FALSE),
RX_EN_IDLE_RESET_FR_1 => (FALSE),
RX_EN_IDLE_RESET_PH_1 => (FALSE),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => LOOPBACK0_IN,
LOOPBACK1 => LOOPBACK1_IN,
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => tied_to_ground_i,
CLK11 => tied_to_ground_i,
CLKINEAST0 => tied_to_ground_i,
CLKINEAST1 => tied_to_ground_i,
CLKINWEST0 => tied_to_ground_i,
CLKINWEST1 => tied_to_ground_i,
GCLK00 => tied_to_ground_i,
GCLK01 => tied_to_ground_i,
GCLK10 => tied_to_ground_i,
GCLK11 => tied_to_ground_i,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0 => open,
RXCHARISK1 => open,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0 => RXDISPERR0_OUT,
RXDISPERR1 => RXDISPERR1_OUT,
RXNOTINTABLE0 => RXNOTINTABLE0_OUT,
RXNOTINTABLE1 => RXNOTINTABLE1_OUT,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_IN,
RXSLIDE0 => tied_to_ground_i,
RXSLIDE1 => tied_to_ground_i,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "10",
RXDATAWIDTH1 => "10",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => tied_to_ground_i,
RXRESET1 => tied_to_ground_i,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => tied_to_ground_i,
GATERXELECIDLE1 => tied_to_ground_i,
IGNORESIGDET0 => tied_to_ground_i,
IGNORESIGDET1 => tied_to_ground_i,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => tied_to_ground_i,
RXCDRRESET1 => tied_to_ground_i,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => RXEQMIX0_IN,
RXEQMIX1 => RXEQMIX1_IN,
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => tied_to_ground_i,
RXBUFRESET1 => tied_to_ground_i,
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => RXLOSSOFSYNC0_OUT,
RXLOSSOFSYNC1 => RXLOSSOFSYNC1_OUT,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => open,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => open,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL0 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPVAL1 => tied_to_ground_vec_i(3 downto 0),
TXCHARISK0 => TXCHARISK0_IN,
TXCHARISK1 => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => tied_to_ground_i,
TXENPMAPHASEALIGN1 => tied_to_ground_i,
TXPMASETPHASE0 => tied_to_ground_i,
TXPMASETPHASE1 => tied_to_ground_i,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "10",
TXDATAWIDTH1 => "10",
TXOUTCLK0 => TXOUTCLK0_OUT,
TXOUTCLK1 => TXOUTCLK1_OUT,
TXRESET0 => tied_to_ground_i,
TXRESET1 => tied_to_ground_i,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => TXDIFFCTRL0_IN,
TXDIFFCTRL1 => TXDIFFCTRL1_IN,
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => TXPREEMPHASIS0_IN,
TXPREEMPHASIS1 => TXPREEMPHASIS1_IN,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end RTL;
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/fmc_refclk_test_xmdf.tcl 0 → 100755
View file @ b718a368
##############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor: Xilinx
## \ \ \/ Version : 1.11
## \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
## / / Filename : fmc_refclk_test_xmdf.tcl
## /___/ /\
## \ \ / \
## \___\/\___\
##
# ::gen_comp_name_xmdf::xmdfApplyParams
# The package naming convention is <core_name>_xmdf
package provide fmc_refclk_test_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::fmc_refclk_test_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::fmc_refclk_test_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name fmc_refclk_test
}
# ::fmc_refclk_test_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::fmc_refclk_test_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/doc/s6_gtpwizard_ds713.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/doc/s6_gtpwizard_gsg546.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/example_design/mgt_usrclk_source_pll.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/example_design/frame_gen.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/example_design/frame_check.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/example_design/fmc_refclk_test_top.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test_tile.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/demo_tb.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/example_design/gtp_attributes.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/example_design/fmc_refclk_test_top.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/chipscope_project.cpj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/data_vio.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/icon.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/ila.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/implement_synplify.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/implement_synplify.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/null_vio.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/shared_vio.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/synplify.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/s6_gtpwizard_v1_11_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/fmc_refclk_test.pf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/demo_tb.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/simulate_isim.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/simulate_isim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/simulate_mti.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/simulate_ncsim.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/simulate_ncsim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/simulate_vcs.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/ucli_commands.key
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/vcs_session.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/wave_isim.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/wave_mti.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test/simulation/functional/wave_ncsim.sv
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fmc_refclk_test_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
#utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fmc_refclk_test
#incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
test/svec/VHDL/svec_pts_gtp_clkfmc/ip_cores/core_gen/mgt_usrclk_source_pll.vhd 0 → 100755
View file @ b718a368
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : mgt_usrclk_source_pll.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module MGT_USRCLK_SOURCE_PLL (for use with GTP Transceivers)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***********************************Entity Declaration*******************************
entity MGT_USRCLK_SOURCE_PLL is
generic
(
MULT : integer := 2;
DIVIDE : integer := 2;
FEEDBACK : string := "CLKFBOUT";
CLK_PERIOD : real := 8.0;
OUT0_DIVIDE : integer := 2;
OUT1_DIVIDE : integer := 2;
OUT2_DIVIDE : integer := 2;
OUT3_DIVIDE : integer := 2
);
port
(
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic;
CLK_IN : in std_logic;
CLKFB_IN : in std_logic;
CLKFB_OUT : out std_logic;
PLL_LOCKED_OUT : out std_logic;
PLL_RESET_IN : in std_logic
);
end MGT_USRCLK_SOURCE_PLL;
architecture RTL of MGT_USRCLK_SOURCE_PLL is
--*********************************Wire Declarations**********************************
signal tied_to_ground_vec_i : std_logic_vector(15 downto 0);
signal tied_to_ground_i : std_logic;
signal tied_to_vcc_i : std_logic;
signal clkout0_i : std_logic;
signal clkout1_i : std_logic;
signal clkout2_i : std_logic;
signal clkout3_i : std_logic;
begin
--*********************************** Beginning of Code *******************************
-- Static signal Assigments
tied_to_ground_i <= '0';
tied_to_ground_vec_i <= (others=>'0');
tied_to_vcc_i <= '1';
-- Instantiate a PLL module to divide the reference clock. Uses internal feedback
-- for improved jitter performance, and to avoid consuming an additional BUFG
pll_adv_i : PLL_BASE
generic map
(
CLKFBOUT_MULT => MULT,
DIVCLK_DIVIDE => DIVIDE,
CLK_FEEDBACK => FEEDBACK,
CLKFBOUT_PHASE => 0.0,
COMPENSATION => "SYSTEM_SYNCHRONOUS",
CLKIN_PERIOD => CLK_PERIOD,
CLKOUT0_DIVIDE => OUT0_DIVIDE,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => OUT1_DIVIDE,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => OUT2_DIVIDE,
CLKOUT2_PHASE => 0.0,
CLKOUT3_DIVIDE => OUT3_DIVIDE,
CLKOUT3_PHASE => 0.0
)
port map
(
CLKIN => CLK_IN,
CLKFBIN => CLKFB_IN,
CLKOUT0 => clkout0_i,
CLKOUT1 => clkout1_i,
CLKOUT2 => clkout2_i,
CLKOUT3 => clkout3_i,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => CLKFB_OUT,
LOCKED => PLL_LOCKED_OUT,
RST => PLL_RESET_IN
);
clkout0_bufg_i : BUFG
port map
(
O => CLK0_OUT,
I => clkout0_i
);
clkout1_bufg_i : BUFG
port map
(
O => CLK1_OUT,
I => clkout1_i
);
clkout2_bufg_i : BUFG
port map
(
O => CLK2_OUT,
I => clkout2_i
);
clkout3_bufg_i : BUFG
port map
(
O => CLK3_OUT,
I => clkout3_i
);
end RTL;
test/svec/VHDL/svec_pts_gtp_clkfmc/rtl/Manifest.py 0 → 100644
View file @ b718a368
files = ["svec_afpga_gtp_clkfmc_top.vhd",
"xvme64x_core.vhd",
"csr_regs.vhd"]
test/svec/VHDL/svec_pts_gtp_clkfmc/rtl/csr_regs.vhd 0 → 100644
View file @ b718a368
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SVEC pts FMC GTP refclk CSR registers
---------------------------------------------------------------------------------------
-- File : ../rtl/csr_regs.vhd
-- Author : auto-generated by wbgen2 from csr_regs.wb
-- Created : Tue Nov 6 14:21:56 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE csr_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity csr_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control register'
csr_ctl_reserved_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status register'
csr_sta_reserved_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'FMC1 clk counter register'
csr_fmc1_clk_cnt_reserved_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'FMC2 clk counter register'
csr_fmc2_clk_cnt_reserved_i : in std_logic_vector(31 downto 0)
);
end csr_regs;
architecture syn of csr_regs is
signal csr_ctl_reserved_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
csr_ctl_reserved_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
csr_ctl_reserved_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= csr_ctl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= csr_sta_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= csr_fmc1_clk_cnt_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= csr_fmc2_clk_cnt_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Reserved
csr_ctl_reserved_o <= csr_ctl_reserved_int;
-- Reserved
-- Reserved
-- Reserved
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
test/svec/VHDL/svec_pts_gtp_clkfmc/rtl/svec_afpga_gtp_clkfmc_top.vhd 0 → 100644
View file @ b718a368
--_________________________________________________________________________________________________
-- |
-- |SVEC PTS| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- svec_afpga_gtp_clkfmc_top |
-- |
---------------------------------------------------------------------------------------------------
-- File svec_afpga_gtp_clkfmc_top.vhd |
-- |
-- Description SVEC top level to be loaded during the PTS test.
-- It measures the frequency of the reference clock coming from the
-- carrier tester FMC (Si570) on both FMC 1 and FMC 2 slots.
-- Measured frequencies are available in a register accessible via
-- wishbone though VME.
-- |
-- Authors Matthieu Cattin |
-- Date 11/2012 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 11/2012 v1 MC First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.wishbone_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
--=================================================================================================
-- Entity declaration
--=================================================================================================
entity svec_afpga_gtp_clkfmc_top is
port
-- INPUTS
-- Clocks and Resets
(
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
rst_n_i : in std_logic; -- Power On Reset
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
-- VME interface
vme_as_n_i : in std_logic;
vme_rst_n_i : in std_logic;
vme_write_n_i : in std_logic;
vme_am_i : in std_logic_vector(5 downto 0);
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_ga_i : in std_logic_vector(5 downto 0);
vme_berr_o : out std_logic;
vme_dtack_n_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
vme_addr_b : inout std_logic_vector(31 downto 1);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_irq_n_o : out std_logic_vector(6 downto 0);
vme_iack_n_i : in std_logic;
vme_iackin_n_i : in std_logic;
vme_iackout_n_o : out std_logic;
vme_dtack_oe_o : out std_logic;
vme_data_dir_o : out std_logic;
vme_data_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_addr_oe_n_o : out std_logic;
vme_retry_oe_o : out std_logic;
-- I2C interface for FMC Tester mezzanaine 0 crosspoint switch
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- I2C interface for FMC Tester mezzanaine 1 crosspoint switch
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic;
-- Upper GTP reference clock (channels 101 and 245, from the carrier)
clk_gtp_carrier_y1_n_i : in std_logic;
clk_gtp_carrier_y1_p_i : in std_logic;
-- Upper GTP reference clock (channels 123 and 267, from the carrier)
clk_gtp_carrier_y0_n_i : in std_logic;
clk_gtp_carrier_y0_p_i : in std_logic;
-- SATA0 interface (straight - MGT245, channel 1)
--sata0_rxp_i : in std_logic;
--sata0_rxn_i : in std_logic;
--sata0_txp_o : out std_logic;
--sata0_txn_o : out std_logic;
-- FMC0 High Speed pins (MGT101, channel 0)
--fmc0_dp0_rxp_i : in std_logic;
--fmc0_dp0_rxn_i : in std_logic;
--fmc0_dp0_txp_o : out std_logic;
--fmc0_dp0_txn_o : out std_logic;
-- FMC0 High Speed pins (MGT267, channel 0)
--fmc1_dp0_rxp_i : in std_logic;
--fmc1_dp0_rxn_i : in std_logic;
--fmc1_dp0_txp_o : out std_logic;
--fmc1_dp0_txn_o : out std_logic;
-- SATA1 interface (crossover - MGT245, channel 0)
--sata1_rxp_i : in std_logic;
--sata1_rxn_i : in std_logic;
--sata1_txp_o : out std_logic;
--sata1_txn_o : out std_logic;
-- SFP interface
--sfp_rxp_i : in std_logic;
--sfp_rxn_i : in std_logic;
--sfp_txp_o : out std_logic;
--sfp_txn_o : out std_logic;
-- LEDs array
fp_ledn_o : out std_logic_vector(7 downto 0);
-- Debug LEDs
dbg_led_n_o : out std_logic_vector(3 downto 0)
);
end svec_afpga_gtp_clkfmc_top;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of svec_afpga_gtp_clkfmc_top is
component xvme64x_core
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic);
end component;
component fmc_refclk_test
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_CLK25_DIVIDER_0 : integer := 4;
WRAPPER_CLK25_DIVIDER_1 : integer := 4;
WRAPPER_PLL_DIVSEL_FB_0 : integer := 5;
WRAPPER_PLL_DIVSEL_FB_1 : integer := 5;
WRAPPER_PLL_DIVSEL_REF_0 : integer := 2;
WRAPPER_PLL_DIVSEL_REF_1 : integer := 2;
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X1_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE0_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_PLLLKDET1_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXDISPERR0_OUT : out std_logic_vector(3 downto 0);
TILE0_RXDISPERR1_OUT : out std_logic_vector(3 downto 0);
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(3 downto 0);
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(3 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(31 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(31 downto 0);
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_RXEQMIX0_IN : in std_logic_vector(1 downto 0);
TILE0_RXEQMIX1_IN : in std_logic_vector(1 downto 0);
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE0_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0);
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARISK0_IN : in std_logic_vector(3 downto 0);
TILE0_TXCHARISK1_IN : in std_logic_vector(3 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(31 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(31 downto 0);
TILE0_TXOUTCLK0_OUT : out std_logic;
TILE0_TXOUTCLK1_OUT : out std_logic;
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXDIFFCTRL0_IN : in std_logic_vector(3 downto 0);
TILE0_TXDIFFCTRL1_IN : in std_logic_vector(3 downto 0);
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic;
TILE0_TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
TILE0_TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0);
--_________________________________________________________________________
--_________________________________________________________________________
--TILE1 (X0_Y1)
------------------------ Loopback and Powerdown Ports ----------------------
TILE1_LOOPBACK0_IN : in std_logic_vector(2 downto 0);
TILE1_LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE1_CLK00_IN : in std_logic;
TILE1_CLK01_IN : in std_logic;
TILE1_GTPRESET0_IN : in std_logic;
TILE1_GTPRESET1_IN : in std_logic;
TILE1_PLLLKDET0_OUT : out std_logic;
TILE1_PLLLKDET1_OUT : out std_logic;
TILE1_RESETDONE0_OUT : out std_logic;
TILE1_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE1_RXDISPERR0_OUT : out std_logic_vector(3 downto 0);
TILE1_RXDISPERR1_OUT : out std_logic_vector(3 downto 0);
TILE1_RXNOTINTABLE0_OUT : out std_logic_vector(3 downto 0);
TILE1_RXNOTINTABLE1_OUT : out std_logic_vector(3 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE1_RXENMCOMMAALIGN0_IN : in std_logic;
TILE1_RXENMCOMMAALIGN1_IN : in std_logic;
TILE1_RXENPCOMMAALIGN0_IN : in std_logic;
TILE1_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE1_RXDATA0_OUT : out std_logic_vector(31 downto 0);
TILE1_RXDATA1_OUT : out std_logic_vector(31 downto 0);
TILE1_RXUSRCLK0_IN : in std_logic;
TILE1_RXUSRCLK1_IN : in std_logic;
TILE1_RXUSRCLK20_IN : in std_logic;
TILE1_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE1_RXEQMIX0_IN : in std_logic_vector(1 downto 0);
TILE1_RXEQMIX1_IN : in std_logic_vector(1 downto 0);
TILE1_RXN0_IN : in std_logic;
TILE1_RXN1_IN : in std_logic;
TILE1_RXP0_IN : in std_logic;
TILE1_RXP1_IN : in std_logic;
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE1_RXLOSSOFSYNC0_OUT : out std_logic_vector(1 downto 0);
TILE1_RXLOSSOFSYNC1_OUT : out std_logic_vector(1 downto 0);
---------------------------- TX/RX Datapath Ports --------------------------
TILE1_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE1_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE1_TXCHARISK0_IN : in std_logic_vector(3 downto 0);
TILE1_TXCHARISK1_IN : in std_logic_vector(3 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE1_TXDATA0_IN : in std_logic_vector(31 downto 0);
TILE1_TXDATA1_IN : in std_logic_vector(31 downto 0);
TILE1_TXOUTCLK0_OUT : out std_logic;
TILE1_TXOUTCLK1_OUT : out std_logic;
TILE1_TXUSRCLK0_IN : in std_logic;
TILE1_TXUSRCLK1_IN : in std_logic;
TILE1_TXUSRCLK20_IN : in std_logic;
TILE1_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE1_TXDIFFCTRL0_IN : in std_logic_vector(3 downto 0);
TILE1_TXDIFFCTRL1_IN : in std_logic_vector(3 downto 0);
TILE1_TXN0_OUT : out std_logic;
TILE1_TXN1_OUT : out std_logic;
TILE1_TXP0_OUT : out std_logic;
TILE1_TXP1_OUT : out std_logic;
TILE1_TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
TILE1_TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0)
);
end component;
component MGT_USRCLK_SOURCE_PLL
generic
(
MULT : integer := 2;
DIVIDE : integer := 2;
FEEDBACK : string := "CLKFBOUT";
CLK_PERIOD : real := 8.0;
OUT0_DIVIDE : integer := 2;
OUT1_DIVIDE : integer := 2;
OUT2_DIVIDE : integer := 2;
OUT3_DIVIDE : integer := 2
);
port
(
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic;
CLK_IN : in std_logic;
CLKFB_IN : in std_logic;
CLKFB_OUT : out std_logic;
PLL_LOCKED_OUT : out std_logic;
PLL_RESET_IN : in std_logic
);
end component;
component csr_regs
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
csr_ctl_reserved_o : out std_logic_vector(31 downto 0);
csr_sta_reserved_i : in std_logic_vector(31 downto 0);
csr_fmc1_clk_cnt_reserved_i : in std_logic_vector(31 downto 0);
csr_fmc2_clk_cnt_reserved_i : in std_logic_vector(31 downto 0)
);
end component csr_regs;
-- Clocks
signal clk_20m_vcxo_buf, clk_pllref_125m_ibuf : std_logic;
signal fmc0_gbtclk0_m2c, clk_125m_pllref : std_logic;
signal sys_clk_62m5_buf, sys_clk_fb, sys_clk_62m5 : std_logic;
-- Resets
signal local_rst_n, local_rst, rst_n_a, vme_rst : std_logic;
signal rst_n_synch : std_logic_vector(1 downto 0);
-- VME mux
signal s_vme_data_b_o : std_logic_vector(31 downto 0);
signal s_vme_data_dir, s_vme_addr_dir : std_logic;
signal s_vme_lword_n_b_o : std_logic;
signal s_vme_addr_b_o : std_logic_vector(31 downto 1);
-- CSR WISHBONE
-- 2x I2C, 1x CSR
constant c_NUM_WB_MASTERS : integer := 3;
-- CSR wishbone address decoder
-- 0x00000 -> FMC0 I2C
-- 0x00100 -> FMC1 I2C
-- 0x00200 -> CSR
constant c_xwb_i2c_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- GSI
device_id => x"12300000",
version => x"00000001",
date => x"20120518",
name => "WB4-I2C-controller ")));
constant c_xwb_csr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- GSI
device_id => x"12300666",
version => x"00000001",
date => x"20121102",
name => "WB4-svec-pts-CSR ")));
constant c_SLAVE_I2C0 : integer := 0;
constant c_SLAVE_I2C1 : integer := 1;
constant c_SLAVE_CSR : integer := 2;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
(c_SLAVE_I2C0 => f_sdb_embed_device(c_xwb_i2c_sdb, x"00000000"),
c_SLAVE_I2C1 => f_sdb_embed_device(c_xwb_i2c_sdb, x"00000100"),
c_SLAVE_CSR => f_sdb_embed_device(c_xwb_csr_sdb, x"00000200"));
constant c_SDB_ADDRESS : t_wishbone_address := x"000F0000";
signal cnx_slave_in : t_wishbone_slave_in;
signal cnx_slave_out : t_wishbone_slave_out;
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal dummy_reg_1, dummy_reg_2 : std_logic_vector(31 downto 0);
-- FMC1 I2C
signal fmc0_scl_in, fmc0_scl_out : std_logic;
signal fmc0_scl_oe_n, fmc0_sda_in : std_logic;
signal fmc0_sda_out, fmc0_sda_oe_n : std_logic;
-- FMC2 I2C
signal fmc1_scl_in, fmc1_scl_out : std_logic;
signal fmc1_scl_oe_n, fmc1_sda_in : std_logic;
signal fmc1_sda_out, fmc1_sda_oe_n : std_logic;
-- LEDs
signal fmc1_led_divider : unsigned(22 downto 0);
signal fmc2_led_divider : unsigned(22 downto 0);
signal dbg_led : std_logic_vector(3 downto 0);
-- GTP
signal clk_gtp_y0, clk_gtp_y1 : std_logic;
signal fmc1_clkout0 : std_logic_vector(1 downto 0);
signal fmc1_clkout1 : std_logic_vector(1 downto 0);
signal fmc1_clkout0_buf : std_logic;
signal fmc1_usrclk : std_logic;
signal fmc1_usrclk2 : std_logic;
signal fmc1_pll_rst : std_logic;
signal fmc1_pll_fb : std_logic;
signal fmc1_pll_lock : std_logic;
signal fmc1_pll_lock0 : std_logic;
signal fmc1_pll_lock1 : std_logic;
signal fmc1_clk_cnt : unsigned(31 downto 0);
signal fmc1_clk_cnt_freeze : std_logic_vector(31 downto 0);
signal fmc1_clk_cnt_sync : std_logic_vector(31 downto 0);
signal fmc1_clk_cnt_sync1 : std_logic_vector(31 downto 0);
signal fmc2_clkout0 : std_logic_vector(1 downto 0);
signal fmc2_clkout1 : std_logic_vector(1 downto 0);
signal fmc2_clkout0_buf : std_logic;
signal fmc2_usrclk : std_logic;
signal fmc2_usrclk2 : std_logic;
signal fmc2_pll_rst : std_logic;
signal fmc2_pll_fb : std_logic;
signal fmc2_pll_lock : std_logic;
signal fmc2_pll_lock0 : std_logic;
signal fmc2_pll_lock1 : std_logic;
signal fmc2_clk_cnt : unsigned(31 downto 0);
signal fmc2_clk_cnt_freeze : std_logic_vector(31 downto 0);
signal fmc2_clk_cnt_sync : std_logic_vector(31 downto 0);
signal fmc2_clk_cnt_sync1 : std_logic_vector(31 downto 0);
-- PPS
signal pps_cnt : unsigned(31 downto 0);
signal pps_p : std_logic;
signal fmc1_pps_sync : std_logic_vector(2 downto 0);
signal fmc1_pps_sync_p : std_logic;
signal fmc2_pps_sync : std_logic_vector(2 downto 0);
signal fmc2_pps_sync_p : std_logic;
begin
---------------------------------------------------------------------------------------------------
-- Clocks --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
U_Buf_CLK_GTP : IBUFDS
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => false) -- Low power (TRUE) vs. performance (FALSE) setting for referenced
port map
(O => clk_125m_pllref,
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_dmtd_clk_pll : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_62m5_buf,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dbg_led(3),
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => clk_125m_pllref);
cmp_sys_clk_65m5_buf : BUFG
port map
(O => sys_clk_62m5,
I => sys_clk_62m5_buf);
cmp_gbtclk_buf1 : IBUFDS
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "DEFAULT")
port map
(O => clk_gtp_y0,
I => clk_gtp_carrier_y0_p_i,
IB => clk_gtp_carrier_y0_n_i);
cmp_gbtclk_buf2 : IBUFDS
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "DEFAULT")
port map
(O => clk_gtp_y1,
I => clk_gtp_carrier_y1_p_i,
IB => clk_gtp_carrier_y1_n_i);
---------------------------------------------------------------------------------------------------
-- Reset --
---------------------------------------------------------------------------------------------------
-- Synchronous process rst_n_synchronizer: Synchronization of the reset inputs to the
-- sys_clk_62m5, using a set of 2 registers
rst_n_i_synchronizer : process (sys_clk_62m5)
begin
if rising_edge (sys_clk_62m5) then
rst_n_synch <= rst_n_synch(0) & (rst_n_a);
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_n_a <= rst_n_i and VME_RST_n_i;
local_rst_n <= rst_n_synch(1);
local_rst <= not rst_n_synch(1);
U_VME_Core : xvme64x_core
port map (
clk_i => sys_clk_62m5,
rst_n_i => local_rst_n,
vme_as_n_i => vme_as_n_i,
vme_rst_n_i => vme_rst,
vme_write_n_i => vme_write_n_i,
vme_am_i => vme_am_i,
vme_ds_n_i => vme_ds_n_i,
vme_ga_i => vme_ga_i,
vme_berr_o => vme_berr_o,
vme_dtack_n_o => vme_dtack_n_o,
vme_retry_n_o => vme_retry_n_o,
vme_lword_n_b_i => vme_lword_n_b,
vme_lword_n_b_o => s_vme_lword_n_b_o,
vme_addr_b_i => vme_addr_b,
vme_addr_b_o => s_vme_addr_b_o,
vme_data_b_i => vme_data_b,
vme_data_b_o => s_vme_data_b_o,
vme_irq_n_o => vme_irq_n_o,
vme_iackin_n_i => vme_iackin_n_i,
vme_iack_n_i => vme_iack_n_i,
vme_iackout_n_o => vme_iackout_n_o,
vme_dtack_oe_o => vme_dtack_oe_o,
vme_data_dir_o => s_vme_data_dir,
vme_data_oe_n_o => vme_data_oe_n_o,
vme_addr_dir_o => s_vme_addr_dir,
vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_retry_oe_o => vme_retry_oe_o,
master_o => cnx_slave_in,
master_i => cnx_slave_out,
irq_i => '0',
irq_ack_o => open);
vme_rst <= vme_rst_n_i and rst_n_i;
--------------------------------------------------------------------------------
-- Davide: buffers similar to the board buffers
vme_data_b <= s_vme_data_b_o when s_vme_data_dir = '1' else (others => 'Z');
vme_addr_b <= s_vme_addr_b_o when s_vme_addr_dir = '1' else (others => 'Z');
vme_lword_n_b <= s_vme_lword_n_b_o when s_vme_addr_dir = '1' else 'Z';
-- Outputs
vme_addr_dir_o <= s_vme_addr_dir;
vme_data_dir_o <= s_vme_data_dir;
U_Intercon : xwb_sdb_crossbar
generic map (
g_num_masters => 1,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => sys_clk_62m5,
rst_n_i => local_rst_n,
slave_i(0) => cnx_slave_in,
slave_o(0) => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- FMC1 I2C to configure Si570
---------------------------------------------------------------------------------------------------
mezz_0_I2C_master_crosspoint_switch : xwb_i2c_master
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map
(clk_sys_i => sys_clk_62m5,
rst_n_i => local_rst_n,
slave_i => cnx_master_out(c_SLAVE_I2C0),
slave_o => cnx_master_in(c_SLAVE_I2C0),
scl_pad_i => fmc0_scl_in,
scl_pad_o => fmc0_scl_out,
scl_padoen_o => fmc0_scl_oe_n,
sda_pad_i => fmc0_sda_in,
sda_pad_o => fmc0_sda_out,
sda_padoen_o => fmc0_sda_oe_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tri-state buffer for SDA and SCL
fmc0_scl_b <= fmc0_scl_out when fmc0_scl_oe_n = '0' else 'Z';
fmc0_scl_in <= fmc0_scl_b;
fmc0_sda_b <= fmc0_sda_out when fmc0_sda_oe_n = '0' else 'Z';
fmc0_sda_in <= fmc0_sda_b;
---------------------------------------------------------------------------------------------------
-- FMC2 I2C to configure Si570
---------------------------------------------------------------------------------------------------
mezz_1_I2C_master_crosspoint_switch : xwb_i2c_master
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map
(clk_sys_i => sys_clk_62m5,
rst_n_i => local_rst_n,
slave_i => cnx_master_out(c_SLAVE_I2C1),
slave_o => cnx_master_in(c_SLAVE_I2C1),
scl_pad_i => fmc1_scl_in,
scl_pad_o => fmc1_scl_out,
scl_padoen_o => fmc1_scl_oe_n,
sda_pad_i => fmc1_sda_in,
sda_pad_o => fmc1_sda_out,
sda_padoen_o => fmc1_sda_oe_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tri-state buffer for SDA and SCL
fmc1_scl_b <= fmc1_scl_out when fmc1_scl_oe_n = '0' else 'Z';
fmc1_scl_in <= fmc1_scl_b;
fmc1_sda_b <= fmc1_sda_out when fmc1_sda_oe_n = '0' else 'Z';
fmc1_sda_in <= fmc1_sda_b;
---------------------------------------------------------------------------------------------------
-- CSR register to read clock counters
---------------------------------------------------------------------------------------------------
cmp_csr_regs : csr_regs
port map(
rst_n_i => local_rst_n,
wb_clk_i => sys_clk_62m5,
wb_addr_i => cnx_master_out(c_SLAVE_CSR).adr(3 downto 2),
wb_data_i => cnx_master_out(c_SLAVE_CSR).dat,
wb_data_o => cnx_master_in(c_SLAVE_CSR).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_CSR).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_CSR).sel,
wb_stb_i => cnx_master_out(c_SLAVE_CSR).stb,
wb_we_i => cnx_master_out(c_SLAVE_CSR).we,
wb_ack_o => cnx_master_in(c_SLAVE_CSR).ack,
csr_ctl_reserved_o => open,
csr_sta_reserved_i => X"DEADBABE",
csr_fmc1_clk_cnt_reserved_i => fmc1_clk_cnt_sync,
csr_fmc2_clk_cnt_reserved_i => fmc2_clk_cnt_sync
);
-- Unused wishbone signals
cnx_master_in(c_SLAVE_CSR).err <= '0';
cnx_master_in(c_SLAVE_CSR).rty <= '0';
cnx_master_in(c_SLAVE_CSR).stall <= '0';
cnx_master_in(c_SLAVE_CSR).int <= '0';
-------------------------------------------------------------------------------------------------
-- GTP reference clock from FMC 1 and FMC 2
---------------------------------------------------------------------------------------------------
cmp_fmc1_usrclk : BUFIO2
generic map (
DIVIDE => 1,
DIVIDE_BYPASS => true
)
port map (
I => fmc1_clkout0(0), --tile0_gtpclkout0_i(0),
DIVCLK => fmc1_clkout0_buf, --tile0_gtpclkout0_0_to_cmt_i,
IOCLK => open,
SERDESSTROBE => open
);
--gtpclkout0_0_pll0_reset_i <= not tile0_plllkdet0_i;
fmc1_pll_rst <= not(fmc1_pll_lock0);
cmp_fmc1_gtpclk_pll : MGT_USRCLK_SOURCE_PLL
generic map (
MULT => 8,
DIVIDE => 1,
FEEDBACK => "CLKFBOUT",
CLK_PERIOD => 8.0,
OUT0_DIVIDE => 32,
OUT1_DIVIDE => 8,
OUT2_DIVIDE => 8,
OUT3_DIVIDE => 1
)
port map (
CLK0_OUT => fmc1_usrclk2, --tile0_txusrclk20_i,
CLK1_OUT => fmc1_usrclk, --tile0_txusrclk0_i,
CLK2_OUT => open,
CLK3_OUT => open,
CLK_IN => fmc1_clkout0_buf, --tile0_gtpclkout0_0_to_cmt_i,
CLKFB_IN => fmc1_pll_fb, --pll0_fb_out_i,
CLKFB_OUT => fmc1_pll_fb, --pll0_fb_out_i,
PLL_LOCKED_OUT => fmc1_pll_lock, --gtpclkout0_0_pll0_locked_i,
PLL_RESET_IN => fmc1_pll_rst --gtpclkout0_0_pll0_reset_i
);
cmp_fmc2_usrclk : BUFIO2
generic map (
DIVIDE => 1,
DIVIDE_BYPASS => true
)
port map (
I => fmc2_clkout0(0), --tile1_gtpclkout0_i(0),
DIVCLK => fmc2_clkout0_buf, --tile1_gtpclkout0_0_to_cmt_i,
IOCLK => open,
SERDESSTROBE => open
);
--gtpclkout0_0_pll1_reset_i <= not tile1_plllkdet0_i;
fmc2_pll_rst <= not(fmc2_pll_lock0);
cmp_fmc2_gtpclk_pll : MGT_USRCLK_SOURCE_PLL
generic map (
MULT => 8,
DIVIDE => 1,
FEEDBACK => "CLKFBOUT",
CLK_PERIOD => 8.0,
OUT0_DIVIDE => 32,
OUT1_DIVIDE => 8,
OUT2_DIVIDE => 8,
OUT3_DIVIDE => 1
)
port map (
CLK0_OUT => fmc2_usrclk2, --tile1_txusrclk20_i,
CLK1_OUT => fmc2_usrclk, --tile1_txusrclk0_i,
CLK2_OUT => open,
CLK3_OUT => open,
CLK_IN => fmc2_clkout0_buf, --tile1_gtpclkout0_0_to_cmt_i,
CLKFB_IN => fmc2_pll_fb, --pll1_fb_out_i,
CLKFB_OUT => fmc2_pll_fb, --pll1_fb_out_i,
PLL_LOCKED_OUT => fmc2_pll_lock, --gtpclkout0_0_pll1_locked_i,
PLL_RESET_IN => fmc2_pll_rst --gtpclkout0_0_pll1_reset_i
);
cmp_gtp_wrapper : fmc_refclk_test
generic map (
WRAPPER_SIM_GTPRESET_SPEEDUP => 0,
WRAPPER_CLK25_DIVIDER_0 => 5,
WRAPPER_CLK25_DIVIDER_1 => 5,
WRAPPER_PLL_DIVSEL_FB_0 => 2,
WRAPPER_PLL_DIVSEL_FB_1 => 2,
WRAPPER_PLL_DIVSEL_REF_0 => 1,
WRAPPER_PLL_DIVSEL_REF_1 => 1,
WRAPPER_SIMULATION => 0
)
port map (
--_____________________________________________________________________
--_____________________________________________________________________
--TILE0 (X1_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_LOOPBACK0_IN => "000", --tile0_loopback0_i,
TILE0_LOOPBACK1_IN => "000", --tile0_loopback1_i,
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN => clk_gtp_y0, --tile0_gtp0_refclk_i,
TILE0_CLK01_IN => clk_gtp_y0, --tile0_gtp0_refclk_i,
TILE0_GTPRESET0_IN => '0', --tile0_gtpreset0_i,
TILE0_GTPRESET1_IN => '0', --tile0_gtpreset1_i,
TILE0_PLLLKDET0_OUT => fmc1_pll_lock0, --tile0_plllkdet0_i,
TILE0_PLLLKDET1_OUT => fmc1_pll_lock1, --tile0_plllkdet1_i,
TILE0_RESETDONE0_OUT => open, --tile0_resetdone0_i,
TILE0_RESETDONE1_OUT => open, --tile0_resetdone1_i,
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXDISPERR0_OUT => open, --tile0_rxdisperr0_i,
TILE0_RXDISPERR1_OUT => open, --tile0_rxdisperr1_i,
TILE0_RXNOTINTABLE0_OUT => open, --tile0_rxnotintable0_i,
TILE0_RXNOTINTABLE1_OUT => open, --tile0_rxnotintable1_i,
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN => '0', --tile0_rxenmcommaalign0_i,
TILE0_RXENMCOMMAALIGN1_IN => '0', --tile0_rxenmcommaalign1_i,
TILE0_RXENPCOMMAALIGN0_IN => '0', --tile0_rxenpcommaalign0_i,
TILE0_RXENPCOMMAALIGN1_IN => '0', --tile0_rxenpcommaalign1_i,
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT => open, --tile0_rxdata0_i,
TILE0_RXDATA1_OUT => open, --tile0_rxdata1_i,
TILE0_RXUSRCLK0_IN => fmc1_usrclk, --tile0_txusrclk0_i,
TILE0_RXUSRCLK1_IN => fmc1_usrclk, --tile0_txusrclk0_i,
TILE0_RXUSRCLK20_IN => fmc1_usrclk2, --tile0_txusrclk20_i,
TILE0_RXUSRCLK21_IN => fmc1_usrclk2, --tile0_txusrclk20_i,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_RXEQMIX0_IN => "00", --tile0_rxeqmix0_i,
TILE0_RXEQMIX1_IN => "00", --tile0_rxeqmix1_i,
TILE0_RXN0_IN => '1', --RXN_IN(0),
TILE0_RXN1_IN => '1', --RXN_IN(1),
TILE0_RXP0_IN => '0', --RXP_IN(0),
TILE0_RXP1_IN => '0', --RXP_IN(1),
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE0_RXLOSSOFSYNC0_OUT => open, --tile0_rxlossofsync0_i,
TILE0_RXLOSSOFSYNC1_OUT => open, --tile0_rxlossofsync1_i,
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT => fmc1_clkout0, --tile0_gtpclkout0_i,
TILE0_GTPCLKOUT1_OUT => fmc1_clkout1, --tile0_gtpclkout1_i,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARISK0_IN => "0000", --tile0_txcharisk0_i,
TILE0_TXCHARISK1_IN => "0000", --tile0_txcharisk1_i,
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN => X"00000000", --tile0_txdata0_i,
TILE0_TXDATA1_IN => X"00000000", --tile0_txdata1_i,
TILE0_TXOUTCLK0_OUT => open, --tile0_txoutclk0_i,
TILE0_TXOUTCLK1_OUT => open, --tile0_txoutclk1_i,
TILE0_TXUSRCLK0_IN => fmc1_usrclk, --tile0_txusrclk0_i,
TILE0_TXUSRCLK1_IN => fmc1_usrclk, --tile0_txusrclk0_i,
TILE0_TXUSRCLK20_IN => fmc1_usrclk2, --tile0_txusrclk20_i,
TILE0_TXUSRCLK21_IN => fmc1_usrclk2, --tile0_txusrclk20_i,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXDIFFCTRL0_IN => "0000", --tile0_txdiffctrl0_i,
TILE0_TXDIFFCTRL1_IN => "0000", --tile0_txdiffctrl1_i,
TILE0_TXN0_OUT => open, --TXN_OUT(0),
TILE0_TXN1_OUT => open, --TXN_OUT(1),
TILE0_TXP0_OUT => open, --TXP_OUT(0),
TILE0_TXP1_OUT => open, --TXP_OUT(1),
TILE0_TXPREEMPHASIS0_IN => "000", --tile0_txpreemphasis0_i,
TILE0_TXPREEMPHASIS1_IN => "000", --tile0_txpreemphasis1_i,
--_____________________________________________________________________
--_____________________________________________________________________
--TILE1 (X0_Y1)
------------------------ Loopback and Powerdown Ports ----------------------
TILE1_LOOPBACK0_IN => "000", --tile1_loopback0_i,
TILE1_LOOPBACK1_IN => "000", --tile1_loopback1_i,
--------------------------------- PLL Ports --------------------------------
TILE1_CLK00_IN => clk_gtp_y1, --tile1_gtp0_refclk_i,
TILE1_CLK01_IN => clk_gtp_y1, --tile1_gtp0_refclk_i,
TILE1_GTPRESET0_IN => '0', --tile1_gtpreset0_i,
TILE1_GTPRESET1_IN => '0', --tile1_gtpreset1_i,
TILE1_PLLLKDET0_OUT => fmc2_pll_lock0, --tile1_plllkdet0_i,
TILE1_PLLLKDET1_OUT => fmc2_pll_lock1, --tile1_plllkdet1_i,
TILE1_RESETDONE0_OUT => open, --tile1_resetdone0_i,
TILE1_RESETDONE1_OUT => open, --tile1_resetdone1_i,
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE1_RXDISPERR0_OUT => open, --tile1_rxdisperr0_i,
TILE1_RXDISPERR1_OUT => open, --tile1_rxdisperr1_i,
TILE1_RXNOTINTABLE0_OUT => open, --tile1_rxnotintable0_i,
TILE1_RXNOTINTABLE1_OUT => open, --tile1_rxnotintable1_i,
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE1_RXENMCOMMAALIGN0_IN => '0', --tile1_rxenmcommaalign0_i,
TILE1_RXENMCOMMAALIGN1_IN => '0', --tile1_rxenmcommaalign1_i,
TILE1_RXENPCOMMAALIGN0_IN => '0', --tile1_rxenpcommaalign0_i,
TILE1_RXENPCOMMAALIGN1_IN => '0', --tile1_rxenpcommaalign1_i,
------------------- Receive Ports - RX Data Path interface -----------------
TILE1_RXDATA0_OUT => open, --tile1_rxdata0_i,
TILE1_RXDATA1_OUT => open, --tile1_rxdata1_i,
TILE1_RXUSRCLK0_IN => fmc2_usrclk, --tile1_txusrclk0_i,
TILE1_RXUSRCLK1_IN => fmc2_usrclk, --tile1_txusrclk0_i,
TILE1_RXUSRCLK20_IN => fmc2_usrclk2, --tile1_txusrclk20_i,
TILE1_RXUSRCLK21_IN => fmc2_usrclk2, --tile1_txusrclk20_i,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE1_RXEQMIX0_IN => "00", --tile1_rxeqmix0_i,
TILE1_RXEQMIX1_IN => "00", --tile1_rxeqmix1_i,
TILE1_RXN0_IN => '1', --RXN_IN(2),
TILE1_RXN1_IN => '1', --RXN_IN(3),
TILE1_RXP0_IN => '0', --RXP_IN(2),
TILE1_RXP1_IN => '0', --RXP_IN(3),
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
TILE1_RXLOSSOFSYNC0_OUT => open, --tile1_rxlossofsync0_i,
TILE1_RXLOSSOFSYNC1_OUT => open, --tile1_rxlossofsync1_i,
---------------------------- TX/RX Datapath Ports --------------------------
TILE1_GTPCLKOUT0_OUT => fmc2_clkout0, --tile1_gtpclkout0_i,
TILE1_GTPCLKOUT1_OUT => fmc2_clkout1, --tile1_gtpclkout1_i,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE1_TXCHARISK0_IN => "0000", --tile1_txcharisk0_i,
TILE1_TXCHARISK1_IN => "0000", --tile1_txcharisk1_i,
------------------ Transmit Ports - TX Data Path interface -----------------
TILE1_TXDATA0_IN => X"00000000", --tile1_txdata0_i,
TILE1_TXDATA1_IN => X"00000000", --tile1_txdata1_i,
TILE1_TXOUTCLK0_OUT => open, --tile1_txoutclk0_i,
TILE1_TXOUTCLK1_OUT => open, --tile1_txoutclk1_i,
TILE1_TXUSRCLK0_IN => fmc2_usrclk, --tile1_txusrclk0_i,
TILE1_TXUSRCLK1_IN => fmc2_usrclk, --tile1_txusrclk0_i,
TILE1_TXUSRCLK20_IN => fmc2_usrclk2, --tile1_txusrclk20_i,
TILE1_TXUSRCLK21_IN => fmc2_usrclk2, --tile1_txusrclk20_i,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE1_TXDIFFCTRL0_IN => "0000", --tile1_txdiffctrl0_i,
TILE1_TXDIFFCTRL1_IN => "0000", --tile1_txdiffctrl1_i,
TILE1_TXN0_OUT => open, --TXN_OUT(2),
TILE1_TXN1_OUT => open, --TXN_OUT(3),
TILE1_TXP0_OUT => open, --TXP_OUT(2),
TILE1_TXP1_OUT => open, --TXP_OUT(3),
TILE1_TXPREEMPHASIS0_IN => "000", --tile1_txpreemphasis0_i,
TILE1_TXPREEMPHASIS1_IN => "000" --tile1_txpreemphasis1_i
);
-------------------------------------------------------------------------------------------------
-- PPS counter
-------------------------------------------------------------------------------------------------
p_pps_cnt : process (sys_clk_62m5)
begin
if rising_edge(sys_clk_62m5) then
if local_rst_n = '0' then
pps_cnt <= to_unsigned(62499999, pps_cnt'length);
pps_p <= '0';
dbg_led(2) <= '0';
elsif pps_cnt = 0 then
pps_cnt <= to_unsigned(62499999, pps_cnt'length);
pps_p <= '1';
dbg_led(2) <= not(dbg_led(2));
else
pps_cnt <= pps_cnt - 1;
pps_p <= '0';
end if;
end if;
end process p_pps_cnt;
-------------------------------------------------------------------------------------------------
-- FMC 1 clock counter
-------------------------------------------------------------------------------------------------
p_fmc1_pps_sync : process (fmc1_usrclk)
begin
if rising_edge(fmc1_usrclk) then
fmc1_pps_sync <= fmc1_pps_sync(1 downto 0) & pps_p;
end if;
end process p_fmc1_pps_sync;
fmc1_pps_sync_p <= fmc1_pps_sync(1) and not(fmc1_pps_sync(2));
p_fmc1_clk_cnt : process (fmc1_usrclk)
begin
if rising_edge(fmc1_usrclk) then
if fmc1_pps_sync_p = '1' then
fmc1_clk_cnt <= (others => '0');
fmc1_clk_cnt_freeze <= std_logic_vector(fmc1_clk_cnt);
else
fmc1_clk_cnt <= fmc1_clk_cnt + 1;
end if;
end if;
end process p_fmc1_clk_cnt;
p_fmc1_clk_cnt_sync : process (sys_clk_62m5)
begin
if rising_edge(sys_clk_62m5) then
if local_rst_n = '0' then
fmc1_clk_cnt_sync1 <= (others => '0');
fmc1_clk_cnt_sync <= (others => '0');
else
fmc1_clk_cnt_sync1 <= fmc1_clk_cnt_freeze;
fmc1_clk_cnt_sync <= fmc1_clk_cnt_sync1;
end if;
end if;
end process p_fmc1_clk_cnt_sync;
p_led_clkfmc1 : process (fmc1_usrclk)
begin
if rising_edge(fmc1_usrclk) then
fmc1_led_divider <= fmc1_led_divider + 1;
if(fmc1_led_divider = 0) then
dbg_led(0) <= not(dbg_led(0));
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------
-- FMC 2 clock counter
-------------------------------------------------------------------------------------------------
p_fmc2_pps_sync : process (fmc2_usrclk)
begin
if rising_edge(fmc2_usrclk) then
fmc2_pps_sync <= fmc2_pps_sync(1 downto 0) & pps_p;
end if;
end process p_fmc2_pps_sync;
fmc2_pps_sync_p <= fmc2_pps_sync(1) and not(fmc2_pps_sync(2));
p_fmc2_clk_cnt : process (fmc2_usrclk)
begin
if rising_edge(fmc2_usrclk) then
if fmc2_pps_sync_p = '1' then
fmc2_clk_cnt <= (others => '0');
fmc2_clk_cnt_freeze <= std_logic_vector(fmc2_clk_cnt);
else
fmc2_clk_cnt <= fmc2_clk_cnt + 1;
end if;
end if;
end process p_fmc2_clk_cnt;
p_fmc2_clk_cnt_sync : process (sys_clk_62m5)
begin
if rising_edge(sys_clk_62m5) then
if local_rst_n = '0' then
fmc2_clk_cnt_sync1 <= (others => '0');
fmc2_clk_cnt_sync <= (others => '0');
else
fmc2_clk_cnt_sync1 <= fmc2_clk_cnt_freeze;
fmc2_clk_cnt_sync <= fmc2_clk_cnt_sync1;
end if;
end if;
end process p_fmc2_clk_cnt_sync;
p_led_clkfmc2 : process (fmc2_usrclk)
begin
if rising_edge(fmc2_usrclk) then
fmc2_led_divider <= fmc2_led_divider + 1;
if(fmc2_led_divider = 0) then
dbg_led(1) <= not(dbg_led(1));
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------
-- LEDS
-------------------------------------------------------------------------------------------------
dbg_led_n_o <= not(dbg_led); -- Debug LEDs are active low
fp_ledn_o <= (others => '0');
end rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
test/svec/VHDL/svec_pts_gtp_clkfmc/rtl/wishbone_pkg.vhd 0 → 100644
View file @ b718a368
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
package wishbone_pkg is
constant c_wishbone_address_width : integer := 32;
constant c_wishbone_data_width : integer := 32;
subtype t_wishbone_address is
std_logic_vector(c_wishbone_address_width-1 downto 0);
subtype t_wishbone_data is
std_logic_vector(c_wishbone_data_width-1 downto 0);
subtype t_wishbone_byte_select is
std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
subtype t_wishbone_cycle_type is
std_logic_vector(2 downto 0);
subtype t_wishbone_burst_type is
std_logic_vector(1 downto 0);
type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
type t_wishbone_address_granularity is (BYTE, WORD);
type t_wishbone_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wishbone_address;
sel : t_wishbone_byte_select;
we : std_logic;
dat : t_wishbone_data;
end record t_wishbone_master_out;
subtype t_wishbone_slave_in is t_wishbone_master_out;
type t_wishbone_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_slave_out;
subtype t_wishbone_master_in is t_wishbone_slave_out;
subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
type t_wishbone_address_array is array(natural range <>) of t_wishbone_address;
type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0):=
(others => 'X');
constant cc_dummy_data : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_slave_in : t_wishbone_slave_in :=
('0', 'X', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
constant cc_dummy_master_out : t_wishbone_master_out := cc_dummy_slave_in;
-- Dangerous! Will stall a bus.
constant cc_dummy_slave_out : t_wishbone_slave_out :=
('X', 'X', 'X', 'X', 'X', cc_dummy_data);
constant cc_dummy_master_in : t_wishbone_master_in := cc_dummy_slave_out;
-- A generally useful function.
function f_ceil_log2(x : natural) return natural;
------------------------------------------------------------------------------
-- SDB declaration
------------------------------------------------------------------------------
constant c_sdb_device_length : natural := 512; -- bits
subtype t_sdb_record is std_logic_vector(c_sdb_device_length-1 downto 0);
type t_sdb_record_array is array(natural range <>) of t_sdb_record;
type t_sdb_product is record
vendor_id : std_logic_vector(63 downto 0);
device_id : std_logic_vector(31 downto 0);
version : std_logic_vector(31 downto 0);
date : std_logic_vector(31 downto 0);
name : string(1 to 19);
end record t_sdb_product;
type t_sdb_component is record
addr_first : std_logic_vector(63 downto 0);
addr_last : std_logic_vector(63 downto 0);
product : t_sdb_product;
end record t_sdb_component;
constant c_sdb_endian_big : std_logic := '0';
constant c_sdb_endian_little : std_logic := '1';
type t_sdb_device is record
abi_class : std_logic_vector(15 downto 0);
abi_ver_major : std_logic_vector(7 downto 0);
abi_ver_minor : std_logic_vector(7 downto 0);
wbd_endian : std_logic; -- 0 = big, 1 = little
wbd_width : std_logic_vector(3 downto 0); -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
sdb_component : t_sdb_component;
end record t_sdb_device;
type t_sdb_bridge is record
sdb_child : std_logic_vector(63 downto 0);
sdb_component : t_sdb_component;
end record t_sdb_bridge;
-- Used to configure a device at a certain address
function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address) return t_sdb_record;
function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address) return t_sdb_record;
function f_sdb_extract_device(sdb_record : t_sdb_record) return t_sdb_device;
function f_sdb_extract_bridge(sdb_record : t_sdb_record) return t_sdb_bridge;
-- For internal use by the crossbar
function f_sdb_embed_product(product : t_sdb_product) return std_logic_vector; -- (319 downto 8)
function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address) return std_logic_vector; -- (447 downto 8)
function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8)) return t_sdb_product;
function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8)) return t_sdb_component;
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_slave_adapter
generic (
g_master_use_struct : boolean;
g_master_mode : t_wishbone_interface_mode;
g_master_granularity : t_wishbone_address_granularity;
g_slave_use_struct : boolean;
g_slave_mode : t_wishbone_interface_mode;
g_slave_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := cc_dummy_sel;
sl_cyc_i : in std_logic := '0';
sl_stb_i : in std_logic := '0';
sl_we_i : in std_logic := '0';
sl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
sl_err_o : out std_logic;
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
ma_cyc_o : out std_logic;
ma_stb_o : out std_logic;
ma_we_o : out std_logic;
ma_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
ma_err_i : in std_logic := '0';
ma_rty_i : in std_logic := '0';
ma_ack_i : in std_logic := '0';
ma_stall_i : in std_logic := '0';
ma_int_i : in std_logic := '0';
master_i : in t_wishbone_master_in := cc_dummy_slave_out;
master_o : out t_wishbone_master_out);
end component;
component wb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
wb_adr_o : out std_logic_vector(c_wishbone_address_width - 1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_sel_o : out std_logic_vector(3 downto 0);
wb_cyc_o : out std_logic;
wb_dat_i : in std_logic_vector (c_wishbone_data_width-1 downto 0);
wb_ack_i : in std_logic;
wb_stall_i : in std_logic := '0');
end component;
component xwb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
component xwb_bus_fanout
generic (
g_num_outputs : natural;
g_bits_per_slave : integer;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_slave_interface_mode : t_wishbone_interface_mode := CLASSIC);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1));
end component;
component xwb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean;
g_address : t_wishbone_address_array;
g_mask : t_wishbone_address_array);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
end component;
-- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
function f_xwb_bridge_manual_sdb( -- take a manual bus size
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
function f_xwb_bridge_layout_sdb( -- determine bus size from layout
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
component xwb_sdb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean := false;
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
end component;
component sdb_rom is
generic(
g_layout : t_sdb_record_array;
g_bus_end : unsigned(63 downto 0));
port(
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end component;
constant c_xwb_dma_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"cababa56",
version => x"00000001",
date => x"20120518",
name => "WB4-Streaming-DMA_0")));
component xwb_dma is
generic(
-- Value 0 cannot stream
-- Value 1 only slaves with async ACK can stream
-- Value 2 only slaves with combined latency <= 2 can stream
-- Value 3 only slaves with combined latency <= 6 can stream
-- Value 4 only slaves with combined latency <= 14 can stream
-- ....
logRingLen : integer := 4
);
port(
-- Common wishbone signals
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Slave control port
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
r_master_i : in t_wishbone_master_in;
r_master_o : out t_wishbone_master_out;
-- Master writer port
w_master_i : in t_wishbone_master_in;
w_master_o : out t_wishbone_master_out;
-- Pulsed high completion signal
interrupt_o : out std_logic
);
end component;
component xwb_clock_crossing is
generic(
sync_depth : natural := 3;
log2fifo : natural := 4);
port(
-- Common wishbone signals
rst_n_i : in std_logic;
-- Slave control port
slave_clk_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
master_clk_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end component;
subtype t_xwb_dpram_init is t_generic_ram_init;
constant c_xwb_dpram_init_nothing : t_xwb_dpram_init := c_generic_ram_nothing;
-- g_size is in words
function f_xwb_dpram(g_size : natural) return t_sdb_device;
component xwb_dpram
generic (
g_size : natural;
g_init_file : string := "";
g_init_value : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave2_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave1_granularity : t_wishbone_address_granularity := WORD;
g_slave2_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end component;
component wb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component xwb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component wb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
scl_pad_i : in std_logic;
scl_pad_o : out std_logic;
scl_padoen_o : out std_logic;
sda_pad_i : in std_logic;
sda_pad_o : out std_logic;
sda_padoen_o : out std_logic);
end component;
component xwb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
scl_pad_i : in std_logic;
scl_pad_o : out std_logic;
scl_padoen_o : out std_logic;
sda_pad_i : in std_logic;
sda_pad_o : out std_logic;
sda_padoen_o : out std_logic);
end component;
component xwb_lm32
generic (
g_profile : string);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0);
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
iwb_o : out t_wishbone_master_out;
iwb_i : in t_wishbone_master_in);
end component;
component wb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "1.0";
g_ow_btp_overdrive : string := "5.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component xwb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "5.0";
g_ow_btp_overdrive : string := "1.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component wb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
pad_cs_o : out std_logic_vector(7 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component xwb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
pad_cs_o : out std_logic_vector(7 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component wb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component xwb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component wb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic);
end component;
component xwb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor);
end component;
component wb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
constant c_xwb_vic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000013",
version => x"00000001",
date => x"20120113",
name => "WB-VIC-Int.Control ")));
component xwb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
end wishbone_pkg;
package body wishbone_pkg is
function f_ceil_log2(x : natural) return natural is
begin
if x <= 1
then return 0;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
function f_sdb_embed_product(product : t_sdb_product)
return std_logic_vector -- (319 downto 8)
is
variable result : std_logic_vector(319 downto 8);
begin
result(319 downto 256) := product.vendor_id;
result(255 downto 224) := product.device_id;
result(223 downto 192) := product.version;
result(191 downto 160) := product.date;
for i in 0 to 18 loop -- string to ascii
result(159-i*8 downto 152-i*8) :=
std_logic_vector(to_unsigned(character'pos(product.name(i+1)), 8));
end loop;
return result;
end;
function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8))
return t_sdb_product
is
variable result : t_sdb_product;
begin
result.vendor_id := sdb_record(319 downto 256);
result.device_id := sdb_record(255 downto 224);
result.version := sdb_record(223 downto 192);
result.date := sdb_record(191 downto 160);
for i in 0 to 18 loop -- ascii to string
result.name(i+1) := character'val(to_integer(unsigned(sdb_record(159-i*8 downto 152-i*8))));
end loop;
return result;
end;
function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address)
return std_logic_vector -- (447 downto 8)
is
variable result : std_logic_vector(447 downto 8);
constant first : unsigned(63 downto 0) := unsigned(sdb_component.addr_first);
constant last : unsigned(63 downto 0) := unsigned(sdb_component.addr_last);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
result(447 downto 384) := std_logic_vector(base);
result(383 downto 320) := std_logic_vector(base + last - first);
result(319 downto 8) := f_sdb_embed_product(sdb_component.product);
return result;
end;
function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8))
return t_sdb_component
is
variable result : t_sdb_component;
begin
result.addr_first := sdb_record(447 downto 384);
result.addr_last := sdb_record(383 downto 320);
result.product := f_sdb_extract_product(sdb_record(319 downto 8));
return result;
end;
function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 496) := device.abi_class;
result(495 downto 488) := device.abi_ver_major;
result(487 downto 480) := device.abi_ver_minor;
result(479 downto 453) := (others => '0');
result(452) := device.wbd_endian;
result(451 downto 448) := device.wbd_width;
result(447 downto 8) := f_sdb_embed_component(device.sdb_component, address);
result( 7 downto 0) := x"01"; -- device
return result;
end;
function f_sdb_extract_device(sdb_record : t_sdb_record)
return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := sdb_record(511 downto 496);
result.abi_ver_major := sdb_record(495 downto 488);
result.abi_ver_minor := sdb_record(487 downto 480);
result.wbd_endian := sdb_record(452);
result.wbd_width := sdb_record(451 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"01"
report "Cannot extract t_sdb_device from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end;
function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
variable first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
variable child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
result(511 downto 448) := std_logic_vector(base + child - first);
result(447 downto 8) := f_sdb_embed_component(bridge.sdb_component, address);
result( 7 downto 0) := x"02"; -- bridge
return result;
end;
function f_sdb_extract_bridge(sdb_record : t_sdb_record)
return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := sdb_record(511 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"02"
report "Cannot extract t_sdb_bridge from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end;
function f_xwb_bridge_manual_sdb(
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := (others => '0');
result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := (others => '0');
result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
result.sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
result.sdb_component.product.device_id := x"eef0b198";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120511";
result.sdb_component.product.name := "WB4-Bridge-GSI ";
return result;
end f_xwb_bridge_manual_sdb;
function f_xwb_bridge_layout_sdb(
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge
is
alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
-- How much space does the ROM need?
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_bytes : natural := c_sdb_device_length / 8;
constant c_rom_bytes : natural := c_rom_entries * c_sdb_bytes;
-- Step 2. Find the size of the bus
function f_bus_end return unsigned is
variable result : unsigned(63 downto 0);
variable sdb_component : t_sdb_component;
begin
if not g_wraparound then
result := (others => '0');
for i in 0 to c_wishbone_address_width-1 loop
result(i) := '1';
end loop;
else
-- The ROM will be an addressed slave as well
result := (others => '0');
result(c_wishbone_address_width-1 downto 0) := unsigned(g_sdb_addr);
result := result + to_unsigned(c_rom_bytes, 64) - 1;
for i in c_layout'range loop
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
if unsigned(sdb_component.addr_last) > result then
result := unsigned(sdb_component.addr_last);
end if;
end loop;
-- round result up to a power of two -1
for i in 62 downto 0 loop
result(i) := result(i) or result(i+1);
end loop;
end if;
return result;
end f_bus_end;
constant bus_end : unsigned(63 downto 0) := f_bus_end;
begin
return f_xwb_bridge_manual_sdb(std_logic_vector(f_bus_end(c_wishbone_address_width-1 downto 0)), g_sdb_addr);
end f_xwb_bridge_layout_sdb;
function f_xwb_dpram(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"66cfeb52";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "WB4-BlockRAM ";
return result;
end f_xwb_dpram;
end wishbone_pkg;
test/svec/VHDL/svec_pts_gtp_clkfmc/rtl/xvme64x_core.vhd 0 → 100644
View file @ b718a368
library ieee;
use ieee.STD_LOGIC_1164.all;
use WORK.wishbone_pkg.all;
use work.vme64x_pack.all;
entity xvme64x_core is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic
);
end xvme64x_core;
architecture wrapper of xvme64x_core is
component VME64xCore_Top
generic (
g_width : integer := 32;
g_addr_width : integer := 64;
g_CRAM_SIZE : integer := 1024);
port (
clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_width - 1 downto 0);
DAT_o : out std_logic_vector(g_width - 1 downto 0);
ADR_o : out std_logic_vector(g_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic;
debug : out std_logic_vector(7 downto 0));
end component;
signal rst_in, rst_out : std_logic;
signal dat_out, dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(63 downto 0);
begin -- wrapper
rst_in <= not rst_n_i;
rst_n_o <= rst_n_i and (not rst_out);
U_Wrapped_VME : VME64xCore_Top
port map (
clk_i => clk_i,
reset_o => rst_out,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_i => VME_LWORD_n_b_i,
VME_LWORD_n_o => VME_LWORD_n_b_o,
VME_ADDR_i => VME_ADDR_b_i,
VME_ADDR_o => VME_ADDR_b_o,
VME_DATA_i => VME_DATA_b_i,
VME_DATA_o => VME_DATA_b_o,
VME_IRQ_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
DAT_i => dat_in,
DAT_o => dat_out,
ADR_o => adr_out,
CYC_o => master_o.cyc,
ERR_i => master_i.err,
RTY_i => master_i.rty,
SEL_o => open,
STB_o => master_o.stb,
ACK_i => master_i.ack,
WE_o => master_o.we,
STALL_i => master_i.stall,
IRQ_i => irq_i,
INT_ack_o => irq_ack_o
);
master_o.dat <= dat_out(31 downto 0);
master_o.sel <= (others => '1');
master_o.adr <= adr_out(29 downto 0) & "00";
dat_in <= master_i.dat;
end wrapper;
test/svec/VHDL/svec_pts_gtp_clkfmc/svec_afpga_gtp_clkfmc.ucf 0 → 100644
View file @ b718a368
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = P3;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[6]" LOC = R7;
NET "vme_irq_n_o[5]" LOC = AH2;
NET "vme_irq_n_o[4]" LOC = AF2;
NET "vme_irq_n_o[3]" LOC = N9;
NET "vme_irq_n_o[2]" LOC = N10;
NET "vme_irq_n_o[1]" LOC = AH4;
NET "vme_irq_n_o[0]" LOC = AG4;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = LVCMOS33;
NET "vme_rst_n_i" IOSTANDARD = LVCMOS33;
#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = LVCMOS33;
NET "vme_retry_n_o" IOSTANDARD = LVCMOS33;
NET "vme_lword_n_b" IOSTANDARD = LVCMOS33;
NET "vme_iackout_n_o" IOSTANDARD = LVCMOS33;
NET "vme_iackin_n_i" IOSTANDARD = LVCMOS33;
NET "vme_iack_n_i" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[5]" IOSTANDARD = LVCMOS33;
NET "vme_dtack_oe_o" IOSTANDARD = LVCMOS33;
NET "vme_dtack_n_o" IOSTANDARD = LVCMOS33;
NET "vme_ds_n_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_ds_n_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_data_oe_n_o" IOSTANDARD = LVCMOS33;
NET "vme_data_dir_o" IOSTANDARD = LVCMOS33;
NET "vme_berr_o" IOSTANDARD = LVCMOS33;
NET "vme_as_n_i" IOSTANDARD = LVCMOS33;
NET "vme_addr_oe_n_o" IOSTANDARD = LVCMOS33;
NET "vme_addr_dir_o" IOSTANDARD = LVCMOS33;
NET "vme_irq_n_o[6]" IOSTANDARD = LVCMOS33;
NET "vme_irq_n_o[5]" IOSTANDARD = LVCMOS33;
NET "vme_irq_n_o[4]" IOSTANDARD = LVCMOS33;
NET "vme_irq_n_o[3]" IOSTANDARD = LVCMOS33;
NET "vme_irq_n_o[2]" IOSTANDARD = LVCMOS33;
NET "vme_irq_n_o[1]" IOSTANDARD = LVCMOS33;
NET "vme_irq_n_o[0]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[31]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[30]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[29]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[28]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[27]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[26]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[25]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[24]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[23]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[22]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[21]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[20]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[19]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[18]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[17]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[16]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[15]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[14]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[13]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[12]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[11]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[10]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[9]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[8]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[7]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[6]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[5]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[4]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[3]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[2]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[1]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[0]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[5]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[4]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[3]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[2]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[31]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[30]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[29]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[28]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[27]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[26]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[25]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[24]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[23]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[22]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[21]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[20]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[19]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[18]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[17]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[16]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[15]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[14]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[13]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[12]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[11]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[10]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[9]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[8]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[7]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[6]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[5]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[4]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[3]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[2]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[1]" IOSTANDARD = LVCMOS33;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "rst_n_i" IOSTANDARD = LVCMOS33;
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33;
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2012/06/15
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50 %;
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50 %;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50 %;
#NET "clk_125m_gtp_p_i" LOC = B19;
#NET "clk_125m_gtp_n_i" LOC = A19;
#NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
#TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
#NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
#TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
#----------------------------------------
# LEDs
#----------------------------------------
NET "fp_ledn_o[0]" LOC = AD27;
NET "fp_ledn_o[1]" LOC = AD26;
NET "fp_ledn_o[2]" LOC = AC28;
NET "fp_ledn_o[3]" LOC = AC27;
NET "fp_ledn_o[4]" LOC = AE27;
NET "fp_ledn_o[5]" LOC = AE30;
NET "fp_ledn_o[6]" LOC = AF28;
NET "fp_ledn_o[7]" LOC = AE28;
NET "dbg_led_n_o[3]" LOC = U7;
NET "dbg_led_n_o[2]" LOC = AG1;
NET "dbg_led_n_o[1]" LOC = AF1;
NET "dbg_led_n_o[0]" LOC = R6;
NET "fp_ledn_o[0]" IOSTANDARD = LVCMOS33;
NET "fp_ledn_o[1]" IOSTANDARD = LVCMOS33;
NET "fp_ledn_o[2]" IOSTANDARD = LVCMOS33;
NET "fp_ledn_o[3]" IOSTANDARD = LVCMOS33;
NET "fp_ledn_o[4]" IOSTANDARD = LVCMOS33;
NET "fp_ledn_o[5]" IOSTANDARD = LVCMOS33;
NET "fp_ledn_o[6]" IOSTANDARD = LVCMOS33;
NET "fp_ledn_o[7]" IOSTANDARD = LVCMOS33;
NET "dbg_led_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "dbg_led_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "dbg_led_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "dbg_led_n_o[0]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC I2Cs
#----------------------------------------
NET "fmc0_scl_b" LOC = P28;
NET "fmc0_sda_b" LOC = P30;
NET "fmc0_scl_b" IOSTANDARD = LVCMOS33;
NET "fmc0_sda_b" IOSTANDARD = LVCMOS33;
NET "fmc1_scl_b" LOC = W29;
NET "fmc1_sda_b" LOC = V30;
NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC High Speed pins
#----------------------------------------
#NET "fmc0_dp0_rxp_i" LOC = D10;
#NET "fmc0_dp0_rxn_i" LOC = C10;
#NET "fmc0_dp0_txp_o" LOC = B9;
#NET "fmc0_dp0_txn_o" LOC = A9;
#NET "fmc1_dp0_rxp_i" LOC = AG20;
#NET "fmc0_gbtclk0_m2c_p_i" LOC = B13;
#NET "fmc0_gbtclk0_m2c_n_i" LOC = A13;
#NET "fmc1_dp0_rxp_i" LOC = AG20;
#NET "fmc1_dp0_rxn_i" LOC = AH20;
#NET "fmc1_dp0_txp_o" LOC = AJ21;
#NET "fmc1_dp0_txn_o" LOC = AK21;
#NET "fmc1_gbtclk0_m2c_p_i" LOC = AG18;
#NET "fmc1_gbtclk0_m2c_n_i" LOC = AH18;
#----------------------------------------
# SFP
#----------------------------------------
#NET "sfp_rxp_i" LOC = D22;
#NET "sfp_rxn_i" LOC = C22;
#NET "sfp_txp_o" LOC = B23;
#NET "sfp_txn_o" LOC = A23;
#----------------------------------------
# SATAs
#----------------------------------------
#NET "sata0_rxp_i" LOC = AG12;
#NET "sata0_rxn_i" LOC = AH12;
#NET "sata0_txp_o" LOC = AJ11;
#NET "sata0_txn_o" LOC = AK11;
#NET "sata1_rxp_i" LOC = AG10;
#NET "sata1_rxn_i" LOC = AH10;
#NET "sata1_txp_o" LOC = AJ9;
#NET "sata1_txn_o" LOC = AK9;
# PlanAhead Generated physical constraints
#NET "clk_gtp_carrier_y1_p_i" LOC = B19;
NET "clk_gtp_carrier_y0_p_i" LOC = B13;
NET "clk_gtp_carrier_y0_n_i" LOC = A13;
#NET "clk_gtp_carrier_y0_p_i" LOC = AJ13;
NET "clk_gtp_carrier_y1_p_i" LOC = AG18;
NET "clk_gtp_carrier_y1_n_i" LOC = AH18;
test/svec/VHDL/svec_pts_gtp_clkfmc/syn/Makefile 0 → 100644
View file @ b718a368
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := svec_afpga.xise
ISE_CRAP := *.b svec_afpga_gtp_clkfmc_top_summary.html *.tcl svec_afpga_gtp_clkfmc_top.bld svec_afpga_gtp_clkfmc_top.cmd_log *.drc svec_afpga_gtp_clkfmc_top.lso *.ncd svec_afpga_gtp_clkfmc_top.ngc svec_afpga_gtp_clkfmc_top.ngd svec_afpga_gtp_clkfmc_top.ngr svec_afpga_gtp_clkfmc_top.pad svec_afpga_gtp_clkfmc_top.par svec_afpga_gtp_clkfmc_top.pcf svec_afpga_gtp_clkfmc_top.prj svec_afpga_gtp_clkfmc_top.ptwx svec_afpga_gtp_clkfmc_top.stx svec_afpga_gtp_clkfmc_top.syr svec_afpga_gtp_clkfmc_top.twr svec_afpga_gtp_clkfmc_top.twx svec_afpga_gtp_clkfmc_top.gise svec_afpga_gtp_clkfmc_top.unroutes svec_afpga_gtp_clkfmc_top.ut svec_afpga_gtp_clkfmc_top.xpi svec_afpga_gtp_clkfmc_top.xst svec_afpga_gtp_clkfmc_top_bitgen.xwbt svec_afpga_gtp_clkfmc_top_envsettings.html svec_afpga_gtp_clkfmc_top_guide.ncd svec_afpga_gtp_clkfmc_top_map.map svec_afpga_gtp_clkfmc_top_map.mrp svec_afpga_gtp_clkfmc_top_map.ncd svec_afpga_gtp_clkfmc_top_map.ngm svec_afpga_gtp_clkfmc_top_map.xrpt svec_afpga_gtp_clkfmc_top_ngdbuild.xrpt svec_afpga_gtp_clkfmc_top_pad.csv svec_afpga_gtp_clkfmc_top_pad.txt svec_afpga_gtp_clkfmc_top_par.xrpt svec_afpga_gtp_clkfmc_top_summary.xml svec_afpga_gtp_clkfmc_top_usage.xml svec_afpga_gtp_clkfmc_top_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
test/svec/VHDL/svec_pts_gtp_clkfmc/syn/Manifest.py 0 → 100644
View file @ b718a368
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-2"
syn_package = "fgg900"
syn_top = "svec_afpga_gtp_clkfmc_top"
syn_project = "svec_afpga.xise"
files = ["../svec_afpga_gtp_clkfmc.ucf"]
fetchto = "../ip_cores"
modules = {
"local": [ "../rtl",
"../ip_cores/core_gen"],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git::no_coregen" ],
"svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
}
test/svec/VHDL/svec_pts_gtp_clkfmc/syn/svec_afpga.xise 0 → 100644
View file @ b718a368
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|svec_afpga_gtp_clkfmc_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/svec_afpga_gtp_clkfmc_top" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
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<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="svec_afpga_gtp_clkfmc_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="svec_afpga_gtp_clkfmc_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="svec_afpga_gtp_clkfmc_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="svec_afpga_gtp_clkfmc_top_synthesis.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="svec_afpga" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../svec_afpga_gtp_clkfmc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
</project>
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