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Commit b763a815 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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tdc pts tests 02, 03, 07, 08 updated not to stop upon error, but show at the end… 

tdc pts tests 02, 03, 07, 08 updated not to stop upon error, but show at the end errors from all the channels
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test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test00.py
View file @ b763a815
......@@ -22,7 +22,7 @@
## The WISHBONE master can be accessed at PCIe base address xC0000. |
## |
## |
## FW to load .bin |
## FW to load tdc_pts_presence.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -70,7 +70,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_presence.bit'#top_tdc.bit'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_presence.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
# Addressing for the retrieval of carrier csr information
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test01.py
View file @ b763a815
......@@ -29,7 +29,7 @@
## 0x0003C: bits 31..0: 125.0 MHz CLK125 counter |
## |
## |
## FW to load .bin |
## FW to load tdc_pts_clks.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -78,7 +78,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_clks.bit'#tdc_pts_presence.bit'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_clks.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
# Addressing for the retrieval of carrier csr information
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test02.py
View file @ b763a815
......@@ -38,7 +38,7 @@
## bit 5: TERM_EN_5 |
## |
## |
## FW to load .bin |
## FW to load tdc_pts_input_pulse.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -256,22 +256,28 @@ def main (default_directory='.'):
print "\n___________________________Results_______________________________\n"
# string to keep the ERROR messages from all the channels
all_msg = ""
# Read counters
for i in CHANNEL_COUNTERS:
if (carrier_csr.rd_reg(i) == 0):
msg = (("ERROR: TDC_IN_FPGA%d: No pulse arrived")%(CHANNEL_COUNTERS.index(i)+1))
os.close(spec.fd)
msg = (("ERROR: TDC_IN_FPGA%d: No pulse arrived ")%(CHANNEL_COUNTERS.index(i)+1))
print (msg)
raise PtsError (msg)
all_msg+=msg
elif (carrier_csr.rd_reg(i) > 100500) or (carrier_csr.rd_reg(i) < 95000): # 0.5% acceptance limit
msg = (("ERROR: TDC_IN_FPGA%d: Pulse width %.5f ms is outside accepted limits [1.005 ms .. 0.995 ms]")%(CHANNEL_COUNTERS.index(i)+1, carrier_csr.rd_reg(i)/1e5))
os.close(spec.fd)
msg = (("ERROR: TDC_IN_FPGA%d: Pulse width %.5f ms is outside accepted limits [1.005 ms .. 0.995 ms] ")%(CHANNEL_COUNTERS.index(i)+1, carrier_csr.rd_reg(i)/1e5))
print (msg)
raise PtsError (msg)
all_msg+=msg
else:
print("TDC_IN_FPGA%d: Pulse width %.5f ms OK")%(CHANNEL_COUNTERS.index(i)+1, carrier_csr.rd_reg(i)/1e5)
if (all_msg != ""):
os.close(spec.fd)
raise PtsError (all_msg)
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test03.py
View file @ b763a815
......@@ -37,7 +37,7 @@
## bit 5: TERM_EN_5 |
## |
## |
## FW to load .bin |
## FW to load tdc_pts_input_pulse.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -202,6 +202,7 @@ def main (default_directory='.'):
################################## Input logic Disabled ##################################
carrier_csr.wr_reg(INPUT_EN, 0x00)
#-----> Fine Delay
print "\n___________________________Fine Delay____________________________"
print "\nFine Delay initializations.."
......@@ -253,15 +254,17 @@ def main (default_directory='.'):
# Bind SPEC object to FMC TDC card
spec.bind(FMC_TDC_ADDR)
# string to keep the ERROR messages from all the channels
all_msg = ""
print "\n_____________________Input logic Disabled________________________\n"
# Read counters
for i in CHANNEL_COUNTERS:
if (carrier_csr.rd_reg(i) != 0):
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; pulse of %.5f ms arrived")%(CHANNEL_COUNTERS.index(i)+1,carrier_csr.rd_reg(i)/1e5))
os.close(spec.fd)
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; pulse of %.5f ms arrived ")%(CHANNEL_COUNTERS.index(i)+1,carrier_csr.rd_reg(i)/1e5))
print (msg)
raise PtsError (msg)
all_msg+=msg
else:
print("ENABLE_INPUTS disabled: TDC_IN_FPGA%d OK") %(CHANNEL_COUNTERS.index(i)+1)
......@@ -293,10 +296,13 @@ def main (default_directory='.'):
if (carrier_csr.rd_reg(i) != 0):
print("ENABLE_INPUTS enabled: TDC_IN_FPGA%d OK")%(CHANNEL_COUNTERS.index(i)+1)
else:
msg = (("ERROR: ENABLE_INPUTS enabled: TDC_IN_FPGA%d: No pulse arrived")%(CHANNEL_COUNTERS.index(i)+1))
os.close(spec.fd)
msg = (("ERROR: ENABLE_INPUTS enabled: TDC_IN_FPGA%d: No pulse arrived ")%(CHANNEL_COUNTERS.index(i)+1))
print (msg)
raise PtsError (msg)
all_msg+=msg
if (all_msg != ""):
os.close(spec.fd)
raise PtsError (all_msg)
os.close(spec.fd)
print "\n\n-----------------------------------------------------------------"
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test04.py
View file @ b763a815
......@@ -24,7 +24,7 @@
## The test reads the unique ID and the temperature and checks if the received |
## values are within reasonable limits. |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -72,7 +72,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_counters.bit'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
FAMILY_CODE = 0x28
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test05.py
View file @ b763a815
......@@ -23,7 +23,7 @@
## |
## The test attempts several writings and readbacks on different EEPROM locations. |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -71,7 +71,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_counters.bit'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
EEPROM_ADDR = 0x50
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test06.py
View file @ b763a815
......@@ -19,7 +19,7 @@
## TDC_RDN, TDC_CSN, TDC_OEN |
## |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test07.py
View file @ b763a815
......@@ -19,7 +19,7 @@
## The test is retrieving the pulses and is checking their accuracy. |
## |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -76,7 +76,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_pllstatus.bit
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......@@ -163,7 +163,7 @@ def main (default_directory='.'):
tdc.channel_term(1, 1)
tdc.channel_term(2, 1)
tdc.channel_term(3, 1)
tdc.channel_term(5, 1)
tdc.channel_term(4, 1)
# Enable timestamps aquisition (TDC_START_FPGA pulse sent at this step)
......@@ -210,6 +210,10 @@ def main (default_directory='.'):
delta = 200000 # rising edges every 200 ns
count = 6
# string to keep the ERROR messages from all the channels
all_msg = ""
for i in range(4): # one iteration per channel;
# channels 4 and 5 receive pulses at the same time
......@@ -233,7 +237,7 @@ def main (default_directory='.'):
spec.bind(FMC_TDC_ADDR)
# Check if timestamps arrived
print "\n________________________TDC_IN_FPGA%d test__________________________\n" %(i+1)
print "\n_________________________TDC_STOP%d test____________________________\n" %(i+1)
time.sleep(1.5)
print "The time now is : %s" %datetime.now()
print "The temperature now is : %3.3f°C" %tdc.mezz_get_temp()
......@@ -242,83 +246,87 @@ def main (default_directory='.'):
if (tdc.get_pointer()) != 0:
timestamps, data = tdc.get_timestamps(0)
# keep only rising edge timestamps belonging to channel under test
for m in range(len(timestamps)):
if ((timestamps[m][2] == 1) and (timestamps[m][1] == channel-1)):
r_edge_timestamps.append(timestamps[m][0])
# keep only rising edge timestamps belonging to channel under test
for m in range(len(timestamps)):
if ((timestamps[m][2] == 1) and (timestamps[m][1] == channel-1)):
r_edge_timestamps.append(timestamps[m][0])
if ((timestamps[m][2] == 1) and (timestamps[m][1] == 4)):
r_edge_timestamps_ch5.append(timestamps[m][0])
# check number of pulses arrived
if (len(r_edge_timestamps)) == 0:
msg = (("ERROR: TDC_IN_FPGA%d: No pulse arrived") %channel)
os.close(spec.fd)
if ((len(r_edge_timestamps)) == 0):
msg = (("ERROR: TDC_STOP%d: No pulse arrived ") %channel)
print (msg)
raise PtsError (msg)
all_msg+=msg
if ((len(r_edge_timestamps_ch5) == 0) and i == 3):
msg = ("ERROR: TDC_STOP5: No pulse arrived ")
print (msg)
all_msg+=msg
elif (len(r_edge_timestamps)) == 6:
print "Number of rising edge timestamps : %d"%(len(r_edge_timestamps))
else:
msg = (("ERROR: TDC_IN_FPGA%d: Unexpected number of pulses arrived; expected 6, arrived %d")%(channel, (len(r_edge_timestamps))))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# evaluate timestamps: for each pulse, calculate the delta; should be 200 ns
for k in range(0,len(r_edge_timestamps),2):
measur = r_edge_timestamps[k+1] - r_edge_timestamps[k]
all_measurs.append(measur)
# average the delta from the 6 pulses
avg = (sum(all_measurs, 0.0) / len(all_measurs))
if (avg > 198800) and (avg < 201200): # +/-1200 ps acceptance limits (+/-500 ps from FD plus +/-700ps from TDC)
print "Pulse delta measurement : %.2f ps"%(avg)
else:
msg = (("ERROR: ACAM IC8: Wrong timestamps; pulse delta %.2f ps is outside accepted limits [198800 ps..201200 ps]") %avg[i])
os.close(spec.fd)
msg = (("ERROR: TDC_STOP%d: Unexpected number of pulses arrived; expected 6, arrived %d ")%(channel, (len(r_edge_timestamps))))
print (msg)
raise PtsError (msg)
all_msg+=msg
if i == 3: # for channel 5 that receives pulses along with channel 4
# if corrent number of timestamps has arrived, continue with the math
if (len(r_edge_timestamps)) == 6:
print "\n________________________TDC_IN_FPGA5 test__________________________\n"
# evaluate timestamps: for each pulse, calculate the delta; should be 200 ns
for k in range(0,len(r_edge_timestamps),2):
measur = r_edge_timestamps[k+1] - r_edge_timestamps[k]
all_measurs.append(measur)
# keep only rising edge timestamps belonging to channel 5
for m in range(len(timestamps)):
if ((timestamps[m][2] == 1) and (timestamps[m][1] == 4)):
r_edge_timestamps_ch5.append(timestamps[m][0])
# check number of pulses arrived
if (len(r_edge_timestamps_ch5)) == 0:
msg = ("ERROR: TDC_IN_FPGA5: No pulse arrived")
os.close(spec.fd)
print (msg)
raise PtsError (msg)
elif (len(r_edge_timestamps_ch5)) == 6:
print "Number of rising edge timestamps : %d"%(len(r_edge_timestamps_ch5))
else:
msg = (("ERROR: TDC_IN_FPGA5: Unexpected number of pulses arrived; expected 6, arrived %d")%((len(r_edge_timestamps_ch5))))
os.close(spec.fd)
print (msg)
raise PtsError (msg)
# channel 5: for each pulse, calculate the delta; should be 200 ns
for k in range(0,len(r_edge_timestamps_ch5),2):
measur = r_edge_timestamps_ch5[k+1] - r_edge_timestamps_ch5[k]
all_measurs_ch5.append(measur)
# channel 5: average the delta from the 6 pulses
avg = ((sum(all_measurs_ch5, 0.0) / len(all_measurs_ch5)))
if (avg > 198800) and (avg < 201200):
# average the delta from the 6 pulses
avg = (sum(all_measurs, 0.0) / len(all_measurs))
if (avg > 198800) and (avg < 201200): # +/-1200 ps acceptance limits (+/-500 ps from FD plus +/-700ps from TDC)
print "Pulse delta measurement : %.2f ps"%(avg)
else:
msg = (("ERROR: ACAM IC8: Wrong timestamps; pulse delta %.2f ps is outside accepted limits [198800 ps..201200 ps]") %avg)
os.close(spec.fd)
print (msg)
raise PtsError (msg)
else:
msg = (("ERROR: ACAM IC8: Wrong timestamps; pulse delta %.2f ps is outside accepted limits [198800 ps..201200 ps] ") %avg[i])
print (msg)
all_msg+=msg
if i == 3: # for channel 5 that receives pulses along with channel 4
print "\n________________________TDC_STOP5 test__________________________\n"
# check number of pulses arrived
if (len(r_edge_timestamps_ch5)) == 0:
msg = ("ERROR: TDC_STOP5: No pulse arrived ")
print (msg)
all_msg+=msg
elif (len(r_edge_timestamps_ch5)) == 6:
print "Number of rising edge timestamps : %d"%(len(r_edge_timestamps_ch5))
else:
msg = (("ERROR: TDC_STOP5: Unexpected number of pulses arrived; expected 6, arrived %d ")%((len(r_edge_timestamps_ch5))))
print (msg)
all_msg+=msg
if ((len(r_edge_timestamps_ch5)) == 6):
# channel 5: for each pulse, calculate the delta; should be 200 ns
for k in range(0,len(r_edge_timestamps_ch5),2):
measur = r_edge_timestamps_ch5[k+1] - r_edge_timestamps_ch5[k]
all_measurs_ch5.append(measur)
# channel 5: average the delta from the 6 pulses
avg = ((sum(all_measurs_ch5, 0.0) / len(all_measurs_ch5)))
if (avg > 198800) and (avg < 201200):
print "Pulse delta measurement : %.2f ps"%(avg)
else:
msg = (("ERROR: ACAM IC8: Wrong timestamps; pulse delta %.2f ps is outside accepted limits [198800 ps..201200 ps] ") %avg)
print (msg)
all_msg+=msg
del r_edge_timestamps
del all_measurs
if (all_msg != ""):
os.close(spec.fd)
print (all_msg)
raise PtsError (all_msg)
os.close(spec.fd)
print "\n-----------------------------------------------------------------\n\n\n"
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test08.py
View file @ b763a815
......@@ -25,7 +25,7 @@
## disabling the ENABLE_INPUTS signal and testing for pulses on the TDC_IN_FPGA |
## lines, rather than the TDC_STOP lines that are tested in this test. |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -82,7 +82,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_pllstatus.bit
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......@@ -211,6 +211,9 @@ def main (default_directory='.'):
delta = 200000 # rising edges every 200 ns
# string to keep the ERROR messages from all the channels
all_msg = ""
for i in range(4): # one iteration per channel;
# channels 4 and 5 receive pulses at the same time
......@@ -229,7 +232,7 @@ def main (default_directory='.'):
spec.bind(FMC_TDC_ADDR)
# Check if timestamps arrived
print "\n___________________TDC_IN_FPGA%d disable test___________________\n" %channel
print "\n____________________TDC_STOP%d disable test_____________________\n" %channel
time.sleep(1.5)
print "The time now is : %s" %datetime.now()
print "The temperature now is : %3.3f°C" %tdc.mezz_get_temp()
......@@ -244,10 +247,9 @@ def main (default_directory='.'):
if ((timestamps[m][2] == 1) and (timestamps[m][1] == i)):
timestamp_arrived = timestamp_arrived+1
if (timestamp_arrived != 0):
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; %d pulses sent, %d pulses received") %(channel, count, timestamp_arrived))
os.close(spec.fd)
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_STOP%d failure; %d pulses sent, %d pulses received") %(channel, count, timestamp_arrived))
print (msg)
raise PtsError (msg)
all_msg+=msg
else:
print("Channel disabling : OK! no pulses arrived")
......@@ -261,23 +263,25 @@ def main (default_directory='.'):
elif ((timestamps[m][2] == 1) and (timestamps[m][1] == 4)):
timestamp_arrived_ch5 = timestamp_arrived_ch5+1
if (timestamp_arrived_ch4 != 0):
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; %d pulses sent, %d pulses received") %(channel, count, timestamp_arrived_ch4))
os.close(spec.fd)
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_STOP%d failure; %d pulses sent, %d pulses received") %(channel, count, timestamp_arrived_ch4))
print (msg)
raise PtsError (msg)
all_msg+=msg
else:
print("Channel disabling : OK! no pulses arrived")
if (timestamp_arrived_ch5 != 0):
print "\n___________________TDC_IN_FPGA5 disable test____________________\n"
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_IN_FPGA%d failure; %d pulses sent, %d pulses received") %(count, timestamp_arrived_ch5))
os.close(spec.fd)
print "\n___________________TDC_STOP5 disable test____________________\n"
msg = (("ERROR: ENABLE_INPUTS disabled: TDC_STOP5 failure; %d pulses sent, %d pulses received") %(count, timestamp_arrived_ch5))
print (msg)
raise PtsError (msg)
all_msg+=msg
else:
print "\n___________________TDC_IN_FPGA5 disable test____________________\n"
print "\n___________________TDC_STOP5 disable test____________________\n"
print("Channel disabling : OK! no pulses arrived")
if (all_msg != ""):
os.close(spec.fd)
raise PtsError (all_msg)
os.close(spec.fd)
print "\n-----------------------------------------------------------------\n\n\n"
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test09.py
View file @ b763a815
......@@ -19,7 +19,7 @@
## channels; if there are registered pulses one or both signals are faulty. |
## |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -76,7 +76,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_pllstatus.bit
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test10.py
View file @ b763a815
......@@ -24,7 +24,7 @@
## The TDC_ERR register can be reset by writing '1' at PCIe address: 0xC004C |
## |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -83,7 +83,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_fpga_in.bit'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test11.py
View file @ b763a815
......@@ -20,7 +20,7 @@
## The ACAM timestamps are retrieved and evaluated: the pulse duration is expected |
## to be higher when the DAC value is high and lower when the DAC value is low. |
## |
## FW to load .bin |
## FW to load tdc_allothertests.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -78,7 +78,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'#tdc_pllstatus.bit'#eva_tdc_for_v2.bit' #evas_tdc_irq8.bit'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_allothertests.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM_PATH = '../firmwares/fmc_delay_spec.bin'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
......
test/fmctdc1ns5cha/software/fmctdc1ns5cha/python/test12.py
View file @ b763a815
......@@ -21,7 +21,7 @@
## if all the LEDs are blinking as expected. |
## |
## |
## FW to load .bin |
## FW to load tdc_pts_leds.bit |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
......@@ -66,7 +66,7 @@ def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_leds.bit'#tdc_carrier_info2.bit'#eva_tdc_for_v2.bit'#evas_tdc_leds.bit'#evas_tdc_ctrl_dac.bit'
FMC_TDC_BITSTREAM_PATH = '../firmwares/tdc_pts_leds.bit'
FPGA_LOADER_PATH = '../../../gnurabbit/user/fpga_loader'
print "\n-------------------------------------------------------------------"
......
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