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ba20a0fe
Commit
ba20a0fe
authored
Dec 21, 2012
by
Richard R. Carrillo
Committed by
Benoit Rat
May 08, 2013
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SPEC test07 modified to test all DDR memory address lines
parent
6d7014ac
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3 changed files
with
132 additions
and
168 deletions
+132
-168
test07.bin
test/spec/firmwares/test07.bin
+0
-0
gn4124.py
test/spec/python/gn4124.py
+1
-0
test07.py
test/spec/python/test07.py
+131
-168
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test/spec/firmwares/test07.bin
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ba20a0fe
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test/spec/python/gn4124.py
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ba20a0fe
...
...
@@ -166,6 +166,7 @@ class CGN4124:
# Start DMA transfer
def
start_dma
(
self
):
self
.
wr_reg
(
0
,
0x50000
+
2
*
4
,
1
)
# Enable interrupt
self
.
dma_item_cnt
=
0
self
.
dma_csr
.
wr_bit
(
self
.
R_DMA_CTL
,
self
.
DMA_CTL_START
,
1
)
# The following two lines should be removed
...
...
test/spec/python/test07.py
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ba20a0fe
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