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Commit c4a2585a authored by Benoit Rat's avatar Benoit Rat
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spec: upload the vhdl files to generate the new ddr test 07

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test/spec/vhdl/readme.txt
View file @ c4a2585a
......@@ -12,3 +12,8 @@ test_temp_sensor -> test09
test_si570 -> test06
test_sata_dp0 -> test05
test_usb_uart -> test10
===============================================
the test_ddr from vhdl_bkp_from_samuel is now replaced by the new
one generated from spec _pts_new_ddr
test/spec/vhdl/spec_pts_new_ddr/LICENSE.txt 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/adc/rtl/Manifest.py 0 → 100644
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files = ["fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_csr.vhd",
"offset_gain_s.vhd"]
test/spec/vhdl/spec_pts_new_ddr/adc/rtl/fmc_adc_100Ms_core.vhd 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/adc/rtl/fmc_adc_100Ms_csr.vhd 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/adc/rtl/offset_gain.vhd 0 → 100644
View file @ c4a2585a
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Offset and gain correction
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: offset_gain_corr (offset_gain_corr.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 24-11-2011
--
-- version: 1.0
--
-- description: Offset and gain correction with saturation.
-- Latency = 2
--
-- ___ ___ ________
-- | | offset_data | | product | |
-- data_i ---->| + |------------>| X |-------->|saturate|--> data_o
-- |___| |___| |________|
-- ^ ^
-- | |
-- offset_i gain_i
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
------------------------------------------------------------------------------
-- Entity declaration
------------------------------------------------------------------------------
entity offset_gain is
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(16 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Unsigned data input
data_o : out std_logic_vector(15 downto 0) --! Unsigned data output
);
end entity offset_gain;
------------------------------------------------------------------------------
-- Architecture declaration
------------------------------------------------------------------------------
architecture rtl of offset_gain is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal rst : std_logic := '0';
signal data_offset : std_logic_vector(17 downto 0) := (others => '0');
signal gain : std_logic_vector(17 downto 0) := (others => '0');
signal product : std_logic_vector(35 downto 0) := (others => '0');
begin
------------------------------------------------------------------------------
-- Active high reset for MULT_MACRO
------------------------------------------------------------------------------
rst <= not(rst_n_i);
------------------------------------------------------------------------------
-- Add offset to input data
------------------------------------------------------------------------------
p_offset : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
data_offset <= (others => '0');
gain <= (others => '0');
else
-- propagate sign for signed offset_i
data_offset <= std_logic_vector(unsigned(("00" & data_i)) +
unsigned((offset_i(16) & offset_i)));
gain <= "00" & gain_i;
end if;
end if;
end process p_offset;
------------------------------------------------------------------------------
-- Multiple input data + offset by gain
------------------------------------------------------------------------------
-- MULT_MACRO: Multiply Function implemented in a DSP48E
-- Xilinx HDL Libraries Guide, version 12.4
------------------------------------------------------------------------------
cmp_multiplier : MULT_MACRO
generic map (
DEVICE => "SPARTAN6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
LATENCY => 0, -- Desired clock cycle latency, 0-4
WIDTH_A => 18, -- Multiplier A-input bus width, 1-25
WIDTH_B => 18) -- Multiplier B-input bus width, 1-18
port map (
P => product, -- Multiplier ouput, WIDTH_A+WIDTH_B
A => gain, -- Multiplier input A, WIDTH_A
B => data_offset, -- Multiplier input B, WIDTH_B
CE => '1', -- 1-bit active high input clock enable
CLK => clk_i, -- 1-bit positive edge clock input
RST => rst -- 1-bit input active high reset
);
------------------------------------------------------------------------------
-- Saturate addition and multiplication result
------------------------------------------------------------------------------
p_saturate : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
data_o <= (others => '0');
else
if product(34) = '1' then
data_o <= (others => '0'); -- saturate negative
elsif (product(34) = '0' and product(31) = '1') then
data_o <= (others => '1'); -- saturate positive
else
data_o <= product(30 downto 15);
end if;
end if;
end if;
end process p_saturate;
end architecture rtl;
test/spec/vhdl/spec_pts_new_ddr/adc/rtl/offset_gain_s.vhd 0 → 100644
View file @ c4a2585a
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Offset and gain correction, signed data input and output (two's complement)
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: offset_gain_corr_s (offset_gain_corr_s.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 24-11-2011
--
-- version: 1.0
--
-- description: Offset and gain correction with saturation.
-- Latency = 2
--
-- ___ ___ ________
-- | | offset_data | | product | |
-- data_i ---->| + |------------>| X |-------->|saturate|--> data_o
-- |___| |___| |________|
-- ^ ^
-- | |
-- offset_i gain_i
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
------------------------------------------------------------------------------
-- Entity declaration
------------------------------------------------------------------------------
entity offset_gain_s is
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(15 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Signed data input (two's complement)
data_o : out std_logic_vector(15 downto 0) --! Signed data output (two's complement)
);
end entity offset_gain_s;
------------------------------------------------------------------------------
-- Architecture declaration
------------------------------------------------------------------------------
architecture rtl of offset_gain_s is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal rst : std_logic := '0';
signal data_in_d : std_logic_vector(15 downto 0) := (others => '0');
signal data_offset : std_logic_vector(17 downto 0) := (others => '0');
signal gain : std_logic_vector(17 downto 0) := (others => '0');
signal product : std_logic_vector(35 downto 0) := (others => '0');
begin
------------------------------------------------------------------------------
-- Active high reset for MULT_MACRO
------------------------------------------------------------------------------
rst <= not(rst_n_i);
------------------------------------------------------------------------------
-- Add offset to input data
------------------------------------------------------------------------------
p_offset : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
data_offset <= (others => '0');
gain <= (others => '0');
data_in_d <= (others => '0');
else
data_in_d <= data_i;
-- propagate sign for signed offset_i
data_offset <= std_logic_vector(signed(data_i(15) & data_i(15) & data_i) +
signed(offset_i(15) & offset_i(15) & offset_i));
gain <= "00" & gain_i;
end if;
end if;
end process p_offset;
------------------------------------------------------------------------------
-- Multiple input data + offset by gain
------------------------------------------------------------------------------
-- MULT_MACRO: Multiply Function implemented in a DSP48E
-- Xilinx HDL Libraries Guide, version 12.4
------------------------------------------------------------------------------
cmp_multiplier : MULT_MACRO
generic map (
DEVICE => "SPARTAN6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
LATENCY => 0, -- Desired clock cycle latency, 0-4
WIDTH_A => 18, -- Multiplier A-input bus width, 1-25
WIDTH_B => 18) -- Multiplier B-input bus width, 1-18
port map (
P => product, -- Multiplier ouput, WIDTH_A+WIDTH_B
A => gain, -- Multiplier input A, WIDTH_A
B => data_offset, -- Multiplier input B, WIDTH_B
CE => '1', -- 1-bit active high input clock enable
CLK => clk_i, -- 1-bit positive edge clock input
RST => rst -- 1-bit input active high reset
);
------------------------------------------------------------------------------
-- Saturate addition and multiplication result
------------------------------------------------------------------------------
p_saturate : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
data_o <= (others => '0');
else
if (data_offset(15) = '1' and data_offset(16) = '0') then
data_o <= X"7FFF"; -- saturate positive
elsif (data_offset(15) = '0' and data_offset(16) = '1') then
data_o <= X"8000"; -- saturate negative
else
data_o <= product(30 downto 15);
end if;
end if;
end if;
end process p_saturate;
end architecture rtl;
test/spec/vhdl/spec_pts_new_ddr/adc/rtl/offset_gain_s_tb.vhd 0 → 100644
View file @ c4a2585a
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:48:27 02/05/2010
-- Design Name:
-- Module Name: offset_gain_s_tb.vhd
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: offsetgain
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity offset_gain_s_tb is
end offset_gain_s_tb;
architecture behavior of offset_gain_s_tb is
-- Component Declaration for the Unit Under Test (UUT)
component offset_gain_s
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(15 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Unsigned data input
data_o : out std_logic_vector(15 downto 0) --! Unsigned data output
);
end component offset_gain_s;
--Inputs
signal rst_n_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal offset_i : std_logic_vector(15 downto 0) := (others => '0');
signal gain_i : std_logic_vector(15 downto 0) := (others => '0');
signal data_i : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal data_o : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_i_period : time := 8 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : offset_gain_s port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
offset_i => offset_i,
gain_i => gain_i,
data_i => data_i,
data_o => data_o
);
-- Clock process definitions
clk_i_process : process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state
rst_n_i <= '0';
wait for 10 us;
rst_n_i <= '1';
wait for clk_i_period*10;
-- insert stimulus here
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(1000, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(32700, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-1000, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(-32700, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10000, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(32700, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10000, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(-32700, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(0, 16));
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait;
end process;
end;
test/spec/vhdl/spec_pts_new_ddr/adc/rtl/offset_gain_tb.vhd 0 → 100644
View file @ c4a2585a
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:48:27 02/05/2010
-- Design Name:
-- Module Name: C:/mcattin/fpga_design/cvorb_cvorg/sources/offsetgain_tb.vhd
-- Project Name: cvorg_v3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: offsetgain
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity offsetgain_tb is
end offsetgain_tb;
architecture behavior of offsetgain_tb is
-- Component Declaration for the Unit Under Test (UUT)
component offset_gain
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(16 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Unsigned data input
data_o : out std_logic_vector(15 downto 0) --! Unsigned data output
);
end component offset_gain;
--Inputs
signal rst_n_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal offset_i : std_logic_vector(16 downto 0) := (others => '0');
signal gain_i : std_logic_vector(15 downto 0) := (others => '0');
signal data_i : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal data_o : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_i_period : time := 8 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : offset_gain port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
offset_i => offset_i,
gain_i => gain_i,
data_i => data_i,
data_o => data_o
);
-- Clock process definitions
clk_i_process : process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state
rst_n_i <= '0';
wait for 10 us;
rst_n_i <= '1';
wait for clk_i_period*10;
-- insert stimulus here
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
data_i <= std_logic_vector(to_unsigned(1, 16));
wait for 1 us;
wait until rising_edge(clk_i);
data_i <= std_logic_vector(to_unsigned(3, 16));
wait for 1 us;
wait until rising_edge(clk_i);
data_i <= std_logic_vector(to_unsigned(32768, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(65535, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(32000, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(34000, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(32768, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(32768, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-32768, 17));
gain_i <= std_logic_vector(to_unsigned(33768, 16));
data_i <= std_logic_vector(to_unsigned(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-298, 17));
gain_i <= std_logic_vector(to_unsigned(32090, 16));
data_i <= std_logic_vector(to_unsigned(60857, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(16384, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
-- offset_i <= "010000000000000";
offset_i <= "01111111111111111";
gain_i <= X"8000";
data_i <= (others => '1');
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= "10000000000000000";
-- offset_i <= "011111111111111";
gain_i <= X"8000";
data_i <= (others => '0');
wait;
end process;
end;
test/spec/vhdl/spec_pts_new_ddr/adc/wb_gen/Makefile 0 → 100644
View file @ c4a2585a
WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
\ No newline at end of file
test/spec/vhdl/spec_pts_new_ddr/adc/wb_gen/fmc_adc_100Ms_csr.h 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/chipscope/acq_to_ddr.cdc 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/chipscope/acq_to_ddr.cpj 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/chipscope/datapath.cdc 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/_xmsgs/ngcbuild.xmsgs 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/_xmsgs/pn_parser.xmsgs 0 → 100644
View file @ c4a2585a
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/tmp/_cg/wb_ddr_fifo.vhd&quot; into library work</arg>
</msg>
</messages>
test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/_xmsgs/xst.xmsgs 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes.asy 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes.ejp 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes.gise 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes.ucf 0 → 100755
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes.vhd 0 → 100755
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes.vho 0 → 100755
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes.xco 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes.xise 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes/implement/xst.prj 0 → 100755
View file @ c4a2585a
vhdl work ../../adc_serdes.vhd
vhdl work ../example_design/adc_serdes_exdes.vhd
test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes/implement/xst.scr 0 → 100755
View file @ c4a2585a
run
-ifmt MIXED
-top adc_serdes_exdes
-p xc6slx45t-fgg484-3
-ifn xst.prj
-ofn adc_serdes_exdes
-keep_hierarchy soft
-equivalent_register_removal no
-max_fanout 65535
test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/adc_serdes/simulation/functional/simcmds.tcl 0 → 100755
View file @ c4a2585a
# file: simcmds.tcl
# create the simulation script
vcd dumpfile isim.vcd
vcd dumpvars -m /adc_serdes_tb -l 0
run 50000ns
quit
test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/coregen.cgc 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/coregen.cgp 0 → 100644
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test/spec/vhdl/spec_pts_new_ddr/spec/ip_cores/coregen.log 0 → 100644
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