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Commit c8967109 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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TDC PTS files added

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test/fmctdc1ns5cha/python/tdc_pts_acam.py 0 → 100644
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#! /usr/bin/env python
# coding: utf8
##_________________________________________________________________________________________________
## |
## |TDC PTS| |
## |
## CERN,BE/CO-HT |
##________________________________________________________________________________________________|
##-------------------------------------------------------------------------------------------------
## |
## TDC ACAM test |
## |
##-------------------------------------------------------------------------------------------------
## |
## Description Testing of the communication with the ACAM chip IC8 of the TDC board. |
## The test is checking if the status of all the ACAM registers is as expected. |
## In detal these lines are tested: TDC_D[27..0], TDC_ADR[3..0], RESET_N, TDC_WRN, |
## TDC_RDN, TDC_CSN, TDC_OEN |
## |
## |
## FW to load .bin |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE |
## ------------------------------------ |
## This source file is free software; you can redistribute it and/or modify it under the terms of |
## the GNU Lesser General Public License as published by the Free Software Foundation; either |
## version 2.1 of the License, or (at your option) any later version. |
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
## See the GNU Lesser General Public License for more details. |
## You should have received a copy of the GNU Lesser General Public License along with this |
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import --
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
import csr
# Import specific modules
import fmc_tdc
sys.path.append('../../../../fmc_delay/software/python/')
##-------------------------------------------------------------------------------------------------
## Main --
##-------------------------------------------------------------------------------------------------
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/tdc_pllstatus.bit'#eva_tdc_for_v2.bit' #evas_tdc_irq8.bit'
# SPEC object declaration
spec = rr.Gennum()
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "---------------------- ACAM communication test --------------------"
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
spec.bind(FMC_TDC_ADDR)
# Load FMC TDC firmware
print "\n_________________________Initialisations_________________________\n"
print "Loading FMC TDC firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# TDC configuration
print "\n__________________________Configuration__________________________\n"
tdc.config_acam()
time.sleep(1)
tdc.reset_acam()
# Check ACAM status
print "\n______________________ACAM status register_______________________\n"
acam_status_test = tdc.read_acam_status()-0xC4000800
if acam_status_test == 0:
print "ACAM IC8: Status register OK"
else:
raise PtsError ("ERROR: ACAM IC8: No communication")
# Check other ACAM configuration regs
print "\n______________________ACAM other registers________________________\n"
acam_readback_regs = []
acam_readback_regs = tdc.readback_acam_config()
for i in range(len(tdc.ACAM_READBACK_REGS)):
if (acam_readback_regs[i] == tdc.ACAM_READBACK_REGS[i]):
print "ACAM IC8: reg 0x%02X: 0x%08X OK"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i])
else:
print "ERROR! ACAM IC8: Configuration registers failure; reg 0x%02X: received 0x%08X, expected 0x%08X"%(tdc.ACAM_READBACK_ADDR[i], acam_readback_regs[i], tdc.ACAM_READBACK_REGS[i])
print "\n-----------------------------------------------------------------\n\n\n"
if __name__ == '__main__' :
main()
test/fmctdc1ns5cha/python/tdc_pts_acam_errflag.py 0 → 100644
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test/fmctdc1ns5cha/python/tdc_pts_acam_inputs_enable.py 0 → 100644
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test/fmctdc1ns5cha/python/tdc_pts_acam_tstamps.py 0 → 100644
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test/fmctdc1ns5cha/python/tdc_pts_acam_tstamps_dis.py 0 → 100644
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#! /usr/bin/env python
# coding: utf8
##_________________________________________________________________________________________________
## |
## |TDC PTS| |
## |
## CERN,BE/CO-HT |
##________________________________________________________________________________________________|
##-------------------------------------------------------------------------------------------------
## |
## TDC Channels test |
## |
##-------------------------------------------------------------------------------------------------
## |
## Description Testing of the TDC_START_DIS and TDC_STOP_DIS signals; when activated no |
## timestamps should be registered by the ACAM. |
## The test is using thr Fine Delay as pulse generator sending pulses to all the TDC |
## channels; if there are registered pulses one or both signals are faulty. |
## |
## |
## FW to load .bin |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE |
## ------------------------------------ |
## This source file is free software; you can redistribute it and/or modify it under the terms of |
## the GNU Lesser General Public License as published by the Free Software Foundation; either |
## version 2.1 of the License, or (at your option) any later version. |
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
## See the GNU Lesser General Public License for more details. |
## You should have received a copy of the GNU Lesser General Public License along with this |
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import --
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os
import math
import pylab
from pylab import *
from datetime import datetime
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
import csr
# Import specific modules
import fmc_tdc
sys.path.append('../../../../fmc_delay/software/python/')
import fdelay_lib
##-------------------------------------------------------------------------------------------------
## Main --
##-------------------------------------------------------------------------------------------------
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/tdc_acam_misc.bit'#tdc_pllstatus.bit'#eva_tdc_for_v2.bit' #evas_tdc_irq8.bit'
FMC_DELAY_ADDR = '1a39:0004/1a39:0004@0005:0000'
FMC_DELAY_BITSTREAM = '../firmwares/fmc_delay_spec.bin'
FMC_TDC_CHANNEL_NB = 5
CARRIER_CSR = 0xC0000
ACAM_STARTDIS = 0x40
ACAM_STOPDIS = 0x44
# SPEC object declaration
spec = rr.Gennum()
#-----> TDC
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- FMC TDC -----------------------------"
print "-------------------------- Channels test --------------------------"
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
spec.bind(FMC_TDC_ADDR)
carrier_csr = csr.CCSR(spec, CARRIER_CSR)
# Load FMC TDC firmware
print "\n_________________________Initialisations_________________________\n"
print "Loading FMC TDC firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# TDC configuration
print "\n__________________________Configuration__________________________\n"
tdc.config_acam()
time.sleep(1)
# Check ACAM status
print "\n______________________________ACAM________________________________\n"
tdc.reset_acam()
acam_status_test = tdc.read_acam_status()-0xC4000800
if acam_status_test == 0:
print "ACAM status register OK!"
else:
raise PtsError ("ERROR: ACAM IC8: No communication")
acam_regs = []
acam_regs=tdc.readback_acam_config()
if (acam_regs == [0xC1F0FC81, 0xC0000000, 0xC0000E02, 0xC0000000, 0xC200000F, 0xC00007D0, 0xC00000FC, 0xC0001FEA, 0x00000000, 0x00000000, 0x00000000, 0xC3000000, 0xC4000800, 0xC0000000]):
print("\nCommunication with ACAM and ACAM registers OK!")
else:
raise PtsError("\nERROR: ACAM IC8: Configuration registers failure")
# Enable the 5 TDC channels
tdc.enable_channels()
for ch in range(1,FMC_TDC_CHANNEL_NB+1):
tdc.channel_term(ch, 1)
# Enable timestamps aquisition
tdc.start_acq()
# StartDis, StopDis
carrier_csr.wr_reg(ACAM_STARTDIS,0x1)
carrier_csr.wr_reg(ACAM_STOPDIS,0x1)
#-----> Fine Delay
print "\n___________________________Fine Delay____________________________"
print "\nFine Delay initializations.."
# Bind SPEC object to FMC Fine Delay card
print "Fine Delay address to parse %s"%(FMC_DELAY_ADDR)
for name, value in spec.parse_addr(FMC_DELAY_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
spec.bind(FMC_DELAY_ADDR)
# Load FMC Fine Delay firmware
print "\nLoading FMC Fine Delay firmware...",
sys.stdout.flush()
spec.load_firmware(FMC_DELAY_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
# Fine Delay object declaration
fdelay = fdelay_lib.FineDelay(spec.get_fd())
# Set UTC and Coarse time in the Fine Delay
fdelay.set_time(0, 0)
fd_time = fdelay_lib.fd_timestamp()
fd_time = fdelay.get_time()
# Configure the Fine Delay as a pulse generator
enable = 1
t_start_coarse = 0
width = 100000 # pulse width 100 ns
delta = 200000 # rising edges every 200 ns
count = 6
all_measurs = []
avg = []
print "\n____________________Fine Delay sending pulses____________________\n"
for i in range(4): # one iteration per channel;
# channels 4 and 5 receive pulses at the same time
#-----> Fine Delay
time.sleep(0.5) # somehow needed
channel = i+1
t_start_utc = fdelay.get_time().utc+1 # starting in 1 sec
fdelay.conf_pulsegen(channel, enable, t_start_utc, t_start_coarse, width, delta, count)
if (i < 3):
print "%d pulses sent to Channel %d" %(count,channel)
else:
print "%d pulses sent to Channel %d" %(count,channel)
print "%d pulses sent to Channel 5" %(count)
#-----> TDC
# Bind SPEC object to FMC TDC card
spec.bind(FMC_TDC_ADDR)
# Check if any timestamp arrived
time.sleep(1)
print "\n___________________ACAM StartDis, StopDis test___________________\n"
print "The time now is : %s" %datetime.now()
print "The temperature now is : %3.3f°C" %tdc.mezz_get_temp()
print "TDC Write pointer : %d"%(tdc.get_pointer())
if (tdc.get_pointer() == 0):
print ("ACAM StartDis and StopDis signals : OK!")
else:
print ("ERROR: ACAM IC8: StartDis and/or StopDis: pulses registered, despite disabling;")
print (" %d pulses sent, %d timestamps registered") %(count*FMC_TDC_CHANNEL_NB,(tdc.get_pointer()/32))
print "\n-----------------------------------------------------------------\n\n\n"
if __name__ == '__main__' :
main()
test/fmctdc1ns5cha/python/tdc_pts_clks.py 0 → 100644
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test/fmctdc1ns5cha/python/tdc_pts_dac.py 0 → 100644
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test/fmctdc1ns5cha/python/tdc_pts_eeprom.py 0 → 100644
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#! /usr/bin/env python
# coding: utf8
##_________________________________________________________________________________________________
## |
## |TDC PTS| |
## |
## CERN,BE/CO-HT |
##________________________________________________________________________________________________|
##-------------------------------------------------------------------------------------------------
## |
## TDC EEPROM test |
## |
##-------------------------------------------------------------------------------------------------
## |
## Description Testing of the "EEPROM 24AA64" chip on the TDC board (IC10). The firmware loaded |
## to the FPGA on the carrier implements the interface for the communication between |
## the PCIe bus and the I2C of the EEPROM; this interface is an I2C WISHBONE master, |
## running with a system clock of 50MHz. |
## |
## The I2C WISHBONE master can be accessed at base address 0x60000. |
## The I2C address of the EEPROM is x50, predefined in the part number. |
## |
## The test attempts several writings and readbacks on different EEPROM locations. |
## |
## FW to load .bin |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE |
## ------------------------------------ |
## This source file is free software; you can redistribute it and/or modify it under the terms of |
## the GNU Lesser General Public License as published by the Free Software Foundation; either |
## version 2.1 of the License, or (at your option) any later version. |
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
## See the GNU Lesser General Public License for more details. |
## You should have received a copy of the GNU Lesser General Public License along with this |
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import --
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
# Import specific modules
import fmc_tdc
sys.path.append('../../../../fmc_delay/software/python/')
import fdelay_lib
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/tdc_counters.bit'#tdc_carrier_info.bit'#eva_tdc_for_v2.bit'#evas_tdc_leds.bit'#evas_tdc_ctrl_dac.bit'#evas_tdc_irq8.bit'
EEPROM_ADDR = 0x50
# SPEC object declaration
spec = rr.Gennum()
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- TDC PTS -----------------------------"
print "--------------------------- EEPROM test ---------------------------"
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
# Load FMC TDC firmware
print "\n_________________________Initialisations_________________________\n"
print "Loading FMC Fine Delay firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
print "\n__________________________EEPROM IC10 test_______________________\n"
# Scan FMC I2C bus
periph_addr = tdc.mezz_i2c_scan()
# Check that the EEPROM is detected on the I2C bus
if(0 == len(periph_addr)):
raise PtsError("ERROR: EEPROM IC10: No peripheral detected on system management I2C bus")
else:
if(1 != len(periph_addr)):
raise PtsError("ERROR: EEPROM IC10: Signal integrity problem detected on system management I2C bus, %d devices detected instead of 1"%(len(periph_addr)))
else:
if(EEPROM_ADDR != periph_addr[0]):
raise PtsError("ERROR: EEPROM IC10: Wrong device mounted on system management I2C bus, address is:0x%.2X expected:0x%.2X"%(periph_addr[0],EEPROM_ADDR))
# Write, read back and compare
addr = 0x20
wr_data = [0x55, 0xAA, 0x00, 0xFF]
rd_data = []
print('EEPROM IC10: Writting data at EEPROM address 0x%.2X: ')%addr,
print wr_data
tdc.mezz_i2c_eeprom_write(addr, wr_data)
time.sleep(0.1)
print('EEPROM IC10: Reading data from EEPROM address 0x%.2X:')%addr,
rd_data = tdc.mezz_i2c_eeprom_read(addr, len(wr_data))
print rd_data
if(rd_data != wr_data):
raise PtsError("ERROR: EEPROM IC10: Data reading/ writing failed")
else:
print('\nEEPROM IC10: Data comparison OK')
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
main()
test/fmctdc1ns5cha/python/tdc_pts_inputs_fpga.py 0 → 100644
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test/fmctdc1ns5cha/python/tdc_pts_inputs_fpga_enable.py 0 → 100644
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test/fmctdc1ns5cha/python/tdc_pts_leds.py 0 → 100644
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#! /usr/bin/env python
# coding: utf8
##_________________________________________________________________________________________________
## |
## |TDC PTS| |
## |
## CERN,BE/CO-HT |
##________________________________________________________________________________________________|
##-------------------------------------------------------------------------------------------------
## |
## TDC LEDs test |
## |
##-------------------------------------------------------------------------------------------------
## |
## Description Testing of the LEDs on the front panel of the TDC board. |
## |
## Upon firmware loading the 6 LEDs on the TDC front panel start blinking one by one |
## on a cyclic way; |
## This test needs the operator's input; when prompted, the operatior needs to report|
## if all the LEDs are blinking as expected. |
## |
## |
## FW to load .bin |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE |
## ------------------------------------ |
## This source file is free software; you can redistribute it and/or modify it under the terms of |
## the GNU Lesser General Public License as published by the Free Software Foundation; either |
## version 2.1 of the License, or (at your option) any later version. |
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
## See the GNU Lesser General Public License for more details. |
## You should have received a copy of the GNU Lesser General Public License along with this |
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import --
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
import csr
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/tdc_pts_leds.bit'#tdc_carrier_info2.bit'#eva_tdc_for_v2.bit'#evas_tdc_leds.bit'#evas_tdc_ctrl_dac.bit'
print "\n-------------------------------------------------------------------"
print "----------------------------- TDC PTS -----------------------------"
print "---------------------------- LEDs test ----------------------------"
# SPEC object declaration
spec = rr.Gennum()
print "\n_________________________Initialisations_________________________\n"
# Load FMC TDC firmware
print "Loading FMC TDC firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
print "\n_________________________LEDs inspection_________________________\n"
ask = raw_input("--> Are all the TDC front panel LEDs blinking one by one [y/n]: ")
ask = ask.upper()
if (ask == "N"):
raise PtsError ("ERROR: Front Panel LEDs")
else:
print ("LEDs inspected OK!")
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
main()
test/fmctdc1ns5cha/python/tdc_pts_onewire.py 0 → 100644
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#! /usr/bin/env python
# coding: utf8
##_________________________________________________________________________________________________
## |
## |TDC PTS| |
## |
## CERN,BE/CO-HT |
##________________________________________________________________________________________________|
##-------------------------------------------------------------------------------------------------
## |
## TDC OneWire test |
## |
##-------------------------------------------------------------------------------------------------
## |
## Description Testing of the "Thermometer & Unique ID, DS18B20" chip on the TDC board (IC14). |
## The firmware loaded to the FPGA on the carrier implements the interface for the |
## communication between the PCIe bus and the One Wire of the DS18B20; this interface|
## is a One-Wire WISHBONE master, running with a 50MHz system clock. |
## |
## The One-Wire WISHBONE master can be accessed base address 0x80000. |
## The family code of the DS18B20 is x28, predefined in the part number. |
## |
## The test reads the unique ID and the temperature and checks if the received |
## values are within reasonable limits. |
## |
## FW to load .bin |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE |
## ------------------------------------ |
## This source file is free software; you can redistribute it and/or modify it under the terms of |
## the GNU Lesser General Public License as published by the Free Software Foundation; either |
## version 2.1 of the License, or (at your option) any later version. |
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
## See the GNU Lesser General Public License for more details. |
## You should have received a copy of the GNU Lesser General Public License along with this |
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import --
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
# Import specific modules
import fmc_tdc
sys.path.append('../../../../fmc_delay/software/python/')
import fdelay_lib
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/tdc_counters.bit'#tdc_carrier_info2.bit'#eva_tdc_for_v2.bit'#evas_tdc_irq8.bit'
FAMILY_CODE = 0x28
# SPEC object declaration
spec = rr.Gennum()
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "----------------------------- TDC PTS -----------------------------"
print "--------------------------- 1-Wire test ---------------------------"
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
spec.bind(FMC_TDC_ADDR)
print "\n_________________________Initialisations_________________________\n"
# Load FMC TDC firmware
print "Loading FMC TDC firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
# TDC object declaration
tdc = fmc_tdc.CFMCTDC(spec)
# Read unique ID and print to log
print "\n____________________________Unique ID____________________________\n"
unique_id = tdc.mezz_get_unique_id()
if(unique_id == -1):
raise PtsError("ERROR: TEMPID IC14: Cannot access the device")
else:
print('TEMPID IC14: Unique ID: %.12X OK') % unique_id
if((unique_id & 0xFF) != FAMILY_CODE):
family_code = unique_id & 0xFF
print('TEMPID IC14: Family Code: 0x%.8X') % family_code
raise PtsError ("ERROR: TEMPID IC14: Wrong Family Code:0x.2X is different than the expected:0x%.2X" % family_code,FAMILY_CODE)
# Read temperature and print to log
print "\n___________________________Temperature___________________________\n"
temp = tdc.mezz_get_temp()
if (temp > 100 or temp < 20):
raise PtsError ("ERROR: TEMPID IC14: Temperature measurement %3.3f°C is out of the accepted limits [20°C .. 100°C] " % temp)
else:
print('TEMPID IC14: Temperature: %3.2f°C OK') % temp
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
main()
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#! /usr/bin/env python
# coding: utf8
##_________________________________________________________________________________________________
## |
## |TDC PTS| |
## |
## CERN,BE/CO-HT |
##________________________________________________________________________________________________|
##-------------------------------------------------------------------------------------------------
## |
## TDC Presence test |
## |
##-------------------------------------------------------------------------------------------------
## |
## Description Testing of the presence of the TDC board on the SPEC carrier. |
## |
## The test retrieves information on the carrier board: pcb version, carrier type, |
## status, control, mezzzanine presence. |
## Note that the mezzanine presence flag comes from the FMC pin prsnt_m2c_n_i. |
## |
## The WISHBONE master can be accessed at PCIe base address xC0000. |
## |
## |
## FW to load .bin |
## Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
## Website http://www.ohwr.org/projects/pts |
## Date 11/01/2013 |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE |
## ------------------------------------ |
## This source file is free software; you can redistribute it and/or modify it under the terms of |
## the GNU Lesser General Public License as published by the Free Software Foundation; either |
## version 2.1 of the License, or (at your option) any later version. |
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
## See the GNU Lesser General Public License for more details. |
## You should have received a copy of the GNU Lesser General Public License along with this |
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import --
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os
# Add common modules location tp path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
import csr
# Import specific modules
import fmc_tdc
sys.path.append('../../../../fmc_delay/software/python/')
import fdelay_lib
def main (default_directory='.'):
# Constants declaration
FMC_TDC_ADDR = '1a39:0004/1a39:0004@000B:0000'
FMC_TDC_BITSTREAM = '../firmwares/tdc_pts_presence.bit'#top_tdc.bit'#tdc_counters.bit'#tdc_carrier_info2.bit'#eva_tdc_for_v2.bit'#evas_tdc_leds.bit'#evas_tdc_ctrl_dac.bit'#evas_tdc_irq8.bit'
FMC_TDC_CHANNEL_NB = 5
# Addressing for the retrieval of carrier csr information
CARRIER_CSR = 0x00000 # base address
CSR_TYPE_VER = 0x00
CSR_BSTM_TYPE = 0x04
CSR_BSTM_DATE = 0x08
CSR_STATUS = 0x0C
CSR_CTRL = 0x10
PCB_VER_MASK = 0x000F
CARRIER_TYPE_MASK = 0xFFFF0000
STATUS_FMC_PRES = (1<<0)
# SPEC object declaration
spec = rr.Gennum()
# Bind SPEC object to FMC TDC card
print "\n-------------------------------------------------------------------"
print "---------------------------- FMC TDC ---------------------------- "
print "-------------------- Mezzanine presence test --------------------"
print "\n_______________________________Info______________________________\n"
print "FMC TDC address to parse: %s"%(FMC_TDC_ADDR)
for name, value in spec.parse_addr(FMC_TDC_ADDR).iteritems():
print "%s:0x%04X"%(name, value)
spec.bind(FMC_TDC_ADDR)
carrier_csr = csr.CCSR(spec, CARRIER_CSR)
tdc = fmc_tdc.CFMCTDC(spec)
print "\n_________________________Initialisations_________________________\n"
# Load FMC TDC firmware
print "Loading FMC TDC firmware...",
spec.load_firmware(FMC_TDC_BITSTREAM)
time.sleep(2)
print "Firmware loaded!"
# Check bitsteam type
bitstream_type = carrier_csr.rd_reg(CSR_BSTM_TYPE)
print('Bitstream type :%.8X') % bitstream_type
if(bitstream_type == 0xFFFFFFFF):
raise PtsError ("FATAL ERROR: Firmware not properly loaded")
if(bitstream_type != 0x1):
raise PtsError ("FATAL ERROR: Wrong bitstream type loaded")
# Carrier Information
print "\n___________________________Carrier info__________________________\n"
print("PCB version : %d") % (PCB_VER_MASK & carrier_csr.rd_reg(CSR_TYPE_VER))
print("Carrier type : %d") % ((CARRIER_TYPE_MASK & carrier_csr.rd_reg(CSR_TYPE_VER))>>16)
print("Bitstream type : 0x%.8X") % (carrier_csr.rd_reg(CSR_BSTM_TYPE))
print("Bitstream date : 0x%.8X") % (carrier_csr.rd_reg(CSR_BSTM_DATE))
print("Status : 0x%.8X") % (carrier_csr.rd_reg(CSR_STATUS))
print("Control : 0x%.8X") % (carrier_csr.rd_reg(CSR_CTRL))
# Check mezzanine presence flag
print "\n__________________________Presence test__________________________\n"
status = carrier_csr.rd_reg(CSR_STATUS)
if(status & STATUS_FMC_PRES):
print('Carrier csr status :%.8X') % status
print ("FATAL ERROR: Mezzanine appears missing.")
#raise PtsError ("FATAL ERROR: Mezzanine appears missing.")
else:
print("Mezzanine present OK\n")
print "\n\n-----------------------------------------------------------------"
if __name__ == '__main__' :
main()
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test/fmctdc1ns5cha/vhdl/tdc_pts_clks/rtl/ip_cores/genram_pkg.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-01-24
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
-- Generic RAM initialized with nothing.
constant c_generic_ram_nothing : t_generic_ram_init(-1 downto 0, -1 downto 0) :=
(others => (others => '0'));
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0):= f_gen_dummy_vec('1', (g_data_width+7)/8);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic := '0';
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
web_i : in std_logic := '0';
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_shiftreg_fifo
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
full_o : out std_logic;
almost_full_o : out std_logic;
q_valid_o : out std_logic
);
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector is
variable tmp : std_logic_vector(size-1 downto 0);
begin
for i in 0 to size-1 loop
tmp(i) := val;
end loop; -- i
return tmp;
end f_gen_dummy_vec;
end genram_pkg;
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------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_ddr_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: BUFIO2 Based DDR clock generator. Takes in a differential clock
-- and instantiates two sets of 2 BUFIO2s, one for each half bank
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity clock_generator_ddr_s2_diff is
generic (
S : integer := 2; -- Parameter to set the serdes factor
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic; -- differential clock input
ioclkap : out std_logic; -- A P ioclock from BUFIO2
ioclkan : out std_logic; -- A N ioclock from BUFIO2
serdesstrobea : out std_logic; -- A serdes strobe from BUFIO2
ioclkbp : out std_logic; -- B P ioclock from BUFIO2 - leave open if not required
ioclkbn : out std_logic; -- B N ioclock from BUFIO2 - leave open if not required
serdesstrobeb : out std_logic; -- B serdes strobe from BUFIO2 - leave open if not required
gclk : out std_logic) ; -- global clock output from BUFIO2
end clock_generator_ddr_s2_diff;
architecture arch_clock_generator_ddr_s2_diff of clock_generator_ddr_s2_diff is
signal clkint : std_logic; --
signal gclk_int : std_logic; --
signal freqgen_in_p : std_logic; --
signal tx_bufio2_x1 : std_logic; --
begin
gclk <= gclk_int;
iob_freqgen_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => freqgen_in_p);
bufio2_inst1 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => false, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => true) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkap, -- Output Clock for IO
DIVCLK => tx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => serdesstrobea) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst2 : BUFIO2 generic map(
I_INVERT => true, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => false) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkan, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst3 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => false, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => true) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkbp, -- Output Clock for IO
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => serdesstrobeb) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst4 : BUFIO2 generic map(
I_INVERT => true, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => false) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkbn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufg_tx : BUFG port map (I => tx_bufio2_x1, O => gclk_int);
end arch_clock_generator_ddr_s2_diff;
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# Date: Thu Feb 3 16:41:04 2011
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: f66dfaab
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_32x512.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_32x512.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_32x512.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_32x512.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_32x512.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
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