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dd792351
Commit
dd792351
authored
May 30, 2012
by
Matthieu Cattin
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test08: Uses common modules, added exception handling.
parent
f1e6d0e5
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test08.py
test/fmcadc100m14b4cha/python/test08.py
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test/fmcadc100m14b4cha/python/test08.py
View file @
dd792351
...
@@ -5,17 +5,26 @@
...
@@ -5,17 +5,26 @@
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Website: http://www.ohwr.org
# Last modifications: 30/5/2012
# Import system modules
import
sys
import
sys
import
rr
import
time
import
time
import
os
import
os
from
numpy
import
*
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../gnurabbit/python/'
)
sys
.
path
.
append
(
'../../../common/'
)
# Import common modules
from
ptsexcept
import
*
from
ptsexcept
import
*
import
rr
import
spec_fmc_adc
# Import specific modules
import
fmc_adc
from
fmc_adc_spec
import
*
from
fmc_adc
import
*
from
numpy
import
*
import
calibr_box
import
calibr_box
import
find_usb_tty
import
find_usb_tty
from
PAGE.Agilent33250A
import
*
from
PAGE.Agilent33250A
import
*
...
@@ -29,15 +38,6 @@ Note: Requires test00.py to run first to load the firmware!
...
@@ -29,15 +38,6 @@ Note: Requires test00.py to run first to load the firmware!
"""
"""
# Calibration box vendor and product IDs
BOX_USB_VENDOR_ID
=
0x10c4
# Cygnal Integrated Products, Inc.
BOX_USB_PRODUCT_ID
=
0xea60
# CP210x Composite Device
# Agilent AWG serial access vendor and product IDs
AWG_USB_VENDOR_ID
=
0x0403
# Future Technology Devices International, Ltd
AWG_USB_PRODUCT_ID
=
0x6001
# FT232 USB-Serial (UART) IC
AWG_BAUD
=
57600
NB_CHANNELS
=
4
NB_CHANNELS
=
4
PRE_TRIG_SAMPLES
=
1000
PRE_TRIG_SAMPLES
=
1000
...
@@ -63,16 +63,6 @@ SW6_TOL = 20000
...
@@ -63,16 +63,6 @@ SW6_TOL = 20000
SW7_TOL
=
20000
SW7_TOL
=
20000
def
load_firmware
(
default_directory
):
print
(
'Load firmware to FPGA'
)
path_fpga_loader
=
'../../../gnurabbit/user/fpga_loader'
;
path_firmware
=
'../firmwares/spec_fmcadc100m14b4cha.bin'
;
firmware_loader
=
os
.
path
.
join
(
default_directory
,
path_fpga_loader
)
bitstream
=
os
.
path
.
join
(
default_directory
,
path_firmware
)
print
firmware_loader
+
' '
+
bitstream
os
.
system
(
firmware_loader
+
' '
+
bitstream
)
time
.
sleep
(
2
);
def
hex2signed
(
value
):
def
hex2signed
(
value
):
if
(
value
&
0x8000
):
if
(
value
&
0x8000
):
return
-
((
~
value
&
0xFFFF
)
+
1
)
return
-
((
~
value
&
0xFFFF
)
+
1
)
...
@@ -80,7 +70,7 @@ def hex2signed(value):
...
@@ -80,7 +70,7 @@ def hex2signed(value):
return
value
return
value
def
acq_config
(
fmc
):
def
acq_config
(
fmc
):
print
(
'Initialise FMC board
\n
'
)
print
"Initialise FMC board
\n
"
# Set trigger
# Set trigger
fmc
.
set_soft_trig
()
fmc
.
set_soft_trig
()
# Set acquisition
# Set acquisition
...
@@ -88,7 +78,7 @@ def acq_config(fmc):
...
@@ -88,7 +78,7 @@ def acq_config(fmc):
fmc
.
set_post_trig_samples
(
POST_TRIG_SAMPLES
)
fmc
.
set_post_trig_samples
(
POST_TRIG_SAMPLES
)
fmc
.
set_shots
(
NB_SHOTS
)
fmc
.
set_shots
(
NB_SHOTS
)
def
get_channels_mean
(
fmc
,
spec_fmc
):
def
get_channels_mean
(
fmc
,
carrier
):
# Make sure no acquisition is running
# Make sure no acquisition is running
fmc
.
stop_acq
()
fmc
.
stop_acq
()
# Start acquisition
# Start acquisition
...
@@ -103,16 +93,16 @@ def get_channels_mean(fmc, spec_fmc):
...
@@ -103,16 +93,16 @@ def get_channels_mean(fmc, spec_fmc):
timeout
+=
1
timeout
+=
1
if
(
ACQ_TIMEOUT
<
timeout
):
if
(
ACQ_TIMEOUT
<
timeout
):
print
"Acquisition timeout. Missing trigger?."
print
"Acquisition timeout. Missing trigger?."
print
"Acq FSm state:
%
s"
%
fmc
.
get_acq_fsm_state
()
print
"Acq FSm state:
%
s"
%
fmc
.
get_acq_fsm_state
()
return
1
return
1
# Retrieve data trough DMA
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" iinterrupt
# Enable "DMA done" iinterrupt
spec_fmc
.
set_irq_en_mask
(
0x1
)
carrier
.
set_irq_en_mask
(
0x1
)
# Read ACQ_LENGTH samples after the trigger for all channels
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
spec_fmc
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" iinterrupt
# Disable "DMA done" iinterrupt
spec_fmc
.
set_irq_en_mask
(
0x0
)
carrier
.
set_irq_en_mask
(
0x0
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
# calculate mean value for each channel
# calculate mean value for each channel
channels_mean
=
[]
channels_mean
=
[]
...
@@ -127,15 +117,15 @@ def set_awg_offset(gen, sine, offset):
...
@@ -127,15 +117,15 @@ def set_awg_offset(gen, sine, offset):
def
print_current_adc_value
(
fmc
,
channel
,
file
):
def
print_current_adc_value
(
fmc
,
channel
,
file
):
adc_value
=
fmc
.
get_current_adc_value
(
channel
)
adc_value
=
fmc
.
get_current_adc_value
(
channel
)
print
(
'CH
%
d ADC value:0x
%.4
X
%
d'
)
%
(
channel
,
adc_value
,
adc_value
)
print
"CH
%
d ADC value:0x
%.4
X
%
d"
%
(
channel
,
adc_value
,
adc_value
)
file
.
write
(
'CH
%
d: 0x
%.4
X
%
d
\n
'
%
(
channel
,
adc_value
,
adc_value
))
file
.
write
(
'CH
%
d: 0x
%.4
X
%
d
\n
'
%
(
channel
,
adc_value
,
adc_value
))
# Routine to test SSR (Solid State Relay)
# Routine to test SSR (Solid State Relay)
# Basic operation: Set AWG DC offset and SSRs -> read ADC value, change 1 SSR -> read ADC -> check ADC values difference
# Basic operation: Set AWG DC offset and SSRs -> read ADC value, change 1 SSR -> read ADC -> check ADC values difference
# Options: retry -> run the same test several times
# Options: retry -> run the same test several times
# threshold -> minimum number of try to pass the test
# threshold -> minimum number of try to pass the test
def
sw_test
(
box
,
gen
,
sine
,
spec_fmc
,
fmc
,
sw
,
ssr_1
,
ssr_2
,
diff_tol
):
def
sw_test
(
box
,
gen
,
sine
,
carrier
,
fmc
,
sw
,
ssr_1
,
ssr_2
,
diff_tol
):
print
(
'
\n
Testing switch
%
d
\n
-------------------------'
)
%
sw
print
"
\n
Testing switch
%
d
\n
-------------------------"
%
sw
error
=
0
error
=
0
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
...
@@ -144,32 +134,32 @@ def sw_test(box, gen, sine, spec_fmc, fmc, sw, ssr_1, ssr_2, diff_tol):
...
@@ -144,32 +134,32 @@ def sw_test(box, gen, sine, spec_fmc, fmc, sw, ssr_1, ssr_2, diff_tol):
time
.
sleep
(
BOX_SET_SLEEP
)
time
.
sleep
(
BOX_SET_SLEEP
)
fmc
.
set_ssr
(
i
,
ssr_1
)
fmc
.
set_ssr
(
i
,
ssr_1
)
#time.sleep(SSR_SET_SLEEP)
#time.sleep(SSR_SET_SLEEP)
adc_value_before
=
get_channels_mean
(
fmc
,
spec_fmc
)[
i
-
1
]
adc_value_before
=
get_channels_mean
(
fmc
,
carrier
)[
i
-
1
]
fmc
.
set_ssr
(
i
,
ssr_2
)
fmc
.
set_ssr
(
i
,
ssr_2
)
#time.sleep(SSR_SET_SLEEP)
#time.sleep(SSR_SET_SLEEP)
adc_value
=
get_channels_mean
(
fmc
,
spec_fmc
)[
i
-
1
]
adc_value
=
get_channels_mean
(
fmc
,
carrier
)[
i
-
1
]
diff
=
adc_value_before
-
adc_value
diff
=
adc_value_before
-
adc_value
print
(
'CH
%
d ssr=0x
%.2
X:
%6
d ssr=0x
%.2
X:
%6
d diff:
%6
d ,min_diff:
%6
d'
)
%
(
i
,
ssr_1
,
adc_value_before
,
ssr_2
,
adc_value
,
abs
(
diff
),
diff_tol
)
print
"CH
%
d ssr=0x
%.2
X:
%6
d ssr=0x
%.2
X:
%6
d diff:
%6
d ,min_diff:
%6
d"
%
(
i
,
ssr_1
,
adc_value_before
,
ssr_2
,
adc_value
,
abs
(
diff
),
diff_tol
)
if
(
diff_tol
>
abs
(
diff
)):
if
(
diff_tol
>
abs
(
diff
)):
print
(
'#### SW
%
d of channel
%
d is malfunctioning'
)
%
(
sw
,
i
)
print
"#### SW
%
d of channel
%
d is malfunctioning"
%
(
sw
,
i
)
#raise PtsError('SW%d of channel %d is malfunctioning' % (sw, i))
#raise PtsError('SW%d of channel %d is malfunctioning' % (sw, i))
error
+=
1
error
+=
1
fmc
.
set_ssr
(
i
,
0x0
)
fmc
.
set_ssr
(
i
,
0x0
)
#time.sleep(SSR_SET_SLEEP)
#time.sleep(SSR_SET_SLEEP)
return
error
return
error
def
adc_mid_test
(
spec_fmc
,
fmc
,
tol
):
def
adc_mid_test
(
carrier
,
fmc
,
tol
):
print
(
'
\n
Testing ADC middle scale, all switches opened.
\n
-------------------------'
)
print
"
\n
Testing ADC middle scale, all switches opened.
\n
-------------------------"
error
=
0
error
=
0
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
ssr_1
=
0x0
ssr_1
=
0x0
fmc
.
set_ssr
(
i
,
ssr_1
)
fmc
.
set_ssr
(
i
,
ssr_1
)
#time.sleep(SSR_SET_SLEEP)
#time.sleep(SSR_SET_SLEEP)
diff
=
get_channels_mean
(
fmc
,
spec_fmc
)[
i
-
1
]
diff
=
get_channels_mean
(
fmc
,
carrier
)[
i
-
1
]
print
(
'CH
%
d ssr=0x
%.2
X, value:
%6
d, expected value:
%
d, diff:
%6
d, tolerence:
%
d'
)
%
(
i
,
ssr_1
,
diff
,
ADC_MID_VALUE
,
diff
,
tol
)
print
"CH
%
d ssr=0x
%.2
X, value:
%6
d, expected value:
%
d, diff:
%6
d, tolerence:
%
d"
%
(
i
,
ssr_1
,
diff
,
ADC_MID_VALUE
,
diff
,
tol
)
if
(
abs
(
diff
)
>
tol
):
if
(
abs
(
diff
)
>
tol
):
print
(
'#### One of channel
%
d switches is malfunctioning'
)
%
i
print
"#### One of channel
%
d switches is malfunctioning"
%
i
#raise PtsError('One of channel %d switches is malfunctioning' % i)
#raise PtsError('One of channel %d switches is malfunctioning' % i)
error
+=
1
error
+=
1
return
error
return
error
...
@@ -177,87 +167,127 @@ def adc_mid_test(spec_fmc, fmc, tol):
...
@@ -177,87 +167,127 @@ def adc_mid_test(spec_fmc, fmc, tol):
def
main
(
default_directory
=
'.'
):
def
main
(
default_directory
=
'.'
):
# Load firmware
# Constants declaration
#load_firmware(default_directory)
TEST_NB
=
8
EXPECTED_BITSTREAM_TYPE
=
0x1
# Calibration box vendor and product IDs
BOX_USB_VENDOR_ID
=
0x10c4
# Cygnal Integrated Products, Inc.
BOX_USB_PRODUCT_ID
=
0xea60
# CP210x Composite Device
# Agilent AWG serial access vendor and product IDs
AWG_USB_VENDOR_ID
=
0x0403
# Future Technology Devices International, Ltd
AWG_USB_PRODUCT_ID
=
0x6001
# FT232 USB-Serial (UART) IC
AWG_BAUD
=
57600
start_test_time
=
time
.
time
()
print
"================================================================================"
print
"Test
%02
d start
\n
"
%
TEST_NB
# SPEC object declaration
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Carrier object declaration (SPEC board specific part)
# Used to check that the firmware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
raise
PtsCritical
(
"Carrier init failed, test stopped:
%
s"
%
e
)
# Mezzanine object declaration (FmcAdc100m14b4cha board specific part)
try
:
fmc
=
CFmcAdc100m
(
spec
)
except
FmcAdc100mOperationError
as
e
:
raise
PtsCritical
(
"Mezzanine init failed, test stopped:
%
s"
%
e
)
try
:
# Others objects declaration
usb_tty
=
find_usb_tty
.
CttyUSB
()
awg_tty
=
usb_tty
.
find_usb_tty
(
AWG_USB_VENDOR_ID
,
AWG_USB_PRODUCT_ID
)
box_tty
=
usb_tty
.
find_usb_tty
(
BOX_USB_VENDOR_ID
,
BOX_USB_PRODUCT_ID
)
gen
=
Agilent33250A
(
device
=
awg_tty
[
0
],
bauds
=
AWG_BAUD
)
sine
=
SineWaveform
()
box
=
calibr_box
.
CCalibr_box
(
box_tty
[
0
])
# Set sine params -> ~ DC level
sine
.
frequency
=
0.000001
sine
.
amplitude
=
0.001
sine
.
dc
=
1
# Set AWG and turn it ON
gen
.
connect
()
gen
.
output
=
True
# Configure acquisition
acq_config
(
fmc
)
# Reset offset DACs to mid-scale (no offset)
fmc
.
dc_offset_reset
()
# Uncomment the following block to check calibration box output connections
"""
print "Ckecking calibration box output connections"
set_awg_offset(gen, sine, 2)
for i in range(1,NB_CHANNELS+1):
print "Channel
%
d"
%
i
fmc.set_ssr(i,0x1)
time.sleep(SSR_SET_SLEEP)
box.select_output_ch(i) # connect AWG to current channel
time.sleep(BOX_SET_SLEEP)
print get_channels_mean(fmc, carrier)
fmc.set_ssr(i,0x0)
time.sleep(SSR_SET_SLEEP)
"""
# Objects declaration
# Test switches
spec
=
rr
.
Gennum
()
# bind to the SPEC board
error
=
0
spec_fmc
=
spec_fmc_adc
.
CSpecFmcAdc100Ms
(
spec
)
fmc
=
fmc_adc
.
CFmcAdc100Ms
(
spec
)
usb_tty
=
find_usb_tty
.
CttyUSB
()
awg_tty
=
usb_tty
.
find_usb_tty
(
AWG_USB_VENDOR_ID
,
AWG_USB_PRODUCT_ID
)
box_tty
=
usb_tty
.
find_usb_tty
(
BOX_USB_VENDOR_ID
,
BOX_USB_PRODUCT_ID
)
gen
=
Agilent33250A
(
device
=
awg_tty
[
0
],
bauds
=
AWG_BAUD
)
sine
=
SineWaveform
()
box
=
calibr_box
.
CCalibr_box
(
box_tty
[
0
])
# Set sine params -> ~ DC level
error
+=
adc_mid_test
(
carrier
,
fmc
,
ADC_MID_TOL
)
sine
.
frequency
=
0.000001
sine
.
amplitude
=
0.001
sine
.
dc
=
1
# Set AWG and turn it ON
# Set AWG offset
gen
.
connect
()
awg_offset
=
0.25
gen
.
output
=
True
set_awg_offset
(
gen
,
sine
,
awg_offset
)
print
"
\n
=> AWG offset:
%1.3
fV"
%
awg_offset
# Configure acquisition
error
+=
sw_test
(
box
,
gen
,
sine
,
carrier
,
fmc
,
1
,
0x00
,
0x01
,
SW1_TOL
)
acq_config
(
fmc
)
error
+=
sw_test
(
box
,
gen
,
sine
,
carrier
,
fmc
,
4
,
0x01
,
0x09
,
SW4_TOL
)
error
+=
sw_test
(
box
,
gen
,
sine
,
carrier
,
fmc
,
5
,
0x41
,
0x51
,
SW5_TOL
)
error
+=
sw_test
(
box
,
gen
,
sine
,
carrier
,
fmc
,
6
,
0x00
,
0x60
,
SW6_TOL
)
error
+=
sw_test
(
box
,
gen
,
sine
,
carrier
,
fmc
,
7
,
0x01
,
0x41
,
SW7_TOL
)
# Reset offset DACs to mid-scale (no offset)
# Set AWG offset
fmc
.
dc_offset_reset
()
awg_offset
=
0.01
set_awg_offset
(
gen
,
sine
,
awg_offset
)
print
"
\n
=> AWG offset:
%1.3
fV"
%
awg_offset
# Uncomment the fillowing pblock to check calibration box output connections
error
+=
sw_test
(
box
,
gen
,
sine
,
carrier
,
fmc
,
2
,
0x20
,
0x22
,
SW2_TOL
)
"""
error
+=
sw_test
(
box
,
gen
,
sine
,
carrier
,
fmc
,
3
,
0x22
,
0x26
,
SW3_TOL
)
print "Ckecking calibration box output connections"
set_awg_offset(gen, sine, 2)
for i in range(1,NB_CHANNELS+1):
print "Channel
%
d"
%
i
fmc.set_ssr(i,0x1)
time.sleep(SSR_SET_SLEEP)
box.select_output_ch(i) # connect AWG to current channel
time.sleep(BOX_SET_SLEEP)
print get_channels_mean(fmc, spec_fmc)
fmc.set_ssr(i,0x0)
time.sleep(SSR_SET_SLEEP)
"""
# Test switches
error
=
0
error
+=
adc_mid_test
(
spec_fmc
,
fmc
,
ADC_MID_TOL
)
# Set AWG offset
# Make sure all switches are OFF
awg_offset
=
0.25
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
set_awg_offset
(
gen
,
sine
,
awg_offset
)
fmc
.
set_ssr
(
i
,
0x00
)
print
(
'AWG offset:
%1.3
fV'
)
%
awg_offset
error
+=
sw_test
(
box
,
gen
,
sine
,
spec_fmc
,
fmc
,
1
,
0x00
,
0x01
,
SW1_TOL
)
error
+=
sw_test
(
box
,
gen
,
sine
,
spec_fmc
,
fmc
,
4
,
0x01
,
0x09
,
SW4_TOL
)
error
+=
sw_test
(
box
,
gen
,
sine
,
spec_fmc
,
fmc
,
5
,
0x41
,
0x51
,
SW5_TOL
)
error
+=
sw_test
(
box
,
gen
,
sine
,
spec_fmc
,
fmc
,
6
,
0x00
,
0x60
,
SW6_TOL
)
error
+=
sw_test
(
box
,
gen
,
sine
,
spec_fmc
,
fmc
,
7
,
0x01
,
0x41
,
SW7_TOL
)
# Set AWG offset
# Switch AWG OFF
awg_offset
=
0.01
gen
.
output
=
False
set_awg_offset
(
gen
,
sine
,
awg_offset
)
gen
.
close
()
print
(
'AWG offset:
%1.3
fV'
)
%
awg_offset
error
+=
sw_test
(
box
,
gen
,
sine
,
spec_fmc
,
fmc
,
2
,
0x20
,
0x22
,
SW2_TOL
)
# Check if an error occured during switches test
error
+=
sw_test
(
box
,
gen
,
sine
,
spec_fmc
,
fmc
,
3
,
0x22
,
0x26
,
SW3_TOL
)
if
(
error
!=
0
):
raise
PtsError
(
'An error occured during switches test, check log for details.'
)
else
:
print
"
\n
All switches are working fine!"
# Make sure all switches are OFF
except
(
FmcAdc100mSpecOperationError
,
FmcAdc100mOperationError
,
CalibrBoxOperationError
)
as
e
:
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
raise
PtsError
(
"Test failed:
%
s"
%
e
)
fmc
.
set_ssr
(
i
,
0x00
)
# Switch AWG OFF
gen
.
output
=
False
gen
.
close
()
# Check if an error occured during switches test
print
""
if
(
error
!=
0
):
print
"==> End of test
%02
d"
%
TEST_NB
raise
PtsError
(
'An error occured during switches test, check log for details.'
)
print
"================================================================================"
e
lse
:
e
nd_test_time
=
time
.
time
()
print
"
\n
All switches are working fine!"
print
"Test
%02
d elapsed time:
%.2
f seconds
\n
"
%
(
TEST_NB
,
end_test_time
-
start_test_time
)
# Following commented code scan all SSR configurations to find good ones for testing switches
# Following commented code scan all SSR configurations to find good ones for testing switches
...
@@ -335,13 +365,13 @@ def main (default_directory='.'):
...
@@ -335,13 +365,13 @@ def main (default_directory='.'):
# Following commented code is for testing the tests
# Following commented code is for testing the tests
"""
"""
sw_test(box, gen, sine, 0.25,
spec_fmc
, fmc, 1, 0x00, 0x00, SW1_TOL)
sw_test(box, gen, sine, 0.25,
carrier
, fmc, 1, 0x00, 0x00, SW1_TOL)
sw_test(box, gen, sine, 0.25,
spec_fmc
, fmc, 4, 0x01, 0x01, SW4_TOL)
sw_test(box, gen, sine, 0.25,
carrier
, fmc, 4, 0x01, 0x01, SW4_TOL)
sw_test(box, gen, sine, 0.25,
spec_fmc
, fmc, 5, 0x41, 0x41, SW5_TOL)
sw_test(box, gen, sine, 0.25,
carrier
, fmc, 5, 0x41, 0x41, SW5_TOL)
sw_test(box, gen, sine, 0.25,
spec_fmc
, fmc, 6, 0x00, 0x00, SW6_TOL)
sw_test(box, gen, sine, 0.25,
carrier
, fmc, 6, 0x00, 0x00, SW6_TOL)
sw_test(box, gen, sine, 0.25,
spec_fmc
, fmc, 7, 0x01, 0x01, SW7_TOL)
sw_test(box, gen, sine, 0.25,
carrier
, fmc, 7, 0x01, 0x01, SW7_TOL)
sw_test(box, gen, sine, 0.01,
spec_fmc
, fmc, 2, 0x20, 0x20, SW2_TOL)
sw_test(box, gen, sine, 0.01,
carrier
, fmc, 2, 0x20, 0x20, SW2_TOL)
sw_test(box, gen, sine, 0.01,
spec_fmc
, fmc, 3, 0x22, 0x22, SW3_TOL)
sw_test(box, gen, sine, 0.01,
carrier
, fmc, 3, 0x22, 0x22, SW3_TOL)
"""
"""
...
...
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